Organic light emitting diode display device and driving method thereof

Abstract

Disclosed herein is an organic light emitting diode display device and a driving method thereof, the organic light emitting diode display device comprising: a display panel, in which pixels adjacent to each other are paired and arranged to share a single data line in a pixel area defined by a plurality of gate lines and a plurality of data lines; a gate driver configured to drive the plurality of gate lines; a data driver configured to output a data voltage to a data voltage output channel based on the pixel arrangement; a data switch configured to alternately select pixels and electrically connect the pixels to the data voltage output channel of the data driver; and a timing controller configured to control the data switch as well as the gate driver and the data driver, so that even in a simplified structure of the data driving circuit, the data driving circuit can be driven at a high driving frequency and image quality degradation and image distortion can be prevented.

Description

Technical Field

[0001] The present disclosure relates to an organic light emitting diode display device capable of preventing image quality degradation and image distortion even during high-speed driving and a driving method thereof. Background Art

[0002] Flat panel image display devices are used in various electronic devices including mobile phones, tablet PCs, notebook computers, etc. As flat panel image display devices, liquid crystal display devices, organic light emitting diode display devices, electrowetting display devices, field emission devices, etc. are used.

[0003] Liquid crystal display devices, organic light emitting diode display devices, etc. adjust the amount of transmitted light or emitted light of each pixel to display an image through an image display panel in which a plurality of pixels are arranged in a matrix form. To this end, a panel driving circuit for driving the pixels of the image display panel is installed or electrically connected to the image display panel.

[0004] The organic light emitting diode display device includes color filters such as red, green, and blue color filters in each pixel region where the organic light emitting diode is disposed, and each pixel emits red, green, and blue light to display a color image.

[0005] In recent years, as organic light emitting diode display devices are applied to a wide range of devices such as mobile communication devices, tablet PCs, notebook computers, etc., there is an increasing demand for improvement and enhancement of organic light emitting diode display devices applied to a wider range of devices.

[0006] As means for improving the applicability of organic light emitting diode display devices to mobile communication devices, tablet PCs, notebook computers, and the like, methods such as correcting image data or changing the pixel arrangement of an image display panel have been proposed.

[0007] As an example, the output channels that output image signals are alternately connected to a pair of data lines adjacent to each other, and the image signals are alternately provided to the pair of data lines, so that the structure of the data driving circuit can be simplified.

[0008] Furthermore, pixels adjacent to each other share a single data line, and the image display panel is driven according to a dual rated driving (DRD) method, so that the structure of a data driving circuit can be simplified.

[0009] In recent years, the driving frequency of the image display panel is changed to change the image display speed. In the case of increasing the driving frequency to drive the image display panel at high speed, the driving period of the pixel is shortened. As a result, the image may be distorted.

[0010] In a simplified structure of a data driving circuit that switches and alternately outputs image signals or alternately drives pixels adjacent to each other, it is difficult to increase the driving frequency of the data driving circuit. Summary of the invention

[0011] The present disclosure relates to an organic light emitting diode display device and a driving method thereof that can prevent image quality degradation and image distortion even when an image display panel to which a simplified data driving circuit is applied is driven at a high speed.

[0012] The present disclosure relates to an organic light emitting diode display device and a driving method thereof that can prevent image quality degradation and image distortion in a simplified structure of a data driving circuit that switches and alternately outputs image signals and alternately drives pixels adjacent to each other even if the data driving circuit is driven at a high driving frequency.

[0013] The various aspects of the present disclosure are not limited to the contents that have been described. In addition, those skilled in the art to which the present disclosure belongs can clearly understand other aspects and advantages that are not mentioned based on the following description.

[0014] In the display panel of the organic light emitting diode display device according to the embodiment, pixels adjacent to each other along the gate line direction can be paired and arranged to share a single data line. Therefore, the total number of data lines can be half (1 / 2) of the total number of pixel columns, and a plurality of R, G, B pixels or R, G, B, W pixels can be driven according to a dual rated drive method (DRD).

[0015] To this end, the timing controller may arrange and output image data so that all pixels are driven and emit light according to the DRD method while alternately driving mutually adjacent pixels of the display panel at least in 1 horizontal period. In this case, the timing controller may arrange and output image data so that a pair of mutually adjacent pixels sharing a data line continuously emit light at least in units of 1 horizontal period.

[0016] The data switcher may be provided with a plurality of multiplexers or multiplexer circuits composed of a plurality of switch elements. The data switcher may electrically connect the 2i-1th and 2ith pixels to the data voltage output channel according to the first and second selection signals input by the timing controller, thereby alternately driving the 2i-1th and 2ith pixels.

[0017] The gate driver may continuously generate a first gate conduction signal according to a gate control signal, and may continuously provide the first gate conduction signal to pixels in odd columns based on a connection structure of the gate lines. Next, the gate driver may continuously generate a second gate conduction signal according to the gate control signal, and continuously provide the second gate conduction signal to pixels in even columns based on a connection structure of the gate lines. In addition, the gate driver may continuously generate a plurality of light-emitting control signals in response to the gate control signal, and may continuously provide each light-emitting control signal to each light-emitting control line.

[0018] The organic light emitting diode display device and the driving method thereof according to the embodiments of the present disclosure can be driven at an increased driving frequency, and image quality degradation and image distortion can be prevented even in a simplified structure of a data driving circuit that switches and alternately outputs image signals and alternately drives pixels adjacent to each other.

[0019] The details in the above technical problems, technical solutions and technical effects are not intended to specify the essential features in the attached claims. Therefore, the scope of the rights of the claims is not limited to the details in the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings constitute a part of this specification and, together with the specification, illustrate one or more embodiments of the present disclosure and explain the present disclosure, wherein;

[0021] Figure 1 is a block diagram specifically illustrating an organic light emitting diode display device according to an embodiment of the present disclosure;

[0022] Figure 2 It is shown Figure 1 Figure 1 shows a diagram of a data switcher and pixel arrangement;

[0023] Figure 3 It is shown Figure 1 A block diagram of a pixel arrangement of a data line sharing structure in FIG.

[0024] Figure 4 It specifically shows Figure 3 A circuit diagram of any pixel in; and

[0025] Figure 5 It shows the input to Figure 1 Timing diagram of the data switcher and pixel control signals. DETAILED DESCRIPTION

[0026] The advantages and features of the present disclosure and the methods for realizing the advantages and features of the present disclosure can be clearly understood according to the embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those of ordinary skill in the art to which the present disclosure belongs. The present disclosure should only be limited according to the scope of the appended claims.

[0027] The shapes, sizes, ratios, angles and quantities of the parts shown in the drawings of the present disclosure are given as examples only, and the present disclosure is not limited to the details set forth herein. Throughout the specification, the same reference numerals represent the same parts. When describing the present disclosure, if it is considered that the detailed description including the common knowledge of the related art makes the main points of the present disclosure unnecessarily vague, it will not be specifically described. Throughout the specification, unless explicitly stated otherwise, the terms "including", "having", "consisting of..." etc. should imply including any other parts without excluding any other parts, and the singular forms "one", "said" and "the" are also intended to include plural forms.

[0028] When describing components, error tolerance should be considered even if there is no explicit description. When spatial terms such as "on", "upper", "lower", "adjacent", etc. are used in this disclosure, one or more additional components may be inserted between two components unless terms such as "immediately" or "directly" are used.

[0029] When time terms such as "after," "next," "subsequently," "before," etc. are used to describe a time sequence, one or more additional events may be inserted between two events unless terms such as "immediately" or "directly" are used.

[0030] The features of various embodiments of the present disclosure may be partially or completely mixed or combined, and may be technically linked and connected in various ways. In addition, each embodiment may be implemented independently or in combination with each other.

[0031] Hereinafter, an organic light emitting diode display device and a driving method thereof according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram specifically illustrating an organic light emitting diode display device according to an embodiment of the present disclosure.

[0033] Figure 1 The organic light emitting diode display device in the embodiment may include an organic light emitting diode display panel 10 (referred to as “display panel”), a gate driver 200 , a data driver 300 , a data switch 100 , a power supply 400 , and a timing controller 500 .

[0034] The display panel 10 may be configured such that a plurality of R, G, B pixels (P) or R, G, B, W pixels (P) are respectively arranged in a pixel area defined by the intersecting gate lines (GL1 to GLn) and data lines (DL1 to DLm). The pixels P arranged close to each other along the direction of the gate lines (GL1 to GLn) may be paired and arranged to share a single data line (DL1 to DLm). Therefore, the total number of data lines (DLm) may be half (1 / 2) of the total number of pixel columns, and a plurality of R, G, B pixels (P) or R, G, B, W pixels (P) may be driven according to a dual rated drive (DRD) method.

[0035] A pair of pixels (P) sharing a data line respectively may include a pixel circuit and an organic light emitting diode, the pixel circuit is connected to a data line (DLm) and a power line (PLn) shared by a plurality of gate lines (GLn), and the organic light emitting diode is connected between the pixel circuit and a low potential power signal (GND) power line. Hereinafter, the connection between the gate lines (GL1 to GLn) and the data lines (DL1 to DLm) of the display panel 10 and each pixel P will be described with reference to the accompanying drawings.

[0036] The timing controller 500 may arrange and output the image data (RGB) so that all pixels (P) are driven and emit light according to the DRD method while alternately driving the adjacent pixels of the display panel 10 at least in one horizontal period. The timing controller 500 may arrange and output the image data (RGB) so that multiple pairs of adjacent pixels (P) sharing a data line continuously emit light at least based on the unit of one horizontal period. Hereinafter, m, n, and i are natural numbers other than 0 and may be the same or different.

[0037] In addition, the timing controller 500 can generate a gate control signal (GVS) and a data control signal (DVS) using the synchronization signals (DCLK, DE, Hsync and Vsync), and can transmit the gate control signal (GVS) and the data control signal (DVS) to the gate driver 200 and the data driver 300, respectively, thereby driving the gate lines (GL1 to GLn) and the data lines (DL1 to DLm) of the display panel 10 according to the DRD method.

[0038] The data driver 300 may receive image data arranged by the timing controller 500 at least based on a single horizontal line section. The image data arranged by the timing controller 500 is data arranged so that pixels (P) adjacent to each other are continuously driven and emit light in at least 1 horizontal period while all pixels (P) are driven according to the DRD method.

[0039] Therefore, the data driver 300 uses a data control signal (DVS) (e.g., a source start pulse, a source shift clock, a source output enable signal, etc.) to convert the image data arranged in each 1 / 2 horizontal period based on each 1 / 2 horizontal line portion into an analog data voltage so that pixels adjacent to each other are alternately driven within each horizontal period.

[0040] Specifically, the data driver 300 can sample the image data input according to the source shift clock based on each 1 / 2 horizontal line section, and can convert the image data into a data voltage. In addition, in each 1 / 2 horizontal period in which a gate turn-on signal is provided to each gate line (GL1 to GLn), the data driver 300 can respond to the source output enable signal, and can provide the data voltage of each 1 / 2 horizontal line section to each output channel (CH1 to CHn). As described above, the data driver 300 can generate a data voltage so that pixels adjacent to each other sharing a data line continue to emit light during at least 1 horizontal period, and can continuously provide the data voltage to the output channel (CH1 to CHn) so that the data voltage is synchronized with the output timing of the gate turn-on signal.

[0041] The data switch 100 may be provided with a plurality of multiplexers or a plurality of multiplexer circuits composed of a plurality of switching elements. The data switch 100 may electrically connect the 2i-1th and 2i-th pixels to the data voltage output channels (CH1 to CHn) so that the 2i-1th and 2i-th pixels are alternately driven according to the first and second selection signals (Dmux1 and Dmux2) input by the timing controller 500.

[0042] That is, the data switch 100 may respond to the first selection signal (Dmux1) and may electrically connect the 2i-1th pixel to the corresponding data voltage output channel (CH1 to CHn) during a 1 / 2 or 1 horizontal period. In addition, the data switch 100 may respond to the second selection signal (Dmux2) and may electrically connect the 2ith pixel to the corresponding data voltage output channel (CH1 to CHn) during a subsequent 1 / 2 or 1 horizontal period.

[0043] The gate driver 200 may output a gate-on signal to each gate line (GL1 to GLn) in an order determined according to the gate control signal (GVS). Specifically, the gate driver 200 may be provided with a built-in circuit, such as at least one of a level shifter, a shift register, a delay circuit, and a trigger, etc., to continuously generate a gate-on signal (e.g., a scan pulse) according to a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal, etc. included in the gate control signal (GVS). In this case, the gate driver 200 may continuously generate a gate-on signal according to the GSC shift GSP. In addition, the gate driver 200 may provide the continuously generated gate-on signal to each gate line (GL1 to GLn) based on the connection structure of the gate lines (GL1 to GLn) of the display panel 10.

[0044] As an example, the gate driver 200 may continuously generate a first gate turn-on signal according to the gate control signal (GVS), and may continuously provide the first gate turn-on signal to the pixels of the odd columns based on the connection structure of the gate lines. In addition, the gate driver 200 may continuously generate a second gate turn-on signal according to the gate control signal (GVS), and may continuously provide the second gate turn-on signal to the pixels of the even columns based on the connection structure of the gate lines.

[0045] In addition, the gate driver 200 may continuously generate a plurality of light emitting control signals in response to the gate control signal (GVS), and may continuously provide each light emitting control signal to each light emitting control line.

[0046] Figure 2 It is shown Figure 1 Diagram of the data switcher and pixel arrangement.

[0047] for Figure 2 The data switch 100 in the embodiment pairs pixels (P) adjacent to each other in the direction of the gate line (GL) and sets them to share a single data line. Therefore, the data switch 100 performs a switching operation so that the data voltage output through the data voltage output channels (CH1 to CHn) is alternately transmitted to odd and even pixels based on the arrangement of the pixels (P).

[0048] Specifically, the data switcher 100 can electrically connect the 2i-1th and 2ith pixels to each data voltage output channel (CH1 to CHn) so that the 2i-1th and 2ith pixels are alternately driven according to the first and second selection signals (Dmux1 and Dmux2) input by the timing controller 500.

[0049] To this end, the data switcher 100 may include a plurality of first conversion switches (TS1) and a plurality of second conversion switches (TS2), wherein the plurality of first conversion switches respond to a first selection signal (Dmux1) input during a 1 / 2 or 1 horizontal period and connect the data voltage output channels (CH1 to CHn) to the 2i-1th (odd) pixels, respectively, and the plurality of second conversion switches respond to a second selection signal (Dmux2) input during a 1 / 2 or 1 horizontal period and connect the data voltage output channels (CH1 to CHn) to the 2ith (even) pixels, respectively.

[0050] Figure 3 It is shown Figure 1 Block diagram of pixel arrangement in a data line sharing structure.

[0051] like Figure 3 As shown, for the display panel 10, all data lines (DL1 to DLm) may be arranged to be reduced to 1 / 2 of all pixel columns, and the number of all gate lines (GL1 to GLn) may be increased to 2 or 4 times relative to all pixel rows.

[0052] Pixels P adjacent to each other in the direction of the gate line GL are paired and share a single data line. Specifically, the 2m-1th data line (DL1, DL3, ... DL2m-1) as an odd data line can be arranged between the 4m-3th and 4m-2th pixel columns, and the pixels (red (R) and green (G)) arranged in the 4m-3th and 4m-2th pixel columns can share the 2m-1th data line.

[0053] The 2mth data line (DL2, DL4, ... DL2m) as an even data line can be set between the 4m-1th and 4mth pixel columns, and the pixels (blue (B) and white (W)) set in the 4m-1th and 4mth pixel columns can share the 2mth data line.

[0054] Each pixel (red (R) and blue (B)) arranged in an odd column can be arranged in a pixel area defined by two intersecting gate lines (for example, the 4n-3rd and 4n-2nd gate lines) and a single data line (DL). Each pixel (red (R) and blue (B)) arranged in an odd column can be enabled by the first gate turn-on signal (Scan1 (2n-1), Scan1 (2n)) continuously input through the 4n-3rd and 4n-2nd gate lines, and can display an image according to the light emitting control signal.

[0055] Each pixel (green (G) and white (W)) arranged in an even-numbered column may be arranged in a pixel region defined by two intersecting gate lines (e.g., the 4n-1th and 4nth gate lines) and a single data line (DL). Each pixel (green (G) and white (W)) arranged in an even-numbered column may be enabled by a second gate turn-on signal (Scan2 (2n-1), Scan2 (2n)) continuously input through the 4n-1th and 4nth gate lines, and may display an image according to a light emission control signal.

[0056] Figure 4 It specifically shows Figure 3 The circuit diagram of any pixel in Figure 5 It shows the input to Figure 1 Timing diagram of the data switcher and pixel control signals.

[0057] refer to Figure 4 , each pixel (P) (for example, a green pixel (G) arranged in the first row and the second column) may include a pixel circuit and an organic light emitting diode OLED, the pixel circuit being connected to each of a gate line, an initialization voltage (Vini) input line, a first data line DL1, a light emitting control line EL, etc., the organic light emitting diode OLED being connected between the pixel circuit and a low potential power signal GND power line and being equivalently represented by a diode.

[0058] The pixel circuit may have a source follower type compensation circuit structure. The pixel circuit may include first and second switch elements (ST1 and ST2), a storage capacitor (Cst), a drive switch element (DT), and a light emitting control element (ET). The pixel circuit of the present invention is not limited to the source follower type compensation circuit structure, and the structure of the internal compensation circuit may have different designs.

[0059] refer to Figure 4 and Figure 5 The first switching element (ST1) of the pixel circuit can be switched (turned on) by the gate turn-on signal (Scan2(1)) from the gate line, and can transmit the data voltage input from the corresponding first data line (DL1) to the first node to which the driving switching element (DT) is connected.

[0060] In this case, the second switching element (ST2) can be switched (turned on) by a gate turn-on signal (Scan2(2)) from the gate line, and an initialization voltage (Vini) input from the data driver 300 or a power source, etc. can be provided to a second node to which the driving switching element (DT) and the light emitting control element (ET) are connected. The second switching element (ST2) can receive and use other gate shift clocks or at least one clock pulse, etc. as a gate turn-on signal.

[0061] For the driving switch element (DT), the gate terminal may be connected to a first node connected to the first switching element (ST1), the drain terminal may be connected to a second node connected to the light emitting control element (ET), and the source terminal (or driving voltage input terminal) may be connected to a high potential voltage source (Vdd). Therefore, the driving switch element (DT) may store a threshold voltage (Vth) in the storage capacitor (Cst) by means of a data voltage input through the first switching element (ST1) and an initialization voltage (Vini) input through the second switching element (ST2). In addition, the driving switch element (DT) may provide a driving voltage of an organic light emitting diode to a second node connected to the light emitting control element (ET), the driving voltage of the organic light emitting diode corresponding to the image data voltage compensated for the threshold voltage (Vth).

[0062] During a period in which a light emitting control signal (EM1) is input through the light emitting control line (EL), the light emitting control element (ET) can provide a driving voltage of the organic light emitting diode input to the second node to the organic light emitting diode (OLED), and can control the organic light emitting diode (OLED) so that the organic light emitting diode (OLED) emits light.

[0063] refer to Figure 5 , the first selection signal (Dmux1) generated by the timing controller 500 can be provided to the data switch 100 as a low logic voltage level (Dmux1(on)) as a turn-on level within the first driving period (Rh) of 1 horizontal period (1H), thereby providing the data voltage (Data(V)) to the pixels arranged in the 2n-1th column (odd column) along the gate lines (GL1 to GLn).

[0064] Next, the second selection signal (Dmux2) generated by the timing controller 500 can be provided to the data switch 100 as a low logic voltage level (Dmux2 (on), period F) as a turn-on level within the second driving period (Gh) of 1 horizontal period (1H), thereby providing the data voltage (Data (V)) to the pixels arranged in the 2nth column (even column) along the direction of the gate lines (GL1 to GLn). In 1 horizontal period (1H), the second driving period (Gh) for driving the pixels arranged in the 2nth column (even column) can be longer than the first driving period (Rh) for driving the pixels arranged in the 2n-1th column (odd column) (Gh>Rh).

[0065] That is, in 1 horizontal period (1H), the first driving period (Rh) for driving the pixels set in the 2n-1th column (odd column) can be shorter than the second driving period (Gh) for driving the pixels set in the 2nth column (even column) (Rh<Gh).

[0066] In low-speed driving (e.g., 60 Hz driving), the charging rate has less influence on the pixels arranged in the 2n-1th column (odd column) and the 2nth column (even column) than on the entire charging period. Therefore, there is no problem with the image displayed on the pixels arranged in the 2nth column (even column).

[0067] However, when driving at high speed (e.g., 90 Hz to 120 Hz or higher), the horizontal period (1H) is shortened or reduced. Therefore, the charging rate is reduced as a whole. In this case, the charging rate of the pixels in the 2nth column (even column) is affected by the driving period and charging rate of the pixels in the 2n-1th column (odd column).

[0068] To prevent this from happening, in the present disclosure, a second drive period (Gh) for driving pixels disposed in the 2nth column (even column) during one horizontal period (1H) can be set or changed so that the second drive period (Gh) is longer than the first drive period (Rh) for driving pixels disposed in the 2n-1th column (odd column).

[0069] The first selection signal (Dmux1) generated for switching to provide the data voltage to the pixels set in the 2n-1th column (odd column) can be delayed by a predetermined period (period A) relative to the source output enable (SOE) signal generated by the timing generator 500 and can be generated as a turn-on signal.

[0070] In addition, the second selection signal (Dmux2) generated for switching to provide the data voltage to the pixels set in the 2nth column (even column) and the first selection signal (Dmux1) generated for switching to provide the data voltage to the pixels set in the 2n-1th column (odd column) can be generated during the same time period, or the second selection signal (Dmux2) can be generated during a time period that is 1% to 20% longer than the time period of the first selection signal (Dmux1).

[0071] That is, the on period of the second selection signal (Dmux2) may be the same as the on period of the first selection signal (Dmux1), or the second selection signal (Dmux2) may be generated as an on signal with any period 1% to 20% longer than the first selection signal (Dmux1).

[0072] In 1 horizontal period (1H), when the second driving period (Gh) for driving the pixels set in the 2nth column (even column) is longer than the first driving period (Rh) for driving the pixels set in the 2n-1th column (odd column), the charging rate of the pixels set in the 2nth column (even column) can be improved.

[0073] The period during which the second gate turn-on signal (Scan2(1) and Scan2(2)) is input as the turn-on signal can be set to be longer than the period (enable period) during which the second selection signal (Dmux2) is input as the turn-on signal, and even after the second selection signal (Dmux2) is input as the turn-on signal, the second gate turn-on signal (Scan2(1) and Scan2(2)) can be input as the turn-on signal, thereby inputting the turn-on signal to the pixel in the 2nth column (even column). That is, even after the period C during which the second selection signal (Dmux2) is input as the cut-off signal, the second gate turn-on signal (Scan2(1) and Scan2(2)) can be input as the turn-on signal to the pixel (P) in the 2nth column (even column). In this case, the pixel set in the 2nth column (even column) can emit light for a longer period, and the brightness characteristics of the pixel can be improved.

[0074] A period during which the first selection signal (Dmux1) is generated to supply the data voltage to the pixels (P) of the pixel row in the subsequent column may be delayed by a predetermined period (period K; for example, 1.0 to 1.5 μs) relative to a period during which the second gate turn-on signals (Scan2(1) and Scan2(2)) supplied to the pixels arranged in the 2nth column (even column) (i.e., the previous column) are turned on, and then the first selection signal (Dmux1) may be supplied to the data switcher 100. As described above, a predetermined delay (e.g., period K) is inserted between the driving period of the pixels in the 2nth column (even column) (i.e., the previous column) and the driving period of the pixels (P) of the pixel row in the subsequent column, thereby minimizing a change in the charging rate (brightness and saturation) in the subsequent column based on a change in the charging period in the previous column.

[0075] The organic light emitting diode display device and the driving method thereof according to the embodiments of the present disclosure can be driven at a high driving frequency, and even in a simplified structure of a data driving circuit that switches and alternately outputs image signals and alternately drives pixels adjacent to each other, image quality degradation and image distortion can be prevented.

[0076] The present disclosure has been described with reference to the embodiments shown in the accompanying drawings. However, the present disclosure is not limited to the embodiments and drawings set forth herein. In addition, a person of ordinary skill in the art may make various modifications within the scope of the technical spirit of the present disclosure. In addition, although not explicitly described during the description of the embodiments of the present disclosure, the effects and predictable effects according to the configuration of the present disclosure should be included within the scope of the present disclosure.

Claims

1. An organic light emitting diode display device, comprising: a display panel in which pixels adjacent to each other in a direction of gate lines are paired and arranged to share a single data line in a pixel area defined by a plurality of gate lines and a plurality of data lines; A gate driver configured to continuously provide a gate-on signal to a plurality of gate lines; a data driver configured to output a data voltage to a data voltage output channel based on a pixel arrangement of the display panel; a data switch configured to alternately select pixels and electrically connect the pixels to a data voltage output channel of a data driver, thereby alternately supplying data voltages to pixels adjacent to each other along a direction of the gate lines; and a timing controller configured to generate first and second selection signals and gate and data control signals for selecting each pixel, respectively, and provide the generated signals to the data switch and the gate and data drivers, wherein the first selection signal is provided to the data switch in a first driving period of one horizontal cycle, thereby providing a data voltage to pixels arranged in the 2n-1th column (odd number column) along the direction of the gate line, supplying the second selection signal to the data switcher in a second driving period of one horizontal cycle, thereby supplying the data voltage to the pixels arranged in the 2nth column (even-numbered column) along the direction of the gate line, The first driving period is a period in which the data driver outputs a data voltage for driving pixels arranged in a 2n-1th column, The second driving period is a period during which the data driver outputs a data voltage for driving pixels arranged in a 2n-th column, In one horizontal period, the second driving period is longer than the first driving period, The first selection signal and the second selection signal are respectively generated to be delayed by a predetermined period with respect to the source output enable signal generated by the timing controller, The second selection signal is generated during a period that is one of 1% to 20% longer than the first selection signal.

2. The organic light emitting diode display device according to claim 1, wherein: The timing controller is configured to arrange image data and provide the image data to the data driver so that all pixels are driven and emit light according to a dual rated driving (DRD) method while alternately driving pixels adjacent to each other in at least 1 horizontal period.

3. The organic light emitting diode display device according to claim 2, wherein: The gate driver is configured to continuously generate a first gate turn-on signal according to the gate control signal and continuously provide the first gate turn-on signal to the pixels arranged in the 2n-1th column, The gate driver is configured to continuously generate a second gate turn-on signal according to the gate control signal and continuously provide the second gate turn-on signal to the pixels arranged in the 2nth column, and The gate driver is configured to sequentially generate a plurality of light emitting control signals in response to the gate control signal, and sequentially provide each light emitting control signal to each pixel through each light emitting control line.

4. The organic light emitting diode display device according to claim 3, wherein: The period during which the second gate turn-on signal is output is longer than the period (enable period) during which the second selection signal is output, and the second gate turn-on signal is output even after the second selection signal is output.

5. A method for driving a display panel, the method pairing pixels adjacent to each other along a gate line direction and arranging them to share a single data line in a pixel area defined by a plurality of gate lines and a plurality of data lines, the method comprising: Continuously providing a gate-on signal to a plurality of gate lines; outputting a data voltage to a data voltage output channel based on a pixel arrangement of the display panel, thereby alternately supplying the data voltage to pixels adjacent to each other along a direction of the gate line; and generating a first selection signal and a second selection signal so that the data switch selects each pixel, and respectively generates a gate control signal and a data control signal, and provides the generated signals to the gate driver and the data driver, The first selection signal is provided to the data switcher in the first driving period of one horizontal cycle, and the pixels arranged in the 2n-1th column (odd-numbered column) along the gate line are electrically connected to the data voltage output channel of the data driver, so that the data voltage is provided to the pixels arranged in the 2n-1th column. The second selection signal is provided to the data switcher in a second driving period of one horizontal cycle, and the pixels arranged in the 2nth column (even-numbered column) along the gate line are electrically connected to the data voltage output channel of the data driver, thereby providing the data voltage to the pixels arranged in the 2nth column. The first driving period is a period in which the data driver outputs a data voltage for driving pixels arranged in a 2n-1th column, The second driving period is a period during which the data driver outputs a data voltage for driving pixels arranged in a 2n-th column, In one horizontal period, the second driving period is longer than the first driving period, The first selection signal and the second selection signal are respectively generated to be delayed by a predetermined period with respect to the source output enable signal generated by the timing controller, The second selection signal is generated during a period that is one of 1% to 20% longer than the first selection signal.

6. The method according to claim 5, wherein: The step of generating the first selection signal and the second selection signal includes arranging image data and providing the image data to a data driver so that all pixels are driven and emit light according to a dual rated drive (DRD) method while alternately driving pixels adjacent to each other in at least 1 horizontal period.

7. The method according to claim 6, wherein: The step of continuously providing a gate turn-on signal to a plurality of gate lines comprises: continuously generating a first gate turn-on signal according to a gate control signal and continuously providing the first gate turn-on signal to pixels arranged in a 2n-1th column, continuously generating a second gate turn-on signal according to the gate control signal and continuously providing the second gate turn-on signal to the pixels arranged in the 2nth column, and A plurality of light emitting control signals are sequentially generated in response to the gate control signal, and each light emitting control signal is sequentially provided to each pixel through each light emitting control line.

8. The method according to claim 7, wherein: The period during which the second gate turn-on signal is output is longer than the period (enable period) during which the second selection signal is output, and the second gate turn-on signal is output even after the second selection signal is output.

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