Semiconductor device package and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer, and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends in a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and is spaced apart from the first conductive layer.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package having a conductive layer and a method of manufacturing the same. Background Art

[0002] A semiconductor device package may include one or more semiconductor devices mounted on a carrier and encapsulated by an encapsulation material. To improve the performance of a semiconductor device package, several semiconductor devices may be stacked within the package, which can minimize the device footprint on the carrier and simplify future miniaturization. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes a first semiconductor device, a first conductive layer, and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends in a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and is spaced apart from the first conductive layer.

[0004] In one or more embodiments, a semiconductor device package includes a first semiconductor device, a second semiconductor device, and a first conductive layer. The first semiconductor device has a first surface. The second semiconductor device is stacked on the first semiconductor device. The second semiconductor device has a first surface and a second surface, the first surface being substantially perpendicular to the first surface of the first semiconductor device, and the second surface being substantially parallel to the first surface of the first semiconductor device. The first conductive layer is disposed in direct contact with the first surface of the first semiconductor device, the first surface of the second semiconductor device, and the second surface of the second semiconductor device.

[0005] In one or more embodiments, a method for manufacturing a semiconductor device package includes providing a first semiconductor device. The first semiconductor device has a first conductive pad. The method further includes stacking a second semiconductor device on the first semiconductor device. The method further includes forming an insulating material on the first semiconductor device and the second semiconductor device. The method further includes partially removing the insulating material to form a support structure at a corner. The corner is defined by a portion of a surface of the first semiconductor device and a portion of a surface of the second semiconductor device. The method further includes forming a first conductive layer and a second conductive layer, both of which directly contact the first conductive pad and are spaced apart from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When reading the following detailed description, various aspects of the present disclosure can be easily understood based on the following detailed description. It should be noted that various features may not necessarily be drawn to scale. For the sake of clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 2 A perspective view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0009] Figure 3A An enlarged top view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0010] Figure 3B An enlarged top view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0011] Figure 3C An enlarged top view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0012] Figure 4A An enlarged cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0013] Figure 4B An enlarged cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0014] Figure 4C An enlarged cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0015] Figure 5 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0016] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D 、 Figure 6E 、 Figure 6F 、 Figure 6G 、 Figure 6H 、 Figure 6I 、 Figure 6J 、 Figure 6K and Figure 6L A method of manufacturing a semiconductor device package according to some embodiments of the present disclosure is presented.

[0017] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D and Figure 7E A method of manufacturing a semiconductor device package according to some embodiments of the present disclosure is presented.

[0018] Figure 8 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0019] Figure 9 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0020] Figure 10 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0021] Throughout the drawings and detailed description, common reference numerals are used to designate the same or similar elements. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be restrictive. In the present disclosure, reference to forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations being discussed.

[0023] The following describes embodiments of the present disclosure in detail. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0024] Figure 1 A cross-sectional view of a semiconductor device package 100 according to some embodiments of the present disclosure is shown. Semiconductor device package 100 may include semiconductor devices 110 , 120 , 130 , conductive layer 210 , conductive layer 220 , support structure 160 , support structure 170 , and encapsulation layer 180 .

[0025] The semiconductor device 110 may have a surface 110a (which may also be referred to as an "upper surface"). The semiconductor device 110 may have a conductive pad 111. The semiconductor device 110 may be attached to the carrier 101 via an adhesive layer 191. The carrier 101 may include, for example, but not limited to, a molding compound, bismaleimide triazine (BT), polyimide (PI), polybenzoxazole (PBO), a solder resist, an Ajinomoto build-up film (ABF), polypropylene (PP), an epoxy resin-based material, or a combination of two or more thereof. The carrier 101 may include an interconnect structure such as a redistribution layer (RDL) or a grounding element. The carrier 101 may include one or more conductive pads that are close to, adjacent to, or embedded in the surface of the carrier 101 and exposed at the surface. The carrier 101 may include a solder resist (or a solder resist layer) on a surface of the carrier 101 to fully expose a conductive pad for electrical connection or to expose at least a portion thereof.

[0026] The semiconductor device 120 may be stacked on the semiconductor device 110. The semiconductor device 120 may be attached to the semiconductor device 110 via an adhesive layer 192. The semiconductor device 120 may have a surface 120s (which may also be referred to as a "side") that is substantially perpendicular to the surface 110a of the semiconductor device 110. The semiconductor device 120 may have a surface 120a (which may also be referred to as an "upper surface") that is substantially parallel to the surface 110a of the semiconductor device 110. The semiconductor device 120 may have a conductive pad 121.

[0027] The semiconductor device 130 may be stacked on the semiconductor device 120. The semiconductor device 130 may be attached to the semiconductor device 120 via an adhesive layer 193. The semiconductor device 130 may have a surface 130a (which may also be referred to as an "upper surface") and a surface 130s (which may also be referred to as a "side") substantially perpendicular to the surface 130a. In some embodiments, the surface 130s of the semiconductor device 130 may be substantially perpendicular to the surface 120a of the semiconductor device 120. In some embodiments, the surface 130a of the semiconductor device 130 may be substantially parallel to the surface 120a of the semiconductor device 120. The semiconductor device 130 may have a conductive pad 131.

[0028] Each of semiconductor devices 110, 120, and 130 may include a chip or die comprising a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures therein. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or a combination thereof. In some embodiments, the height of semiconductor devices 110, 120, and / or 130 may be in a range of approximately 100 μm to approximately 300 μm.

[0029] Conductive layer 210 can electrically connect semiconductor device 110 to semiconductor device 120. Conductive layer 210 can be positioned in direct contact with conductive pad 111 of semiconductor device 110. Conductive layer 210 can extend in a direction substantially parallel to surface 111a (which can also be referred to as an "upper surface") of conductive pad 111. Conductive layer 210 can extend onto and directly contact a portion of surface 111a of conductive pad 111. Conductive layer 210 can be positioned in direct contact with conductive pad 121 of semiconductor device 120. Conductive layer 210 can extend in a direction substantially parallel to surface 121a (which can also be referred to as an "upper surface") of conductive pad 121. Conductive layer 210 can extend onto and directly contact a portion of surface 121a of conductive pad 121. Conductive layer 210 can be positioned in direct contact with surface 110a of semiconductor device 110, surface 120s of semiconductor device 120, and surface 120a of semiconductor device 120. In some embodiments, the conductive layer 210 may have an inclined surface. In some embodiments, the conductive layer 210 may have a curved surface. In some embodiments, the thickness of the conductive layer 210 may be in a range of about 7 μm to about 15 μm.

[0030] Conductive layer 220 may electrically connect semiconductor device 120 to semiconductor device 130. Conductive layer 220 may be spaced apart from conductive layer 210. In some embodiments, conductive layer 220 may be spaced apart from conductive layer 210 by a distance D1 of at least 20 μm, at least 30 μm, at least 40 μm, or at least 50 μm. Conductive layer 220 may be positioned in direct contact with conductive pad 121 of semiconductor device 120. Conductive layer 220 may extend in a direction substantially parallel to surface 121 a of conductive pad 121. Conductive layer 220 may extend onto and be in direct contact with a portion of surface 121 a of conductive pad 121. Conductive layer 220 may be positioned in direct contact with surface 120 a of semiconductor device 120. Conductive layer 220 may be positioned in direct contact with conductive pad 131 of semiconductor device 130. Conductive layer 220 may extend in a direction substantially parallel to surface 131 a (which may also be referred to as an “upper surface”) of conductive pad 131. Conductive layer 220 may extend onto and directly contact a portion of surface 131a of conductive liner 131. Conductive layer 220 may be positioned in direct contact with surface 130s of semiconductor device 130. Conductive layer 220 may be in direct contact with surface 130a of semiconductor device 130. In some embodiments, conductive layer 220 may have an inclined surface. In some embodiments, conductive layer 220 may have a curved surface. In some embodiments, the thickness of conductive layer 220 may be in a range of approximately 7 μm to approximately 15 μm.

[0031] In some embodiments, the conductive layer 210 and / or the conductive layer 220 may include, for example but not limited to, aluminum (Al), gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), one or more other metals or alloys, or a combination of two or more thereof.

[0032] The stacked semiconductor devices are typically electrically connected by wire bonding or by conductive pillars. An encapsulation layer is then formed to cover the semiconductor devices and the wires and / or pillars. The wires and / or pillars have a relatively large length. Relatively long wires and / or pillars may be damaged during the encapsulation operation (for example, the wires and / or pillars may break due to relatively strong molding flow), which may greatly increase the difficulty and manufacturing cost of the reworking process of the wires and / or pillars. On the contrary, by designing the conductive layers 210 and 220 according to some embodiments of the present disclosure, the length of each conductive layer in the conductive layers 210 and 220 can be relatively short. Therefore, damage to the conductive layer 210 and / or the conductive layer 220 caused by relatively strong molding flow can be avoided. Therefore, the difficulty and manufacturing cost of the reworking process of the conductive layer 210 and / or the conductive layer 220 can be significantly reduced, and the yield and reliability of the semiconductor device package 100 can be improved.

[0033] In addition, during the manufacturing process of the semiconductor device package, defects may be discovered in the semiconductor device, and anomalies may occur during the formation process of the conductive layer, which may increase the difficulty and manufacturing cost of the reworking process of the semiconductor device package. By designing the conductive layers 210 and 220 according to some embodiments of the present disclosure, the lengths of the conductive layers 210 and 220 can be relatively short, and these conductive layers can electrically connect the semiconductor device 120 to the semiconductor devices 110 and 130, respectively. Therefore, the semiconductor devices 110, 120, and 130 can be electrically connected via a conductive structure comprising separate, relatively short conductive segments (e.g., conductive layers 210 and 220), which can significantly reduce the possibility of damage to the entire conductive structure. Therefore, when a portion of these conductive segments (e.g., conductive layer 210 or conductive layer 220) is damaged, only fewer components (e.g., fewer parts of the semiconductor device) need to be reworked. Therefore, the difficulty and manufacturing cost of the reworking process of the semiconductor device package 100 can be significantly reduced, and the manufacturing yield of the semiconductor device package 100 can be significantly improved.

[0034] Furthermore, by designing the conductive layers 210 and 220 according to some embodiments of the present disclosure, different semiconductor devices (e.g., semiconductor devices 110, 120, and 130) can be electrically connected to different signal sources through different conductive layers, which can provide greater design flexibility and more device applications. Furthermore, the relatively short conductive layers 210 and 220 can reduce unwanted electrical interference (e.g., inductance effects when the package operates at higher frequencies), and thus can provide improved electrical performance while occupying a relatively small vertical space.

[0035] The support structure 160 may be disposed on the semiconductor device 110. A portion 110a1 of the surface 110a of the semiconductor device 110 and a portion 120s1 of the surface 120s of the semiconductor device 120 may define a corner C1. The support structure 160 may be disposed in the corner C1.

[0036] Support structure 160 may be positioned in direct contact with surface 120s of semiconductor device 120. Support structure 160 may be in direct contact with portion 110a1 of surface 110a of semiconductor device 110. Support structure 160 may be in direct contact with portion 120s1 of surface 120s of semiconductor device 120. Conductive layer 210 may be positioned in direct contact with support structure 160. Conductive layer 210 may be in direct contact with portion 110a1 of surface 110a of semiconductor device 110. Conductive layer 210 may be in direct contact with portion 120s2 of surface 120s of semiconductor device 120. In some embodiments, the interface between support structure 160 and semiconductor device 120 and the interface between conductive layer 210 and semiconductor device 120 may be continuous. In some embodiments, support structure 160 may have an inclined concave surface. Conductive layer 210 may be in direct contact with the inclined concave surface of support structure 160. In some embodiments, the thickness of the conductive layer 210 at the corner C1 may be in a range of about 10 μm to about 13 μm.

[0037] The support structure 170 may be disposed on the semiconductor device 120. A portion 120a1 of the surface 120a of the semiconductor device 120 and a portion 130s1 of the surface 130s of the semiconductor device 130 may define a corner C2. The support structure 170 may be disposed in the corner C2.

[0038] Support structure 170 may be positioned in direct contact with surface 130s of semiconductor device 130. Support structure 170 may be in direct contact with portion 120a1 of surface 120a of semiconductor device 120. Support structure 170 may be in direct contact with portion 130s1 of surface 130s of semiconductor device 130. Conductive layer 220 may be positioned in direct contact with support structure 170. Conductive layer 220 may be in direct contact with portion 120a2 of surface 120a of semiconductor device 120. Conductive layer 220 may be in direct contact with portion 130s2 of surface 130s of semiconductor device 130. In some embodiments, the interface between support structure 170 and semiconductor device 130 and the interface between conductive layer 220 and semiconductor device 130 may be continuous. In some embodiments, support structure 170 may have an inclined concave surface. Conductive layer 220 may be in direct contact with the inclined concave surface of support structure 170. In some embodiments, the thickness of the conductive layer 220 at the corner C2 may be in a range of about 10 μm to about 13 μm.

[0039] In some embodiments, support structure 160 and / or support structure 170 may include, for example but not limited to, ABF, polyimide (PI), epoxy-based materials, or a combination of two or more thereof.

[0040] When a conductive layer with a relatively small thickness (e.g., equal to or less than 15 μm) is formed in a corner defined by two surfaces that are substantially perpendicular to each other, the portion of the conductive layer in the corner may be easily cracked or broken due to the sharp angle defined by the two surfaces of the corner. According to some embodiments of the present disclosure, a conductive layer (e.g., conductive layer 210 and / or conductive layer 220) can be formed on a support structure (e.g., support structure 160 and / or support structure 170) disposed in a corner (e.g., corner C1 and / or corner C2), so that the conductive layer can be raised and supported by the support structure at the corner, and the angle of the conductive layer at the corner can be smoothed. Therefore, the problem of cracking or breaking of the conductive layer formed at a corner with a sharp angle can be avoided, and the reliability of the conductive layer can be improved.

[0041] Encapsulation layer 180 may be disposed on semiconductor device 110, semiconductor device 120, semiconductor device 130, conductive layer 210, and conductive layer 220. Encapsulation layer 180 may be in direct contact with conductive pad 111 of semiconductor device 110. Encapsulation layer 180 may be in direct contact with conductive pad 121 of semiconductor device 120. Encapsulation layer 180 may be in direct contact with conductive pad 131 of semiconductor device 130. In some embodiments, encapsulation layer 180 may include, for example, but not limited to, epoxy resin with filler, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material in which silicone is dispersed, or a combination thereof.

[0042] According to Figure 1 In some embodiments of the present disclosure, semiconductor device package 100 may further include semiconductor devices 110' and 120', support structures 160' and 170', and conductive layers 210' and 220'. Semiconductor device 110' may have a conductive pad 111'. Semiconductor device 120' may have a conductive pad 121'. Semiconductor device 130 may further have a conductive pad 131'. Semiconductor device 110' may be attached to carrier 101 via adhesive layer 191'. Semiconductor device 120' may be attached to semiconductor device 110' via adhesive layer 192'. Semiconductor device 120' may be attached to semiconductor device 130 via adhesive layer 193. Semiconductor device 130 may be stacked on semiconductor devices 120 and 120'. Conductive layer 220' may be spaced apart from conductive layer 210' above semiconductor device 120'. Conductive layer 210' and conductive layer 220' may be in direct contact with conductive pad 121' of semiconductor device 120. Conductive layer 220' may be in direct contact with conductive pad 131' of semiconductor device 130. Conductive layer 210' may be in direct contact with conductive pad 111' of semiconductor device 110. Figure 1 In some of the illustrated embodiments, the structure of the semiconductor device package 100 may be symmetrical about the semiconductor device 130 .

[0043] Figure 2 A perspective view of a portion of a semiconductor device package 100 according to some embodiments of the present disclosure is shown. The figure has been simplified to provide a better understanding of various aspects of the present disclosure.

[0044] like Figure 2As shown, conductive layer 210 may extend onto and directly contact a portion of the upper surface (e.g., surface 120a) of semiconductor device 120. Conductive layer 210 may extend onto and directly contact a portion of the side surface (e.g., surface 120s) of semiconductor device 120. Conductive layer 210 may extend onto and directly contact a portion of the upper surface (e.g., surface 110a) of semiconductor device 110. Two opposing end portions of conductive layer 210 may extend onto and directly contact conductive pad 111 of semiconductor device 110 and conductive pad 121 of semiconductor device 120, respectively. In some embodiments, the conductive layer 210 can extend continuously onto and across the surface 121a of the conductive pad 121, the surface 120a of the semiconductor device 120, the surface 120s of the semiconductor device 120, the surface 110a of the semiconductor device 110, and the surface 111a of the conductive pad 111 to electrically connect the conductive pad 121 of the semiconductor device 120 to the conductive pad 111 of the semiconductor device 110.

[0045] like Figure 2 As shown, conductive layer 220 may extend onto and directly contact a portion of the upper surface (e.g., surface 130a) of semiconductor device 130. Conductive layer 220 may extend onto and directly contact a portion of the side surface (e.g., surface 130s) of semiconductor device 130. Conductive layer 220 may extend onto and directly contact a portion of the upper surface (e.g., surface 120a) of semiconductor device 120. Opposite end portions of conductive layer 220 may extend onto and directly contact conductive pad 121 of semiconductor device 120 and conductive pad 131 of semiconductor device 130, respectively. In some embodiments, conductive layer 220 may continuously extend onto and across surface 131a of conductive liner 131, surface 130a of semiconductor device 130, surface 130s of semiconductor device 130, surface 120a of semiconductor device 120, and surface 121a of conductive liner 121 to electrically connect conductive pad 131 of semiconductor device 130 to conductive pad 121 of semiconductor device 120. The conductive layer 210 may be spaced apart from the conductive layer 220 over the conductive liner 121 .

[0046] Figure 3AAn enlarged top view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown. Conductive layer 210 may cover portion 121A of conductive pad 121. Portion 121A of conductive pad 121 may be in direct contact with conductive layer 210. Conductive layer 220 may cover portion 121B of conductive pad 121. Portion 121B of conductive pad 121 may be in direct contact with conductive layer 220. Portion 121A of conductive pad 121 may be opposite portion 121B of conductive pad 121. Portion 121A of conductive pad 121 may be spaced apart from portion 121B of conductive pad 121. In some embodiments, width W2 of conductive pad 121 may be substantially greater than width W1 of conductive layer 210.

[0047] Figure 3B An enlarged top view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown. Figure 3B The structure in is similar to Figure 3A , except that in some embodiments, the width W3 of the conductive pad 121 may be smaller than the width W1 of the conductive layer 210 .

[0048] Figure 3C An enlarged top view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown. Figure 3C The structure in is similar to Figure 3A , except that in some embodiments, the width W4 of the conductive pad 121 may be substantially equal to the width W1 of the conductive layer 210 .

[0049] Figure 4A An enlarged cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown. Figure 4A The structure in is similar to Figure 1 1B , except that in some embodiments, the conductive pad 421 of the semiconductor device 120 may include a pad 421A and a pad 421B that are spaced apart from each other. The conductive layer 210 and the conductive layer 220 may be disposed in direct contact with the pad 421A and the pad 421B, respectively. The pad 421A may be electrically connected to the pad 421B via an internal interconnect structure (not shown) within the semiconductor device 120.

[0050] Figure 4B An enlarged cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown. Figure 4B The structure in is similar to Figure 11 , except that in some embodiments, the conductive pad 422 of the semiconductor device 120 may protrude from the surface 120a of the semiconductor device 120. The conductive pad 422 may have a surface 422a (which may also be referred to as an "upper surface") and a surface 422s1 (which may also be referred to as a "side") substantially perpendicular to the surface 422a. The conductive layer 210 may be in direct contact with the surface 422a and the surface 422s1 of the conductive pad 422 of the semiconductor device 120. The conductive pad 422 may have a surface 422s2 opposite to the surface 422s1. The conductive layer 220 may be in direct contact with the surface 422a and the surface 422s2 of the conductive pad 422.

[0051] Figure 4C An enlarged cross-sectional view of a portion of a semiconductor device package according to some embodiments of the present disclosure is shown. Figure 4C The structure in is similar to Figure 1 , except that in some embodiments, the conductive layer 410 may include sub-layers 411 , 412 , and 413 .

[0052] Sublayer 411 may be positioned in direct contact with conductive pad 121. Sublayer 412 may be positioned in direct contact with sublayer 411. Sublayer 413 may be positioned in direct contact with sublayer 412. In some embodiments, sublayer 411 and sublayer 412 may be seed layers, and sublayer 413 may be a conductive layer. Seed layer 411 may be positioned in direct contact with surface 110a of semiconductor device 110. Seed layer 411 may be positioned in direct contact with conductive pad 111 of semiconductor device 110. Seed layer 411 may be positioned in direct contact with conductive pad 121 of semiconductor device 120. Conductive layer 420 may include sublayers 421, 422, and 423. In some embodiments, sublayer 421 and sublayer 422 may be seed layers, and sublayer 423 may be a conductive layer. Seed layer 421 may be disposed in direct contact with conductive pads 121 and 131 of semiconductor device 120 and 130. In some embodiments, seed layer 421 may be formed of or include titanium (Ti), and seed layer 412 may be formed of or include copper (Cu).

[0053] Figure 5 A cross-sectional view of a semiconductor device package 200 according to some embodiments of the present disclosure is shown. The semiconductor device package 200 may include semiconductor devices 110, 110', 120, 120', and 130, conductive layers 210, 210', 220, and 220', support structures 150, 150', 160, 160', 170, and 170', an encapsulation layer 180, an interconnect structure 610, electrical contacts 620, and external connectors 630.

[0054] Interconnect structure 610 may be disposed on semiconductor devices 110, 110', 120, 120', and 130. Interconnect structure 610 may include a redistribution layer (RDL). Interconnect structure 610 may include conductive elements (e.g., pads, conductive lines, and / or vias) and a dielectric layer. A portion of the conductive element may be covered or encapsulated by the dielectric layer, while another portion 611 of the conductive element may be exposed from the dielectric layer to provide electrical connections for semiconductor devices 110, 110', 120, 120', and 130.

[0055] Electrical contacts 620 (e.g., solder balls) may be disposed between interconnect structure 610 and semiconductor devices 110, 110', 120, 120', and 130. Electrical contacts 620 may be in direct contact with exposed portions 611 of conductive elements of interconnect structure 610. Electrical contacts 620 may be in direct contact with conductive layer 220. Electrical contacts 620 may be in direct contact with conductive layer 220'. In some embodiments, electrical contacts 620 may include conductive bumps.

[0056] External connectors 630 (e.g., solder balls) may be disposed on a surface of the interconnect structure 610 facing away from the semiconductor devices 110, 110', 120, 120', and 130. The external connectors 630 may provide electrical connections between the semiconductor package devices 110, 110', 120, 120', and 130 and external components (e.g., external circuits or circuit boards). In some embodiments, the external connectors 630 may include controlled collapse chip connection (C4) bumps, ball grid arrays (BGAs), and / or land grid arrays (LGAs).

[0057] Figure 6A 、 6B , 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J, 6K, and 6L illustrate methods of manufacturing a semiconductor device package 100 according to some embodiments of the present disclosure. The various figures have been simplified to provide a better understanding of various aspects of the present disclosure.

[0058] refer to Figure 6A, a carrier 101 may be provided. A semiconductor device 110 having a conductive liner 111 may be disposed on the carrier 101. A semiconductor device 110′ having a conductive liner 111′ may be disposed on the carrier 101. The semiconductor devices 110 and 110′ may be attached to the carrier 101 via adhesive layers 191 and 191′, respectively. A semiconductor device 120 having a conductive liner 121 may be stacked on the semiconductor device 110. A semiconductor device 120′ having a conductive liner 121′ may be stacked on the semiconductor device 110′. The semiconductor device 120 may be attached to the semiconductor device 110 via an adhesive layer 192. The semiconductor device 120′ may be attached to the semiconductor device 110′ via an adhesive layer 192′. A semiconductor device 130 having conductive pads 131 and 131′ may be stacked on the semiconductor devices 120 and 120′. In some embodiments, the adhesive layers 191 , 191 ′, 192 , 192 ′, and / or 193 may include a die attach film (DAF).

[0059] refer to Figure 6B , an insulating material 510 may be formed on the semiconductor devices 110, 110', 120, 120', and 130. The insulating material 510 may cover the semiconductor devices 110, 110', 120, 120', and 130 and at least a portion of the surface 101a (which may also be referred to as the "upper surface") of the carrier 101. In some embodiments, the insulating material 510 may include PI, epoxy resin, or a combination thereof. In some embodiments, the insulating material 510 may be formed by a coating process such as a spin coating process.

[0060] refer to Figure 6C , the insulating material 510 may be partially removed. Multiple exposure processes E1, E2, and E3 may be performed on multiple portions of the insulating material 510. In some embodiments, each of the exposure processes E1, E2, and E3 may use a corresponding alignment mask. Each corresponding alignment mask may correspond to an edge portion (e.g., Figure 6D Each edge portion in edge portions 110E, 120E and 130E).

[0061] refer to Figure 6DAfter performing exposure processes E1, E2, and E3 on a portion of insulating material 510, a development process may be performed to remove the exposed portion of insulating material 510. The remaining unexposed portion of insulating material 510 may form support structures 150, 160, and 170. Partially removing insulating material 510 may expose edge portions 110E, 120E, and 130E of semiconductor devices 110, 110', 120, 120', and 130. Edge portion 110E of semiconductor devices 110 and 110' may be defined by exposure process E1. Edge portion 120E of semiconductor devices 120 and 120' may be defined by exposure process E2. Edge portion 130E of semiconductor device 130 may be defined by exposure process E3.

[0062] refer to Figure 6E A seed layer 520 may be formed on the support structures 150, 160, and 170 and the semiconductor devices 110, 110', 120, 120', and 130. In some embodiments, the seed layer 520 may include multiple layers, for example, a titanium (Ti) layer and a copper (Cu) layer formed on the titanium (Ti) layer. In some embodiments, the seed layer 520 may be formed by sputtering.

[0063] refer to Figure 6F , a photoresist material 530 may be formed on the seed layer 520 .

[0064] refer to Figure 6G , the photoresist material 530 may be partially removed. Multiple exposure processes E4, E5, and E6 may be performed on multiple portions of the photoresist material 530. In some embodiments, each of the exposure processes E4, E5, and E6 may use a corresponding alignment mask. Each corresponding alignment mask may correspond to the position of each conductive layer to be subsequently formed (e.g., conductive layers 210, 220, and 230).

[0065] refer to Figure 6H After performing exposure processes E4, E5, and E6 on a portion of the photoresist material 530, a development process may be performed to remove the exposed portion of the photoresist material 530 to form a patterned photoresist layer PR. The patterned photoresist layer PR has a plurality of openings to expose a plurality of predetermined regions R1, R2, and R3. Portions of the seed layer 520 located in the predetermined regions R1, R2, and R3 may be exposed from the patterned photoresist layer PR.

[0066] refer to Figure 6I , a conductive material layer 540 may be formed on the plurality of predetermined regions R1, R2, and R3. The conductive material layer 540 may be formed to directly contact the seed layer 520. In some embodiments, the conductive material layer 540 may be formed by an electroplating process.

[0067] refer to Figure 6J After forming the conductive material layer 540 on the plurality of predetermined regions R1, R2, and R3, the patterned photoresist layer PR may be removed. After forming the conductive material layer 540 on the plurality of predetermined regions R1, R2, and R3, the portion of the seed layer 520 located below the patterned photoresist layer PR may be removed. In some embodiments, the patterned photoresist layer PR may be removed by a stripping process. In some embodiments, the portion of the seed layer 520 may be removed by a wet etching process. After removing the patterned photoresist layer PR and the portion of the seed layer 520 located below the patterned photoresist layer PR, conductive layers 210, 220, and 230 are formed in the predetermined regions R2, R3, and R1, respectively. The conductive layers 210, 220, and 230 may include portions of the conductive material layer 540 and portions of the seed layer 520.

[0068] refer to Figure 6K , an encapsulation material 550 may be formed on semiconductor devices 110, 110', 120, 120', and 130. Encapsulation material 550 may be formed on conductive layers 210, 210', 220, 220', 230, and 230. Encapsulation material 550 may cover conductive layers 210, 210', 220, 220', 230, and 230'.

[0069] refer to Figure 6L , the encapsulation material 550 may be partially removed to form the encapsulation layer 180. The encapsulation material 550 may be partially removed to expose a portion of the conductive layer 220. The encapsulation material 550 may be partially removed to expose a portion of the conductive layer 220'. In some embodiments, the encapsulation material 550 may be partially removed by a grinding process.

[0070] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D and Figure 7E A method of manufacturing a semiconductor device package 200 according to some embodiments of the present disclosure is shown. The various figures have been simplified to provide a better understanding of various aspects of the present disclosure.

[0071] refer to Figure 7A , an interconnect structure 610 may be provided, the interconnect structure 610 having an external connector 630 formed thereon. The interconnect structure 610 may be formed on a carrier 801. The external connector 630 may be formed on the interconnect structure 610.

[0072] refer to Figure 7B, a carrier 802 can be attached to the interconnect structure 610 and the external connector 630. The carrier 802 can be bonded to the surface of the interconnect structure 610 where the external connector 630 is located. The carrier 801 can then be removed to expose a portion 611 of the conductive elements and / or redistribution layer of the interconnect structure 610. One or more electrical contacts 620 can then be formed to directly contact the exposed portion 611.

[0073] refer to Figure 7C , the carrier 802 can be removed.

[0074] refer to Figure 7D The interconnect structure 610 may be bonded to the stacked semiconductor devices (eg, semiconductor devices 110 , 110 ′, 120 , 120 ′, and 130 ). The interconnect structure 610 may be bonded to the conductive layers 220 and 220 ′ through electrical contacts 620 .

[0075] refer to Figure 7E , the carrier 101 may be removed to form the semiconductor device package 200 .

[0076] Figure 8 A cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure is shown. The semiconductor device package 1 may include a substrate 2, stacked semiconductor devices 3, 4, 5, and 6, a conductive layer 7, and an insulating layer 8. The semiconductor devices 3, 4, 5, and 6 may have conductive pads 3a, 4a, 5a, and 6a, respectively. The substrate 2 may have a conductive pad 2a. The conductive layer 7 may electrically connect the conductive pads 2a, 3a, 4a, 5a, and 6a. The conductive layer 7 may be separated from the upper surface and side surfaces of the semiconductor devices 3, 4, 5, and 6 by the insulating layer 8. The insulating layer 8 may be a continuous layer having perforations. Portions of the conductive layer 7 may be filled in the through-holes of the insulating layer 8 to electrically connect to the conductive pads 2a, 3a, 4a, 5a, and 6a. The semiconductor device package 1 may further include laser-blocking layers 9a, 9b, 9c, and 9d disposed on the conductive pads 3a, 4a, 5a, and 6a, respectively. In some embodiments, the laser-blocking layers 9a, 9b, 9c, and / or 9d may be formed of nickel (Ni), lead (Pb), gold (Au), or a combination of two or more thereof, or Ni, Pb, Au, or a combination of two or more thereof. The conductive layer 7 may directly contact the laser-blocking layers 9a, 9b, 9c, and 9d. The conductive layer 7 may be separated from the conductive pads 3a, 4a, 5a, and 6a by the laser-blocking layers 9a, 9b, 9c, and 9d, respectively. The conductive layer 7 may electrically connect all of the conductive pads 3a, 4a, 5a, and 6a of the semiconductor devices 3, 4, 5, and 6 to the conductive pad 2a of the substrate 2. The conductive layer 7 is relatively long and may be damaged in subsequent processes, which may increase the difficulty and manufacturing cost of the reworking process of the conductive layer 7.

[0077] according to Figure 8 In some embodiments shown, the conductive layer 7 electrically connecting all semiconductor devices 3, 4, 5, and 6 to the substrate 2 may have a relatively large length. During the manufacturing process of the semiconductor device package 1, defects may be found in the semiconductor devices 3, 4, 5, and / or 6, anomalies may occur in the formation process of the relatively long conductive layer 7, and the conductive layer 7 may also be damaged during the encapsulation operation. Any or all of these situations may increase the difficulty and manufacturing cost of the reworking process of the damaged conductive layer 7. In addition, according to Figure 8 In some embodiments shown, all semiconductor devices 3, 4, 5, and 6 can only be connected to the same signal source if they share the same conductive layer 7. Furthermore, the relatively large length of the conductive layer 7 may occupy a relatively large vertical space and may cause some problems (e.g., inductance effects when the package operates at a relatively high frequency).

[0078] Figure 9 A cross-sectional view of a semiconductor device package 10 according to some embodiments of the present disclosure is shown. The semiconductor device package 10 may include a carrier 15, semiconductor devices 11 and 12, wires 13, 14, 16, and 17, and an encapsulation layer 18. The semiconductor devices 11 and 12 may be stacked on the carrier 15 and encapsulated by the encapsulation layer 18. The semiconductor devices 11 and 12 may be electrically connected to the carrier 15 via wires 13 and 14, respectively. The relatively large length of the wires 13, 14, 16, and 17 may occupy a relatively large vertical space (e.g., a height of approximately 150 μm), which may cause undesirable inductance effects. Moreover, the wires 13, 14, 16, and 17 may also be damaged during the encapsulation operation (e.g., the wires 13, 14, 16, and 17 may be broken due to relatively strong mold flow).

[0079] In some embodiments, multiple wires may be bonded to a single conductive pad of semiconductor device 11 and / or semiconductor device 12. However, due to the reduced size of the conductive pad, a wire formed first on the conductive pad may be damaged or broken by a subsequently formed wire during the wire bonding process. In addition, the large diameter of the wire (e.g., approximately 15 μm to approximately 50 μm) may adversely affect the accuracy of the wire bonding process for multiple wires on a single conductive pad.

[0080] Figure 10A cross-sectional view of a semiconductor device package 20 according to some embodiments of the present disclosure is shown. The semiconductor device package 20 may include semiconductor devices 21 and 22, conductive pillars 23 and 24, an encapsulation layer 28, electrical contacts 29, and an interconnect structure 30. The stacked semiconductor devices 21 and 22 may be electrically connected to the interconnect structure 30 via the conductive pillars 23 and 24, respectively. The conductive pillars 23 and 24 may be formed by, for example, forming perforations in the encapsulation layer 28 by a laser drilling process and then filling the perforations with a conductive material. The laser drilling process may reduce manufacturing yield. In addition, relatively long conductive pillars 23 and 24 may be damaged during the encapsulation operation (for example, the conductive pillars may break due to relatively strong mold flow), which may greatly increase the difficulty and manufacturing cost of the rework process of the conductive pillars. Moreover, it is difficult to control the uniformity of the height of the conductive pillars, which may increase the difficulty of the subsequent planarization process.

[0081] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," "left," "right," etc. may be used herein for ease of description to describe the relationship of one element or feature to another or more elements or features as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device when in use or operating. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can also be interpreted in a corresponding manner. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to or coupled to the other element, or there can be intermediate elements.

[0082] As used herein, the terms "approximately," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely as well as instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise indicated. The term "substantially coplanar" may refer to a position difference between two surfaces positioned along the same plane that is within a few microns (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of the position difference positioned along the same plane. When a value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the values.

[0083] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure can be readily used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device package, comprising: A first semiconductor device having a first conductive pad; a first conductive layer disposed in direct contact with the first conductive pad and extending in a direction substantially parallel to a surface of the first conductive pad; as well as a second conductive layer disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer, The first conductive layer comprises: a first sublayer contacting the first conductive pad, an upper surface of the first semiconductor device, and a side surface of the first semiconductor device; a second sublayer that contacts and completely covers the first sublayer; and The third sub-layer contacts and completely covers the second sub-layer.

2. The semiconductor device package according to claim 1, further comprising: a second semiconductor device stacked on the first semiconductor device, wherein the second conductive layer comprises: a fourth sublayer contacting the first conductive pad, an upper surface of the first semiconductor device, and a side surface of the second semiconductor device; a fifth sublayer that contacts and completely covers the fourth sublayer; and The sixth sub-layer contacts and completely covers the fifth sub-layer. 3 . The semiconductor device package of claim 2 , wherein the fourth sub-layer contacts an upper surface of the second semiconductor device and a second conductive pad of the second semiconductor device. The semiconductor device package according to claim 3 , wherein the first sub-layer and the fourth sub-layer comprise seed layers.

5. The semiconductor device package according to claim 2, further comprising: a third semiconductor device stacked below the first semiconductor device and having a third conductive pad, wherein the first conductive layer comprises: A first portion contacting the third conductive pad, a second portion contacting the side surface of the first semiconductor device, a third portion contacting the upper surface of the first semiconductor device, and a fourth portion extending between the first portion and the second portion, wherein the fourth portion includes an inclined straight line portion.

6. The semiconductor device package according to claim 5, wherein the second conductive layer comprises: a fifth portion contacting the upper surface of the first semiconductor device, a sixth portion contacting the side surface of the second semiconductor device, a seventh portion contacting the upper surface of the second semiconductor device, and an eighth portion extending between the fifth portion and the sixth portion, wherein the eighth portion includes an inclined straight line portion. 7 . The semiconductor device package according to claim 1 , wherein the first conductive pad protrudes from the upper surface of the first semiconductor device, wherein the first conductive layer contacts a side surface of the first conductive pad and contacts a portion of an upper surface of the first conductive pad. 8 . The semiconductor device package according to claim 7 , wherein a first portion of the first conductive layer contacting an upper surface of the first semiconductor device and a second portion of the first conductive layer contacting an upper surface of the first conductive pad form a step shape.

9. A semiconductor device package, comprising: A first semiconductor device having a first conductive pad; a first conductive layer disposed in direct contact with the first conductive pad; a second conductive layer disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer; as well as a second semiconductor device stacked on the first semiconductor device; The first conductive pad protrudes from the upper surface of the first semiconductor device, and the first conductive layer contacts the side surface of the first conductive pad and contacts a portion of the upper surface of the first conductive pad. 10 . The semiconductor device package according to claim 9 , wherein a first portion of the first conductive layer contacting an upper surface of the first semiconductor device and a second portion of the first conductive layer contacting an upper surface of the first conductive pad form a step shape.

11. The semiconductor device package according to claim 9, wherein the first conductive layer comprises: a first sublayer contacting the first conductive pad, an upper surface of the first semiconductor device, and a side surface of the first semiconductor device; a second sublayer, which contacts and completely covers the first sublayer; and The third sub-layer contacts and completely covers the second sub-layer.

12. The semiconductor device package according to claim 11, wherein the second conductive layer comprises: a fourth sublayer contacting the first conductive pad, an upper surface of the first semiconductor device, and a side surface of the second semiconductor device; a fifth sublayer, which contacts and completely covers the fourth sublayer; and The sixth sub-layer contacts and completely covers the fifth sub-layer. 13 . The semiconductor device package of claim 12 , wherein the fourth sub-layer contacts an upper surface of the second semiconductor device and a second conductive pad of the second semiconductor device. The semiconductor device package according to claim 13 , wherein the first sub-layer and the fourth sub-layer comprise seed layers.

15. The semiconductor device package according to claim 12, further comprising: a third semiconductor device stacked below the first semiconductor device and having a third conductive pad, wherein the first conductive layer comprises: A first portion contacting the third conductive pad, a second portion contacting the side surface of the first semiconductor device, a third portion contacting the upper surface of the first semiconductor device, and a fourth portion extending between the first portion and the second portion, wherein the fourth portion includes an inclined straight line portion.

16. The semiconductor device package according to claim 15, wherein the second conductive layer comprises: a fifth portion contacting the upper surface of the first semiconductor device, a sixth portion contacting the side surface of the second semiconductor device, a seventh portion contacting the upper surface of the second semiconductor device, and an eighth portion extending between the fifth portion and the sixth portion, wherein the eighth portion includes an inclined straight line portion. 17 . The semiconductor device package according to claim 9 , wherein the second conductive layer contacts the second side surface of the first conductive pad and contacts a second portion of an upper surface of the first conductive pad.

18. A method of manufacturing a semiconductor device package, the method comprising: providing a first semiconductor device having a first conductive pad; stacking a second semiconductor device on the first semiconductor device; forming an insulating material on the first semiconductor device and the second semiconductor device; partially removing the insulating material to form a support structure at a corner, the corner being defined by a portion of a surface of the first semiconductor device and a portion of a surface of the second semiconductor device; as well as forming a first conductive layer and a second conductive layer, both of which directly contact the first conductive pad and are spaced apart from each other, The first conductive layer comprises: a first sublayer contacting the first conductive pad, an upper surface of the first semiconductor device, and a side surface of the first semiconductor device; a second sublayer that contacts and completely covers the first sublayer; and The third sub-layer contacts and completely covers the second sub-layer.

19. The method according to claim 18, wherein The insulating material is partially removed to expose edge portions of the first semiconductor device and the second semiconductor device, wherein the second conductive layer comprises: a fourth sublayer contacting the first conductive pad, an upper surface of the first semiconductor device, and a side surface of the second semiconductor device; a fifth sublayer, which contacts and completely covers the fourth sublayer; and The sixth sub-layer contacts and completely covers the fifth sub-layer.

20. The method of claim 19, wherein forming the first conductive layer and forming the second conductive layer comprises: forming a patterned photoresist layer on the first semiconductor device and the second semiconductor device through a plurality of exposure processes and a development process, wherein the patterned photoresist layer has a plurality of openings exposing a plurality of predetermined areas; forming a conductive material layer on the plurality of predetermined areas; as well as The patterned photoresist layer is removed to form the first conductive layer and the second conductive layer on the first conductive pad of the first semiconductor device, wherein the first conductive pad protrudes from the upper surface of the first semiconductor device, and wherein the first conductive layer contacts the side surface of the first conductive pad and contacts a portion of the upper surface of the first conductive pad.

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