Semiconductor structure of memory device and method for forming the same

Abstract

Embodiments of the present invention relate to semiconductor structures for memory devices and methods for forming the same. Some embodiments of the present invention disclose a memory structure for a memory device, comprising a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure comprises a first layer and a second layer, with the first layer interposed between the second layer and the first gate structure. The first and second layers comprise the same semiconductor material and the same dopant. The first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the first dopant concentration.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure of a memory device and a method for forming the same. Background Art

[0002] Non-volatile memory (NVM) is commonly used in various devices, such as computers. NVM is a type of memory storage that can retain data even when it is not powered. NVM can be electrically or mechanically addressable. Examples of electrically addressable NVM include flash memory, EPROM, and EEPROM. NVM functionality includes allowing information to be programmed into it, read from it, and erased.

[0003] Common types of flash memory devices include stacked-gate flash memory devices and split-gate flash memory devices. Split-gate flash memory devices offer several advantages over stacked-gate flash memory devices, such as lower power consumption, higher injection efficiency, less susceptibility to short-channel effects, and over-erase immunity. Examples of split-gate flash memory devices include silicon-oxide-nitride-oxide-silicon (SONOS) split-gate flash memory devices, metal-oxide-nitride-oxide-silicon (MONOS) split-gate flash memory devices, and third-generation SUPERFLASH (ESF3) memory devices. Summary of the Invention

[0004] An embodiment of the present invention relates to a memory structure for a memory device, comprising: a first gate structure; and a second gate structure adjacent to the first gate structure, wherein the second gate structure comprises a first layer and a second layer, the first layer being between the second layer and the first gate structure, the first layer and the second layer comprising the same semiconductor material and the same dopant, the first layer having a first dopant concentration, and the second layer having a second dopant concentration different from the first dopant concentration.

[0005] An embodiment of the present invention relates to a memory device comprising: a substrate; a first gate structure located on the substrate; a first doped region located in the substrate; and a second gate structure located on the substrate and adjacent to the first gate structure, wherein the first gate structure is disposed between the second gate structure and the first doped region; and wherein the second gate structure comprises a first layer having a first dopant concentration and a second layer having a second dopant concentration different from the first dopant concentration.

[0006] An embodiment of the present invention relates to a method for forming a semiconductor structure, comprising: receiving a substrate, the substrate including a first gate structure formed thereon; forming a first semiconductor layer having a first dopant concentration on the substrate and the first gate structure; forming a second semiconductor layer having a second dopant concentration on the first semiconductor layer; performing an etch-back operation to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer using an etchant, wherein an etch rate of the first semiconductor layer after exposure to the etchant is greater than an etch rate of the second semiconductor layer after exposure to the etchant; forming a hard mask spacer on the first semiconductor layer and the second semiconductor layer, wherein a portion of the second semiconductor layer is exposed through the hard mask spacer; and removing the portion of the second semiconductor layer and a portion of the first semiconductor layer through the hard mask spacer to form a second gate structure and expose a portion of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the embodiments of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention.

[0009] Figure 2 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention.

[0010] Figure 3 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention.

[0011] Figure 4 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention.

[0012] Figure 5 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention.

[0013] Figure 6 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention.

[0014] Figure 7 is a flow chart illustrating a method for fabricating a semiconductor structure for a memory device according to aspects of an embodiment of the present invention.

[0015] Figures 8A to 8K Cross-sectional views of semiconductor structures illustrating memory devices at various stages of fabrication constructed according to aspects of one or more embodiments of the present invention.

[0016] Figures 9A to 9D Cross-sectional views of semiconductor structures illustrating memory devices at various stages of fabrication constructed according to aspects of one or more embodiments of the present invention.

[0017] FIG. 10A to FIG. 10D Cross-sectional views of semiconductor structures illustrating memory devices at various stages of fabrication constructed according to aspects of one or more embodiments of the present invention.

[0018] Figure 11 A cross-sectional view of a semiconductor structure illustrating a memory device at a stage of fabrication constructed according to aspects of one or more embodiments of the present invention.

[0019] Figure 12A and Figure 12B Cross-sectional views of semiconductor structures illustrating memory devices at various stages of fabrication constructed according to aspects of one or more embodiments of the present invention. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples of the different features for implementing the provided subject matter. Specific examples of components and arrangements will be described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, reference to "forming a first component above or on a second component" may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components may be formed between the first and second components so that the first and second components may not be in direct contact. In addition, embodiments of the present invention may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] This description of the illustrative embodiments is intended to be read in conjunction with the accompanying drawings, which are considered part of the entire written description. In the description of the embodiments disclosed herein, any reference to direction or orientation is intended solely for ease of description and is in no way intended to limit the scope of the embodiments of the present invention. Relative terms such as "lower," "upper," "horizontal," "vertical," "above," "below," "upward," "downward," "top," and "bottom," and their derivatives (e.g., "horizontally," "downwardly," "upwardly," etc.), should be interpreted as referring to the orientation shown in the drawings subsequently described or discussed. Such relative terms are used solely for ease of description and do not necessarily require that the device be constructed or operated in a particular orientation. Unless expressly stated otherwise, terms such as "attached," "attached," "connected," and "interconnected" refer to relationships in which structures are fixed or attached to each other, directly or indirectly through intervening structures, and to removable or rigid attachments or relationships between the two. Furthermore, the features and advantages of the embodiments of the present invention are described by reference to the embodiments. Accordingly, the embodiments of the present invention should not be expressly limited to the embodiments illustrating some non-limiting possible combinations of features that may exist alone or in combination with other features, and the scope of the embodiments of the present invention is defined by the appended claims.

[0022] Although the numerical ranges and parameters describing the broad scope of the embodiments of the present invention are approximate, the numerical values ​​described in the specific examples should be reported as precisely as possible. However, any numerical value inherently contains certain errors that are necessarily due to the deviations found in the corresponding test measurements. In addition, as used herein, the terms "substantially," "about," or "approximately" generally mean within a value or range that would be expected by a person of ordinary skill in the art. Alternatively, the terms "substantially," "about," or "approximately" mean within the acceptable standard error of the mean value as considered by a person of ordinary skill in the art. A person of ordinary skill in the art will understand that the acceptable standard error may vary depending on the technology. Except in the operating / working examples or unless otherwise expressly provided, all numerical ranges, quantities, values, and percentages disclosed herein (e.g., numerical ranges, quantities, values, and percentages of material quantities, durations, temperatures, operating conditions, quantitative ratios, and the like) should be understood as being modified in all instances by the terms "substantially," "approximately," or "approximately." Therefore, unless otherwise indicated, the numerical parameters described in the embodiments of the present invention and the appended claims are approximate values ​​that may vary as needed. Finally, each numerical parameter should at least be interpreted in light of the number of reported significant digits and by applying ordinary rounding techniques. In this article, ranges can be expressed from an endpoint to the other endpoint or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints.

[0023] Flash memory includes an array of flash memory devices and logic devices that support the operation of the flash memory devices. Embedded flash memory methods have been developed to integrate the flash memory device array and logic devices. In some embodiments, the embedded flash memory device can be formed with polysilicon gates insulated by silicon dioxide and logic devices such as, for example, address decoders or read / write circuits.

[0024] When forming an embedded flash memory device, a gate stack may be formed on a substrate, and a polysilicon layer for forming a polysilicon gate (i.e., a select gate for flash memory or a control gate for SONOS memory) is deposited on the substrate and fills the gaps between the gate stacks. Subsequently, the polysilicon layer is etched back, and a hard mask layer is formed on the thinned polysilicon layer. The polysilicon layer is patterned through the hard mask layer to form the select gate or the control gate. It has been found that when filling the gaps between the gate stacks, seams or voids may form in the polysilicon layer. After the etch-back operation, the seams become grooves, and the grooves are filled with the hard mask layer. The hard mask layer filling the grooves is referred to as mask residue, and the mask residue interferes with the patterning of the polysilicon layer. As a result, the silicon residue remains on the substrate and produces defects that adversely affect yield.

[0025] Embodiments of the present invention provide a semiconductor structure and method for forming the same to mitigate silicon residue defects. According to some embodiments of the present invention, polysilicon layers with different dopant concentrations are formed to fill gaps between gate structures, thereby providing different etch rates. Due to the differences in etch rates, the profile of the polysilicon layer is modified during the etch-back operation. In some embodiments, even if seams or voids are formed during the formation of the polysilicon layer, the recess problem can be mitigated after the etch-back operation. Consequently, mask residue problems and silicon residue defects are mitigated, thereby improving yield.

[0026] Figure 1is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention. In some embodiments, a semiconductor structure 100a is provided. The semiconductor structure 100a includes a substrate 102, with a memory region 104a and a peripheral region 104b defined on the substrate 102. In some embodiments, the substrate 102 may include silicon, germanium, or a bulk substrate of a Group III or Group V element. In other embodiments, the substrate 102 may include a semiconductor-on-insulator (SOI) substrate, but the embodiments of the present invention are not limited in this regard. The semiconductor structure 100a includes a memory device 110 located in the memory region 104a and devices 112a / 112b located in the logic region 104b. In some embodiments, the device 112a may be a power device, and the device 112b may be a core device, but the embodiments of the present invention are not limited in this regard. The semiconductor structure 100a may further include isolation structures 106a and 106b disposed in the substrate 102. The isolation structure 106a may be located between the memory region 104a and the peripheral region 104b to electrically isolate the memory region 104a and the peripheral region 104b from each other, and the isolation structure 106b may be located in the peripheral region 104b to electrically isolate the devices 112a and 112b from each other. In addition, the dummy structure 113 may be disposed on the substrate 102 and / or the isolation structure 106a, such as Figure 1 However, the embodiments of the present invention are not limited thereto.

[0027] refer to Figure 1 , each memory device 110 may include a first gate structure 120 on a substrate 102, a second gate structure 130 adjacent to the first gate structure 120, and a third gate structure 140 adjacent to the first gate structure 120. Figure 1As shown in FIG, first gate structure 120 is disposed between second gate structure 130 and third gate structure 140. In some embodiments, first gate structure 120 includes a floating gate 122 on substrate 102, a control gate 124 on floating gate 122, and a dielectric structure 126 between floating gate 122 and control gate 124. Furthermore, floating gate 122 is electrically isolated from substrate 102 by dielectric layer 128. Second gate structure 130 is a select gate and is electrically isolated from substrate 102 by dielectric layer 134. Third gate structure 140 is an erase gate and is electrically isolated from substrate 102 by spacer 144. First doped region 150a and second doped region 150b are disposed in substrate 102. Third gate structure 140 is disposed on first doped region 150a and is electrically isolated from first doped region 150a by spacer 144. First gate structure 120 and second gate structure 130 are disposed between first doped region 150a and second doped region 150b. Furthermore, the first gate structure 120 is disposed between the second gate structure 130 and the first doped region 150a, and the second gate structure 130 is disposed between the second doped region 150b and the first gate structure 120. In some embodiments, the first doped region 150a refers to a source region in the memory device 110 and the second doped region 150b refers to a drain region in the memory device 110. In some embodiments, two memory devices 110 share one source region 150a, such as Figure 1 As shown in .

[0028] In some embodiments, the second gate structure 130 and the third gate structure 140 may comprise similar compositions, as will be described in detail below. In other embodiments, the second gate structure 130 and the third gate structure 140 may comprise different compositions, as will be described in detail below.

[0029] Still refer to Figure 1 The second gate structure 130 (ie, the selection gate) includes a first layer 132a and a second layer 132b. Figure 1As shown in FIG, the first layer 132a is disposed between the first gate structure 120 and the second layer 132b and between the substrate 102 and the second layer 132b. In some embodiments, the first layer 132a may include an L-shape, but embodiments of the present invention are not limited thereto. The third gate structure 140 (i.e., the erase gate) includes the first layer 132a and the second layer 132b. As mentioned above, the third gate structure 140 may include a composition similar to that of the second gate structure 130. In some embodiments, the composition of the first layer 132a and the second layer 132b of the third gate structure 140 is the same as that of the first layer 132a and the second layer 132b of the second gate structure; therefore, for the sake of brevity, details of the first layer 132a and the second layer 132b are omitted from the description. In some embodiments, differences can be observed between the first layer 132a of the third gate structure 140 and the first layer 132a of the second gate structure 130. That is, the first layer 132 a of the second gate structure 130 may include an L shape, but the first layer 132 a of the third gate structure 140 may include a U shape, but the embodiment of the present invention is not limited thereto.

[0030] The first layer 132a and the second layer 132b of the second gate structure 130 may include the same semiconductor material, such as (but not limited to) polysilicon. Furthermore, the first layer 132a and the second layer 132b of the second gate structure 130 may include the same dopant. In some embodiments, when the second gate structure 130 is an n-type gate structure, the first layer 132a and the second layer 132b may include the same n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)), but the present invention is not limited thereto. In some alternative embodiments, when the second gate structure 130 is a p-type gate structure, the first layer 132a and the second layer 132b may include the same p-type dopant (e.g., boron (B)), but the present invention is not limited thereto. Obviously, although the first layer 132a and the second layer 132b include the same dopant, the dopant concentration of the first layer 132a is different from the dopant concentration of the second layer 132b. It should be noted that when the second gate structure 130 is an n-type gate structure, the dopant concentration of the second layer 132b is less than the dopant concentration of the first layer 132a. For example (but not limited to), for an n-type gate structure, the dopant concentration of P in the first layer 132a is greater than about 1E19 cm -3 , and the dopant concentration of P in the second layer 132b is less than about 5E18cm -3 In contrast, when the second gate structure 130 is a p-type gate structure 130, the dopant concentration of the second layer 132b is greater than the dopant concentration of the first layer 132a. For example (but not limited to), for a p-type gate structure 130, the dopant concentration of B in the first layer 132a is less than about 5E18cm -3, and the dopant concentration of B in the second layer 132b is greater than about 1E19 cm -3 In some embodiments, the thickness of the second layer 132b is greater than the thickness of the first layer 132a. In some embodiments, the ratio of the thickness of the second layer 132b to the thickness of the first layer 132a is about 2:1, but the present invention is not limited thereto. For example (but not limited to), the thickness of the first layer 132a may be between about Arrive at the appointment and the thickness of the second layer 132b may be between about Arrive at the appointment In addition, the width of the first layer 132 a exposed through the top surface of the second gate structure 130 is smaller than the width of the second layer 132 b exposed through the top surface of the second gate structure 130 .

[0031] As semiconductor components become increasingly smaller, the logic devices of such embedded memory devices are reaching their performance limits. Therefore, in some embodiments, high-k metal gate (HKMG) technology is employed. HKMG technology uses a metal gate separated from the underlying substrate by a high dielectric constant (relative to silicon dioxide) material. High-k materials reduce leakage current and increase the effect of Fermi level pinning, allowing the gate to operate at a lower threshold voltage. Furthermore, high-k materials and metal gates together reduce power consumption.

[0032] refer to Figure 1 Logic devices 112a and 112b may each include a metal gate 114, a gate dielectric layer 116, and source / drain regions 118. Furthermore, power device 112a may have a thicker gate dielectric layer 116 than the gate dielectric layer of core device 112b. Metal gate 114 may include a p-type or n-type work function metal layer and a gapfill metal layer. Although not shown in the figures, in some embodiments, metal gate 114 may include a barrier layer or an etch stop layer.

[0033] It should be noted that the top surface of the substrate 102 in the memory region 104a and the top surface of the substrate 102 in the logic region 104b are at different levels. In other words, the top surfaces of the first doped region 150a and the second doped region 150b of the memory device 110 may be lower than the top surfaces of the source / drain regions 118 of the logic devices 112a and 112b. In some embodiments, the step height between the top surfaces of the first doped region 150a / the second doped region 150b and the top surfaces of the source / drain regions 118 may be between about 100 nm and 100 nm. Arrive at the appointment However, the embodiments of the present invention are not limited thereto.

[0034] In some embodiments, spacers 152 may be formed on the sidewalls of each gate structure 120, 130, 140, and 114. In some embodiments, metal silicide 154 may be formed on the top surfaces of the second gate structure 130, the third gate structure 140, the second doped region 150b, and the source / drain region 118. Figure 1 . In some embodiments, an interlayer dielectric (ILD) layer 160 may be formed on substrate 102 to cover memory device 110 and logic devices 112a and 112b. In some embodiments, a connection structure 162 may be formed in ILD layer 160. Connection structure 162 is formed to electrically connect the second doped region 150b of memory device 110 to interconnect structure 170 and to electrically connect the source / drain regions 118 of logic devices 112a and 112b to interconnect structure 170. In some embodiments, interconnect structure 170 may include a dielectric layer 172 and a conductive member 174, which may include a metal layer and a via.

[0035] Figure 2 1 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention. In some embodiments, a semiconductor structure 100b having a memory device 110 is provided. It should be noted that Figure 1 and Figure 2 The same elements in the present invention are depicted by the same reference numerals and are omitted in the description for the sake of brevity. Figure 1 and Figure 2 In addition, for the sake of brevity, Figure 2 The logic region 104b is omitted. In some embodiments, in the second gate structure 130, the thickness of the first layer 132a is less than the thickness of the second layer 132b. However, the width of the first layer 132a exposed through the top surface of the second gate structure 130 may be the same as the width of the second layer 132b exposed through the top surface of the second gate structure 130, as shown in FIG. Figure 2 In some embodiments, the first layer 132a of the third gate structure 140 may include the same composition as the first layer 132a of the second gate structure 130, and the second layer 132b of the third gate structure 140 may include the same composition as the second layer 132b of the second gate structure 130. Compared to the second gate structure 130, in the third gate structure 140, the thickness of the first layer 132a and the thickness of the second layer 132b may be the same, as shown in FIG. Figure 2 In addition, the thickness of the first layer 132a of the second gate structure 130 is substantially the same as the thickness of the first layer 132a of the third gate structure 140, while the thickness of the second layer 132b of the second gate structure 130 is greater than the thickness of the second layer 132b of the third gate structure 140.

[0036] Figure 3 1 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention. In some embodiments, a semiconductor structure 100c having a memory device 110 is provided. It should be noted that Figure 1 and Figure 3 The same elements in the present invention are depicted by the same reference numerals and are omitted in the description for the sake of brevity. Figure 1 and Figure 3 In addition, for the sake of brevity, Figure 3 The logic region 104b is omitted. In some embodiments, in the second gate structure 130, the thickness of the first layer 132a is greater than the thickness of the second layer 132b. In some embodiments, in the second gate structure 130, the width of the uppermost surface of the first layer 132a is also greater than the width of the uppermost surface of the second layer 132b. Figure 3 In some embodiments, the third gate structure 140 may include a first layer 132 a that includes the same composition as the first layer 132 a of the second gate structure 130 .

[0037] Figure 4 1 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention. In some embodiments, a semiconductor structure 100d having a memory device 110 is provided. It should be noted that Figure 1 and Figure 4 The same elements in the present invention are depicted by the same reference numerals and are omitted in the description for the sake of brevity. Figure 1 and Figure 4 In addition, for the sake of brevity, Figure 4Logic region 104b is omitted. In some embodiments, second gate structure 130 further includes a third layer 132c disposed between first layer 132a and second layer 132b. Similarly, third gate structure 140 includes a third layer 132c disposed between first layer 132a and second layer 132b. The third layer 132c of second gate structure 130 includes the same semiconductor material and dopant as the first layer 132a and second layer 132b of second gate structure 130. Similarly, the third layer 132c of third gate structure 140 includes the same semiconductor material and dopant as the first layer 132a and second layer 132b of third gate structure 140. Notably, the dopant concentration of the third layer 132c of the second gate structure 130 and the third gate structure 140 is between the dopant concentration of the first layer 132a and the dopant concentration of the second layer 132b of the second gate structure 130 and the third gate structure 140. The dopant concentration of the third layer 132c of the second gate structure 130 is the same as the dopant concentration of the third layer 132c of the third gate structure 140. In some embodiments, in the second gate structure 130, the thickness ratio of the first layer 132a, the second layer 132b, and the third layer 132c is 1:1:1, but the present invention is not limited thereto. In some embodiments, the thickness of the second layer 132b of the second gate structure 130 is greater than the thickness of the first layer 132a and the third layer 132c of the second gate structure 130, such as Figure 4 . The thicknesses of the first layer 132a, the second layer 132b, and the third layer 132c of the third gate structure 140 may be similar to those of the first layer 132a, the second layer 132b, and the third layer 132c of the second gate structure 130, but the present invention is not limited thereto. In some embodiments, the first layer 132a and the third layer 132c of the second gate structure 130 have an L shape, while the first layer 132a and the third layer 132c of the third gate structure 140 have a U shape, but the present invention is not limited thereto.

[0038] Figure 5 1 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to aspects of an embodiment of the present invention. In some embodiments, a semiconductor structure 100e having a memory device 110 is provided. It should be noted that Figure 4 and Figure 5 The same elements in the present invention are depicted by the same reference numerals and are omitted in the description for the sake of brevity. Figure 4 and Figure 5 In addition, for the sake of brevity, Figure 5The logic region 104b is omitted. In some embodiments, the second gate structure 130 further includes a third layer 132c and a fourth layer 132d disposed between the first layer 132a and the second layer 132b. Similarly, the third gate structure 140 includes a third layer 132c and a fourth layer 132d disposed between the first layer 132a and the second layer 132b. The third layer 132c and the fourth layer 132d of the second gate structure 130 include the same semiconductor material and dopant as the first layer 132a and the second layer 132b of the second gate structure 130. Similarly, the third layer 132c and the fourth layer 132d of the third gate structure 140 include the same semiconductor material and dopant as the first layer 132a and the second layer 132b of the third gate structure 140. The fourth layer 132d of the second gate structure 130 is adjacent to the third layer 132c of the second gate structure 130, and the fourth layer 132d of the third gate structure 140 is adjacent to the third layer 132c of the third gate structure 140. In both the second gate structure 130 and the third gate structure 140, the dopant concentration of the fourth layer 132d is greater than the dopant concentration of the third layer 132c, but is between the dopant concentrations of the first layer 132a and the second layer 132b. The dopant concentration of the fourth layer 132d of the second gate structure 130 is the same as the dopant concentration of the fourth layer 132d of the third gate structure 140. In some embodiments, the thickness ratio of the first layer 132a, the second layer 132b, the third layer 132c, and the fourth layer 132d of the second gate structure 130 and the third gate structure 140 is 1:1:1:1, but embodiments of the present invention are not limited thereto. In some embodiments, although not shown, the fourth layer 132d of the second gate structure 130 and the third gate structure 140 may be disposed between the third layer 132c and the second layer 132b. In some alternative embodiments, the fourth layer 132d of the second gate structure 130 and the third gate structure 140 may be disposed between the third layer 132c and the first layer 132a, such as Figure 5 As shown in .

[0039] In some embodiments, for an n-type gate structure, the dopant concentration may gradually decrease from the first layer 132a, the fourth layer 132d, and the third layer 132c to the second layer 132b. In some embodiments, for an n-type gate structure, the first layer 132a, which has the highest dopant concentration among the four layers, is positioned closest to the first gate structure 120 and the substrate 102. For an n-type gate structure, the second layer 132b, which has the lowest dopant concentration among the four layers, is positioned furthest from the first gate structure 120 and the substrate 102. Regardless of the arrangement of the two layers in the depicted embodiment, the arrangement of the third layer 132c and the fourth layer 132d is not limited. The arrangement of the first layer 132a, the second layer 132b, the third layer 132c, and the fourth layer 132d of the third gate structure 140 may be the same as the arrangement of the first layer 132a, the second layer 132b, the third layer 132c, and the fourth layer 132d of the second gate structure 130. In some embodiments, for a p-type gate structure, the dopant concentration may gradually increase from the first layer 132a, the fourth layer 132d, and the third layer 132c to the second layer 132b. In some embodiments, for a p-type gate structure, the first layer 132a, which has the lowest dopant concentration among the four layers, is positioned closest to the first gate structure 120 and the substrate 102. For a p-type gate structure, the second layer 132b, which has the highest dopant concentration among the four layers, is positioned furthest from the first gate structure 120 and the substrate 102. Regardless of the arrangement of the two layers in the depicted embodiment, the arrangement of the third layer 132c and the fourth layer 132d is not limited. The arrangement of the first layer 132a, the second layer 132b, the third layer 132c, and the fourth layer 132d of the third gate structure 140 may be the same as the arrangement of the first layer 132a, the second layer 132b, the third layer 132c, and the fourth layer 132d of the second gate structure 130. In some embodiments, the first layer 132a, the third layer 132c and the fourth layer 132d of the second gate structure 130 have an L shape, and the first layer 132a, the third layer 132c and the fourth layer 132d of the third gate structure 140 have a U shape, but the embodiment of the present invention is not limited thereto.

[0040] Figure 6 1 is a schematic diagram illustrating a cross-sectional view of a semiconductor structure for a memory device according to an embodiment of the present invention. In some embodiments, a semiconductor structure 100f having a memory device 110 is provided. It should be noted that Figure 1 and Figure 6 The same elements in the present invention are depicted by the same reference numerals and are omitted in the description for the sake of brevity. Figure 1 and Figure 6 In addition, for the sake of brevity, Figure 6Logic region 104b is omitted. In some embodiments, memory device 110 of semiconductor structure 100f may be a SONOS memory device. Therefore, first gate structure 120 is referred to as a select gate, and second gate structure 130 is referred to as a control gate. First gate structure 120 is electrically isolated from substrate 102 by dielectric layer 128, while second gate structure 130 is electrically isolated from substrate 102 and first gate structure 120 by ONO structure 136. First gate structure 120 may comprise a semiconductor material. In some embodiments, second gate structure 130 may comprise a first layer 132a and a second layer 132b, which may be similar to the layers described above. In some embodiments, second gate structure 130 may comprise a first layer 132a, a second layer 132b, and a third layer 132c, which may be similar to the layers described above. In some other embodiments, second gate structure 130 may comprise a first layer 132a, a second layer 132b, a third layer 132c, and a fourth layer 132d, which may be similar to the layers described above. In some embodiments, the metal silicide 154 is formed on the top surfaces of the first gate structure 120, the second gate structure 130, the first doped region 150a, and the second doped region 150b. Figure 6 As shown in .

[0041] Figure 7 1 is a flow chart illustrating a method 10 for fabricating a semiconductor structure for a memory device according to aspects of an embodiment of the present invention. Method 10 includes several operations (11, 12, 13, 14, 15, and 16). Method 10 for fabricating a semiconductor structure for a semiconductor device will be further described according to one or more embodiments. It should be noted that the operations of method 10 for fabricating a semiconductor structure for a semiconductor device may be rearranged or otherwise modified within the scope of various aspects. It should further be noted that additional processes may be provided before, during, and after method 10, and that some additional processes may be only briefly described herein. Therefore, other implementations are possible within the scope of the various aspects described herein.

[0042] In operation 11, a substrate is received. In some embodiments, the substrate includes a first gate structure formed thereon.

[0043] In operation 12, a first semiconductor layer is formed on the substrate and the first gate structure. In some embodiments, the first semiconductor layer has a first dopant concentration.

[0044] In operation 13, a second semiconductor layer is formed on the first semiconductor layer. In some embodiments, the second semiconductor layer has a second dopant concentration.

[0045] In operation 14, an etch-back operation is performed to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer using an etchant. In some embodiments, an etch rate of the first semiconductor layer relative to the etchant is greater than an etch rate of the second semiconductor layer relative to the etchant.

[0046] In operation 15, hard mask spacers are formed on the first semiconductor layer and the second semiconductor layer. In some embodiments, a portion of the second semiconductor layer is exposed by the hard mask spacers.

[0047] In operation 16 , a portion of the second semiconductor layer and a portion of the first semiconductor layer are removed through the hard mask spacers to form a second gate structure and expose a portion of the substrate.

[0048] refer to Figure 8A In some embodiments, a substrate 102 is received. It should be noted that the substrate 102 may include a memory region 104a and a logic region 104b separated from each other by an isolation structure 106a. The arrangement of the memory region 104a, the logic region 104b, and the isolation structure 106a may be similar to Figure 1 Therefore, for the sake of simplicity, Figure 8A The memory region 104a, logic region 104b, and isolation structures 106a and 106b are omitted. A plurality of gate structures 120 are disposed on substrate 102. In some embodiments, each of gate structures 120 includes a first gate electrode 122, i.e., a floating gate (FG), separated and electrically isolated from substrate 102 by a dielectric layer 128. Each of gate structures 120 includes a second gate electrode 124, i.e., a control gate (CG), separated and electrically isolated from first gate electrode 122 by a dielectric structure 126. The dielectric layer 128 interposed between floating gate 122 and substrate 102 serves as a floating gate dielectric, and the dielectric structure 126 interposed between floating gate 122 and control gate 124 serves as an inter-polysilicon dielectric (IPD) spacer. Floating gate 122 and control gate 124 may comprise polysilicon, doped polysilicon, or combinations thereof, but embodiments of the present invention are not limited thereto. The dielectric layer 128 may include an oxide (e.g., silicon oxide (SiO)), but other materials are also acceptable. The dielectric structure 126 may include a composite film (e.g., an oxide-nitride-oxide (ONO) film), but the embodiments of the present invention are not limited thereto. The patterned mask structure 127 is formed to define the position and size of the gate structure 120. In some embodiments, the patterned mask structure 127 may be a multi-layer structure (e.g., Figure 8A), but other materials are acceptable. The gate structures 120 can be grouped in pairs, such as group 1G1 and group 2G2. In some embodiments, the two gate structures 120 (corresponding to two memory devices) in each group G1, G2 are separated from each other by a spacing S1, as shown in FIG. Figure 8A In some embodiments, the spacing S1 is substantially equal to the width of the source line to be formed. The spacing S1 and the width of the source line can be designed according to different product requirements. For example, the spacing S1 is between about 30 nanometers and about 800 nanometers, but the embodiments of the present invention are not limited thereto. In addition, the two groups G1 and G2 can be separated from each other by a spacing S2, such as Figure 8A As shown in FIG. In some embodiments, the distance S2 between groups G1 and G2 is greater than the spacing S1. The spacing S2 can be designed based on different product requirements. In some embodiments, the spacing S2 is between approximately 50 nanometers and approximately 2000 nanometers, but the present invention is not limited thereto.

[0049] In some embodiments, spacers 152 may be formed on the sidewalls of each gate structure 120. Spacers 152 may be formed to cover the sidewalls of control gate 124 and dielectric structure 126. Spacers 152 may also be formed on portions of patterned mask structure 127 and floating gate 122, such as Figure 8A . In some embodiments of the present invention, the spacers 152 each include a multilayer structure formed by multiple operation processes. For example (but not limited to), the spacer 152 may be an oxide-nitride-oxide (ONO) multilayer structure. In some embodiments, the first doped region 150a is formed in the two gate structures 120 in each group G1, G2. In some embodiments, the first doped region 150a serves as a source region and is shared by the two gate structures 120 in group G1 or G2. After forming the first doped region 150a, the spacer 144 is formed on the first doped region 150a. In some embodiments, the spacer 144 formed between the two gate structures 120 in group G1 or G2 forces the adjacent gate structures 120 to tilt. Therefore, the angle θ between the gate structure 120 and the substrate 102 can be reduced to less than 90°.

[0050] refer to Figure 8BIn some embodiments, a dielectric layer (not shown) is formed on the substrate 102 and a first semiconductor layer 132a is formed on the dielectric layer. The first semiconductor layer 132a is formed on the substrate 102 and the gate structure 120. In some embodiments, the first semiconductor layer 132a is formed after forming the first doped region 150a and forming the spacer 144. The first semiconductor layer 132a may include a semiconductor material, such as silicon. In some embodiments, the first semiconductor layer 132a may be formed by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or the like. In addition, the first semiconductor layer 132a includes an n-type dopant (such as As, Sb, or P) or a p-type dopant (such as B). In some embodiments, the n-type dopant and the p-type dopant may be introduced into the first semiconductor layer 132a by an in-situ doping process. In some embodiments, when the first semiconductor layer 132a is used to form an n-type gate, the dopant concentration of (for example) P in the first semiconductor layer 132a is greater than approximately 1E19 cm -3 In some embodiments, when the first semiconductor layer 132a is used to form a p-type gate, the dopant concentration of (for example) B in the first semiconductor layer 132a is less than 5E18 cm -3 In some embodiments, the thickness of the first semiconductor layer 132a is between about Arrive at the appointment In some embodiments, the first semiconductor layer 132a is conformally formed on the substrate 102 and the gate structure 120. Therefore, the first semiconductor layer 132a covers the top surface of the substrate 102, the top surface of the gate structure 120, the top surface of the spacer 144, and the sidewalls of the gate structure 120. In some embodiments, the unused space between the two gate structures 120 in each group G1 or G2 can be filled with the first semiconductor layer 132a, but the embodiments of the present invention are not limited thereto. In some embodiments, a seam or gap 133a can be formed in the first semiconductor layer 132a, such as Figure 8B As shown in .

[0051] refer to Figure 8CIn some embodiments, the second semiconductor layer 132b is formed on the first semiconductor layer 132a. The second semiconductor layer 132b may include the same semiconductor material as the semiconductor material included in the first semiconductor layer 132a. In some embodiments, the second semiconductor layer 132b may also be formed by CVD, LPCVD, or the like. In some embodiments, the second semiconductor layer 132b may include an undoped semiconductor material. In other embodiments, the second semiconductor layer 132b includes an n-type dopant (e.g., As, Sb, or P) or a p-type dopant (e.g., B). In some embodiments, the n-type dopant and the p-type dopant may be introduced into the second semiconductor layer 132b by an in-situ doping process. Obviously, when the second semiconductor layer 132b is used to form an n-type gate, the dopant concentration of the second semiconductor layer 132b is less than the dopant concentration of the first semiconductor layer 132a. In some embodiments, the dopant concentration of the n-type dopant (e.g., P) of the second semiconductor layer 132b is less than about 5E18 cm -3 , but the present invention is not limited thereto. In contrast, when the second semiconductor layer 132b is used to form a p-type gate, the dopant concentration of the second semiconductor layer 132b is greater than the dopant concentration of the first semiconductor layer 132a. In some embodiments, the dopant concentration of (for example) B in the second semiconductor layer 132b is greater than 1E19cm -3 If the dopant concentration of the second semiconductor layer 132b is less than 1E19cm -3 , the dopant concentration is insufficient to change the etching rate of the second semiconductor layer 132b. The thickness of the second semiconductor layer 132b is greater than the thickness of the first semiconductor layer 132a. In some embodiments, the thickness of the second semiconductor layer 132b is between about Arrive at the appointment In some embodiments, the second semiconductor layer 132b is further formed conformally. In some embodiments, a seam or gap 133b may be formed in the second semiconductor layer 132b, such as Figure 8C In some embodiments, because the angle θ is less than 90°, seams or gaps 133b are easily formed in the second semiconductor layer 132b.

[0052] Additionally, in some embodiments, because the unused space between the two gate structures 120 in the group G1 or G2 is filled with the first semiconductor layer 132 a , no second semiconductor layer 132 b exists between the two gate structures 120 in the group G1 or G2 .

[0053] Still refer to Figure 8CIn some embodiments, a sacrificial layer 135 is formed on the second semiconductor layer 132b. The sacrificial layer 135 may comprise a photoresist material, but the present invention is not limited thereto. The sacrificial layer 135 is formed to achieve a flat top surface for subsequent etching processes. In some embodiments, the sacrificial layer 135 may be formed by a coating technique (e.g., spin coating). The top surface of the formed sacrificial layer 135 is substantially planar.

[0054] refer to Figure 8D , an etch-back operation is performed to remove the sacrificial layer 135, a portion of the second semiconductor layer 132b, and a portion of the first semiconductor layer 132a using an etchant. Figure 8D As shown in FIG, an etchant is used to completely remove the sacrificial layer 135. Furthermore, the etchant removes a portion of the second semiconductor layer 132b and a portion of the first semiconductor layer 132a, exposing the upper portion of the gate structure 120. In some embodiments, due to the different dopant concentrations of the first and second semiconductor layers 132a, 132b, the etching rate of the first semiconductor layer 132a after exposure to the etchant is different from the etching rate of the second semiconductor layer 132b after exposure to the etchant. Notably, the etching rate of the first semiconductor layer 132a after exposure to the etchant is greater than the etching rate of the second semiconductor layer 132b after exposure to the etchant. In some embodiments, when the first and second semiconductor layers 132a, 132b include n-type dopants, the etching rate of the first semiconductor layer 132a is greater than the etching rate of the second semiconductor layer 132b because the dopant concentration of the first semiconductor layer 132a is greater than that of the second semiconductor layer 132b. In some alternative embodiments, when the first semiconductor layer 132a and the second semiconductor layer 132b include p-type dopants, the etching rate of the first semiconductor layer 132a is greater than the etching rate of the second semiconductor layer 132b because the dopant concentration of the first semiconductor layer 132a is less than the dopant concentration of the second semiconductor layer 132b.

[0055] Still refer to Figure 8D Because the etching rate of the first semiconductor layer 132a is greater than the etching rate of the second semiconductor layer 132b, a larger portion of the first semiconductor layer 132a is removed. In some embodiments, after the etch-back operation, a step height Hs is formed between the top surface of the second semiconductor layer 132b and the top surface of the first semiconductor layer 132a. The step height Hs ranges from approximately 0 angstroms to approximately 200 angstroms, but the present invention is not limited thereto. In some embodiments, the etch-back operation can be used to remove the voids or seams 133a in the first semiconductor layer 132a and the voids or seams 133b in the second semiconductor layer 132b.

[0056] In some comparative embodiments, when the etching rate of the second semiconductor layer 132b is equal to or greater than the etching rate of the first semiconductor layer 132a, a portion of the gap or seam 133b may be left on the semiconductor layer by an etch-back operation to form a groove. In some comparative embodiments, the etch-back operation may be used to expand the groove.

[0057] refer to Figure 8E , a hard mask layer 138 may be formed on the substrate 102. In some embodiments, the hard mask layer 138 may be conformally formed so that the hard mask layer 138 covers the sidewalls of the gate structure 120, the top surface of the first semiconductor layer 132a, and the top surface of the second semiconductor layer 132b. In some embodiments, the hard mask layer 138 comprises silicon nitride, but the present invention is not limited thereto. The thickness of the hard mask layer 138 may be used to define the width of the select gate to be formed. In some embodiments, the thickness of the hard mask layer 138 is between about Arrive at the appointment However, the embodiments of the present invention are not limited thereto.

[0058] refer to Figure 8F The hard mask layer 138 is etched back to remove its lateral portion and form hard mask spacers 139 on the sidewalls of the gate structure 120. In addition, a portion of the second semiconductor layer 132b between the two groups G1 and G2 is exposed by the hard mask spacers 139. However, the first semiconductor layer 132a between the two gate structures 120 in the groups G1 and G2 is still covered by the hard mask spacers 139.

[0059] refer to Figure 8G The portion of the second semiconductor layer 132b and the portion of the first semiconductor layer 132a between the two groups G1 and G2 exposed by the hard mask spacers 139 are removed through the hard mask spacers 139 to form the gate structure 130 and expose a portion of the substrate 102. In some embodiments, an etchant is used to remove the portion of the second semiconductor layer 132b and the portion of the first semiconductor layer 132a. In some embodiments, the etchant has a similar etch rate for the first semiconductor layer 132a and the second semiconductor layer 132b. It should be noted that because the seam or void 133b is removed during the etch-back operation, the hard mask layer 138 does not remain on the second semiconductor layer 132b after forming the hard mask spacers 139. Therefore, the first semiconductor layer 132a and the second semiconductor layer 132b between the two groups G1 and G2 can be removed, and the problem of semiconductor material residue can be alleviated. In addition, during the formation of the gate structure 130, the first semiconductor layer 132a between the two gate structures 120 in the groups G1 and G2 is protected by the hard mask spacers 139.

[0060] In some comparative embodiments, when the above-mentioned grooves are formed after the etch-back operation, the grooves may be filled with a hard mask layer. The hard mask layer cannot be removed during the formation of the hard mask spacers 139, and the hard mask residue may hinder the removal of the semiconductor layer during the formation of the gate structure 130. Therefore, the semiconductor residue problem occurs.

[0061] Still refer to Figure 8G The first semiconductor layer 132a is electrically isolated from the first doped region 150a by spacers 144, and the first semiconductor layer 132a may be referred to as the gate structure 140. In some embodiments, the gate structure 130 functions as a select gate (SG) and the gate structure 140 functions as an erase gate (EG). Furthermore, the width of the select gate 130 may be defined by the width of the hard mask spacer 139. In some embodiments, the select gate 130 and the erase gate 140 may comprise different compositions. For example, the select gate 130 may include the first semiconductor layer 132a and the second semiconductor layer 132b, while the erase gate 140 may include the first semiconductor layer 132a.

[0062] In some embodiments, after forming the select gate 130 and the erase gate 140, a sacrificial gate structure (not shown) including an interface dielectric (IL), a high-k gate dielectric layer, and a semiconductor layer may be formed on the substrate 102 in the logic region 104b, and spacers may be formed on the substrate 102 in the logic region 104b.

[0063] refer to Figure 8H , so that a plurality of second doped regions 150b are formed in the portion of the substrate 102 exposed between the pair of two gate structures 130. In some embodiments, the second doped regions 150b act as drain regions. Additionally, in some embodiments, the first doped region 150a and / or the second doped region 150b may be part of an epitaxial layer (e.g., a silicon epitaxial layer formed by an epitaxial process). As mentioned above, the first doped region 150a embedded between the two gate structures 120 acts as a common source region, while the two second doped regions 150b embedded between the two gate structures 130 act as bit lines. In other words, the pair of gate structures 120 and the common source region 150a are arranged between the two bit lines 150b. Furthermore, a channel region is defined between the bit lines 150b and the common source region 150a. In some embodiments, the source / drain region 118 (e.g., Figure 1 ) may be simultaneously formed in the substrate 102 in the logic region 104b.

[0064] refer to Figure 8I, a dielectric structure 160 may be formed on the substrate 102. In some embodiments, although not shown, the dielectric structure 160 may include a contact etch stop layer (CESL). The dielectric structure 160 may further include an interlayer dielectric (ILD) layer on the substrate 102. In some embodiments, the ILD layer is formed to embed all devices on the substrate 102.

[0065] refer to Figure 8J A planarization operation is performed to remove excess portions of the ILD layer, a portion of the patterned mask structure 127, a portion of the hard mask spacer 139, and a portion of the spacer 152. Thus, the top surfaces of the gate structures 130 and 140 are exposed. In some embodiments, a metal silicide 154 may be formed on the top surfaces of the gate structures 130 and 140. Additionally, the metal silicide 154 may be formed on the top surface of the second doped region 150b. The metal silicide 154 is formed to reduce contact resistance. Therefore, even though the gate structure 130 has two different layers (i.e., the first semiconductor layer 132a and the second semiconductor layer 132b), contact resistance is not a problem. Furthermore, the metal silicide 154 on the top surface of the second doped region 150b may be a contact pad, but embodiments of the present invention are not limited thereto. Additionally, the metal silicide 154 may include nickel silicide, cobalt silicide, or titanium silicide, but embodiments of the present invention are not limited thereto. In some embodiments, the top surface of the dummy gate structure may be exposed by planarization. In some embodiments, a protective layer (not shown) may be formed in the memory region 104a, and the dummy gate structure may be removed so that a gate trench is formed in the logic region 104b. Subsequently, a metal gate is formed to fill the gate trench. After the metal gate is formed, a dielectric layer is formed on the substrate 102. In some embodiments, the dielectric layer refers to a portion of the dielectric structure 160, such as Figure 8I As shown in .

[0066] refer to Figure 8K , a dielectric structure 161 may be formed on the substrate 102, and a connection structure 162 may be formed in the dielectric structure 161. Thereafter, an interconnect structure 170 including a dielectric layer 172 and a conductive member 174 (which includes a metal layer and a via) is formed on the dielectric structure 161. Figure 8K As shown in FIG, the conductive member 174 can be electrically connected to the connection structure 162. Thus, a semiconductor structure having a semiconductor device such as Figure 3 As shown in .

[0067] According to the methods provided by some embodiments of the present invention, first and second semiconductor layers 132a and 132b having different etching rates are provided. Therefore, seams or voids 133b can be removed during the etch-back operation. Consequently, the problem of hard mask residue and semiconductor material residue can be alleviated, and the manufacturing yield can be improved.

[0068] Please refer to Figures 9A to 9D , which is a cross-sectional view of a semiconductor structure of a memory device at different stages of fabrication constructed according to aspects of one or more embodiments of the present invention. It should be noted that Figures 8A to 8K and Figures 9A to 9D The same elements in FIG. are depicted by the same reference numerals, and for the sake of brevity, 8A to 8A are omitted in the description. Figure 8K and Figures 9A to 9D In some embodiments, the unused space between the gate structures 120 is not filled with the first semiconductor layer 132a. Figure 9A , the first semiconductor layer 132a is conformally formed on the substrate 102 and the gate structure 120. Thus, the first semiconductor layer 132a covers the top surface of the substrate 102, the top surface of the gate structure 120, the top surface of the dielectric layer 134, and the sidewalls of the gate structure 120.

[0069] After forming the first semiconductor layer 132a, the second semiconductor layer 132b is formed on the first semiconductor layer 132a. The thickness of the second semiconductor layer 132b is greater than that of the first semiconductor layer 132a. In some embodiments, by adjusting the thickness of the first semiconductor layer 132a and the second semiconductor layer 132b, the unused space between the gate structures 120 in each group G1 and G2 and the unused space between the two groups G1 and G2 can be filled with the second semiconductor layer 132b. In some embodiments, a seam or gap 133b can be formed in the second semiconductor layer 132b, such as Figure 9A In addition, a sacrificial layer 135 is formed on the second semiconductor layer 132b to achieve a flat top surface for subsequent etching processes. Therefore, the top surface of the formed sacrificial layer 135 is substantially planar.

[0070] refer to Figure 9BAn etch-back operation is performed using an etchant to remove the sacrificial layer 135, a portion of the second semiconductor layer 132b, and a portion of the first semiconductor layer 132a, thereby exposing the upper portion of the gate structure 120. In some embodiments, due to the different dopant concentrations of the first semiconductor layer 132a and the second semiconductor layer 132b, the etching rate of the first semiconductor layer 132a after exposure to the etchant is greater than the etching rate of the second semiconductor layer 132b after exposure to the etchant, thereby removing a larger portion of the first semiconductor layer 132a. In some embodiments, a step height Hs is formed between the top surface of the second semiconductor layer 132b and the top surface of the first semiconductor layer 132a. The step height Hs ranges from approximately 0 angstroms to approximately 200 angstroms, but embodiments of the present invention are not limited thereto. In some embodiments, the etch-back operation can be used to remove voids or seams 133b in the second semiconductor layer 132b.

[0071] refer to Figure 9C , a hard mask layer (not shown) is formed on the substrate 102. Subsequently, the hard mask layer is etched back to remove its lateral portion and form hard mask spacers 139 on the sidewalls of the gate structure 120. In addition, a portion of the second semiconductor layer 132b between the two groups G1 and G2 is exposed by the hard mask spacers 139. However, the portions of the first semiconductor layer 132a and the second semiconductor layer 132b between the two gate structures 120 in each group G1 and G2 are covered by the hard mask spacers 139.

[0072] refer to Figure 9D The portions of the second semiconductor layer 132b and the first semiconductor layer 132a between the two groups G1 and G2 exposed by the hard mask spacers 139 are removed through the hard mask spacers 139 to form the gate structure 130 and expose a portion of the substrate 102. In some embodiments, an etchant is used to remove the portions of the second semiconductor layer 132b and the first semiconductor layer 132a. In some embodiments, the etchant has similar etching rates for the first semiconductor layer 132a and the second semiconductor layer 132b. As mentioned above, because the seams or voids 133b are removed during the etch-back operation, the hard mask layer 138 does not remain on the second semiconductor layer 132b after the hard mask spacers 139 are formed; therefore, the first semiconductor layer 132a and the second semiconductor layer 132b between the two groups G1 and G2 can be removed, and the problem of semiconductor material residue can be alleviated. However, during the formation of the gate structure 130, portions of the first semiconductor layer 132a and the second semiconductor layer 132b between the two gate structures 120 in each group G1, G2 are protected by the hard mask spacer 139. Figure 9DAs shown in FIG, first semiconductor layer 132a is electrically isolated from first doped region 150a by spacer 144 and may be referred to as gate structure 140. In some embodiments, gate structure 130 functions as a select gate and gate structure 140 functions as an erase gate. In some embodiments, select gate 130 and erase gate 140 may comprise similar compositions. For example, both select gate 130 and erase gate 140 include first semiconductor layer 132a and second semiconductor layer 132b. However, first semiconductor layer 132a in select gate 130 has an L-shape, while first semiconductor layer 132a in erase gate 140 has a U-shape.

[0073] Furthermore, the above operations may be performed to form Figure 1 or Figure 2 The semiconductor structure with the memory device shown in FIG. 4 is shown; therefore, such details are omitted from the description for the sake of brevity.

[0074] Please refer to FIG. 10A to FIG. 10D , which is a cross-sectional view of a semiconductor structure of a memory device at different stages of fabrication constructed according to aspects of one or more embodiments of the present invention. It should be noted that Figures 8A to 8K and FIG. 10A to FIG. 10D The same elements in FIG. are depicted by the same reference numerals, and for the sake of brevity, 8A to 8A are omitted in the description. Figure 8K and FIG. 10A to FIG. 10D Details of the same components shown in Figure 10A As shown in FIG, the first semiconductor layer 132a is conformally formed on the substrate 102 and the gate structure 120. Therefore, the first semiconductor layer 132a covers the top surface of the substrate 102, the top surface of the gate structure 120, the top surface of the dielectric layer, and the sidewalls of the gate structure 120. After the first semiconductor layer 132a is formed, the second semiconductor layer 132b is formed on the first semiconductor layer 132a. In some embodiments, the third semiconductor layer 132c may be formed before the second semiconductor layer 132b is formed, as shown in FIG. Figure 10A. The third semiconductor layer 132c is formed between the first semiconductor layer 132a and the second semiconductor layer 132b. In some embodiments, the thickness ratio of the first semiconductor layer 132a, the second semiconductor layer 132b, and the third semiconductor layer 132c may be 1:1:1, but the embodiments of the present invention are not limited thereto. For example, in other embodiments, the thickness of the second semiconductor layer 132b is greater than the thickness of the first semiconductor layer 132a and the thickness of the third semiconductor layer 132c. In some embodiments, the space between the two groups G1 and G2 is filled with the second semiconductor layer 132b. In some embodiments, the unused space between the two gate structures 120 in each group G1 and G2 may be filled with the first semiconductor layer 132a, the second semiconductor layer 132b, or the third semiconductor layer 132c, depending on the spacing S1 between the two gate structures 120 and the thicknesses of the first semiconductor layer 132a, the second semiconductor layer 132b, and the third semiconductor layer 132c.

[0075] The three semiconductor layers 132a, 132b, and 132c may include the same semiconductor material, such as silicon. In some embodiments, when the gate structure to be formed is an n-type gate structure, the first semiconductor layer 132a, the second semiconductor layer 132b, and the third semiconductor layer 132c may include an n-type dopant, such as As, Sb, or P. When the gate structure to be formed is a p-type gate structure, the first semiconductor layer 132a, the second semiconductor layer 132b, and the third semiconductor layer 132c may include a p-type dopant, such as B. However, the dopant concentration of the third semiconductor layer 132c is between the dopant concentration of the first semiconductor layer 132a and the dopant concentration of the second semiconductor layer 132b. In some embodiments, when the three semiconductor layers 132a, 132b, and 132c are used to form an n-type gate, the dopant concentration of (for example) P in the first semiconductor layer 132a is greater than approximately 1E19 cm -3 The dopant concentration of P in the second semiconductor layer 132b is less than about 5E18 cm -3 , and the dopant concentration of P in the third semiconductor layer 132c is between about 1E19cm -3 To approximately 5E18cm -3 In some alternative embodiments, when the three semiconductor layers 132a, 132b, and 132c are used to form a p-type gate, the dopant concentration of (for example) B in the first semiconductor layer 132a is less than about 5E18 cm -3 , the dopant concentration of B in the second semiconductor layer 132b is greater than about 1E19 cm -3 , and the dopant concentration of B in the third semiconductor layer 132c is between about 5E18cm -3 To approximately 1E19cm -3, but the present invention is not limited thereto. Apparently, due to the different dopant concentrations of the first semiconductor layer 132a, the second semiconductor layer 132b, and the third semiconductor layer 132c, the etching rate of the third semiconductor layer 132c after exposure to the etchant is between the etching rates of the first semiconductor layer 132a and the second semiconductor layer 132b.

[0076] Furthermore, a sacrificial layer 135 is formed on the second semiconductor layer 132b to achieve a flat top surface for subsequent etching processes. Therefore, the top surface of the formed sacrificial layer 135 is substantially planar.

[0077] Still refer to Figure 10A In some embodiments, the seam or gap 133a may be formed in the first semiconductor layer 132a or the third semiconductor layer 132c between two gate structures 120 in groups G1 and / or G2. In some embodiments, the seam or gap 133b may be formed in the second semiconductor layer 132b between groups G1 and G2.

[0078] refer to Figure 10B An etch-back operation is performed using an etchant to remove the sacrificial layer 135, a portion of the second semiconductor layer 132b, a portion of the third semiconductor layer 132c, and a portion of the first semiconductor layer 132a, thereby exposing the upper portion of the gate structure 120. In some embodiments, because the etching rate of the first semiconductor layer 132a is greater than the etching rate of the third semiconductor layer 132c, and the etching rate of the third semiconductor layer 132c is greater than the etching rate of the second semiconductor layer 132b, a step height may be formed between the top surface of the third semiconductor layer 132c and the top surface of the first semiconductor layer 132a, and another step height may be formed between the top surface of the third semiconductor layer 132c and the top surface of the second semiconductor layer 132b. In some embodiments, the semiconductor layers 132a, 132b, and 132c between the two groups G1 and G2 may have a pyramidal configuration, but embodiments of the present invention are not limited thereto. In some embodiments, the seams or gaps 133a in the first semiconductor layer 132a or the third semiconductor layer 132c and the seams or gaps 133b in the second semiconductor layer 132b may be removed by an etch-back operation.

[0079] refer to Figure 10C, a hard mask layer (not shown) can be formed on the substrate 102. Subsequently, the hard mask layer is etched back to remove its lateral portion and form hard mask spacers 139 on the sidewalls of the gate structure 120. In addition, a portion of the second semiconductor layer 132b between the two groups G1 and G2 is exposed by the hard mask spacers 139. In some embodiments, a portion of the third semiconductor layer 132c between the two groups G1 and G2 may also be exposed by the hard mask spacers 139. However, portions of the three semiconductor layers 132a, 132b, and 132c between the two gate structures 120 in each group G1 and G2 are covered by the hard mask spacers 139.

[0080] refer to Figure 10D Portions of the second semiconductor layer 132b, the third semiconductor layer 132c, and the first semiconductor layer 132a between the two groups G1 and G2 and exposed by the hard mask spacers 139 are removed through the hard mask spacers 139 to form the gate structure 130 and expose a portion of the substrate 102. In some embodiments, an etchant is used to remove portions of the second semiconductor layer 132b, the third semiconductor layer 132c, and the first semiconductor layer 132a. In some embodiments, the etchant has a similar etch rate for the first semiconductor layer 132a, the second semiconductor layer 132b, and the third semiconductor layer 132c. As mentioned above, because the seams or voids 133b are removed during the etch-back operation, the hard mask layer 138 does not remain on the second semiconductor layer 132b after the hard mask spacers 139 are formed; thus, the first semiconductor layer 132a and the second semiconductor layer 132b between the two groups G1 and G2 can be removed, and the problem of semiconductor material residue can be alleviated. However, during the formation of the gate structure 130, the semiconductor layer between the two gate structures 120 in each group G1, G2 is protected by the hard mask spacer 139. Figure 10D As shown in FIG, first semiconductor layer 132a is electrically isolated from first doped region 150a by spacer 144 and may be referred to as gate structure 140. In some embodiments, gate structure 130 functions as a select gate and gate structure 140 functions as an erase gate. In some embodiments, select gate 130 and erase gate 140 may comprise similar compositions. For example, both select gate 130 and erase gate 140 include first semiconductor layer 132a and third semiconductor layer 132c. However, first semiconductor layer 132a in select gate 130 has an L-shape, while first semiconductor layer 132a in erase gate 140 has a U-shape.

[0081] Figure 11 is a cross-sectional view of a semiconductor structure of a memory device in a manufacturing stage constructed according to aspects of one or more embodiments of the present invention. It should be noted that Figure 10D and Figure 11 Like elements in the description are depicted by like element numbers, and details of like elements are omitted from the description for the sake of brevity. As mentioned above, the width of the gate structure 130 can be adjusted by the thickness of the hard mask spacer 139. In addition, the composition of the gate structure can be adjusted by the thickness of the first semiconductor layer 132a, the second semiconductor layer 132b, and the third semiconductor layer 132c. In some embodiments, by adjusting the thickness of the semiconductor layers 132a, 132b, and 132c and adjusting the thickness of the hard mask spacer 139, the second semiconductor layer 132b can remain in an appropriate position on the substrate 102. In some embodiments, the gate structure 130 and the gate structure 140 may include similar compositions. In such embodiments, both the gate structure 130 and the gate structure 140 may include the first semiconductor layer 132a, the third semiconductor layer 132c, and the second semiconductor layer 132b, as Figure 11 . However, while the first and third semiconductor layers 132a and 132c in the gate structure 130 have an L-shape, the first and third semiconductor layers 132a and 132c in the gate structure 140 have a U-shape. In other embodiments, the gate structures 130 and 140 may include different compositions. For example, the gate structure 140 may include the first and third semiconductor layers 132a and 132c, while the select gate 130 may include the first, third, and second semiconductor layers 132a, 132c, and 132b.

[0082] In addition, both the first semiconductor layer 132a and the third semiconductor layer 132c in the select gate 130 have an L shape, and the first semiconductor layer 132a and the third semiconductor layer 132c in the erase gate 140 have a U shape.

[0083] Furthermore, the above operations may be performed to form Figure 4 The semiconductor structure with the memory device shown in FIG. 4 is shown; therefore, such details are omitted from the description for the sake of brevity.

[0084] Please refer to Figure 12A and Figure 12B , which is a cross-sectional view of a semiconductor structure of a memory device at different stages of fabrication constructed according to aspects of one or more embodiments of the present invention. It should be noted that Figures 8A to 8K and FIG. 12A to FIG. 12B The same elements in FIG. are depicted by the same reference numerals, and for the sake of brevity, 8A to 8A are omitted in the description. Figure 8K and FIG. 12A to FIG. 12B In some embodiments, four semiconductor layers 132a, 132b, 132c, and 132d are formed between the gate structures 120. Figure 12AAs shown in FIG, the first semiconductor layer 132a is conformally formed on the substrate 102 and the gate structure 120. Therefore, the first semiconductor layer 132a covers the top surface of the substrate 102, the top surface of the gate structure 120, the top surface of the dielectric layer 134, and the sidewalls of the gate structure 120. After the first semiconductor layer 132a is formed, the second semiconductor layer 132b is formed on the first semiconductor layer 132a. In some embodiments, the third semiconductor layer 132c and the fourth semiconductor layer 132d may be formed before the second semiconductor layer 132b is formed. Figure 12A That is, the third semiconductor layer 132c and the fourth semiconductor layer 132d are formed between the first semiconductor layer 132a and the second semiconductor layer 132b. In some embodiments, the fourth semiconductor layer 132d may be formed between the first semiconductor layer 132a and the third semiconductor layer 132c. In some alternative embodiments, the fourth semiconductor layer 132d may be formed between the third semiconductor layer 132c and the second semiconductor layer 132b, as shown in FIG. Figure 12A As shown in .

[0085] In some embodiments, the thickness ratio of the first semiconductor layer 132a, the second semiconductor layer 132b, the third semiconductor layer 132c, and the fourth semiconductor layer 132d may be 1:1:1:1, but the present invention is not limited thereto. In some embodiments, the thickness of the second semiconductor layer 132b is greater than the thickness of the first semiconductor layer 132a, the thickness of the third semiconductor layer 132c, and the thickness of the fourth semiconductor layer 132d. In some embodiments, the space between the two gate structures 120 in each group G1 and G2 may be filled with the first semiconductor layer 132a, the second semiconductor layer 132b, the third semiconductor layer 132c, or the fourth semiconductor layer 132d, depending on the distance S1 between the two gate structures 120 in each group G1 and G2 and the thickness of the first semiconductor layer 132a, the second semiconductor layer 132b, the third semiconductor layer 132c, and the fourth semiconductor layer 132d.

[0086] The four semiconductor layers 132a, 132b, 132c, and 132d may comprise the same semiconductor material, such as silicon. In some embodiments, when the gate structure to be formed is an n-type gate structure, the four semiconductor layers 132a, 132b, 132c, and 132d may comprise an n-type dopant, such as As, Sb, or P. When the gate structure to be formed is a p-type gate structure, the four semiconductor layers 132a, 132b, 132c, and 132d may comprise a p-type dopant, such as B. However, the dopant concentrations of the first semiconductor layer 132a, the second semiconductor layer 132b, the third semiconductor layer 132c, and the fourth semiconductor layer 132d differ from one another. This difference in dopant concentration results in a difference in the etching rates of the four layers. Consequently, the etching rates of the four layers differ from one another.

[0087] Furthermore, a sacrificial layer (not shown) is formed on the second semiconductor layer 132b to achieve a flat top surface for subsequent etching processes.

[0088] In some embodiments, a seam or a gap (not shown) may be formed in the first semiconductor layer 132a, the third semiconductor layer 132c, or the fourth semiconductor layer 132d between two gate structures 120 in group G1 or G2. In some embodiments, a seam or a gap (not shown) may be formed in the second semiconductor layer 132b between two groups G1 and G2.

[0089] Still refer to Figure 12A , an etch-back operation is performed to remove the sacrificial layer, a portion of the second semiconductor layer 132b, a portion of the fourth semiconductor layer 132d, a portion of the third semiconductor layer 132c, and a portion of the first semiconductor layer 132a using an etchant, so that the upper portion of the gate structure 120 is exposed. In some embodiments, because the etching rates of the first semiconductor layer 132a, the third semiconductor layer 132c, the fourth semiconductor layer 132d, and the second semiconductor layer 132b are different from each other, a step height may be formed, such as Figure 12A Obviously, the seams or voids formed in the semiconductor layer can be removed by an etch-back operation.

[0090] refer to Figure 12B, a hard mask layer (not shown) may be formed on the substrate 102. Subsequently, the hard mask layer is etched back to remove lateral portions thereof, and hard mask spacers 139 are formed on the sidewalls of the gate structure 120. Furthermore, a portion of the second semiconductor layer 132b between the two groups G1 and G2 is exposed by the hard mask spacers 139. Subsequently, the portions of the second semiconductor layer 132b, the fourth semiconductor layer 132d, the third semiconductor layer 132c, and the first semiconductor layer 132a between the two groups G1 and G2 exposed by the hard mask spacers 139 are removed to form the gate structure 130 and expose a portion of the substrate 102. In some embodiments, an etchant is used to remove portions of the semiconductor layers 132a, 132b, 132c, and 132d. In some embodiments, the etchant has similar etching rates for the first semiconductor layer 132a, the second semiconductor layer 132b, the third semiconductor layer 132c, and the fourth semiconductor layer 132d. As mentioned above, because the seams or voids are removed during the etch-back operation, no hard mask layer remains on the second semiconductor layer 132b after forming the hard mask spacers 139. Consequently, portions of the four semiconductor layers 132a, 132b, 132c, and 132d between the two groups G1 and G2 can be removed, and the problem of residual semiconductor material can be alleviated. However, during the formation of the gate structures 130, the semiconductor layers between the two gate structures 120 in each group are still protected by the hard mask spacers 139.

[0091] like Figure 12B , the first semiconductor layer 132a is electrically isolated from the first doped region 150a by spacers 144, and the first semiconductor layer 132a may be referred to as the gate structure 140. In some embodiments, the gate structure 130 functions as a select gate, and the gate structure 140 functions as an erase gate. In some embodiments, the select gate 130 and the erase gate 140 may comprise different compositions. For example, the erase gate 140 may include the first semiconductor layer 132a, the third semiconductor layer 132c, and the fourth semiconductor layer 132d, while the select gate 130 may include the first semiconductor layer 132a, the second semiconductor layer 132b, the third semiconductor layer 132c, and the fourth semiconductor layer 132d. However, in some embodiments, the erase gate 140 and the select gate 130 may have similar configurations. In such embodiments, both the selection gate 130 and the erase gate 140 may include a first semiconductor layer 132a, a second semiconductor layer 132b, a third semiconductor layer 132c, and a fourth semiconductor layer 132d, but the first semiconductor layer 132a, the third semiconductor layer 132c, and the fourth semiconductor layer 132d in the selection gate 130 may have a shape different from the first semiconductor layer 132a, the third semiconductor layer 132c, and the fourth semiconductor layer 132d in the erase gate 140, although not shown in the figures.

[0092] Furthermore, the above operations may be performed to form Figure 5 The semiconductor structure with the memory device shown in FIG. 4 is shown; therefore, such details are omitted from the description for the sake of brevity.

[0093] In some embodiments, operations may be performed to form Figure 6 SONOS split-gate flash memory shown in Figure 1.

[0094] It should be understood that in the above method, semiconductors having different dopant concentrations are formed to fill the gaps between the gate structures, thereby providing different etch rates. Due to the differences in etch rates, the profile of the thinned polysilicon layer is modified during the etch-back operation. In some embodiments, even if seams or voids are formed during the formation of the polysilicon layer, the recess problem can be alleviated after the etch-back operation. Consequently, silicon residue defects are reduced, thereby improving yield.

[0095] According to an embodiment of the present invention, a memory structure for a memory device is provided. The semiconductor structure includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer, wherein the first layer is interposed between the second layer and the first gate structure. In some embodiments, the first layer and the second layer include the same semiconductor material and the same dopant. In some embodiments, the first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the first dopant concentration.

[0096] According to another embodiment, a memory device is provided. The memory device includes: a substrate; a first gate structure located on the substrate; a first doped region located in the substrate; and a second gate structure located on the substrate and adjacent to the first gate structure. In some embodiments, the first gate structure is disposed between the second gate structure and the first doped region, and the second gate structure is located on the substrate and adjacent to the first gate structure. In some embodiments, the second gate structure includes a first layer having a first dopant concentration and a second layer having a second dopant concentration different from the first dopant concentration.

[0097] According to an embodiment of the present invention, a method for forming a semiconductor structure is provided. The method includes the following operations: providing a substrate, the substrate including a first gate structure formed thereon. Forming a first semiconductor layer having a first dopant concentration on the substrate and the first gate structure. Forming a second semiconductor layer having a second dopant concentration on the first semiconductor layer. Performing an etchback operation to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer using an etchant. In some embodiments, an etch rate of the first semiconductor layer after exposure to the etchant is greater than an etch rate of the second semiconductor layer after exposure to the etchant. Forming hard mask spacers on the first and second semiconductor layers. In some embodiments, a portion of the second semiconductor layer is exposed through the hard mask spacers. Removing the portions of the second and first semiconductor layers through the hard mask spacers to form a second gate structure and expose a portion of the substrate.

[0098] The features of several embodiments have been summarized above so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art will appreciate that they can readily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the embodiments of the present invention.

[0099] Explanation of symbols

[0100] 10: Method

[0101] 11: Operation

[0102] 12: Operation

[0103] 13: Operation

[0104] 14: Operation

[0105] 15: Operation

[0106] 16: Operation

[0107] 100a: Semiconductor structure

[0108] 100b: Semiconductor structure

[0109] 100c: Semiconductor structure

[0110] 100d: Semiconductor structure

[0111] 100e:Semiconductor structure

[0112] 100f: semiconductor structure

[0113] 102: substrate

[0114] 104a: memory area

[0115] 104b: Peripheral area / logic area

[0116] 106a: Isolation Structure

[0117] 106b: Isolation Structure

[0118] 110: Memory device

[0119] 112a: Logic device / power device

[0120] 112b:Logic device / core device

[0121] 113: Virtual structure

[0122] 114: Metal gate

[0123] 116: Gate dielectric layer

[0124] 118: Source / drain region

[0125] 120: first gate structure

[0126] 122: floating gate / first gate electrode

[0127] 124: control gate / second gate electrode

[0128] 126: Dielectric structure

[0129] 127: Patterned mask structure

[0130] 128: dielectric layer

[0131] 130: Second gate structure / select gate (SG)

[0132] 132a: first layer / first semiconductor layer

[0133] 132b: Second layer / second semiconductor layer

[0134] 132c: third layer / third semiconductor layer

[0135] 132d: Fourth layer / fourth semiconductor layer

[0136] 133a: Seams / Gap

[0137] 133b: Seams / Gap

[0138] 134: dielectric layer

[0139] 135: Sacrificial layer

[0140] 136: Oxide-Nitride-Oxide (ONO) Structure

[0141] 138: Hard mask layer

[0142] 139: Hard mask spacer

[0143] 140: Third gate structure / erase gate (EG)

[0144] 144: Isolation

[0145] 150a: first doped region / source region

[0146] 150b: second doped region / bit line

[0147] 152: spacer

[0148] 154: Metal silicide

[0149] 160: Interlayer dielectric (ILD) layer / dielectric structure

[0150] 161: Dielectric structure

[0151] 162: Connection structure

[0152] 170:Interconnection structure

[0153] 172: dielectric layer

[0154] 174: Conductive member

[0155] G1: Group 1

[0156] G2: Group 2

[0157] Hs: step height

[0158] S1: Spacing

[0159] S2: Spacing

[0160] θ: Angle

Claims

1. A semiconductor structure for a memory device, comprising: a first gate structure; and a second gate structure adjacent to the first gate structure, The second gate structure includes a first layer and a second layer, the first layer is between the second layer and the first gate structure, the first layer and the second layer include the same semiconductor material and the same dopant, the first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the first dopant concentration, and The second gate structure includes an n-type gate structure, and the second dopant concentration of the second layer is less than the first dopant concentration of the first layer. 2 . The semiconductor structure of claim 1 , further comprising a third gate structure, wherein the first gate structure is disposed between the second gate structure and the third gate structure. 3 . The semiconductor structure according to claim 1 , further comprising a metal silicide formed on a top surface of the second gate structure. 4 . The semiconductor structure of claim 1 , wherein the second gate structure further comprises a third layer between the first layer and the second layer, and the third layer has a third dopant concentration between the first dopant concentration of the first layer and the second dopant concentration of the second layer. 5 . The semiconductor structure of claim 4 , wherein the second gate structure further comprises a fourth layer between the first layer and the second layer, and the fourth layer is adjacent to the third layer and has a fourth dopant concentration greater than the third dopant concentration of the third layer.

6. A memory device comprising: substrate; a first gate structure located on the substrate; a first doped region located in the substrate; and a second gate structure located on the substrate and adjacent to the first gate structure, wherein the first gate structure is disposed between the second gate structure and the first doped region; wherein the second gate structure includes a first layer having a first dopant concentration and a second layer having a second dopant concentration different from the first dopant concentration, and The second gate structure includes a p-type gate structure, and the second dopant concentration of the second layer is greater than the first dopant concentration of the first layer.

7. The memory device of claim 6, wherein the first gate structure comprises a floating gate on the substrate, a control gate on the floating gate, and a dielectric structure between the floating gate and the control gate, and the second gate structure comprises a select gate.

8. The memory device of claim 7, further comprising an erase gate on the first doped region.

9. The memory device of claim 6, wherein the first gate structure comprises a select gate and the second gate structure comprises a control gate.

10. The memory device of claim 6, further comprising a metal silicide formed on a top surface of the second gate structure.

11. The memory device of claim 8 , wherein the erase gate comprises a first erase gate layer and a second erase gate layer on the first erase gate layer, the first layer and the second layer of the second gate structure and the first erase gate layer and the second erase gate layer of the erase gate comprising the same semiconductor material and the same dopant.

12. The memory device of claim 6, wherein the second gate structure further comprises a third layer between the first layer and the second layer, and the third layer has a third dopant concentration between the first dopant concentration of the first layer and the second dopant concentration of the second dopant concentration.

13. A method for forming a semiconductor structure, comprising: receiving a substrate including a first gate structure formed thereon; forming a first semiconductor layer having a first dopant concentration on the substrate and the first gate structure; forming a second semiconductor layer having a second dopant concentration on the first semiconductor layer; performing an etch-back operation to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer using an etchant, wherein an etching rate of the first semiconductor layer after being exposed to the etchant is greater than an etching rate of the second semiconductor layer after being exposed to the etchant; forming a hard mask spacer on the first semiconductor layer and the second semiconductor layer, wherein a portion of the second semiconductor layer is exposed through the hard mask spacer; and The portion of the second semiconductor layer and a portion of the first semiconductor layer are removed through the hard mask spacers to form a second gate structure and expose a portion of the substrate. The method according to claim 13 , wherein a thickness of the second semiconductor layer is equal to or greater than a thickness of the first semiconductor layer. 15 . The method of claim 13 , further comprising forming a sacrificial layer on the second semiconductor layer before removing the portion of the second semiconductor layer and the portion of the first semiconductor layer using the etchant.

16. The method of claim 13, further comprising forming a third semiconductor layer between the first semiconductor layer and the second semiconductor layer, wherein an etch rate of the third semiconductor layer after exposure to the etchant is between the etch rate of the first semiconductor layer and the etch rate of the second semiconductor layer. The method according to claim 13 , wherein a step height is formed between a top surface of the second semiconductor layer and a top surface of the first semiconductor layer. 18 . The method of claim 13 , further comprising forming a first doped region in the substrate adjacent to the first gate structure and forming a second doped region in the substrate adjacent to the second gate structure after forming the second gate structure.

19. The method of claim 18, further comprising: The first doped region is formed before forming the first semiconductor layer.

20. The method of claim 19, further comprising: forming an isolation layer on the first doped region; and A third gate structure is formed on the spacer.

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