Vertical nonvolatile memory device including memory cell strings

Abstract

A vertical nonvolatile memory device is disclosed, comprising a memory cell string using a resistance change material. Each memory cell string of the nonvolatile memory device includes: a semiconductor layer extending in a first direction and having a first surface opposite to a second surface; a plurality of gates and a plurality of insulators arranged alternately in the first direction and extending in a second direction perpendicular to the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the first surface of the semiconductor layer and between the plurality of insulators and the first surface of the semiconductor layer; and a dielectric film extending in the first direction on the second surface of the semiconductor layer and having a plurality of mobile oxygen vacancies distributed therein.

Description

Technical Field

[0001] The inventive concept relates to a vertical nonvolatile memory device including memory cell strings. Background Art

[0002] A nonvolatile memory device used as a semiconductor memory device includes a plurality of memory cells that can store information even when power is off and can reuse the stored information when power is supplied. As examples of nonvolatile memory devices, nonvolatile memory devices can be used in mobile phones, digital cameras, personal digital assistants (PDAs), mobile computer devices, stationary computer devices, and other devices.

[0003] Recently, research has been conducted on the use of three-dimensional (or vertical) NAND (VNAND) in chips forming next-generation neuromorphic computing platforms or neural networks. In particular, technologies with high density and low power characteristics and capable of random access to memory cells are needed. Summary of the Invention

[0004] A vertical nonvolatile memory device including a memory cell string using a resistance change material is provided.

[0005] In particular, a vertical nonvolatile memory device is provided that includes a dielectric film including a mixture of a material of a semiconductor layer and a material of a resistance change layer between the semiconductor layer and the resistance change layer in a memory cell string.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to an embodiment, a nonvolatile memory device includes a plurality of memory cell strings. Each of the plurality of memory cell strings includes: a semiconductor layer extending in a first direction and having a first surface opposite to a second surface; a plurality of gates and a plurality of insulators extending in a second direction perpendicular to the first direction, the plurality of gates and the plurality of insulators being alternately arranged in the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the first surface of the semiconductor layer and between the plurality of insulators and the first surface of the semiconductor layer; and a dielectric film extending in the first direction on the second surface of the semiconductor layer, the dielectric film having a plurality of mobile oxygen vacancies distributed therein.

[0008] In some embodiments, the dielectric film may include a mixture of the material of the semiconductor layer and a transition metal oxide.

[0009] For example, in some embodiments, the material of the semiconductor layer may include at least one of Si, Ge, indium gallium zinc oxide (IGZO), and GaAs.

[0010] Furthermore, in some embodiments, the transition metal oxide may include, for example, an oxide of at least one of zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), and praseodymium (Pr).

[0011] As an example, in some embodiments, the ratio of the material of the semiconductor layer in the dielectric film may be, for example, about 20 at. % to about 80 at. %.

[0012] As another example, in some embodiments, the ratio of the material of the semiconductor layer in the dielectric film may be, for example, about 40 at. % to about 60 at. %.

[0013] In some embodiments, the ratio of the material of the semiconductor layer in the dielectric film may be constant within a deviation range of, for example, about 10% throughout the entire region of the dielectric film.

[0014] Furthermore, in some embodiments, the width of the dielectric film in the second direction may be, for example, about 1.5 nm to about 10 nm.

[0015] In some embodiments, the width of the dielectric film may be constant within a deviation range of, for example, about 10%, throughout the entire area of the dielectric film.

[0016] In some embodiments, the dielectric film may include a plurality of first layers and a plurality of second layers. The plurality of first layers may be formed of a material of the semiconductor layer, and the plurality of second layers may be formed of a transition metal oxide. The plurality of first layers and the plurality of second layers may be arranged alternately in a first direction.

[0017] For example, in some embodiments, the plurality of first layers and the plurality of second layers may be formed by atomic layer deposition or chemical vapor deposition.

[0018] In some embodiments, the thickness of each first layer and the thickness of each second layer may be, for example, about 0.1 nm to about 1 nm.

[0019] As an example, in some embodiments, a ratio of the thickness of each first layer to the sum of the thickness of each first layer and each second layer may be, for example, about 20% to about 80%.

[0020] As another example, in some embodiments, a ratio of the thickness of each first layer to the sum of the thickness of each first layer and each second layer may be, for example, about 40% to about 60%.

[0021] In some embodiments, the ratio of the thickness of each first layer to the sum of the thicknesses of each first layer and each second layer may be constant within a deviation range of, for example, about 10% throughout the entire area of the dielectric film.

[0022] In some embodiments, each of the plurality of memory cell strings may further include a resistance change layer facing the second surface of the semiconductor layer and extending in the first direction, and the dielectric film may be between the second surface of the semiconductor layer and the resistance change layer.

[0023] In some embodiments, the dielectric film may include a mixture of a material of the semiconductor layer and a material of the resistance change layer.

[0024] In this case, each corresponding memory cell string in the plurality of memory cell strings may include a plurality of memory cells, and the plurality of memory cells are arranged in a vertical stacking structure of the corresponding memory cell string. Each corresponding memory cell in the plurality of memory cells in the corresponding memory cell string may be defined by: a corresponding gate in the corresponding memory cell among the plurality of gates; a portion of the semiconductor layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction; a portion of the gate insulating layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction; a portion of the dielectric film of the corresponding memory cell string adjacent to the corresponding gate in the second direction; and a portion of the resistance change layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction.

[0025] In some embodiments, the nonvolatile memory device may further include control logic and a bit line. The control logic may be configured to control a voltage applied to at least one of the plurality of memory cell strings so that, during a read mode, a first voltage is applied to an unselected memory cell and a second voltage is applied to a selected memory cell. The first voltage may cause current to flow only through the semiconductor layer of the unselected memory cell. The second voltage may cause current to flow through all of the semiconductor layer, dielectric film, and resistance change layer of the selected memory cell. The bit line may be configured to apply a read voltage to the selected memory cell during a read mode. The unselected memory cell and the selected memory cell may be among the memory cells in the plurality of memory cell strings. The selected memory cell may be in a selected memory cell string among the plurality of memory cell strings.

[0026] In some embodiments, the absolute value of the second voltage may be smaller than the absolute value of the first voltage.

[0027] In some embodiments, the second voltage may have a value that makes the resistance of the semiconductor layer of the selected memory cell greater than or equal to a minimum resistance of a combination of resistances of the dielectric film and the resistance change layer of the selected memory cell.

[0028] Furthermore, in some embodiments, the second voltage may have a value that makes the resistance of the semiconductor layer of the selected memory cell less than or equal to the maximum resistance of the combined resistance of the dielectric film and the resistance change layer of the selected memory cell.

[0029] In some embodiments, the control logic can be configured to apply a third voltage to the selected memory cell during a mode different from the read mode, so as to cause current to flow only through the dielectric film and the resistance change layer of the selected memory cell in the selected memory cell string, and the absolute value of the second voltage can be greater than the absolute value of the third voltage.

[0030] In some embodiments, the control logic may be configured to control a voltage applied to at least one of the plurality of memory cell strings in a programming mode. The control logic may be configured to apply a first voltage to unselected memory cells and a third voltage to selected memory cells during the programming mode. The bit line may be configured to apply a positive programming voltage to the selected memory cell during the programming mode.

[0031] The dielectric film is configured such that, in response to a positive programming voltage being applied to a selected memory cell through a bit line, oxygen vacancies may move in a partial region of the dielectric film of the selected memory cell string corresponding to the selected memory cell toward an interface between a semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, a density of oxygen vacancies may increase at the interface between the semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, and a resistance of the partial region of the dielectric film of the selected memory cell string may decrease.

[0032] Furthermore, in some embodiments, the dielectric film can be configured to have at least four different resistance states.

[0033] In some embodiments, a dielectric film can be configured to change its resistance state based on a phenomenon in which electrons can be trapped and detrapped in traps formed by oxygen vacancies.

[0034] In some embodiments, the control logic may be configured to control a voltage applied to at least one of the plurality of memory cell strings in an erase mode. The control logic may be configured to apply a first voltage to unselected memory cells and a third voltage to selected memory cells during the erase mode. The bit line may be configured to apply a negative erase voltage to the selected memory cell during the erase mode.

[0035] In some embodiments, the dielectric film is configured such that, in response to a negative erase voltage being applied to a selected memory cell through a bit line, oxygen vacancies can move in a partial region of the dielectric film of the selected memory cell string corresponding to the selected memory cell in a direction away from an interface between the semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, a density of oxygen vacancies decreases at the interface between the semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, and a resistance of the partial region of the dielectric film of the selected memory cell string increases.

[0036] According to an embodiment, a nonvolatile memory device includes: a substrate; a plurality of bit lines extending in a first direction; and a plurality of memory cell strings spaced apart from one another on the substrate and extending in a vertical direction perpendicular to the first direction. Each of the plurality of memory cell strings is connected to a corresponding bit line among the plurality of bit lines. Each of the plurality of memory cell strings includes a resistance change layer, a dielectric film surrounding the resistance change layer, a semiconductor layer surrounding the dielectric film, a gate insulating layer surrounding the semiconductor layer, and a plurality of gates and a plurality of insulators surrounding the gate insulating layer. The plurality of gates and the plurality of insulators may be alternately stacked in a vertical direction. The plurality of bit lines may intersect the plurality of gates extending in a second direction perpendicular to the first direction and the vertical direction. Each of the plurality of memory cell strings includes a plurality of memory cells stacked one above the other. Each of the plurality of memory cells is defined by the following, at the same height within the same memory cell string among the plurality of memory cell strings: a corresponding gate among the plurality of gates connected to a corresponding portion of the resistance change layer; a corresponding portion of the resistance change layer; a corresponding portion of the dielectric film; a corresponding portion of the semiconductor layer; and a corresponding portion of the gate insulating layer. Each memory cell is configured to have movable oxygen vacancies inside corresponding portions of the dielectric film in response to a voltage applied to a corresponding gate and a corresponding bit line connected to the memory cell.

[0037] In some embodiments, the nonvolatile memory device may further include control logic coupled to the plurality of gates. The control logic may be configured to read a selected memory cell by applying a read voltage to the selected memory cell string using a corresponding bit line connected to the selected memory cell string, applying a first voltage to unselected memory cells and applying a second voltage to the selected memory cell using two of the plurality of gates. The selected memory cell string may include selected memory cells and unselected memory cells among the plurality of memory cells in the selected memory cell string. The first voltage may cause current to flow only through the corresponding portion of the semiconductor layer of the unselected memory cell. The second voltage may cause current to flow through the corresponding portion of the semiconductor layer, the corresponding portion of the dielectric film, and the corresponding portion of the resistance change layer of the selected memory cell.

[0038] In some embodiments, the nonvolatile memory device may further include control logic coupled to the plurality of gates. The control logic may be configured to program a selected memory cell by applying a positive programming voltage to the selected memory cell string using a corresponding bit line connected to the selected memory cell string while applying a first voltage to unselected memory cells using two of the plurality of gates and applying a turn-off voltage to the selected memory cell. The selected memory cell string may include selected memory cells and unselected memory cells among the plurality of memory cells in the selected memory cell string. The first voltage may cause current to flow only through the corresponding portion of the semiconductor layer of the unselected memory cell. The turn-off voltage may cause current to flow through the corresponding portion of the dielectric film and the corresponding portion of the resistance change layer of the selected memory cell.

[0039] In some embodiments, the nonvolatile memory device may further include control logic coupled to the plurality of gates. The control logic may be configured to erase a selected memory cell by applying a negative erase voltage to the selected memory cell string using a corresponding bit line connected to the selected memory cell string while applying a first voltage to unselected memory cells using two of the plurality of gates and applying a turn-off voltage to the selected memory cell. The selected memory cell string may include selected memory cells and unselected memory cells among the plurality of memory cells in the selected memory cell string. The first voltage may cause current to flow only through the corresponding portion of the semiconductor layer of the unselected memory cell. The turn-off voltage may cause current to flow through the corresponding portion of the dielectric film and the corresponding portion of the resistance change layer of the selected memory cell.

[0040] In some embodiments, the resistance change layer may include an oxide of at least one of zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), and praseodymium (Pr). The semiconductor layer may include silicon, germanium, indium gallium zinc oxide (IGZO), or GaAs. The gate insulating layer may include silicon oxide. The dielectric film may include a mixture of the material of the semiconductor layer and a transition metal oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other aspects, features and effects of certain embodiments of the present disclosure will be more apparent from the following description in conjunction with the accompanying drawings, in which:

[0042] Figure 1 is a block diagram illustrating a storage system according to an embodiment;

[0043] Figure 2 It shows Figure 1 A block diagram of an example implementation of a memory device is shown;

[0044] Figure 3 It shows Figure 1 A block diagram of a memory cell array is shown;

[0045] Figure 4 is a diagram showing an equivalent circuit corresponding to a memory block according to an embodiment;

[0046] Figure 5 is a perspective view schematically illustrating a physical structure corresponding to a memory block according to an embodiment;

[0047] Figure 6A It shows Figure 5 A cross-sectional view of a cross section of the memory block shown in the XZ plane;

[0048] Figure 6B It shows Figure 5 A cross-sectional view of a section of the memory block shown in the YZ plane;

[0049] Figure 7 FIG. 1 is a diagram showing a nonvolatile memory device in a programming mode according to an embodiment. Figure 4 A diagram of the equivalent circuit of a memory block;

[0050] Figure 8 is a diagram schematically illustrating current movement in a dielectric film and a resistance change layer in a programming mode according to an embodiment;

[0051] Figure 9 is a diagram showing an equivalent circuit in a read mode of a memory block according to an embodiment;

[0052] Figure 10 is a diagram illustrating current movement in a selected memory cell in a read mode according to an embodiment;

[0053] Figure 11 is a transmission electron microscope (TEM) photograph showing a structure designed to test the operation of a memory cell according to an embodiment;

[0054] Figure 12 Shows the simulation in Figure 11 Results of the electric field distribution in the structure shown under the operating conditions used to induce resistance changes;

[0055] Figure 13 It is shown in Figure 11 A graph showing the variation of electric field strength as a function of horizontal distance in the structure shown;

[0056] Figure 14 and Figure 15 It shows Figure 11 Example graphs of resistance variation characteristics of the structure shown;

[0057] Figure 16A and Figure 16B is a conceptual example diagram illustrating oxygen vacancy movement causing resistance change in a dielectric film of a memory cell;

[0058] Figure 17 is a cross-sectional view schematically illustrating a structure of a dielectric film in a memory cell according to an embodiment; and

[0059] Figure 18 is a diagram illustrating a neuromorphic device and external devices connected thereto. DETAILED DESCRIPTION

[0060] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the embodiments of the present disclosure may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the embodiments will be described below with reference to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Expressions such as "at least one of" when following a list of elements modify the entire list of elements without modifying the individual elements in the list. For example, "at least one of A, B, and C," "at least one of A, B, or C," "one of A, B, C, or a combination thereof," and "one of A, B, C, and a combination thereof" can be interpreted as covering any of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

[0061] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include a manufacturing tolerance or an operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, it is intended that the geometric shape is not required to be exact, but rather that tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially," it will be understood that these values and shapes should be interpreted as including a manufacturing tolerance or an operating tolerance (e.g., ±10%) around the stated numerical value or shape.

[0062] Hereinafter, a vertical nonvolatile memory device including a memory cell string will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements, and the dimensions of each element in the drawings may be exaggerated for clarity and ease of description. Furthermore, the embodiments described below are merely examples, and various modifications may be made therefrom.

[0063] Hereinafter, descriptions of "over" or "on" may include not only being directly over and in contact with, but also being over without contact with. Unless the context clearly indicates otherwise, singular expressions include plural expressions. Furthermore, when a component is described as "comprising" a certain configuration element, this means that the component may also include other configuration elements without excluding other configuration elements, unless otherwise specified.

[0064] The term "described above" and similar terms may be used with respect to the singular and the plural. If a sequence of steps of a configuration method is clearly described or there is no contradictory description, the sequence may be performed in a suitable order and is not limited to the order described.

[0065] Furthermore, terms such as “unit / part,” “module,” etc. described in the specification mean a unit for processing at least one function or operation, which may be implemented as hardware, software, or a combination of hardware and software.

[0066] Connections of lines between configuration elements or connecting members shown in the drawings represent functional connections and / or physical or circuit connections by way of example, and may be replaced or represented as additional various functional connections, physical connections or circuit connections in actual devices.

[0067] All examples or exemplary terms are only for the purpose of describing the technical concept in detail, and the scope is not limited by the examples or exemplary terms unless defined by the claims.

[0068] Figure 1 is a block diagram showing a storage system according to an embodiment. Figure 1, a memory system 10 according to an embodiment may include a memory controller 100 and a memory device 200. The memory controller 100 may perform a control operation on the memory device 200, and as an example, the memory controller 100 may provide an address ADD and a command CMD to the memory device 200, thereby performing program (or write), read, and erase operations on the memory device 200. In addition, data for a program operation and read data may be transmitted and received between the memory controller 100 and the memory device 200.

[0069] The memory device 200 may include a memory cell array 210 and a voltage generating device 220. The memory cell array 210 may include a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines intersect. The memory cell array 210 may include nonvolatile memory cells that store data in a nonvolatile manner, and may include flash memory cells such as a NAND flash cell array 210 or a NOR flash cell array 210 as nonvolatile memory cells. Hereinafter, embodiments of the inventive concept will be described in detail assuming that the memory cell array 210 includes the flash cell array 210, and therefore, the memory device 200 is a nonvolatile memory device.

[0070] The memory controller 100 may include a write / read controller 110 , a voltage controller 120 , and a data determination processor 130 .

[0071] The write / read controller 110 may generate an address ADD and a command CMD for performing program, read, and erase operations on the memory cell array 210. In addition, the voltage controller 120 may generate a voltage control signal for controlling at least one voltage level used in the nonvolatile memory device 200. For example, the voltage controller 120 may generate a voltage control signal for controlling a voltage level of a word line used to read data from the memory cell array 210 or program data to the memory cell array 210.

[0072] The data determination processor 130 may perform a discrimination operation on the data read from the memory device 200. For example, by determining the data read from the memory cells, the number of on-cells and / or off-cells among the memory cells may be determined. As an operational example, if programming is performed on a plurality of memory cells, the data states of the memory cells may be determined by using a desired read voltage and / or a predetermined read voltage, thereby determining whether the programming has been completed normally for all cells.

[0073] The memory device 200 may include a memory cell array 210 and a voltage generating device 220. As described above, the memory cell array 210 may include nonvolatile memory cells, for example, the memory cell array 210 may include flash memory cells. In addition, the flash memory cells may be implemented in various forms, and for example, the memory cell array 210 may include three-dimensional (or vertical) NAND (VNAND) memory cells.

[0074] The memory controller 100, read / write controller 110, voltage controller 120, and data determination processor 130 may be implemented using processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor running software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like. The memory controller 100, along with the read / write controller 110, voltage controller 120, and data determination processor 130, may operate based on control signals used to control the operation of the memory device 200 discussed herein, thereby converting the memory controller 100 and the read / write controller 110, voltage controller 120, and data determination processor 130 therein into dedicated processing circuitry.

[0075] Figure 2 It shows Figure 1 FIG. 2 is a block diagram of an exemplary embodiment of a memory device 200. Figure 2 , the memory device 200 may further include a row decoder 230 , an input / output circuit 240 , and a control logic 250 .

[0076] The memory cell array 210 may be connected to one or more string select lines SSL, a plurality of word lines WL1 to WLm, and one or more common source lines CSL, and may also be connected to a plurality of bit lines BL1 to BLn. The voltage generating device 220 may generate one or more word line voltages V1 to Vi, and the word line voltages V1 to Vi may be provided to the row decoder 230. Signals for programming, reading, and erasing operations may be applied to the memory cell array 210 through the bit lines BL1 to BLn.

[0077] In addition, data to be programmed can be provided to the memory cell array 210 through the input / output circuit 240, and read data can be provided to an external device (e.g., a memory controller) through the input / output circuit 240. The control logic 250 can provide various control signals related to memory operations to the row decoder 230 and the voltage generating device 220.

[0078] The word line voltages V1 to Vi may be provided to the respective lines SSL, WL1 to WLm, and CSL according to a decoding operation of the row decoder 230. For example, the word line voltages V1 to Vi may include a string selection voltage provided to one or more string selection lines SSL, a word line voltage provided to one or more word lines WL1 to WLm, and a ground selection voltage provided to one or more common source lines CSL.

[0079] The control logic 250, the voltage generating device 220, the row decoder 230, and the input / output circuit 240 can be implemented using processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor running software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like. The control logic 250, along with the voltage generating device 220, the row decoder 230, and the input / output circuit 240, can operate based on control signals for controlling the operation of the memory cell array 210 discussed herein, thereby converting the control logic 250 into a dedicated processing circuit.

[0080] Figure 3 It shows Figure 1 The block diagram of the memory cell array is shown in FIG. Figure 3 , the memory cell array 210 includes a plurality of memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or a vertical structure). For example, each memory block BLK may include a structure extending in the first to third directions. For example, each memory block BLK may include a plurality of memory cell strings extending in the second direction. In addition, the plurality of memory cell strings may be arranged two-dimensionally in the first and third directions. Each memory cell string is connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL. Therefore, each of the memory blocks BLK1 to BLKz may be connected to a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of common source lines CSL. Will refer to Figure 4 The memory blocks BLK1 to BLKz are described in more detail.

[0081] Figure 4 is a diagram showing an equivalent circuit corresponding to a memory block according to an embodiment. For example, Figure 4 Shown in Figure 3 One of the memory blocks BLK1 to BLKz of the memory cell array 210. Figure 3 and Figure 4Each of the memory blocks BLK1 to BLKz includes a plurality of memory cell strings CS11 to CSkn. The plurality of memory cell strings CS11 to CSkn may be two-dimensionally arranged in row and column directions to form a plurality of rows and a plurality of columns. Each of the memory cell strings CS11 to CSkn includes one or more memory cells MC and one or more string selection transistors SST. The memory cells MC and string selection transistors SST in each of the memory cell strings CS11 to CSkn may be stacked in a height direction.

[0082] Multiple rows of multiple memory cell strings CS11 to CSkn are respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SST of the memory cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors SST of the memory cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk.

[0083] In addition, the columns of the plurality of memory cell strings CS11 to CSkn are respectively connected to different bit lines BL1 to BLn. For example, the memory cells MC and string selection transistors SST of the memory cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and string selection transistors SST of the memory cell strings CS1n to CSkn may be commonly connected to the bit line BLn.

[0084] In addition, multiple rows of multiple memory cell strings CS11 to CSkn can be connected to different common source lines CSL1 to CSLk, respectively. For example, the string selection transistors SST of the multiple memory cell strings CS11 to CS1n can be commonly connected to the common source line CSL1, and the string selection transistors SST of the multiple memory cell strings CSk1 to CSkn can be commonly connected to the common source line CSLk.

[0085] Memory cells MC located at the same height from a substrate (or string selection transistor SST) may be commonly connected to one word line WL, and memory cells MC located at different heights may be respectively connected to different word lines WL1 to WLm.

[0086] Figure 4 The memory blocks shown are examples. The embodiments of the inventive concept are not limited to Figure 4The memory block shown. For example, the number of rows of the plurality of memory cell strings CS11 to CSkn can be increased or decreased. As the number of rows of the plurality of memory cell strings CS11 to CSkn changes, the number of string selection lines connected to the plurality of rows of the memory cell strings CS11 to CSkn and the number of memory cell strings connected to one bit line among the memory cell strings CS11 to CSkn can also change. As the number of rows of the memory cell strings CS11 to CSkn changes, the number of common source lines connected to the plurality of rows of the memory cell strings CS11 to CSkn can also change. In addition, the number of columns of the memory cell strings CS11 to CSkn can be increased or decreased. As the number of columns of the memory cell strings CS11 to CSkn changes, the number of bit lines connected to the plurality of columns of the memory cell strings CS11 to CSkn and the number of memory cell strings connected to one string selection line among the memory cell strings CS11 to CSkn can also change.

[0087] The height of each of the memory cell strings CS11 to CSkn can be increased or decreased. For example, the number of memory cells MC stacked in each of the memory cell strings CS11 to CSkn can be increased or decreased. As the number of memory cells MC stacked in each of the memory cell strings CS11 to CSkn changes, the number of word lines WL can also change. For example, the number of string selection transistors provided to each of the memory cell strings CS11 to CSkn can be increased. As the number of string selection transistors provided to each of the memory cell strings CS11 to CSkn changes, the number of string selection lines or common source lines can also change. If the number of string selection transistors increases, the string selection transistors can be stacked in the same form as the memory cells MC.

[0088] For example, writing and reading can be performed on each row of memory cell strings CS11 to CSkn. Memory cell strings CS11 to CSkn can be selected for each row via a common source line CSL, and can be selected for each row via a string select line SSL. Furthermore, within a selected row of memory cell strings CS11 to CSkn, writing and reading can be performed on each page. For example, a page can be a row of memory cells MC connected to one word line WL. Within a selected row of memory cell strings CS11 to CSkn, memory cells MC can be selected for each page via a word line WL.

[0089] In addition, the memory cell MC in each of the memory cell strings CS11 to CSkn may correspond to a circuit in which a transistor and a resistor are connected in parallel. For example, Figure 5 is a perspective view schematically showing a physical structure corresponding to a memory block according to an embodiment, Figure 6A It shows Figure 5 The cross-sectional view of the memory block shown in the XZ plane is Figure 6B It shows Figure 5 A cross-sectional view of a memory block shown in the YZ plane.

[0090] Reference Figure 5 、 Figure 6A and Figure 6B , the memory block includes a substrate 501. The substrate 501 may include a silicon material doped with a first type of impurity. For example, the substrate 501 may include a silicon material doped with a p-type impurity. The substrate 501 may be, for example, a p-type well (e.g., a pocket p-well). Hereinafter, it is assumed that the substrate 501 is p-type silicon, but the substrate 501 is not limited to p-type silicon.

[0091] Doped region 510 is formed in the upper region of substrate 501. For example, doped region 510 is a second-type region electrically opposite to substrate 501. For example, doped region 510 is an n-type region. Hereinafter, it is assumed that doped region 510 is an n-type region. However, doped region 510 is not limited to an n-type region. Doped region 510 may also serve as a common source line.

[0092] A plurality of gates 531 extending in a horizontal direction (e.g., the x-direction and the y-direction) and a plurality of insulators 532 extending in the horizontal direction may be alternately arranged on the substrate 501. In other words, the plurality of gates 531 and the plurality of insulators 532 may be alternately stacked in a vertical direction (e.g., the z-direction) orthogonal to the horizontal direction. For example, the gate 531 may include at least one of a metal material (e.g., copper, silver, etc.) and silicon doped at a high concentration, and the plurality of insulators 532 may include silicon oxide, but the inventive concept is not limited thereto. Each gate 531 is connected to one of a word line WL and a string select line SSL.

[0093] In addition, the memory block includes a plurality of pillars 520 that penetrate a plurality of gates 531 and a plurality of insulators 532 that are alternately arranged in the vertical direction. Each pillar 520 may be configured by a plurality of layers stacked in the horizontal direction. In one embodiment, the outermost layer of the pillar 520 may be a gate insulating layer 521. For example, the gate insulating layer 521 may include silicon oxide. The gate insulating layer 521 may be conformally deposited on the side surfaces of the plurality of gates 531 and the plurality of insulators 532 to extend in the vertical direction.

[0094] In addition, the semiconductor layer 522 may be conformally deposited along the surface of the gate insulating layer 521 to extend in the vertical direction. In one embodiment, the semiconductor layer 522 may include a silicon material doped with a first type of impurity. The semiconductor layer 522 may include a silicon material doped with the same type of impurity as the substrate 501, and for example, when the substrate 501 includes a silicon material doped with p-type impurities, the semiconductor layer 522 may also include a silicon material doped with p-type impurities. Alternatively, the semiconductor layer 522 may also include materials such as Ge, indium gallium zinc oxide (IGZO), and GaAs. For example, the semiconductor layer 522 may include at least one of Si, Ge, indium gallium zinc oxide (IGZO), and GaAs.

[0095] The dielectric film 525 (also referred to as a dielectric layer) may be conformally deposited to extend in a vertical direction along the surface of the semiconductor layer 522. The dielectric film 525 may be formed of a mixture of the material of the semiconductor layer 522 and the material of the resistance change layer 523 to be described below.

[0096] The resistance change layer 523 may be disposed along the surface of the dielectric film 525. The resistance change layer 523 may be disposed in direct contact with the dielectric film 525 and may be conformally deposited on the dielectric film 525. In one embodiment, the resistance change layer 523 may be formed of a material whose resistance changes depending on the applied voltage. Depending on the voltage applied to the gate 531, the resistance change layer 523 may change from a high resistance state to a low resistance state or from a low resistance state to a high resistance state. For example, the resistance change layer 523 may include a transition metal oxide. Specifically, the resistance change layer 523 may include an oxide of at least one element selected from the group consisting of zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), and praseodymium (Pr).

[0097] The dielectric film 525 may be formed of a mixture of a transition metal oxide and the material of the semiconductor layer 522. For example, when the semiconductor layer 522 is made of silicon (Si) and the resistance change layer 523 is formed of HfO2, the dielectric film 525 may be formed of hafnium silicate (Hf silicate, HfSi x O y As another example, when the semiconductor layer 522 is formed of germanium (Ge) and the resistance change layer 523 is formed of Al2O3, the dielectric film 525 may be formed of AlGe. x O yHere, x and y may vary depending on the ratio of the material of the semiconductor layer 522 to the material of the resistance change layer 523 in the dielectric film 525. In addition, various mixtures may be used as the dielectric film 525.

[0098] Depending on the voltage applied to the gate 531, the dielectric film 525, along with the variable resistance layer 523, can change from a high resistance state to a low resistance state, or vice versa. In particular, a plurality of mobile oxygen vacancies are distributed in the dielectric film 525. Therefore, the resistance state of the dielectric film 525 can be easily changed by electrons being trapped or released in the traps formed by the oxygen vacancies. Therefore, the dielectric film 525 substantially provides resistance variation, and the variable resistance layer 523 can provide the dielectric film 525 with a resistance variation material.

[0099] The ratio of the material of the semiconductor layer 522 in the dielectric film 525 can be appropriately selected so that a sufficient amount of oxygen vacancies can be generated inside the dielectric film 525. For example, the ratio of the material of the semiconductor layer 522 in the dielectric film 525 can vary depending on the transition metal oxide and semiconductor material used, and can be approximately 20 at.% to approximately 80 at.%. Alternatively, the ratio of the material of the semiconductor layer 522 in the dielectric film 525 can be, for example, approximately 40 at.% to approximately 60 at.%.

[0100] During the process of forming the memory block, a mixture thin film formed from a mixture of the material of the semiconductor layer 522 and the material of the resistance change layer 523 may be naturally formed at the interface between the semiconductor layer 522 and the resistance change layer 523. However, the naturally formed mixture thin film does not have a uniform composition. In the disclosed embodiment, a dielectric film 525 is intentionally formed between the semiconductor layer 522 and the resistance change layer 523. The dielectric film 525 intentionally formed in this way can have a relatively uniform composition across the entire area of the dielectric film 525. For example, across the entire area of the dielectric film 525, the proportion of the material of the semiconductor layer 522 in the dielectric film 525 can be maintained constant within a deviation range of approximately 10%.

[0101] Furthermore, the width of the dielectric film 525 can be selected to ensure a horizontally movable distance for oxygen vacancies. For example, the horizontal width of the dielectric film 525 can be selected within a range of approximately 1.5 nm to approximately 10 nm. A thin film of a mixture naturally formed between the material of the semiconductor layer 522 and the material of the variable resistance layer 523 does not have a uniform width. However, an intentionally formed dielectric film 525 can have a relatively uniform width across the entire area of the dielectric film 525. For example, the width of the dielectric film 525 can be maintained constant within a deviation of approximately 10% across the entire area of the dielectric film 525.

[0102] The insulating support 524 can be arranged inside the resistance change layer 523. For example, the insulating support 524 may include silicon oxide. One insulating support 524 and the resistance change layer 523, dielectric film 525, semiconductor layer 522, gate insulating layer 521, multiple gates 531, and multiple insulators 532 arranged in sequence on the outside of the insulating support 524 configure a memory cell string CS. Therefore, the insulating support 524 is arranged at the center of the memory cell string CS. The semiconductor layer 522 and the dielectric film 525 and resistance change layer 523 arranged in sequence on the inner surface of the semiconductor layer 522 can be in contact with the doped region 510, that is, in contact with the common source region, thereby being electrically connected to the common source region. The gate 531 and the insulator 532 arranged on the outer surface of the gate insulating layer 521 may not be in contact with the doped region 510.

[0103] The drain 540 may be disposed on the pillar 520. The drain 540 may include a silicon material doped with a second type of impurity. For example, the drain 540 may include a silicon material doped with an n-type impurity. A bit line 550 may be disposed on the drain 540. The bit line 550 extending in the x-direction may intersect the gate 531 extending in the y-direction. The drain 540 and the bit line 550 may be connected via a contact plug. The bit line 550 may include a metal material, and for example, the bit line 550 may include polysilicon. The bit line 550 may include a conductive material.

[0104] In addition, when Figure 4 In comparison, the plurality of gates 531, the plurality of insulators 532, the gate insulating layer 521, the semiconductor layer 522, the dielectric film 525, and the variable resistance layer 523 are configuration elements of the memory cell string CS. Specifically, the gate 531, the gate insulating layer 521, and the semiconductor layer 522 can be configuration elements of a transistor, and the variable resistance layer 523 and the dielectric film 525 can be a resistor. In addition, any one of the gates 531, the portion of the gate insulating layer 521 horizontally adjacent to the gate 531, the portion of the semiconductor layer 522 horizontally adjacent to the gate 531, the portion of the dielectric film 525 horizontally adjacent to the gate 531, and the portion of the variable resistance layer 523 horizontally adjacent to the gate 531 are configuration elements of a memory cell MC. Multiple memory cells MC are arranged in a vertically stacked structure to form each memory cell string CS.

[0105] The dielectric film 525 and the variable resistance layer 523 can have either a high resistance state or a low resistance state, thus allowing "0" and "1" to be written into a memory cell MC. In each memory cell MC, the semiconductor layer 522 of the transistor is connected in parallel to the dielectric film 525 and the variable resistance layer 523, and this parallel structure is arranged vertically and continuously to form a memory cell string CS. Furthermore, a common source line 510 and a bit line 550 can be connected to both ends of the memory cell string CS, respectively. Furthermore, by applying voltage to the common source line 510 and the bit line 550, programming, reading, and erasing processes can be performed on multiple memory cells MC.

[0106] According to this embodiment, the memory block is configured by using a resistance change layer 523 instead of a phase change material, and therefore, heating problems, stress (pressure) problems, etc. caused by the use of phase change materials can be reduced. In addition, by configuring the memory block and operating the memory block as described above, even when the memory cells included in the memory block are repeatedly operated, ion movement between adjacent memory cells, leakage current caused by ion movement, and operation failure can be limited and / or prevented. In addition, the memory block according to this embodiment can solve the size scaling problem between memory cells of the next generation vertical NAND (VNAND), and therefore, the density can be significantly increased. Therefore, the storage capacity can be greatly increased. In particular, by providing a dielectric film 525 through which oxygen vacancies can move between the semiconductor layer 522 and the resistance change layer 523, the resistance state can be changed more easily and accurately.

[0107] Furthermore, the memory block according to the present embodiment may be implemented in the form of a chip to be used as a neuromorphic computing platform. Furthermore, the memory block according to the inventive concept may be implemented in the form of a chip to be used to configure a neural network.

[0108] Figure 7 FIG. 1 is a diagram showing a nonvolatile memory device in a programming mode according to an embodiment. Figure 4 Diagram of the equivalent circuit of a memory block. Figure 7 The plurality of storage units 710 and 720 shown may include Figure 5 The gate electrode 531 , the gate insulating layer 521 , the semiconductor layer 522 , the dielectric film 525 and the resistance change layer 523 are shown.

[0109] The plurality of memory cells 710 and 720 of the memory block may be divided into selected memory cells 710 and unselected memory cells 720. A program mode of a nonvolatile memory device refers to a mode for performing a program operation on memory cells included in a memory block, and the selected memory cell 710 may refer to a memory cell that is a target of the program operation.

[0110] The control logic 250 can control the application of an on-voltage Von to a string select line SSL connected to a selected memory cell 710 among the plurality of string select lines SSL. The control logic 250 can apply the on-voltage Von to word lines WL connected to unselected memory cells 720 among the plurality of word lines WL, and can apply the off-voltage Voff to word lines WL connected to a selected memory cell 710 among the plurality of word lines WL. Here, the on-voltage Von turns on the transistor and can also be referred to as a voltage that allows current to flow only through the semiconductor layer of the transistor. The off-voltage Voff turns off the transistor and can also be referred to as a voltage that limits and / or prevents current from flowing through the semiconductor layer of the transistor. The values of the on-voltage Von and off-voltage Voff can vary depending on the type and thickness of the materials forming the gate 531, gate insulating layer 521, semiconductor layer 522, dielectric film 525, and variable resistance layer 523 that configure the plurality of memory cells MC. Generally, the absolute value of the on-voltage Von can be greater than the absolute value of the off-voltage Voff.

[0111] In addition, a program voltage Vprogram may be applied to a bit line BL connected to the selected memory cell 710 among the plurality of bit lines BL. The program voltage Vprogram may be provided from the outside (e.g., the memory controller 100) through the input / output circuit 240. The program voltage Vprogram is a voltage for recording data in the memory cell MC, and the value of the program voltage Vprogram may vary depending on the data.

[0112] The bit lines BL not connected to the selected memory cell 710 among the plurality of bit lines BL may be grounded or floating. Since the bit lines not connected to the selected memory cell 710 are grounded or floating, power loss due to leakage current can be limited and / or prevented. Then, the control logic 250 may perform a program operation on the selected memory cell 710.

[0113] In programming mode, when an on-voltage Von is applied to an unselected memory cell 720, the semiconductor layer 522 of the unselected memory cell 720 has conductive properties. When an off-voltage Voff is applied to a selected memory cell 710, the semiconductor layer 522 of the selected memory cell 710 has insulating properties. Consequently, a voltage difference corresponding to the programming voltage Vprogram is generated in the selected memory cell 710. When oxygen vacancies move toward the semiconductor layer 522 due to the voltage difference in the selected memory cell 710, the dielectric film 525 and the variable resistance layer 523 of the selected memory cell 710 may be in a low-resistance state. The low-resistance state of the dielectric film 525 and the variable resistance layer 523 of the selected memory cell 710 may indicate a decrease in the resistance value of the selected memory cell 710. In the low-resistance state of the dielectric film 525 and the variable resistance layer 523, the selected memory cell 710 may have ohmic conduction properties.

[0114] Figure 8 Schematically illustrates the movement of current in the dielectric film 525 and the resistance change layer 523 in a programming mode according to an embodiment. Figure 8 The memory block may include a gate 531, an insulator 532, a gate insulating layer 521, a semiconductor layer 522, a dielectric film 525, a resistance change layer 523, and an insulating support 524. The gate insulating layer 521, the semiconductor layer 522, the dielectric film 525, the resistance change layer 523, and the insulating support 524 may extend in the vertical direction. The gate 531 and the insulator 532 may extend in the horizontal direction and may be alternately stacked in the vertical direction. The gate 531, the gate insulating layer 521, and the semiconductor layer 522 may be configuration elements of a transistor, and the dielectric film 525 and the resistance change layer 523 may correspond to a resistor.

[0115] In the programming mode, the control logic 250 controls the on-voltage Von to be applied to the gates 531b of the unselected memory cells 720 and the off-voltage Voff to be applied to the gates 531a of the selected memory cells 710. Thus, the semiconductor layers 522b corresponding to the gates 531b of the unselected memory cells 720 may have conductive properties, and the semiconductor layers 522a corresponding to the gates 531a of the selected memory cells 710 may have insulating properties. When a positive (+) programming voltage Vprogram is applied to a bit line electrically connected to the selected memory cell 710, a voltage difference is generated between the upper and lower portions of the dielectric film 525a and the resistance change layer 523a corresponding to the selected memory cell 710, and a programming current Iprogram may flow through the semiconductor layers 522b corresponding to the gates 531b of the unselected memory cells 720.

[0116] The voltage difference guides the oxygen vacancies in the dielectric film 525a corresponding to the selected memory cell 710 toward the semiconductor layer 522a. Figure 8 As shown, when the density of oxygen vacancies is high in the region of the dielectric film 525a close to the semiconductor layer 522a, a conductive filament is formed, thereby allowing the programming current Iprogram to flow. Therefore, due to the change in the current conduction shape, the dielectric film 525a and the resistance change layer 523a corresponding to the selected memory cell 710 enter a low resistance state. In particular, most of the resistance change occurs inside the dielectric film 525a. At this time, the selected memory cell 710 can have ohmic conduction characteristics. In other words, the selected memory cell 710 can have body conduction characteristics such as jumping, SCLC and Poole-Frenkel. As a result, the resistance state of the dielectric film 525a and the resistance change layer 523a of the selected memory cell 710 changes in response to the programming voltage Vprogram, and therefore, the selected memory cell 710 performs a programming operation.

[0117] In addition, no voltage difference is generated between the upper and lower portions of the dielectric film 525b and the variable resistance layer 523b of the unselected memory cell 720. Therefore, oxygen vacancies do not move within the dielectric film 525b and the variable resistance layer 523b corresponding to the unselected memory cell 720.

[0118] Furthermore, in the erase mode, a negative (-) erase voltage Verase is applied to a bit line electrically connected to the selected memory cell 710. Thus, oxygen vacancies are dispersed in the dielectric film 525 a and the resistance change layer 523 a corresponding to the selected memory cell 710, and thus the dielectric film 525 a and the resistance change layer 523 a corresponding to the selected memory cell 710 may enter a high resistance state.

[0119] Figure 9 is a diagram illustrating an equivalent circuit in a read mode of a memory block according to an embodiment. Figure 9 Each of the plurality of storage units 810 and 820 shown may include Figure 5 The gate 531, gate insulating layer 521, semiconductor layer 522, dielectric film 525, and resistance change layer 523 are shown. The memory cells 810 and 820 of the memory block can be divided into selected memory cells 810 and unselected memory cells 820. The read mode of the nonvolatile memory device may refer to a mode in which a read operation is performed on the memory cells included in the memory block, and the selected memory cell 810 may refer to a memory cell that is the target of the read operation.

[0120] In read mode, the control logic 250 may apply an on-voltage Von to a string select line SSL connected to a selected memory cell 810 among a plurality of string select lines SSL, and may apply an on-voltage Von to a word line WL connected to an unselected memory cell 820 among a plurality of word lines WL. Here, the on-voltage Von turns on the transistor and may also be referred to as a voltage that causes current to flow only through the semiconductor layer 522 of the transistor. The off-voltage Voff turns off the transistor and may also be referred to as a voltage that limits and / or prevents current from flowing through the semiconductor layer 522 of the transistor. The on-voltage Von and the off-voltage Voff may vary depending on the type and thickness of the materials forming the gate 531, gate insulating layer 521, semiconductor layer 522, dielectric film 525, and variable resistance layer 523 configuring the plurality of memory cells MC. Generally, the absolute value of the on-voltage Von may be greater than the absolute value of the off-voltage Voff.

[0121] In addition, the control logic 250 may apply a current-conducting voltage Vion to the word line WL connected to the selected memory cell 810. The current-conducting voltage Vion refers to a voltage having a value that causes current to flow through the semiconductor layer 522, the dielectric film 525, and the resistance change layer 523 of the transistor included in the selected memory cell 810. The absolute value of the current-conducting voltage Vion may be greater than the absolute value of the off voltage Voff and may be less than the absolute value of the on voltage Von. The value of the current-conducting voltage Vion may vary depending on the type, thickness, etc. of the materials forming the gate 531, the gate insulating layer 521, the semiconductor layer 522, the dielectric film 525, and the resistance change layer 523 configuring the plurality of memory cells. In particular, the current-conducting voltage Vion may have a value that causes the resistance distribution of the selected memory cell 810 to have a linear scale.

[0122] In addition, a read voltage Vread may be applied to a bit line BL connected to the selected memory cell 810 among the plurality of bit lines BL. The read voltage Vread may be provided from the outside (e.g., the memory controller 100) through the input / output circuit 240. The read voltage Vread may be a voltage for reading data recorded in the selected memory cell 810. The bit line BL not connected to the selected memory cell 810 among the plurality of bit lines BL may be grounded or floated. Thus, a read operation on the selected memory cell 810 may be performed.

[0123] Figure 10 is a diagram showing current movement in a selected memory cell in a read mode according to an embodiment. Figure 10In read mode, a read voltage Vread is applied to the bit line BL connected to the selected memory cell 810, and a conduction voltage Von is applied to the gate 531d of the unselected memory cell 820. Therefore, the semiconductor layer 522d of the unselected memory cell 820 has conductive properties. Therefore, a read current Iread flows through the semiconductor layer 522d of the unselected memory cell 820. However, a current conduction voltage Von is applied to the gate 531c of the selected memory cell 810. Therefore, a read current Iread flows through the semiconductor layer 522c, dielectric film 525c, and resistance change layer 523c of the selected memory cell 810.

[0124] The current-on voltage Vion may have a value such that the resistance Rsi of the semiconductor layer 522c approximates the combined resistance R1 of the dielectric film 525c and the resistance R2 of the variable resistance layer 523c. The combined resistance is formed by connecting the resistance R1 of the dielectric film 525c and the resistance R2 of the variable resistance layer 523c in parallel. For example, the value of the current-on voltage Vion may be selected such that the resistance Rsi of the semiconductor layer 522c corresponding to the selected memory cell 810 is greater than or equal to the minimum resistance of the combined resistance R1 of the dielectric film 525c and the resistance R2 of the variable resistance layer 523c, or such that the resistance Rsi of the semiconductor layer 522c of the selected memory cell 810 is less than or equal to the maximum resistance of the combined resistance R1 of the dielectric film 525c and the resistance R2 of the variable resistance layer 523c of the selected memory cell 810.

[0125] As a result, the total resistance of the selected memory cell 810 can be determined by the parallel resistance of the resistance Rsi of the semiconductor layer 522c, the resistance R1 of the dielectric film 525c, and the resistance R2 of the variable resistance layer 523c. The read current does not flow through the dielectric film 525d and the variable resistance layer 523d of the unselected memory cells 820, but only through the semiconductor layer 522d. Therefore, the read current can be determined by the total resistance of the selected memory cell 810. Thus, by measuring the intensity of the read current, the total resistance of the selected memory cell 810 can be determined.

[0126] Figure 11 is a transmission electron microscope (TEM) photograph showing a structure designed to test the operation of a memory cell according to an embodiment. Figure 11 , SiO2 layers are stacked on top of n-doped + Si layer, and doped with n + The Si layer is stacked on the SiO2 layer. Then, the dielectric film 525, the resistance change layer 523 and the insulating support body 524 are formed on the n + Si / SiO2 / n + On the side surface of the Si stack structure, doped n+ The Si layer serves as a semiconductor layer for the unselected memory cells that are turned on, and the SiO 2 layer serves as a semiconductor layer for the selected memory cells that are turned off. HfSiO is used as the dielectric film 525 , and HfO 2 is used as the resistance variable layer 523 .

[0127] Figure 12 Shows the simulation in Figure 11 The results of the electric field distribution in the structure shown under the operating conditions for causing the resistance change, Figure 13 It is shown in Figure 11 The electric field strength in the structure shown is a graph showing the change in horizontal distance. + As a result of simulating the electric field distribution through the Si layer, it can be seen that the electric field is concentrated at the interface between the SiO2 layer and the dielectric film 525. Therefore, it can be expected that a resistance change phenomenon occurs in the dielectric film 525 where the electric field is concentrated.

[0128] Figure 14 and Figure 15 It shows Figure 11 First, refer to the example curve diagram of the resistance change characteristics of the structure shown. Figure 14 , it can be seen that a resistance change phenomenon from a high resistance state to a low resistance state occurs at approximately +7 V (a set operation or a program operation), and a resistance change phenomenon from a low resistance state to a high resistance state occurs at approximately -4 V (a reset operation or an erase operation). Furthermore, it can be seen that a resistance change phenomenon occurs in a region of approximately 100 nA or less, and therefore, operations can be performed with very low power consumption.

[0129] Reference Figure 15 , the dielectric film 525 can be Figure 11 The structure shown has four different resistance states. Therefore, when using dielectric film 525, one memory cell can process 2 bits of information. In some embodiments, dielectric film 525 can have more than four different resistance states. Figure 14 and Figure 15 In the graph shown, the dielectric film 525 is formed of the same material, and the resistance change characteristics of the dielectric film 525 can be changed only by controlling the current flowing through the dielectric film 525 .

[0130] For example, in the above reference Figure 7 and Figure 8In the described programming mode, the resistance of the channel of the unselected memory cell 720, that is, the resistance of the semiconductor layer 522b of the unselected memory cell 720, changes depending on the strength of the on-voltage applied to the gate 531b of the unselected memory cell 720. Therefore, when the programming voltage applied to the bit line BL connected to the selected memory cell 710 is fixed, the current flowing through the dielectric film 525a and the resistance change layer 523a of the selected memory cell 710 can be changed depending on the strength of the on-voltage applied to the gate 531b of the unselected memory cell 720. In this way, by selecting the conditions for the current flowing through the dielectric film 525 and the resistance change layer 523 under the control of the on-voltage applied to the gate 531b of the unselected memory cell 720, the resistance change characteristics and resistance state of the dielectric film 525 can be selected.

[0131] Figure 16A and Figure 16B : is a conceptual diagram illustrating oxygen vacancy movement that causes resistance change within the dielectric film 525 of a memory cell. Figure 16A As shown in FIG, when the plurality of oxygen vacancies 0V in the dielectric film 525 are uniformly dispersed inside the dielectric film 525, the dielectric film 525 is in a high resistance state. Figure 16B As shown, when the plurality of oxygen vacancies 0V in the dielectric film 525 move toward the interface with the semiconductor layer 522 and are concentratedly distributed at the interface with the semiconductor layer 522, the dielectric film 525 is in a low resistance state.

[0132] The resistance change of the dielectric film 525 can be described as a phenomenon in which electrons are trapped and released in traps formed by oxygen vacancies (OV). For example, when the oxygen vacancies OV are uniformly dispersed inside the dielectric film 525, electrons are filled in traps separated from each other at regular distances, and therefore, it is difficult for current to flow through the dielectric film 525. Therefore, the dielectric film 525 is in a high resistance state. In addition, when the oxygen vacancies OV in the dielectric film 525 are concentratedly distributed at the interface with the semiconductor layer 522, electrons are filled at the interface between the semiconductor layer 522 and the dielectric film 525 having a high density of oxygen vacancies OV, thereby forming a conductive filament. Therefore, the dielectric film 525 is in a low resistance state.

[0133] Therefore, if the oxygen vacancies (OV) distributed in the dielectric film 525 move to the interface between the dielectric film 525 and the semiconductor layer 522 according to the programming operation, the dielectric film 525 can enter a low resistance state. In contrast, if the oxygen vacancies (OV) accumulated at the interface between the dielectric film 525 and the semiconductor layer 522 move away from the interface between the dielectric film 525 and the semiconductor layer 522 according to the erase operation to be uniformly dispersed inside the dielectric film 525, the dielectric film 525 can return to a high resistance state.

[0134] To this end, a positive programming voltage can be applied to a selected memory cell in a memory cell string via a bit line. At this time, in the portion of the dielectric film 525 corresponding to the selected memory cell, oxygen vacancies (OV) move toward the interface between the semiconductor layer 522 and the dielectric film 525. Thus, if the density of oxygen vacancies (OV) increases at the interface between the semiconductor layer 522 and the dielectric film 525, the resistance of the portion of the dielectric film 525 corresponding to the selected memory cell decreases. Furthermore, a negative (-) erase voltage can be applied to the selected memory cell in a memory cell string via a bit line. At this time, oxygen vacancies (OV) move in the portion of the dielectric film 525 corresponding to the selected memory cell in a direction away from the interface between the semiconductor layer 522 and the dielectric film 525. Consequently, the density of oxygen vacancies (OV) at the interface between the semiconductor layer 522 and the dielectric film 525 decreases. Consequently, the resistance of the portion of the dielectric film 525 corresponding to the selected memory cell increases.

[0135] Figure 17 is a cross-sectional view schematically showing the structure of a dielectric film 525 in a memory cell according to an embodiment. Figure 17 The dielectric film 525 may include a plurality of first layers 525x formed from the material of the semiconductor layer 522 and a plurality of second layers 525y formed from a transition metal oxide. In other words, the second layer 525y may be formed from the material of the resistance change layer 523. The plurality of first layers 525x and the plurality of second layers 525y may be stacked alternately in the vertical direction. Thus, the dielectric film 525 may function as a mixed layer in which the material of the semiconductor layer 522 and the material of the resistance change layer 523 are mixed, on average.

[0136] The plurality of first layers 525x and the plurality of second layers 525y can be formed by, for example, atomic layer deposition or chemical vapor deposition. In particular, when atomic layer deposition is used, the first layers 525x and the second layers 525y can be repeatedly formed very thinly for each atomic layer, so that the material of the semiconductor layer 522 and the material of the resistance variable layer 523 can be mixed very uniformly in the dielectric film 525. For example, the thickness t1 of each first layer 525x and the thickness t2 of each second layer 525y can be selected within a range from about 0.1 nm to about 1 nm.

[0137] The ratio of the material of the semiconductor layer 522 to the material of the resistance change layer 523 in the dielectric film 525 can be determined by the ratio of the thickness t1 of each first layer 525x to the thickness t2 of each first layer 525y. For example, the ratio of the thickness t1 of each first layer 525x to the sum of the thicknesses of each first layer 525x and each second layer 525y (t1+t2) can be approximately 20% to approximately 80%. Alternatively, the ratio of the thickness t1 of each first layer 525x to the sum of the thicknesses of each first layer 525x and each second layer 525y (t1+t2) can be approximately 40% to approximately 60%. The ratio of the thickness t1 of each first layer 525x to the sum of the thicknesses of each first layer 525x and each second layer 525y (t1+t2) can be maintained constant within a deviation range of approximately 10% throughout the entire area of the dielectric film 525. Thus, in the entire region of the dielectric film 525 , the ratio of the material of the semiconductor layer 522 in the dielectric film 525 can be kept constant within a deviation range of about 10%.

[0138] Figure 17 The configuration of the dielectric film 525 shown may be merely an example and is not limited thereto. For example, the dielectric film 525 may be formed by depositing a mixture of the material of the semiconductor layer 522 and the material of the resistance change layer 523 using a chemical vapor deposition method.

[0139] Figure 18 is a diagram illustrating a neuromorphic device and external devices connected thereto.

[0140] Reference Figure 18 , the neuromorphic device 1800 may include a processing circuit 1810 and / or a memory (e.g., on-chip memory) 1820. The neuromorphic device 1800 may include a processing circuit 1810 and / or a memory (e.g., on-chip memory) 1820 based on the present application. Figure 1-17 Implementation of the memory.

[0141] In some example embodiments, the processing circuit 1810 may be configured to control functions for driving the neuromorphic device 1800. For example, the processing circuit 1810 may be configured to control the neuromorphic device 1800 by executing a program stored in the memory 1820 of the neuromorphic device 1800. In some example embodiments, the processing circuit may include: hardware, such as a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1800, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like. In some example embodiments, the processing circuit 1810 may be configured to read various data from / write various data to the external device 1830 and / or operate the neuromorphic device 1800 by using the read / written data. In some embodiments, external device 1830 may include external memory and / or a sensor array having an image sensor (eg, a CMOS image sensor circuit).

[0142] In some embodiments, Figure 18 The neuromorphic device can be applied in a machine learning system. The machine learning system can utilize various artificial neural network organization and processing models, such as convolutional neural network (CNN), deconvolutional neural network, recurrent neural network (RNN) (which optionally includes long short-term memory (LSTM) units and / or gated recurrent units (GRU)), stacked neural network (SNN), state space dynamic neural network (SSDNN), deep belief network (DBN), generative adversarial network (GAN) and / or restricted Boltzmann machine (RBM).

[0143] Alternatively or additionally, such a machine learning system may include: other forms of machine learning models, such as, for example, linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including ensembles such as random forests. Such machine learning models may also be used to provide various services and / or applications, such as image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., which may be executed, run, or processed by electronic devices.

[0144] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

[0145] This application claims the benefit of Korean Patent Application No. 10-2020-0004948 filed on January 14, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A nonvolatile memory device comprising: a plurality of memory cell strings, each of the plurality of memory cell strings comprising: a semiconductor layer extending in a first direction and having a first surface opposite to a second surface, A plurality of gates and a plurality of insulators extend in a second direction perpendicular to the first direction, the plurality of gates and the plurality of insulators being alternately arranged in the first direction, a gate insulating layer extending along the first direction between the plurality of gates and the first surface of the semiconductor layer and between the plurality of insulators and the first surface of the semiconductor layer, and a dielectric film extending along the first direction on the second surface of the semiconductor layer, the dielectric film having a plurality of movable oxygen vacancies distributed therein, When the plurality of oxygen vacancies are uniformly dispersed in the dielectric film, the dielectric film is in a high-resistance state, and when the plurality of oxygen vacancies move toward the interface with the semiconductor layer and are distributed at the interface with the semiconductor layer, the dielectric film is in a low-resistance state. 2 . The nonvolatile memory device according to claim 1 , wherein the dielectric film comprises a mixture of a material of the semiconductor layer and a transition metal oxide. 3 . The nonvolatile memory device according to claim 2 , wherein the material of the semiconductor layer comprises at least one of Si, Ge, indium gallium zinc oxide (IGZO), and GaAs.

4. The nonvolatile memory device according to claim 2, wherein the transition metal oxide comprises an oxide of at least one of zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), lanthanum (La), manganese (Mn), and praseodymium (Pr). 5 . The nonvolatile memory device according to claim 2 , wherein a ratio of the material of the semiconductor layer in the dielectric film is 20 at. % to 80 at. %. 6 . The nonvolatile memory device according to claim 5 , wherein the ratio of the material of the semiconductor layer in the dielectric film is 40 at. % to 60 at. %.

7. The nonvolatile memory device according to claim 5, wherein: The ratio of the material of the semiconductor layer in the dielectric film is constant within a deviation range of 10% throughout the entire region of the dielectric film.

8. The nonvolatile memory device according to claim 1, wherein the width of the dielectric film in the second direction is 1.5 nm to 10 nm, and in, The width of the dielectric film is constant within a deviation range of 10% throughout the entire region of the dielectric film.

9. The nonvolatile memory device according to claim 1, wherein The dielectric film includes a plurality of first layers and a plurality of second layers, The plurality of first layers are formed of a material of the semiconductor layer, the plurality of second layers are formed of a transition metal oxide, and The plurality of first layers and the plurality of second layers are alternately arranged in the first direction. 10 . The nonvolatile memory device of claim 9 , wherein the plurality of first layers and the plurality of second layers are formed by an atomic layer deposition method or a chemical vapor deposition method.

11. The nonvolatile memory device according to claim 9, wherein The thickness of each of the plurality of first layers and the thickness of each of the plurality of second layers are 0.1 nm to 1 nm, and in, A ratio of the thickness of each of the plurality of first layers to the sum of the thicknesses of each of the plurality of first layers and each of the plurality of second layers is constant within a deviation range of 10% in the entire region of the dielectric film. 12 . The nonvolatile memory device of claim 11 , wherein the ratio of the thickness of each of the plurality of first layers to the sum of the thickness of each of the plurality of first layers and each of the plurality of second layers is 20% to 80%. 13 . The nonvolatile memory device of claim 12 , wherein the ratio of the thickness of each of the plurality of first layers to the sum of the thickness of each of the plurality of first layers and each of the plurality of second layers is 40% to 60%.

14. The nonvolatile memory device according to claim 1, wherein Each of the plurality of memory cell strings further includes a resistance change layer, The resistance change layer faces the second surface of the semiconductor layer, The resistance change layer extends in the first direction, and The dielectric film is between the second surface of the semiconductor layer and the variable resistance layer. 15 . The nonvolatile memory device according to claim 14 , wherein the dielectric film includes a mixture of a material of the semiconductor layer and a material of the resistance change layer.

16. The nonvolatile memory device according to claim 15, wherein Each corresponding memory cell string of the plurality of memory cell strings includes a plurality of memory cells arranged in a vertical stack structure of the corresponding memory cell string, and Each corresponding memory cell in the plurality of memory cells in the corresponding memory cell string is defined by: a corresponding gate in the corresponding memory cell among the plurality of gates, a portion of the semiconductor layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction, a portion of the gate insulating layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction, a portion of the dielectric film of the corresponding memory cell string adjacent to the corresponding gate in the second direction, and A portion of the resistance change layer of the corresponding memory cell string is adjacent to the corresponding gate in the second direction.

17. The nonvolatile memory device according to claim 16, further comprising: control logic configured to control a voltage applied to at least one of the plurality of memory cell strings such that during a read mode: A first voltage is applied to unselected memory cells for causing current to flow only through the semiconductor layer of the unselected memory cells, and A second voltage is applied to the selected memory cell to cause current to flow through all of the semiconductor layer, the dielectric film, and the resistance change layer of the selected memory cell; as well as A bit line configured to apply a read voltage to the selected memory cell during a read mode, wherein The unselected memory cells and the selected memory cells are among the memory cells in the plurality of memory cell strings, and The selected memory cell is in a selected memory cell string among the plurality of memory cell strings. 18 . The nonvolatile memory device of claim 17 , wherein an absolute value of the second voltage is smaller than an absolute value of the first voltage.

19. The nonvolatile memory device according to claim 17, wherein the second voltage has a value that makes the resistance of the semiconductor layer of the selected memory cell greater than or equal to the minimum resistance of the combined resistance of the resistance of the dielectric film and the resistance change layer of the selected memory cell.

20. The nonvolatile memory device according to claim 17, wherein the second voltage has a value that makes the resistance of the semiconductor layer of the selected memory cell less than or equal to the maximum resistance of the combined resistance of the resistance of the dielectric film and the resistance change layer of the selected memory cell.

21. The nonvolatile memory device according to claim 17, wherein The control logic is configured to apply a third voltage to the selected memory cell during a mode different from the read mode for causing current to flow only through the dielectric film and the resistance change layer of the selected memory cell in the selected memory cell string, and An absolute value of the second voltage is greater than an absolute value of the third voltage.

22. The nonvolatile memory device according to claim 21, wherein The control logic is configured to control a voltage applied to at least one memory cell string among the plurality of memory cell strings in a program mode, The control logic is configured to apply the first voltage to the unselected memory cells and the third voltage to the selected memory cells during the programming mode, and The bit line is configured to apply a positive program voltage to the selected memory cell during the program mode.

23. The nonvolatile memory device according to claim 22, wherein The dielectric film is configured such that, in response to the positive programming voltage being applied to the selected memory cell through the bit line, the oxygen vacancies move in a partial region of the dielectric film of the selected memory cell string corresponding to the selected memory cell toward an interface between the semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, a density of the oxygen vacancies increases at the interface between the semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, and a resistance of the partial region of the dielectric film of the selected memory cell string decreases. 24 . The nonvolatile memory device of claim 23 , wherein the dielectric film is configured to have at least four different resistance states. 25 . The nonvolatile memory device of claim 24 , wherein the dielectric film is configured to change its resistance state based on a phenomenon in which electrons are trapped and detrapped in traps formed by the oxygen vacancies.

26. The nonvolatile memory device according to claim 21, wherein The control logic is configured to control a voltage applied to at least one memory cell string among the plurality of memory cell strings in an erase mode, The control logic is configured to apply the first voltage to the unselected memory cells and the third voltage to the selected memory cells during the erase mode, and The bit line is configured to apply a negative erase voltage to the selected memory cell during the erase mode.

27. The nonvolatile memory device according to claim 26, wherein: The dielectric film is configured such that, in response to the negative erase voltage being applied to the selected memory cell through the bit line, the oxygen vacancies in the partial region of the dielectric film of the selected memory cell string corresponding to the selected memory cell move in a direction away from the interface between the semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, the density of the oxygen vacancies decreases at the interface between the semiconductor layer of the selected memory cell string and the dielectric film of the selected memory cell string, and the resistance of the partial region of the dielectric film of the selected memory cell string increases.

28. A nonvolatile memory device comprising: substrate; a plurality of bit lines extending in a first direction; as well as A plurality of memory cell strings are spaced apart from each other on the substrate and extend in a vertical direction perpendicular to the first direction, wherein Each of the plurality of memory cell strings is connected to a corresponding bit line among the plurality of bit lines, Each of the plurality of memory cell strings includes a resistance change layer, a dielectric film surrounding the resistance change layer, a semiconductor layer surrounding the dielectric film, a gate insulating layer surrounding the semiconductor layer, and a plurality of gates and a plurality of insulators surrounding the gate insulating layer. The plurality of gates and the plurality of insulators are alternately stacked in the vertical direction, The plurality of bit lines cross the plurality of gates extending in a second direction perpendicular to the first direction and the vertical direction, Each of the plurality of memory cell strings includes a plurality of memory cells stacked one upon another, Each of the plurality of memory cells is defined by the following, at the same height in the same memory cell string among the plurality of memory cell strings: a corresponding gate connected to a corresponding portion of the resistance change layer, the corresponding portion of the resistance change layer, a corresponding portion of the dielectric film, a corresponding portion of the semiconductor layer, and a corresponding portion of the gate insulating layer among the plurality of gates, and Each memory cell is configured to have movable oxygen vacancies inside the corresponding portion of the dielectric film in response to a voltage applied to the corresponding gate and the corresponding bit line connected to the memory cell.

29. The nonvolatile memory device according to claim 28, further comprising: control logic coupled to the plurality of gates, The control logic is configured to read the selected memory cell by applying a read voltage to the selected memory cell string using the corresponding bit line connected to the selected memory cell string while applying a first voltage to unselected memory cells and a second voltage to a selected memory cell using two gates of the plurality of gates, the selected memory cell string including the selected memory cell and the unselected memory cells among the plurality of memory cells in the selected memory cell string, The first voltage causes current to flow only through the corresponding portion of the semiconductor layer of the unselected memory cell, and The second voltage causes current to flow through the corresponding portion of the semiconductor layer, the corresponding portion of the dielectric film, and the corresponding portion of the resistance change layer of the selected memory cell.

30. The nonvolatile memory device according to claim 28, further comprising: control logic coupled to the plurality of gates, The control logic is configured to program the selected memory cell by applying a positive programming voltage to the selected memory cell string using the corresponding bit line connected to the selected memory cell string while applying a first voltage to unselected memory cells using two gates of the plurality of gates and applying an off voltage to the selected memory cell, the selected memory cell string including the selected memory cell and the unselected memory cells among the plurality of memory cells in the selected memory cell string, The first voltage causes current to flow only through the corresponding portion of the semiconductor layer of the unselected memory cell, and The off voltage causes current to flow through the corresponding portion of the dielectric film and the corresponding portion of the resistance change layer of the selected memory cell.

31. The nonvolatile memory device according to claim 28, further comprising: control logic coupled to the plurality of gates, The control logic is configured to erase the selected memory cell by applying a negative erase voltage to the selected memory cell string using the corresponding bit line connected to the selected memory cell string while applying a first voltage to unselected memory cells using two gates of the plurality of gates and applying an off voltage to the selected memory cell, the selected memory cell string including the selected memory cell and the unselected memory cells among the plurality of memory cells in the selected memory cell string, The first voltage causes current to flow only through the corresponding portion of the semiconductor layer of the unselected memory cell, and The off voltage causes current to flow through the corresponding portion of the dielectric film and the corresponding portion of the resistance change layer of the selected memory cell.

32. The nonvolatile memory device according to claim 28, wherein The resistance variable layer includes an oxide of at least one of zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), and praseodymium (Pr). The semiconductor layer includes silicon, germanium, indium gallium zinc oxide (IGZO) or GaAs, The gate insulating layer includes silicon oxide, and The dielectric film includes a mixture of a material of the semiconductor layer and a transition metal oxide.

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