Thin film transistor substrate and display device

Abstract

The present disclosure relates to a thin film transistor substrate and a display apparatus including the same, the display apparatus including a first thin film transistor on a substrate. The first thin film transistor includes a first semiconductor layer having a first channel region, a first source region, and a first drain region; a first lower gate electrode between the substrate and the first semiconductor layer; a first upper gate electrode on the first semiconductor layer and overlapping the first channel region; and a first electrode layer on the first upper gate electrode and electrically connected to at least one of the first source region and the first drain region. The first lower gate electrode overlaps the first channel region and the first drain region.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0178502, filed on December 30, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] One or more embodiments relate to a thin film transistor substrate and a display apparatus including the same, and to a thin film transistor substrate and a display apparatus including the same having improved resolution. BACKGROUND

[0004] Generally, a display apparatus can include a display element and a driving circuit that can control an electrical signal applied to the display element. The driving circuit can include a thin film transistor (TFT), a storage capacitor, and a wiring.

[0005] In order to precisely control light emission and an amount of light emission of the display element, the number of TFTs electrically connected to the display element has been increased. Accordingly, research has been actively conducted to address the problem of high integration and power consumption of the display apparatus.

[0006] It should be appreciated that this BACKGROUND section is partially intended to provide useful background information for understanding the technology. However, this BACKGROUND section can also include ideas, concepts or recognitions that were not part of what is known or appreciated by those having skill in the relevant art as of the corresponding effective filing date of the disclosure herein. SUMMARY

[0007] One or more embodiments can include a thin film transistor substrate and a display apparatus including the same having improved resolution. However, this is merely an example, and the scope of the disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the presented embodiments.

[0009] According to one or more embodiments, a thin film transistor substrate can include a first thin film transistor disposed on a substrate. The first thin film transistor can include a first semiconductor layer including a first channel region, a first source region, and a first drain region; a first lower gate electrode disposed between the substrate and the first semiconductor layer; a first upper gate electrode disposed on the first semiconductor layer and overlapping the first channel region; and a first electrode layer disposed on the first upper gate electrode and electrically connected to at least one of the first source region and the first drain region, wherein the first lower gate electrode can overlap the first channel region and the first drain region.

[0010] In an embodiment, the first lower gate electrode can overlap the first semiconductor layer, and can not overlap the first source region.

[0011] In an embodiment, the first upper gate electrode can include an end adjacent to the first source region, the first lower gate electrode can include an end adjacent to the first source region, and in a plan view, the end of the first upper gate electrode and the end of the first lower gate electrode can coincide with each other.

[0012] In an embodiment, in a plan view, a distance between the first lower gate electrode and a conductive layer disposed on the substrate can be the same as a distance between the first upper gate electrode and the conductive layer.

[0013] In an embodiment, the conductive layer can be a scan line.

[0014] In an embodiment, the first semiconductor layer can include a silicon semiconductor material or an oxide semiconductor material.

[0015] In an embodiment, the thin film transistor substrate can further include a second thin film transistor disposed on the substrate. The second thin film transistor can include a second semiconductor layer; a second gate electrode partially overlapping the second semiconductor layer; and a second electrode layer disposed on the second gate electrode and electrically connected to the second semiconductor layer, wherein the first semiconductor layer can include an oxide semiconductor material, and the second semiconductor layer can include a silicon semiconductor material.

[0016] In an embodiment, the thin-film transistor substrate can further include a third thin-film transistor disposed on the substrate. The third thin-film transistor can include a third semiconductor layer including a third channel region, a third source region, and a third drain region; a third lower gate electrode disposed between the substrate and the third semiconductor layer; a third upper gate electrode disposed on the third semiconductor layer and overlapping the third channel region; and a third electrode layer disposed on the third upper gate electrode and electrically connected to at least one of the third source region and the third drain region, wherein the third lower gate electrode can overlap the third channel region and the third drain region, and the third semiconductor layer can include an oxide semiconductor material.

[0017] In an embodiment, the first semiconductor layer and the third semiconductor layer can be integral with each other and can have a solitary shape.

[0018] In an embodiment, the third lower gate electrode can overlap the third semiconductor layer and can not overlap the third source region.

[0019] In an embodiment, the third upper gate electrode can include an end adjacent to the third source region, the third lower gate electrode can include an end adjacent to the third source region, and in a plan view, the end of the third upper gate electrode and the end of the third lower gate electrode can coincide with each other.

[0020] In an embodiment, the first thin-film transistor can be a compensation thin-film transistor, and the third thin-film transistor can be an initialization thin-film transistor.

[0021] In an embodiment, the thin-film transistor substrate can include a boost capacitor including a lower electrode and an upper electrode, wherein the lower electrode and the second gate electrode can be disposed on the same layer, and the upper electrode and the first semiconductor layer can be disposed on the same layer.

[0022] In an embodiment, the upper electrode can extend from the first semiconductor layer.

[0023] According to one or more embodiments, a display device can include a first thin-film transistor disposed on a substrate and a display element electrically connected to the first thin-film transistor. The first thin-film transistor can include a first semiconductor layer including a first channel region, a first source region, and a first drain region; a first lower gate electrode disposed between the substrate and the first semiconductor layer; a first upper gate electrode disposed on the first semiconductor layer and overlapping the first channel region; and a first electrode layer disposed on the first upper gate electrode and electrically connected to at least one of the first source region and the first drain region, and the first lower gate electrode can overlap the first channel region and the first drain region.

[0024] In an embodiment, the first lower gate electrode can overlap the first semiconductor layer, and can not overlap the first source region.

[0025] In an embodiment, the first upper gate electrode can include an end adjacent to the first source region, the first lower gate electrode can include an end adjacent to the first source region, and the end of the first upper gate electrode and the end of the first lower gate electrode can coincide with each other in a plan view.

[0026] In an embodiment, the first semiconductor layer can include a silicon semiconductor material or an oxide semiconductor material.

[0027] In an embodiment, the display apparatus can further include a second thin film transistor disposed on the substrate. The second thin film transistor can include a second semiconductor layer, a second gate electrode partially overlapping the second semiconductor layer, and a second electrode layer disposed on the second gate electrode and electrically connected to the second semiconductor layer, wherein the first semiconductor layer can include an oxide semiconductor material, and the second semiconductor layer can include a silicon semiconductor material.

[0028] In an embodiment, the display apparatus can further include a third thin film transistor disposed on the substrate. The third thin film transistor can include a third semiconductor layer including a third channel region, a third source region, and a third drain region, a third lower gate electrode disposed between the substrate and the third semiconductor layer, a third upper gate electrode disposed on the third semiconductor layer and overlapping the third channel region, and a third electrode layer disposed on the third upper gate electrode and electrically connected to at least one of the third source region and the third drain region, wherein the third lower gate electrode can overlap the third channel region and the third drain region, and the third semiconductor layer can include an oxide semiconductor material.

[0029] In an embodiment, the third lower gate electrode can overlap the third semiconductor layer, and can not overlap the third source region.

[0030] In an embodiment, the third upper gate electrode can include an end adjacent to the third source region, the third lower gate electrode can include an end adjacent to the third source region, and the end of the third upper gate electrode and the end of the third lower gate electrode can coincide with each other in a plan view.

[0031] In an embodiment, the first semiconductor layer and the third semiconductor layer can be integral with each other, and can have a solitary shape.

[0032] In an embodiment, the display device can further include a boost capacitor including a lower electrode and an upper electrode, wherein the lower electrode and the second gate electrode can be disposed on the same layer, and the upper electrode and the first semiconductor layer can be disposed on the same layer.

[0033] In an embodiment, the display device can further include a storage capacitor including the second gate electrode as a first electrode, and a second electrode disposed on the second gate electrode, wherein the first lower gate electrode and the second electrode can be disposed on the same layer. BRIEF DESCRIPTION OF DRAWINGS

[0034] These and / or other aspects will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings in which:

[0035] Figure 1 is a plan view of a display device according to an embodiment;

[0036] Figure 2 is a plan view of a display device according to an embodiment;

[0037] Figure 3 is a plan view of a display panel according to an embodiment;

[0038] Figure 4 is a schematic cross-sectional view of a portion of a thin film transistor substrate included in a display device according to an embodiment;

[0039] Figure 5 is an equivalent circuit diagram of one pixel of a display panel according to an embodiment;

[0040] Figure 6 is a plan view of one pixel circuit of a display panel according to an embodiment;

[0041] Figure 7 is a schematic cross-sectional view of a pixel circuit taken along line II-II' of Figure 6

[0042] Figure 8 is an equivalent circuit diagram of one pixel of a display panel according to an embodiment;

[0043] Figure 9 is a plan view of one pixel circuit of a display panel according to an embodiment;

[0044] Figures 10A-10D is a plan view of some layers of Figure 9

[0045] Figure 11A and Figure 11B is a schematic cross-sectional view of a pixel circuit taken along line II-II' of Figure 9 ​​a schematic cross-sectional view of the pixel circuit taken along line III-III' of

[0046] Figure 12 is a graph showing a change in channel potential according to an embodiment. Figure 9 a schematic cross-sectional view of the pixel circuit taken along line IV-IV' of

[0047] Figure 13 is a graph showing a change in channel potential according to an embodiment. DETAILED DESCRIPTION

[0048] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description.

[0049] In order to describe the embodiments of the present disclosure, some components not related to the present specification can not be provided, and the same reference numerals refer to the same elements throughout the specification.

[0050] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the present disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0051] The terms "and" and "or" can be used in the conjunctive or disjunctive sense and can be understood to be equivalent to "and / or". In the present specification and claims, for the purpose of interpreting the meaning of the terms, the phrase "at least one of (a kind)" is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0052] Because the present disclosure can have various modified embodiments, various embodiments are illustrated in the drawings and described in the detailed description. The following embodiments described by referring to the drawings will clarify the advantages and features of the embodiments and the method of implementing the same. However, the present disclosure can be implemented in many different forms, and should not be construed as being limited to the embodiments set forth herein.

[0053] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout, and repetitive descriptions thereof will be omitted.

[0054] It will be understood that, although the terms“first,”“second,” etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element could be termed a first element.

[0055] Singular expressions of articles include plural expressions, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes,”“including,” and / or“has,”“having” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or any combinations thereof.

[0056] When a layer, film, region, substrate, area, or element is referred to as being“on” another layer, film, region, substrate, area, or element, it can be directly on the other layer, film, region, substrate, area, or element or intervening layers, films, regions, substrates, areas, or elements can also be present. In contrast, when an element is referred to as being“directly on” another element, there are no intervening layers, films, regions, substrates, areas, or elements between them. Also, when a layer, film, region, substrate, area, or element is referred to as being“under” or“beneath” another layer, film, region, substrate, area, or element, it can be directly under the other layer, film, region, substrate, area, or element, or intervening layers, films, regions, substrates, areas, or elements can also be present. In contrast, when an element is referred to as being“directly under” or“directly beneath” another element, there are no intervening layers, films, regions, substrates, areas, or elements between them. Also,“over” or“above” can include being positioned above or below, and does not necessarily mean a direction based on gravity.

[0057] For purposes of the description hereinafter, spatially relative terms, such as "below", "beneath", "lower", "above", "upper" and the like, can be used to describe the relative position of one element or component to another element or component as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device shown in the figures is turned over, elements described as "below" or "beneath" other elements or components would then be oriented "above" the other elements or components. Thus, the exemplary term "below" can encompass both a position and an orientation. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative terms used herein are to be interpreted accordingly.

[0058] In the drawings, the size and thickness of elements can be exaggerated for better understanding, clarity and ease of description. The present disclosure, however, is not limited to the sizes and thicknesses shown. In the drawings, the thickness of layers, films, panels, regions, and other elements can be exaggerated for clarity. In the drawings, the thickness of some layers and regions can be exaggerated for better understanding and ease of description.

[0059] Further, in the specification, the phrase "in plan view" refers to viewing a portion of an object from above, while the phrase "in schematic cross-section" refers to a schematic cross-section taken by cutting the portion of the object perpendicularly from the side.

[0060] In addition, the terms "overlapping" or "overlapped" mean that a first object can be above or below or to the side of a second object, and vice versa. In addition, the term "overlapping" can include layering, stacking, facing or facing towards, extending over, covering or partially covering, or any other suitable term as would be recognized and understood by one of ordinary skill in the art. The terms "facing" and "facing towards" mean that a first element can be directly or indirectly opposite a second element. Where a third element is interposed between the first element and the second element, the first element and the second element can be understood to indirectly oppose each other, even though the first element and the second element still face each other. When elements are described as "not overlapping" or "not overlapped", this can include the elements being spaced apart from each other, offset from each other, separated from each other, or any other suitable term as would be recognized and understood by one of ordinary skill in the art.

[0061] While embodiments can be implemented differently, a particular order of processes can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in reverse order from the described order.

[0062] "about" or "approximately," as used herein, includes the recited value and means within a reasonable deviation of the stated value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0063] It will be understood that when a layer, region, or element is referred to as being "connected" or "coupled" to another layer, region, or element, it can be directly connected or coupled to the other layer, region, or element or intervening layers, regions, or elements can be present. For example, as used herein, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, or intervening layers, intervening regions, or intervening elements can be present.

[0064] Also, as used herein, when an element is referred to as being "contacted" or "in contact" with another element, it can be "electrically contacted" or "physically contacted" with the other element; or "indirectly contacted" or "directly contacted" with the other element.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0066] The first direction DR1, the second direction DR2, and the third direction DR3 (not shown) are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 (not shown) can be perpendicular to each other, or can represent different directions that can not be perpendicular to each other.

[0067] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0068] Figure 1 and Figure 2 is a schematic plan view of a display device 1 according to an embodiment.

[0069] Referring to Figure 1 and Figure 2The display apparatus 1 can include a display area DA in which an image can be implemented or displayed and a peripheral area PA around the display area DA. The display apparatus 1 can provide or display an image to the outside by using light emitted from the display area DA. It should be understood that the "image" can include more than one image and thus can include a plurality of images.

[0070] The substrate 100 can be divided into a display area DA in which an image can be displayed and a peripheral area PA around the display area DA.

[0071] The substrate 100 can include various materials such as glass, metal, or plastic. According to an embodiment, the substrate 100 can include a flexible material. Here, the flexible material can refer to a substrate that can be well bent, folded, or rolled. The substrate 100 of the flexible material can include an ultra-thin glass, metal, or plastic, or other flexible materials within the spirit and scope of the present disclosure.

[0072] In the display area DA of the substrate 100, pixels PX including various display elements such as organic light emitting diodes OLED (see Figure 5 ) can be arranged or disposed. The pixels PX can be plural, and the pixels PX can be arranged or disposed in various forms such as a stripe array, a pentile array, and a mosaic array, etc. to implement an image.

[0073] When the display area DA is viewed in a plan view, the display area DA can be provided in a substantially rectangular shape as shown in Figure 1 or a substantially circular shape as shown in Figure 2 . In an embodiment, the display area DA can be provided in a substantially polygonal shape such as a triangle, a pentagon, and a hexagon, a substantially elliptical shape, or an amorphous shape, etc. within the spirit and scope of the present disclosure.

[0074] The peripheral area PA of the substrate 100 can be an area around the display area DA and can be an area in which an image can not be displayed. In the peripheral area PA, various wirings that can transmit an electrical signal to be applied to the display area DA and a pad to which a printed circuit board or a driver IC chip can be attached can be positioned or disposed.

[0075] Hereinafter, a display apparatus including an organic light emitting diode as a display element will be described for convenience. However, embodiments can be applied to various types of display apparatuses such as a liquid crystal display apparatus, an electrophoretic display apparatus, and an inorganic EL display apparatus, etc. within the spirit and scope of the present disclosure.

[0076] Figure 3 is a plan view of a display panel 10 according to an embodiment.

[0077] Referring to Figure 3 , the display panel 10 can include a display area DA and a peripheral area PA and pixels PX located in the display area DA. Each pixel PX can include a display element such as an organic light emitting diode OLED (see Figure 5 ). Each pixel PX can emit light of, for example, red, green, blue, or white through the organic light emitting diode OLED. Hereinafter, in the present specification, each pixel PX can represent a sub-pixel that can emit a different color. Each pixel PX can be one of, for example, a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. The display area DA can be covered or overlapped by an encapsulation member (not shown) to protect the display area DA from external air or moisture.

[0078] Each pixel PX can be electrically connected to an external circuit arranged or disposed in the peripheral area PA. The first scan driving circuit 130, the second scan driving circuit 131, the emission control driving circuit 133, the terminal 140, the data driving circuit 150, the first power wiring 160, and the second power wiring 170 can be arranged or disposed in the peripheral area PA.

[0079] The emission control driving circuit 133 can provide an emission control signal to each pixel PX through an emission control line EL. The first scan driving circuit 130 can provide a scan signal to each pixel PX through a scan line SL. The second scan driving circuit 131 can be arranged or disposed in parallel with the first scan driving circuit 130, and the display area DA is located therebetween. Some pixels PX in the display area DA can be electrically connected to the first scan driving circuit 130, and other pixels PX can be electrically connected to the second scan driving circuit 131. In an embodiment, the second scan driving circuit 131 can be omitted.

[0080] The terminal 140 can be on one side of the substrate 100. The terminal 140 can be exposed without being covered or overlapped by the insulating layer, and can be electrically connected to a printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB can be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB can transmit a signal or power of a controller (not shown) to the display panel 10.

[0081] The control signals generated by the controller can be transmitted to the first scan driving circuit 130 and the second scan driving circuit 131, respectively, through the printed circuit board PCB. The controller can provide a first power voltage ELVDD and a second power voltage ELVSS to the first power wiring 160 and the second power wiring 170, respectively, through the first connection wiring 161 and the second connection wiring 171 (see Figure 5). The first power voltage ELVDD can be supplied to each pixel PX through a drive voltage line PL electrically connected to the first power wiring 160, and the second power voltage ELVSS can be supplied to the opposite electrode 330 (see FIG. 2B) of each pixel PX electrically connected to the second power wiring 170 (to be described later). Figure 7

[0082] The data driving circuit 150 can be electrically connected to the data line DL. A data signal of the data driving circuit 150 can be supplied to each pixel PX through a connection wiring 151 electrically connected to the terminal 140 and the data line DL electrically connected to the connection wiring 151. Figure 3 It is shown that the data driving circuit 150 can be provided on a printed circuit board PCB. However, in an embodiment, the data driving circuit 150 can be provided on the substrate 100. For example, the data driving circuit 150 can be provided between the terminal 140 and the first power wiring 160.

[0083] The first power wiring 160 can include a first sub-wiring 162 and a second sub-wiring 163 extending in parallel in the second direction DR2, and the display area DA is provided between the first sub-wiring 162 and the second sub-wiring 163. The second power wiring 170 can partially surround the display area DA in a substantially ring shape having one side open.

[0084] Figure 4 is a schematic cross-sectional view of a portion of a thin-film transistor substrate TB included in the display apparatus 1 according to an embodiment.

[0085] Referring to Figure 4 , the thin-film transistor substrate TB according to an embodiment can include a thin-film transistor T having a semiconductor layer A, a lower gate electrode Ga, an upper gate electrode Gb, and an electrode layer E, wherein the semiconductor layer A can have a channel region C, a source region S, and a drain region D, and the electrode layer E can be disposed on or over the upper gate electrode Gb and can be electrically connected to at least one of the source region S and the drain region D. The lower gate electrode Ga can overlap the semiconductor layer A, for example, can overlap the channel region C and the drain region D. It should be understood that the term "region" can also be referred to as "area".

[0086] As shown in Figure 4 , an edge of the lower gate electrode Ga and an edge of the upper gate electrode Gb can be aligned in a thickness direction from the substrate 100 to the second interlayer insulating layer 119. In other words, the edge of the lower gate electrode Ga and the edge of the upper gate electrode Gb can be coincident in the thickness direction from the substrate 100 to the second interlayer insulating layer 119. In this case, the coincident can mean the aligned.

[0087] ​The lower gate electrode Ga can be disposed or provided to overlap at least a portion of the semiconductor layer A, and can overlap the semiconductor layer A by avoiding or being separated from the source region S. In other words, the lower gate electrode Ga can overlap the channel region C and the drain region D of the semiconductor layer A. The lower gate electrode Ga can include a portion that at least partially overlaps the channel region C and a portion that at least partially overlaps the drain region D. The lower gate electrode Ga can be provided not to overlap the source region S.

[0088] Hereinafter, referring to Figure 4 , the configuration or structure included in the thin film transistor substrate TB will be described in more detail according to a stacking order.

[0089] The substrate 100 can include a glass material, a ceramic material, a metal material, or a material having a flexible or bendable characteristic. When the substrate 100 is flexible or bendable, the substrate 100 can include a polymer resin such as polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0090] The substrate 100 can have a single-layer or multi-layer structure of a material, and in the case of a multi-layer structure, the substrate 100 can include an inorganic layer. In an embodiment, the substrate 100 can have an organic / inorganic / organic structure.

[0091] The barrier layer 110 (see Figure 7 ) can be included between the substrate 100 and the buffer layer 111. The barrier layer 110 can prevent or minimize the penetration of impurities from the substrate 100 into the semiconductor layer A. The barrier layer 110 can include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite material, and can have a single-layer structure or a multi-layer structure including an inorganic material and / or an organic material.

[0092] Although Figure 4 It is shown that the semiconductor layer A can be provided on the first interlayer insulating layer 117, which will be described later, but the semiconductor layer A can also be provided on the buffer layer 111. The semiconductor layer A can include amorphous silicon or polycrystalline silicon. In an embodiment, the semiconductor layer A can include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer A can be an InSnZnO (ITZO) semiconductor layer or an InGaZnO (IGZO) semiconductor layer, etc., within the spirit and scope of the present disclosure.

[0093] The thin film transistor T can include a semiconductor layer A, a gate electrode G arranged or disposed to at least partially overlap the semiconductor layer A, and an electrode layer E electrically connected to the semiconductor layer A.

[0094] The semiconductor layer A can include a channel region C and a source region S and a drain region D respectively located on one side and the other side of the channel region C. The semiconductor layer A can be a single layer or multiple layers. As Figure 4 The gate electrode G can be respectively above and below the semiconductor layer A as shown in

[0095] The first gate insulating layer 113 and the second gate insulating layer 115 can be disposed on the substrate 100, and the third gate insulating layer 118 can be stacked or disposed on the semiconductor layer A. The first gate insulating layer 113, the second gate insulating layer 115, and the third gate insulating layer 118 can include silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). Figure 4 The buffer layer 111, the first gate insulating layer 113, and the second gate insulating layer 115 between the substrate 100 and the lower gate electrode Ga, which can be omitted, are shown.

[0096] In an embodiment, as shown in Figure 4 The third gate insulating layer 118 can be patterned to overlap a portion of the semiconductor layer A as shown in The region in which the third gate insulating layer 118 and the semiconductor layer A can overlap can be understood as the channel region C. The source region S and the drain region D can be subjected to a process such as conductive or impurity doping by plasma treatment, in which the portion of the semiconductor layer A overlapping the third gate insulating layer 118 can not be exposed to the plasma treatment or impurity doping, and thus can have a property different from that of the source region S and the drain region D. In other words, when the semiconductor layer A is subjected to plasma treatment or doping with impurities, by using the upper gate electrode Gb on the third gate insulating layer 118 as a self-aligned mask, the channel region C which is not doped with impurities can be formed at the position overlapping the third gate insulating layer 118, and the source region S and the drain region D doped with impurities can be formed at both sides of the channel region C, respectively.

[0097] In an embodiment, since the first gate insulating layer 113 and the second gate insulating layer 115 are stacked on the substrate 100, the third gate insulating layer 118 can also be arranged or disposed to cover or overlap the semiconductor layer A.

[0098] As shown in Figure 4As illustrated in FIG. 1, the gate electrode G can be positioned or disposed above and below the semiconductor layer A, respectively. In more detail, the lower gate electrode Ga can be positioned or disposed below the semiconductor layer A with the first interlayer insulating layer 117 therebetween, and the upper gate electrode Gb can be positioned or disposed above the semiconductor layer A with the third gate insulating layer 118 therebetween. For example, the gate electrode G can be a single layer or a multi-layer of at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0099] In an embodiment, when the third gate insulating layer 118 is patterned by using the upper gate electrode Gb as a mask, the third gate insulating layer 118 can also have a shape substantially the same as that of the upper gate electrode Gb.

[0100] In an embodiment, the lower gate electrode Ga can overlap the semiconductor layer A, for example, can overlap the channel region C and the drain region D. For example, the lower gate electrode Ga can overlap the semiconductor layer A by avoiding or being separated from or not overlapping the source region S. The lower gate electrode Ga can be disposed not to overlap the source region S.

[0101] The thin film transistor T can include a second interlayer insulating layer 119 covering or overlapping the upper gate electrode Gb, the source region S, and the drain region D positioned on the first interlayer insulating layer 117.

[0102] The electrode layer E disposed on the second interlayer insulating layer 119 can include a source electrode and a drain electrode. The source electrode can be electrically connected to the source region S, and the drain electrode can be electrically connected to the drain region D. Figure 4 The electrode layer E of FIG. 1 illustrates the drain electrode electrically connected to the drain region D. For example, the electrode layer E can be a single layer or a multi-layer of at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. In an embodiment, the electrode layer E can be a single layer of Mo or a multi-layer of Mo / Al / Mo. The electrode layer E can be electrically connected to the data line DL and / or the driving voltage line PL.

[0103] The interlayer insulating layers 117 and 119 can include an inorganic material including an oxide or a nitride. For example, the interlayer insulating layers 117 and 119 can include SiO2, SiN X , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0104] The interlayer insulating layers 117 and 119 can include an organic material such as acryl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0105] The electrode layer E can be covered with or overlapped with an inorganic protective layer (not shown). The inorganic protective layer can have a single-layer or multi-layer structure including silicon nitride (SiN x ) and silicon oxide (SiO x ). The inorganic protective layer can be introduced to cover and protect some of the wiring located on the second interlayer insulating layer 119.

[0106] In an embodiment, the lower gate electrode Ga can overlap the semiconductor layer A, for example, can overlap the channel region C and the drain region D. For example, the lower gate electrode Ga can overlap the semiconductor layer A by avoiding or being separated from the source region S, so that the lower gate electrode Ga can be disposed not to overlap the source region S. This will be described in more detail with reference to Figure 13 .

[0107] Figure 13 is a graph showing a change in channel potential according to an embodiment.

[0108] Referring to Figure 13 , the semiconductor layer A can include the source region S, the channel region C, and the drain region D. The x-axis indicates a position of a point away from the source region S in the semiconductor layer A, and the y-axis indicates a channel potential, for example, energy, according to the x-axis position. By Figure 13 , it can be seen that the change in channel potential when the lower gate electrode Ga can be under the semiconductor layer A and can overlap exactly with the middle of the channel region C of the semiconductor layer A (Ref. 1), when the lower gate electrode Ga moves about 1 μm toward the source region S (S direction), when the lower gate electrode Ga moves about 1 μm toward the drain region D (D direction), and when the lower gate electrode Ga does not exist (Ref. 2).

[0109] In more detail, when the lower gate electrode Ga can be under the semiconductor layer A and can overlap exactly with the middle of the channel region C of the semiconductor layer A (Ref. 1), the portion of the lower gate electrode Ga that can overlap the semiconductor layer A can be a portion of the channel region C, the source region S, and the drain region D. For example, in Figure 13 , when the lower gate electrode Ga can be under the semiconductor layer A and can overlap exactly with the middle of the channel region C of the semiconductor layer A (Ref. 1), based on the schematic cross-section shown in Figure 4 , the lower gate electrode Ga can overlap the source region S and the drain region D by a width of about 1 μm, respectively.

[0110] When the lower gate electrode Ga is moved by about 1 μm toward the source region S (S direction), the lower gate electrode Ga can overlap the semiconductor layer A by avoiding or separating from the drain region D, so that the lower gate electrode Ga can not overlap the drain region D.

[0111] Similarly, when the lower gate electrode Ga is moved by about 1 μm toward the drain region D (D direction), it can be seen that the lower gate electrode Ga can overlap the semiconductor layer A by avoiding or separating from the source region S, so that the lower gate electrode Ga can not overlap the source region S.

[0112] The ideal channel potential corresponds to the shape of a unit step function which is symmetric with respect to the y axis. Referring to Figure 13 Part I, when the lower gate electrode Ga can overlap under the semiconductor layer A and just the middle of the channel region C of the semiconductor layer A (Ref. 1), the energy change can most resemble the ideal channel potential.

[0113] When the lower gate electrode Ga is not present (Ref. 2), the field effect caused by the drain region D will be strong, so that the change of the channel potential will be large. When the lower gate electrode Ga is moved by about 1 μm toward the source region S (S direction), the change of the channel potential can be smaller than when the lower gate electrode Ga is not present (Ref. 2). However, compared with the case where the lower gate electrode Ga can overlap under the semiconductor layer A and just the middle of the channel region C of the semiconductor layer A (Ref. 1), the change of the channel potential will be large.

[0114] However, when the lower gate electrode Ga is moved by about 1 μm toward the drain region D (D direction), the change of the channel potential can remain the same as when the lower gate electrode Ga can overlap under the semiconductor layer A and just the middle of the channel region C of the semiconductor layer A (Ref. 1).

[0115] As shown in Figure 4 When the lower gate electrode Ga included in the thin film transistor substrate TB overlaps the semiconductor layer A by avoiding or separating from the source region S and further does not overlap the source region S, the change of the channel potential can remain the same as when the lower gate electrode Ga can overlap under the semiconductor layer A and just the middle of the channel region C of the semiconductor layer A (Ref. 1).

[0116] When the lower gate electrode Ga avoids or separates from the source region S and overlaps only the channel region C and the drain region D of the semiconductor layer A, the lower gate electrode Ga can maintain the same channel potential value as when the lower gate electrode Ga can overlap the channel region C and a part of the source region S and the drain region D.

[0117] Because the lower gate electrode Ga overlaps the channel region C and the drain region D, interference with an adjacent signal close to the source region S can be reduced. As the width of the lower gate electrode Ga in one direction is reduced, an adjacent device can be positioned or disposed closer thereto, thereby improving resolution. This will be described in detail with reference to Figure 6 and Figure 9 .

[0118] Figure 5 is an equivalent circuit diagram of one pixel PX of a display panel according to an embodiment.

[0119] Referring to Figure 5 , the pixel PX can include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC can include thin film transistors and a storage capacitor Cst. The thin film transistors and the storage capacitor Cst can be electrically connected to signal lines SWL, SIL, EL, and DL, an initialization voltage line VIL, and a driving voltage line PL.

[0120] Although Figure 5 it is shown that each pixel PX can be electrically connected to the signal lines SWL, SIL, EL, and DL, the initialization voltage line VIL, and the driving voltage line PL, the disclosure is not limited thereto. In an embodiment, at least one of the signal lines SWL, SIL, EL, and DL, the initialization voltage line VIL, and the driving voltage line PL can be shared by adjacent pixels.

[0121] The thin film transistors can include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7.

[0122] The signal lines SWL, SIL, EL, and DL can include a scan line SWL that can transmit a scan signal GW, a previous scan line SIL that can transmit a previous scan signal GI to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL that can transmit an emission control signal EM to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL that can transmit a data signal Dm, which crosses or intersects the scan line SWL. The driving voltage line PL can transmit a first power voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VIL can transmit an initialization voltage Vint that can initialize the driving thin film transistor T1 and the pixel electrode 310 (see FIG. 4, which will be described later). Figure 6

[0123] ​The driving gate electrode G1 of the driving thin film transistor T1 can be electrically connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the driving source region S1 of the driving thin film transistor T1 can be electrically connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain region D1 of the driving thin film transistor T1 can be electrically connected to the pixel electrode 310 of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin film transistor T2, and can supply the driving current I OLED to the organic light emitting diode OLED.

[0124] The switching gate electrode G2 of the switching thin film transistor T2 can be electrically connected to the scan line SWL, the switching source region S2 of the switching thin film transistor T2 can be electrically connected to the data line DL, and the switching drain region D2 of the switching thin film transistor T2 can be electrically connected to the driving source region S1 of the driving thin film transistor T1 and can be electrically connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 can be turned on in response to the scan signal GW received through the scan line SWL, and can perform a switching operation that can transfer the data signal Dm transferred to the data line DL to the driving source region S1 of the driving thin film transistor T1.

[0125] The compensation gate electrode G3 of the compensation thin film transistor T3 can be electrically connected to the scan line SWL, the compensation source region S3 of the compensation thin film transistor T3 can be electrically connected to the driving drain region D1 of the driving thin film transistor T1 and can be electrically connected to the pixel electrode 310 of the organic light emitting diode OLED through the emission control thin film transistor T6, and the compensation drain region D3 of the compensation thin film transistor T3 can be electrically connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain region D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 can be turned on in response to the scan signal GW received through the scan line SWL, and can electrically connect the driving gate electrode G1 of the driving thin film transistor T1 to the driving drain region D1, thereby connecting the driving thin film transistor T1 in a diode manner.

[0126] The first initialization gate electrode G4 of the first initialization thin film transistor T4 can be electrically connected to the previous scan line SIL, the first initialization source region S4 of the first initialization thin film transistor T4 can be electrically connected to the second initialization drain region D7 of the second initialization thin film transistor T7 and the initialization voltage line VIL, and the first initialization drain region D4 of the first initialization thin film transistor T4 can be electrically connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain region D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 can be turned on in response to a previous scan signal GI received through the previous scan line SIL, and can initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0127] The operation control gate electrode G5 of the operation control thin film transistor T5 can be electrically connected to the emission control line EL, the operation control source region S5 of the operation control thin film transistor T5 can be electrically connected to the driving voltage line PL, and the operation control drain region D5 of the operation control thin film transistor T5 can be electrically connected to the driving source region S1 of the driving thin film transistor T1 and the switching drain region D2 of the switching thin film transistor T2.

[0128] The emission control gate electrode G6 of the emission control thin film transistor T6 can be electrically connected to the emission control line EL, the emission control source region S6 of the emission control thin film transistor T6 can be electrically connected to the driving drain region D1 of the driving thin film transistor T1 and the compensation source region S3 of the compensation thin film transistor T3, and the emission control drain region D6 of the emission control thin film transistor T6 can be electrically connected to the second initialization source region S7 of the second initialization thin film transistor T7 and the pixel electrode 310 of the organic light emitting diode OLED.

[0129] The operation control thin film transistor T5 and the emission control thin film transistor T6 can be simultaneously turned on in response to an emission control signal EM received through the emission control line EL, so that a first power voltage ELVDD can be transmitted to the organic light emitting diode OLED, and a driving current I OLED may flow through the organic light emitting diode OLED.

[0130] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 can be electrically connected to the previous scan line SIL. The second initialization source region S7 of the second initialization thin-film transistor T7 can be electrically connected to the emission control drain region D6 of the emission control thin-film transistor T6 and the pixel electrode 310 of the organic light-emitting diode OLED. Furthermore, the second initialization drain region D7 of the second initialization thin-film transistor T7 can be electrically connected to the first initialization source region S4 of the first initialization thin-film transistor T4 and the initialization voltage line VIL. The second initialization thin-film transistor T7 can be turned on in response to the previous scan signal GI received through the previous scan line SIL, so as to initialize the pixel electrode 310 of the organic light-emitting diode OLED.

[0131] although Figure 5 The present disclosure describes a scenario where the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be electrically connected to the previous scan line SIL, but this disclosure is not limited thereto. In an embodiment, the first initialization thin-film transistor T4 can be electrically connected to the previous scan line SIL and driven according to the previous scan signal GI, and the second initialization thin-film transistor T7 can be electrically connected to a separate signal line (e.g., the next scan line) and driven according to the signal transmitted to the signal line.

[0132] The second storage capacitor plate Cst2 of the storage capacitor Cst can be electrically connected to the drive voltage line PL. And the opposite electrode 330 of the organic light-emitting diode OLED (see below for details) Figure 6 It can be electrically connected to the second power supply voltage ELVSS. Therefore, the organic light-emitting diode (OLED) can receive a drive current I from the driving thin-film transistor T1. OLED It emits light to display the image.

[0133] Figure 5 The compensation thin-film transistor T3 and the first initialization thin-film transistor T4 are shown to have dual gate electrodes. However, the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 can also have single gate electrodes.

[0134] Figure 5 The pixel circuit PC shown includes seven thin-film transistors and one storage capacitor, but this disclosure is not limited thereto. Depending on the design of the pixel circuit PC, the number of thin-film transistors and the number of storage capacitors can vary, for example, six or fewer, or eight or more.

[0135] Figure 6 This is a plan view of a pixel circuit PC of a display panel according to an embodiment, and Figure 7 It is along Figure 6 A schematic cross-sectional view of the pixel circuit PC, taken from line II-II'. Figure 7 In, withFigure 4 The same reference numbers in different drawings denote the same elements. Further, Figure 7 The structure in which the driving thin film transistor T1, the compensation thin film transistor T3, and the storage capacitor Cst are mainly shown, and some components or elements can be omitted.

[0136] Referring to Figure 6 and Figure 7 The driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can be arranged or disposed along the semiconductor layer 1130. The semiconductor layer 1130 can be disposed on the substrate 100, the barrier layer 110 can include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and the buffer layer 111 can include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0137] In an embodiment, the lower gate electrode G1a of the driving thin film transistor T1 and the separate signal line SL' can be included or disposed between the barrier layer 110 and the buffer layer 111. The lower gate electrode G1a of the driving thin film transistor T1 and the separate signal line SL' can include a metal such as Mo, Al, Cu, Ti, and an alloy thereof. The separate signal line SL' can extend in the second direction DR2.

[0138] Some regions or portions of the semiconductor layer 1130 can correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. In other words, it can be understood that the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can be electrically connected to each other and curved in various shapes. Figure 7 The driving semiconductor layer 1130a of the driving thin film transistor T1 and the compensation semiconductor layer 1130c of the compensation thin film transistor T3, which correspond to a portion of the semiconductor layer 1130, are shown.

[0139] The semiconductor layer 1130 can include amorphous silicon or polysilicon. In an embodiment, the semiconductor layer 1130 can include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn.

[0140] The semiconductor layer 1130 can include a channel region and source and drain regions at both sides of the channel region, which can be understood as source and drain electrodes of a corresponding thin-film transistor. Hereinafter, the terms source and drain regions can be used instead of source and drain electrodes.

[0141] The semiconductor layer 1130 can be formed of a single layer or multiple layers, and the thin-film transistor can include an electrode layer (e.g., E3 in FIG. 11) electrically connected to at least one of the source and drain regions. Figure 7

[0142] The driving thin-film transistor T1 can include an upper gate electrode G1b of the driving thin-film transistor T1 overlapping with a driving channel region C1 and a driving source region S1 and a driving drain region D1 at both sides of the driving channel region C1. The driving channel region C1 of the driving thin-film transistor T1 overlapping with the upper gate electrode G1b can have a substantially curved shape such as an omega or an arc shape to form a long channel length in a narrow space. When the driving channel region C1 is long, a driving range of a gate voltage can be widened, so that a gradation of light emitted from an organic light-emitting diode OLED (see FIG. 11) can be more precisely controlled, and display quality can be improved. Figure 7

[0143] In an embodiment, a lower gate electrode G1a of the driving thin-film transistor T1 can overlap with the driving channel region C1 and the driving drain region D1. As shown in FIG. 11, the lower gate electrode G1a of the driving thin-film transistor T1 can have a shape substantially the same as that of the upper gate electrode G1b of the driving thin-film transistor T1, but can be greater than the upper gate electrode G1b of the driving thin-film transistor T1 at a remaining portion except for an end portion adjacent to the driving source region S1. For example, in a plan view, the lower gate electrode G1a of the driving thin-film transistor T1 can not exist under the driving source region S1. Figure 7

[0144] The switching thin-film transistor T2 can include a switching gate electrode G2 overlapping with a switching channel region and a switching source region S2 and a switching drain region D2 at both sides of the switching channel region. The switching drain region D2 can be electrically connected to the driving source region S1.

[0145] The compensation thin-film transistor T3 can be a dual-gate thin-film transistor having a compensation gate electrode G3 overlapping with two compensation channel regions C3 and can include a compensation source region S3 and a compensation drain region D3 at both sides of the compensation channel region C3. The compensation thin-film transistor T3 can be electrically connected to the upper gate electrode G1b of the driving thin-film transistor T1 through a node connection line 1174 to be described later.

[0146] ​​​The first initialization thin film transistor T4 can be a double gate thin film transistor having a first initialization gate electrode G4 overlapping with two first initialization channel regions, and can include a first initialization source region S4 and a first initialization drain region D4 positioned at both sides of the first initialization channel regions.

[0147] The operation control thin film transistor T5 can include an operation control gate electrode G5 overlapping with an operation control channel region, and can include an operation control source region S5 and an operation control drain region D5 positioned at both sides of the operation control channel region. The operation control drain region D5 can be electrically connected to the driving source region S1.

[0148] The emission control thin film transistor T6 can include an emission control gate electrode G6 overlapping with an emission control channel region, and can include an emission control source region S6 and an emission control drain region D6 positioned at both sides of the emission control channel region. The emission control source region S6 can be electrically connected to the driving drain region D1.

[0149] The second initialization thin film transistor T7 can include a second initialization gate electrode G7 overlapping with a second initialization channel region, and a second initialization source region S7 and a second initialization drain region D7 positioned at both sides of the second initialization channel region.

[0150] The above-described thin film transistors can be electrically connected to the signal lines SWL, SIL, EL, and DL, the initialization voltage line VIL, and the driving voltage line PL.

[0151] The first gate insulating layer 113 can be disposed on the above-described semiconductor layer 1130, and the scan line SWL, the previous scan line SIL, the emission control line EL, the upper gate electrode G1b of the driving thin film transistor T1, and the initialization voltage line VIL can be disposed on the first gate insulating layer 113. The first gate insulating layer 113 can include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. The scan line SWL, the previous scan line SIL, the emission control line EL, the upper gate electrode G1b of the driving thin film transistor T1, and the initialization voltage line VIL can include a metal such as Mo, Al, Cu, Ti and an alloy thereof.

[0152] The scan line SWL can extend in the second direction DR2. Some regions or portions of the scan line SWL can correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, regions of the scan line SWL overlapping with the channel regions of the switching thin film transistor T2 and the compensation thin film transistor T3 can be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0153] The previous scan line SIL can extend in the second direction DR2, and some regions or portions of the previous scan line SIL can respectively correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, some regions or portions of the previous scan line SIL that overlap with channel regions of the first initialization drive thin film transistor T4 and the second initialization drive thin film transistor T7 can respectively be the first initialization gate electrode G4 and the second initialization gate electrode G7.

[0154] The emission control line EL can extend in the second direction DR2. Some regions or portions of the emission control line EL can respectively correspond to the operation control gate electrode G5 and the emission control gate electrode G6. For example, some regions or portions of the emission control line EL that overlap with channel regions of the operation control thin film transistor T5 and the emission control thin film transistor T6 can respectively be the operation control gate electrode G5 and the emission control gate electrode G6.

[0155] The upper gate electrode G1b of the drive thin film transistor T1 can be a floating electrode, and can be electrically connected to the compensation thin film transistor T3 through the node connection line 1174.

[0156] The initialization voltage line VIL can extend in the second direction DR2. The initialization voltage line VIL can be electrically connected to the first initialization drive thin film transistor T4 and the second initialization drive thin film transistor T7 through the initialization connection line 1173.

[0157] In Figure 11A , the initialization voltage line VIL can be disposed on the second gate insulating layer 115. However, in an embodiment, the initialization voltage line VIL can be disposed on the planarization layer 120, and can include a material that is the same as or similar to a material of the pixel electrode 310.

[0158] The electrode voltage line HL can be located on the scan line SWL, the previous scan line SIL, the emission control line EL, the upper gate electrode G1b of the drive thin film transistor T1, and the initialization voltage line VIL described above, and the second gate insulating layer 115 including an inorganic material is disposed between the electrode voltage line HL and the scan line SWL, the previous scan line SIL, the emission control line EL, the upper gate electrode G1b of the drive thin film transistor T1, and the initialization voltage line VIL. The second gate insulating layer 115 can include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0159] A portion of the electrode voltage line HL can cover or overlap at least a portion of the upper gate electrode G1b of the drive thin film transistor T1, and can form a storage capacitor Cst together with the upper gate electrode G1b of the drive thin film transistor T1. For example, the upper gate electrode G1b of the drive thin film transistor T1 can be a first storage capacitor plate Cst1 of the storage capacitor Cst, and a portion of the electrode voltage line HL can be a second storage capacitor plate Cst2 of the storage capacitor Cst.

[0160] The electrode voltage line HL and the second storage capacitor plate Cst2 can be electrically connected to the drive voltage line PL. In this regard, Figure 6 It is shown that the electrode voltage line HL can be electrically connected to the drive voltage line PL located on the electrode voltage line HL through the contact hole 1158. The electrode voltage line HL can have the same voltage level as the voltage level of the drive voltage line PL (constant voltage, for example, approximately +5V). The electrode voltage line HL can be understood as a kind of lateral drive voltage line.

[0161] Since the drive voltage line PL can extend in the first direction DR1, and the electrode voltage line HL which can be electrically connected to the drive voltage line PL can extend in the second direction DR2 which crosses or intersects the first direction DR1, the drive voltage line PL and the electrode voltage line HL can form a grid structure in the display area.

[0162] The conductive layer CL can be provided on the second storage capacitor plate Cst2 and the electrode voltage line HL, and a first interlayer insulating layer 117 including an inorganic material is provided between the conductive layer CL and the second storage capacitor plate Cst2 and the electrode voltage line HL. The conductive layer CL can include a data line DL, a drive voltage line PL, an initialization connection line 1173, and a node connection line 1174. The data line DL, the drive voltage line PL, the initialization connection line 1173, and the node connection line 1174 can include Al, Cu, Ti, and the like, and can be a single layer or multiple layers. In an embodiment, the drive voltage line PL and the data line DL can have a multi-layer structure of Ti / Al / Ti.

[0163] The data line DL can extend in the first direction DR1, and can be electrically connected to the switching source region S2 of the switching thin film transistor T2 through the contact hole 1154. A portion of the data line DL can be understood as a switching source region.

[0164] The drive voltage line PL can extend in the first direction DR1, and can be electrically connected to the electrode voltage line HL through the contact hole 1158, as described above. As an example, the drive voltage line PL can be electrically connected to the operation control thin film transistor T5 through the contact hole 1155. The drive voltage line PL can be electrically connected to the operation control source region S5 through the contact hole 1155.

[0165] One end of the initialization connection line 1173 can be electrically connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through the contact hole 1152, and the other end can be electrically connected to the initialization voltage line VIL described above through the contact hole 1151.

[0166] One end of the node connection line 1174 can be electrically connected to the compensation drain region D3 through the contact hole 1156 and the compensation electrode layer E3, and the other end can be electrically connected to the upper gate electrode G1b of the driving thin film transistor T1 through the contact hole 1157.

[0167] The planarization layer 120 can be disposed on the data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174, and the planarization layer 120 can include a general-purpose polymer such as benzocyclobutene (BCB), polyimide (PI), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), and polystyrene (PS), a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol polymer, or a blend thereof. The organic light emitting diode OLED can be disposed on the planarization layer 120. The organic light emitting diode OLED can include the pixel electrode 310, the intermediate layer 320 including an organic light emitting layer, and the counter electrode 330.

[0168] Referring to Figure 7 An edge of the pixel electrode 310 can be covered or overlapped with the pixel definition layer 125 located on the planarization layer 120, and a central region of the pixel electrode 310 can be exposed through an opening of the pixel definition layer 125. The pixel definition layer 125 can be formed by spin coating or the like with one or more organic insulating materials of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. The pixel electrode 310 can include a reflective film of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound including the same. In an embodiment, the pixel electrode 310 can include a film formed of ITO, IZO, ZnO, or In2O3 located above / below the reflective layer. The intermediate layer 320 can be disposed on the pixel electrode 310 exposed through the opening.

[0169] The intermediate layer 320 of the organic light emitting diode OLED can include an organic emission layer. The organic emission layer can include an organic material including a fluorescent or phosphorescent material that can emit red light, green light, blue light, or white light. The organic emission layer can include a low molecular weight organic material or a high molecular weight organic material. Although not shown, a functional layer such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) can be selectively arranged or disposed above and below the organic emission layer. The intermediate layer 320 can be arranged or disposed corresponding to each of the pixel electrodes 310. However, the disclosure is not limited thereto. The intermediate layer 320 can include a layer that can be integrated with the pixel electrode 310, and various modifications can be made within the spirit and scope of the disclosure.

[0170] The counter electrode 330 can be arranged or disposed to face the pixel electrode 310, and the intermediate layer 320 is disposed between the counter electrode 330 and the pixel electrode 310. The counter electrode 330 can include a conductive material having a low work function. For example, the counter electrode 330 can include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Alternatively, the counter electrode 330 can include a layer including, for example, ITO, IZO, ZnO, or In2O3, on a (semi-)transparent layer including the above-described material.

[0171] Referring to Figure 6 and Figure 7 The thin film transistor substrate TB according to the embodiment can include a driving thin film transistor T1. The lower gate electrode G1a of the driving thin film transistor T1 can overlap the driving semiconductor layer 1130a, for example, can overlap the driving channel region C1 and the driving drain region D1. For example, the lower gate electrode G1a of the driving thin film transistor T1 can be disposed not to overlap the driving source region S1, and can overlap the driving semiconductor layer 1130a by avoiding or being separated from the driving source region S1.

[0172] In this case, since a value close to an ideal channel potential as described with respect to Figure 13 can be maintained, and the lower gate electrode G1a of the driving thin film transistor T1 can overlap the driving channel region C1 and the driving drain region D1, interference with an adjacent signal close to the driving source region S1 can be reduced.

[0173] Since the area of the lower gate electrode G1a of the driving thin film transistor T1 can be reduced when the driving source region S1 can be avoided, adjacent devices can be arranged or disposed closer thereto. For example, the area of the pixel circuit PC can be reduced, and the resolution can be improved.

[0174] In the embodiment, the area of the lower gate electrode G1a of the driving thin film transistor T1 can be reduced with respect to the case in whichFigure 6 The device arranged or disposed at the left side of the straight line I extending in the first direction DR1 can be moved to the right side of the second direction DR2 by about 1 pm. As a result, the length of each pixel circuit PC in the second direction DR2 can be reduced by about 1 pm, so that more pixel circuits PC can be arranged or disposed in the thin-film transistor substrate TB, thereby obtaining high resolution.

[0175] Referring to the straight line I extending in the first direction DR1, Figure 6 In the plan view, one end of the upper gate electrode G1b of the drive thin-film transistor T1 adjacent to the drive source region S1 can coincide with one end of the lower gate electrode G1a of the drive thin-film transistor T1.

[0176] In an embodiment, the thin-film transistor substrate TB can include a conductive layer CL arranged or disposed in the first direction DR1. The data line DL can be included as a part of the conductive layer CL. In the plan view, a gap (distance) W1a between the lower gate electrode G1a of the drive thin-film transistor T1 and the data line DL can be equal to a gap (distance) W1b between the upper gate electrode G1b of the drive thin-film transistor T1 and the data line DL.

[0177] Figure 6 and Figure 7 It is shown that the drive thin-film transistor T1 can have the lower gate electrode G1a of the drive thin-film transistor T1, but the other thin-film transistors T2 to T7 can also have the lower gate electrode and the lower gate electrode can overlap the semiconductor layer by avoiding or being separated from the respective source regions.

[0178] Figure 8 is an equivalent circuit diagram of one pixel PX of the display panel according to an embodiment.

[0179] Referring to Figure 8 , the pixel PX can include signal lines SL1, SL2, SLp, SLn, EL, and DL; and thin-film transistors T1, T2, T3, T4, T5, T6, and T7 electrically connected to the signal lines SL1, SL2, SLp, SLn, EL, and DL; a storage capacitor Cst; a boost capacitor Cbt; an initialization voltage line VIL; a driving voltage line PL; and an organic light emitting diode OLED as a display element. In an embodiment, at least one of the signal lines SL1, SL2, SLp, SLn, EL, and DL, for example, the initialization voltage line VIL and / or the driving voltage line PL, can be shared by adjacent pixels PX.

[0180] The thin film transistors can include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initializing thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initializing thin film transistor T7.

[0181] Some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as n-channel MOSFETs (NMOS), and the remaining thin film transistors can be provided as p-channel MOSFETs (PMOS).

[0182] For example, as shown in FIG. 1A, the compensation thin film transistor T3 and the first initializing thin film transistor T4 among the thin film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as NMOS, and the remaining thin film transistors can be provided as PMOS. Figure 8

[0183] In an embodiment, the compensation thin film transistor T3, the first initializing thin film transistor T4, and the second initializing thin film transistor T7 among the thin film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as NMOS, and the remaining thin film transistors can be provided as PMOS. Alternatively, only one thin film transistor among the thin film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as NMOS, and the remaining thin film transistors can be provided as PMOS. Alternatively, the thin film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as NMOS.

[0184] The signal lines SL1, SL2, SLp, SLn, EL, and DL can include a first scan line SL1 that transmits a first scan signal Sn, a second scan line SL2 that transmits a second scan signal Sn', a previous scan line SLp that transmits a previous scan signal Sn-1 to the first initializing thin film transistor T4, an emission control line EL that transmits an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, a next scan line SLn that transmits a next scan signal Sn+1 to the second initializing thin film transistor T7, and a data line DL that can cross or intersect the first scan line SL1 and can transmit a data signal Dm.

[0185] The driving voltage line PL can transmit a first power voltage ELVDD to the driving thin film transistor T1, and the initializing voltage line VIL can transmit an initializing voltage Vint that can initialize the driving thin film transistor T1 and the pixel electrode.

[0186] ​The driving gate electrode of the driving thin-film transistor T1 can be electrically connected to the storage capacitor Cst, the driving source region of the driving thin-film transistor T1 can be electrically connected to the driving voltage line PL via the operation control thin-film transistor T5, and the driving drain region of the driving thin-film transistor T1 can be electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin-film transistor T6. The driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin-film transistor T2, and can supply the driving current I OLED to the organic light emitting diode OLED.

[0187] The switching gate electrode of the switching thin-film transistor T2 can be electrically connected to the first scan line SL1, the switching source region of the switching thin-film transistor T2 can be electrically connected to the data line DL, and the switching drain region of the switching thin-film transistor T2 can be electrically connected to the driving source region of the driving thin-film transistor T1 and can be electrically connected to the driving voltage line PL through the operation control thin-film transistor T5. The switching thin-film transistor T2 can be turned on in response to the first scan signal Sn received through the first scan line SL1, and can perform a switching operation that can transfer the data signal Dm transferred to the data line DL to the driving source region of the driving thin-film transistor T1.

[0188] The compensation gate electrode of the compensation thin-film transistor T3 can be electrically connected to the second scan line SL2. The compensation drain region of the compensation thin-film transistor T3 can be electrically connected to the driving drain region of the driving thin-film transistor T1 and can be electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin-film transistor T6. The compensation source region of the compensation thin-film transistor T3 can be electrically connected to the first electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin-film transistor T1 through the node connection line 166. The compensation source region can be electrically connected to the first initialization drain region of the first initialization thin-film transistor T4.

[0189] The compensation thin-film transistor T3 can be turned on in response to the second scan signal Sn' received through the second scan line SL2, and can electrically connect the driving drain region of the driving thin-film transistor T1 to the driving gate electrode, thereby connecting the driving thin-film transistor T1 in a diode manner.

[0190] The first initialization gate electrode of the first initialization thin film transistor T4 can be electrically connected to a previous scan line SLp. The first initialization source region of the first initialization thin film transistor T4 can be electrically connected to the second initialization source region of the second initialization thin film transistor T7 and an initialization voltage line VIL. The first initialization drain region of the first initialization thin film transistor T4 can be electrically connected to a first electrode CE1 of a storage capacitor Cst, a compensation source region of a compensation thin film transistor T3, and a driving gate electrode of a driving thin film transistor T1. The first initialization thin film transistor T4 can be turned on in response to a previous scan signal Sn-1 received through the previous scan line SLp, and can initialize a voltage of the driving gate electrode of the driving thin film transistor T1 by transmitting an initialization voltage Vint to the driving gate electrode of the driving thin film transistor T1.

[0191] The operation control gate electrode of the operation control thin film transistor T5 can be electrically connected to an emission control line EL, the operation control source region of the operation control thin film transistor T5 can be electrically connected to a driving voltage line PL, and the operation control drain region of the operation control thin film transistor T5 can be electrically connected to a driving source region of the driving thin film transistor T1 and a switching drain region of the switching thin film transistor T2.

[0192] The emission control gate electrode of the emission control thin film transistor T6 can be electrically connected to the emission control line EL, the emission control source region of the emission control thin film transistor T6 can be electrically connected to a driving drain region of the driving thin film transistor T1 and a compensation drain region of the compensation thin film transistor T3, and the emission control drain region of the emission control thin film transistor T6 can be electrically connected to a second initialization drain region of the second initialization thin film transistor T7 and a pixel electrode of the organic light emitting diode OLED.

[0193] The operation control thin film transistor T5 and the emission control thin film transistor T6 can be simultaneously turned on in response to an emission control signal En received through the emission control line EL, so that a first power voltage ELVDD can be transmitted to the organic light emitting diode OLED, and a driving current I OLED may flow through the organic light emitting diode OLED.

[0194] A second initialization gate electrode G7 of the second initialization thin film transistor T7 can be electrically connected to a next scan line SLn, a second initialization drain region of the second initialization thin film transistor T7 can be electrically connected to an emission control drain region of the emission control thin film transistor T6 and a pixel electrode of the organic light emitting diode OLED, and a second initialization source region of the second initialization thin film transistor T7 can be electrically connected to a first initialization source region of the first initialization thin film transistor T4 and an initialization voltage line VIL. The second initialization thin film transistor T7 can be turned on in response to a next scan signal Sn+1 received through the next scan line SLn to initialize the pixel electrode of the organic light emitting diode OLED.

[0195] The second initialization thin film transistor T7 can be electrically connected to a next scan line SLn as shown in FIG. 1B. Figure 8 In an embodiment, the second initialization thin film transistor T7 can be electrically connected to an emission control line EL and can be driven according to an emission control signal En. Meanwhile, Figure 7 The positions of the source region and the drain region of the thin film transistor can be changed depending on the type (p-type or n-type) of the thin film transistor.

[0196] The storage capacitor Cst can include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst can be electrically connected to a driving gate electrode of the driving thin film transistor T1, and the second electrode CE2 of the storage capacitor Cst can be electrically connected to a driving voltage line PL. The storage capacitor Cst can store a charge corresponding to a difference between a driving gate electrode voltage of the driving thin film transistor T1 and a first power voltage ELVDD.

[0197] The boost capacitor Cbt can include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 can be electrically connected to a switching gate electrode of the switching thin film transistor T2 and a first scan line SL1, and the fourth electrode CE4 can be electrically connected to a compensation source region of the compensation thin film transistor T3 and a node connection line 166. The boost capacitor Cbt can boost a voltage of a first node N1 when a first scan signal Sn supplied to the first scan line SL1 can be cut off. In this way, when the voltage of the first node N1 is boosted, a black gray scale can be clearly presented.

[0198] The first node N1 can be an area to which the driving gate electrode of the driving thin film transistor T1, the compensation source region of the compensation thin film transistor T3, the first initialization drain region of the first initialization thin film transistor T4, and the fourth electrode CE4 of the boost capacitor Cbt can be electrically connected.

[0199] The operation of each pixel PX according to an embodiment can be as follows.

[0200] When the previous scan signal Sn-1 is supplied through the previous scan line SLp during the initialization period, the first initialization thin film transistor T4 can be turned on in response to the previous scan signal Sn-1, and an initialization voltage Vint supplied from the initialization voltage line VIL can initialize the driving thin film transistor T1.

[0201] When the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2 during the data programming period, the switching thin film transistor T2 and the compensation thin film transistor T3 can be turned on in response to the first scan signal Sn and the second scan signal Sn'. Here, the driving thin film transistor T1 can be connected in a diode manner when the compensation thin film transistor T3 can be turned on, and can be biased in a forward direction.

[0202] A compensation voltage Dm+Vth (Vth is a negative value) of a threshold voltage Vth of the driving thin film transistor T1 subtracted from a data signal Dm supplied from the data line DL can be applied to the driving gate electrode G1 of the driving thin film transistor T1.

[0203] The first power voltage ELVDD and the compensation voltage Dm+Vth can be applied to both ends of the storage capacitor Cst, and a charge corresponding to a voltage difference between the both ends can be stored in the storage capacitor Cst.

[0204] During the light emission period, the operation control thin film transistor T5 and the emission control thin film transistor T6 can be turned on by an emission control signal En supplied from the emission control line EL. A driving current I OLED , corresponding to a difference between a voltage of the driving gate electrode G1 of the first thin film transistor T1 and the first power voltage ELVDD can be generated. OLED The organic light emitting diode OLED can be supplied with the driving current I

[0205] In an embodiment, at least one of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 can include a semiconductor layer including an oxide, and the other thin film transistors can include a semiconductor layer including silicon.

[0206] More specifically, the driving thin film transistor directly affecting the brightness of the display apparatus can include a semiconductor layer composed of polysilicon having high reliability, thereby realizing a high resolution display apparatus.

[0207] Meanwhile, since the oxide semiconductor has high carrier mobility and low leakage current, a voltage drop can not be large even though a driving time can be long. For example, since a color change of an image due to a voltage drop can be small even at low frequency driving, low frequency driving can be performed.

[0208] Thus, since the oxide semiconductor has less off current, at least one of the compensation thin-film transistor T3, the first initialization thin-film transistor T4, and the second initialization thin-film transistor T7 electrically connected to the drive gate electrode G1 of the drive thin-film transistor T1 can be used as an oxide semiconductor to prevent off current from flowing to the drive gate electrode G1, and power consumption can be reduced.

[0209] Figure 9 is a plan view of some layers of Figures 10A-10D Figure 9 Figure 11A and Figure 11B is a schematic cross-sectional view of the pixel circuit PC taken along line III-III' of Figure 9 Figure 12 is a cross-sectional view of the pixel circuit PC taken along line IV-IV' of Figure 9

[0210] Figures 10A-10D is a plan view of some layers of Figure 9 Figure 10A illustrates the semiconductor layer Act and the conductive layer CL located on the substrate 100 and the buffer layer 111, and Figure 10B illustrates the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 and the like located on the second gate insulating layer 115. For example, Figure 10C illustrates the contact holes CNT1-1, CNT1-2, CNT2, CNT3-1, CNT3-2, CNT4-1, CNT4-2, CNT4-3, CNT5-1, CNT5-2, and CNT6 electrically connecting the devices, the node connection line 166, and the electrode layers 165, 167, 168, and 169 located on the second interlayer insulating layer 119, respectively, and Figure 10D illustrates the data line DL and the drive voltage line PL located on the first planarization layer 121, and the contact holes CNT7, CNT8, CNT9, and CNT10 electrically connecting the devices, respectively. Hereinafter, they will be described in more detail. Figure 9

[0211] Referring to Figure 9 , Figure 10A , Figure 10B , Figure 10C and Figure 10D , the pixel circuit PC of the display device according to the embodiment can include a data line DL and a drive voltage line PL extending in a first direction DR1, and a first scan line SL1, a second scan line SL2, a previous scan line SLp, and a next scan line SLn extending in a second direction DR2 (see Figure 7 ​​​​​​), an emission control line EL, and an initialization voltage line VIL.

[0212] The pixel circuit PC can include a drive thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, a second initialization thin film transistor T7, a storage capacitor Cst, and a boost capacitor Cbt.

[0213] In an embodiment, the drive thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can be provided as thin film transistors including a silicon semiconductor.

[0214] The compensation thin film transistor T3 and the first initialization thin film transistor T4 can each be provided as a thin film transistor including an oxide semiconductor.

[0215] The semiconductor layers of the drive thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can be located on the same layer and can include the same or similar material. For example, the semiconductor layers can include polysilicon.

[0216] The semiconductor layers of the drive thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can be disposed on a buffer layer 111 located on the substrate 100 (see Figure 11A the buffer layer 111 of FIG. 1).

[0217] The semiconductor layers of the drive thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can be electrically connected to each other and can be curved in various shapes.

[0218] The semiconductor layers of the drive thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can each include a channel region and source and drain regions located at both sides of the channel region. For example, the source and drain regions can be doped with impurities, and the impurities can include N-type impurities or P-type impurities. The source and drain regions can correspond to source and drain electrodes, respectively. Hereinafter, the terms source and drain regions can be used instead of source and drain electrodes.

[0219] The driving thin film transistor T1 can include a driving semiconductor layer and a driving gate electrode G1. The driving semiconductor layer can include a driving channel region C1 and a driving source region S1 and a driving drain region D1 located at both sides of the driving channel region C1. The driving semiconductor layer can have a substantially curved shape, and the driving channel region C1 can be formed longer than the other channel regions C2 to C7. For example, because the driving semiconductor layer can have a curved multiple shape, such as an omega (or arched) shape or a letter "S", a long channel length can be formed in a narrow space. Because the driving channel region C1 can be formed longer, a driving range of a gate voltage applied to the driving gate electrode G1 can be widened, so that a gradation of light emitted from the organic light emitting diode OLED can be more precisely controlled, and display quality can be improved. The driving gate electrode G1 can be isolated or island-shaped, and can be disposed to overlap the driving channel region C1 and a first gate insulating layer 113 (see Figure 11A ) located between the driving gate electrode G1 and the driving channel region C1.

[0220] The storage capacitor Cst can overlap the driving thin film transistor T1. The storage capacitor Cst can include a first electrode CE1 and a second electrode CE2. The driving gate electrode G1 can not only perform a function of a gate electrode of the driving thin film transistor T1, but also perform a function of the first electrode CE1 of the storage capacitor Cst. For example, it can be understood that the driving gate electrode G1 and the first electrode CE1 can be integral. The second electrode CE2 of the storage capacitor Cst can be disposed to overlap the first electrode CE1 and a second gate insulating layer 115 (see Figure 12 ) located between the second electrode CE2 and the first electrode CE1. Here, the second gate insulating layer 115 can function as a dielectric layer of the storage capacitor Cst.

[0221] The second electrode CE2 can have a storage opening SOP. The storage opening SOP can be formed by removing a portion of the second electrode CE2, and can have a closed shape. The node connection line 166 can be electrically connected to the first electrode CE1 through a first connection contact hole CNT1-1 in the storage opening SOP. The second electrode CE2 can be electrically connected to the driving voltage line PL through a first driving contact hole CNT5-1 and an eighth contact hole CNT8. The second electrode CE2 can extend in the second direction DR2 to transmit the first power voltage ELVDD in the second direction DR2. Accordingly, in the display area DA, the driving voltage line PL and the second electrode CE2 can form a mesh structure.

[0222] The switch thin film transistor T2 can include a switch semiconductor layer and a switch gate electrode G2. The switch semiconductor layer can include a switch channel region C2 and a switch source region S2 and a switch drain region D2 located at both sides of the switch channel region C2. The switch source region S2 can be electrically connected to the data line DL through the second contact hole CNT2, the seventh contact hole CNT7, and the first electrode layer 165, and the switch drain region D2 can be electrically connected to the driving source region S1.

[0223] The operation control thin film transistor T5 can include an operation control semiconductor layer and an operation control gate electrode G5. The operation control semiconductor layer can include an operation control channel region C5 and an operation control source region S5 and an operation control drain region D5 located at both sides of the operation control channel region C5. The operation control source region S5 can be electrically connected to the driving voltage line PL through the second driving contact hole CNT5-2 and the eighth contact hole CNT8, and the operation control drain region D5 can be electrically connected to the driving source region S1. The operation control gate electrode G5 can be disposed as a part of the emission control line EL.

[0224] The emission control thin film transistor T6 can include an emission control semiconductor layer and an emission control gate electrode G6. The emission control semiconductor layer can include an emission control channel region C6 and an emission control source region S6 and an emission control drain region D6 located at both sides of the emission control channel region C6. The emission control source region S6 can be electrically connected to the driving drain region D1, and the emission control drain region D6 can be electrically connected to the second electrode layer 167 through the sixth contact hole CNT6. The second electrode layer 167 can be electrically connected to the pixel electrode 310 (see Figure 11A of the organic light emitting diode OLED) through the upper electrode layer 177 disposed or arranged on another layer, the ninth contact hole CNT9, and the tenth contact hole CNT10. The emission control gate electrode G6 can be disposed as a part of the emission control line EL.

[0225] The second initialization thin film transistor T7 can include a second initialization semiconductor layer and a second initialization gate electrode G7. The second initialization semiconductor layer can include a first initialization channel region C7, a second initialization source region S7, and a second initialization drain region D7 located at both sides of the second initialization channel region C7. The second initialization source region S7 can be electrically connected to the initialization voltage line VIL through the fifth connection contact hole CNT4-3 and the third electrode layer 168, and the second initialization drain region D7 can be electrically connected to the first initialization source region S4 which will be described later. The second initialization gate electrode G7 can be disposed as a part of the next scan line SLn.

[0226] The first interlayer insulating layer 117 (see Figure 11A) can be provided on thin film transistors T1, T2, T5, T6, and T7 including silicon semiconductors, and thin film transistors T3 and T4 including oxide semiconductors can be provided on the first interlayer insulating layer 117.

[0227] The semiconductor layer AO3 of the compensation thin film transistor T3 and the semiconductor layer AO4 of the first initialization thin film transistor T4 can be provided on the same layer and can include the same or similar material. For example, the semiconductor layers can include an oxide semiconductor.

[0228] The compensation thin film transistor T3 can include a compensation semiconductor layer AO3 (see Figure 11A ) including an oxide semiconductor and a compensation gate electrode G3. The compensation semiconductor layer AO3 can include a compensation channel region C3 and a compensation source region S3 and a compensation drain region D3 arranged or provided on one side and the other side of the compensation channel region C3, respectively. The compensation source region S3 can be bridged to the driving gate electrode G1 through a node connection line 166. One end of the node connection line 166 can be electrically connected to the compensation source region S3 through a second connection contact hole CNT1-2, and the other end of the node connection line 166 can be electrically connected to the driving gate electrode G1 through a first connection contact hole CNT1-1. The compensation source region S3 can be electrically connected to the first initialization drain region D4 located on the same layer. The compensation drain region D3 can be electrically connected to the driving semiconductor layer of the driving thin film transistor T1 and the emission control semiconductor layer of the emission control thin film transistor T6 through a fourth electrode layer 169. The compensation gate electrode G3 can be provided as part of the second scan line SL2.

[0229] The first initialization thin film transistor T4 can include a first initialization semiconductor layer AO4 (see Figure 11A ) including an oxide semiconductor and a first initialization gate electrode G4. The first initialization semiconductor layer AO4 can include a first initialization channel region C4 and a first initialization source region S4 and a first initialization drain region D4 located at both sides of the first initialization channel region C4. The first initialization source region S4 can be electrically connected to the third electrode layer 168 through a third connection contact hole CNT4-1, and the third electrode layer 168 can be electrically connected to the initialization voltage line VIL through a fourth connection contact hole CNT4-2. The first initialization drain region D4 can be bridged to the driving gate electrode G1 through the node connection line 166. The first initialization gate electrode G4 can be provided as part of the previous scan line SLp.

[0230] Referring to Figure 10B , in an embodiment, the compensation semiconductor layer AO3 and the first initialization semiconductor layer AO4 can be integral with each other and can have a shape of an island or an island.

[0231] A third gate insulating layer 118 (see Figure 11A ) can be provided between the compensation semiconductor layer AO3 and the compensation gate electrode G3, and can be provided between the first initialization semiconductor layer AO4 and the first initialization gate electrode G4, to correspond to each of the channel regions C3 and C4.

[0232] A third electrode CE3, which can be one electrode of a boost capacitor Cbt, can be provided as part of the first scan line SL1, and can be electrically connected to the switch gate electrode G2. A fourth electrode CE4 of the boost capacitor Cbt can be arranged or provided to overlap the third electrode CE3, and can include an oxide semiconductor. The fourth electrode CE4 can be provided or arranged on the same layer as the compensation semiconductor layer AO3 of the compensation thin film transistor T3 and the first initialization semiconductor layer AO4 of the first initialization thin film transistor T4, and thus, can be provided or arranged as a region between the compensation semiconductor layer AO3 and the initialization semiconductor layer AO4. Optionally, the fourth electrode CE4 can extend from the first initialization semiconductor layer AO4. Optionally, the fourth electrode CE4 can extend from the compensation semiconductor layer AO3.

[0233] A second interlayer insulating layer 119 (see Figure 11A ) can be provided on the thin film transistors T3 and T4 including the oxide semiconductor, and the drive voltage line PL, the node connection line 166, and the electrode layers 165, 167, 168, and 169 can be provided on the second interlayer insulating layer 119.

[0234] A first planarization layer 121 (see Figure 11A ) can be arranged or provided to cover or overlap the drive voltage line PL and the data line DL.

[0235] In an embodiment, the first scan line SL1, the next scan line SLn, and the emission control line EL can be provided or arranged on the same layer as the layer of the drive gate electrode G1, and can be formed of the same or similar material as the material of the drive gate electrode G1.

[0236] In an embodiment, some wirings can be provided as two conductive layers disposed on different layers. For example, the second scan line SL2 can include a lower scan line 143 and an upper scan line 153 located on different layers. The lower scan line 143 can be provided or disposed on the same layer as a layer of the second electrode CE2 of the storage capacitor Cst, and can be formed of a material that is the same as or similar to a material of the second electrode CE2 of the storage capacitor Cst, and the upper scan line 153 can be disposed on the third gate insulating layer 118. The lower scan line 143 can be arranged or disposed to at least partially overlap the upper scan line 153. Since the lower scan line 143 and the upper scan line 153 can correspond to a portion of the compensation gate electrode G3 of the compensation thin-film transistor T3, the compensation thin-film transistor T3 can have a dual gate structure including a lower gate electrode G3a and an upper gate electrode G3b located below and above the compensation semiconductor layer AO3, respectively (see Figure 11B ).

[0237] In an embodiment, the first initialization thin-film transistor T4 can include at least a portion of the semiconductor layer by having one gate electrode. In this case, the first initialization thin-film transistor T4 can have a single gate structure. In an embodiment, the previous scan line SLp can include a lower previous scan line and an upper previous scan line located on different layers. The lower previous scan line can be provided or disposed on the same layer as a layer of the second electrode CE2 of the storage capacitor Cst, and can be formed of a material that is the same as or similar to a material of the second electrode CE2 of the storage capacitor Cst, and the upper previous scan line can be disposed on the third gate insulating layer 118. The lower previous scan line can be arranged or disposed to at least partially overlap the upper previous scan line. Since the lower previous scan line and the upper previous scan line can correspond to a portion of the first initialization gate electrode G4 of the first initialization thin-film transistor T4, the first initialization thin-film transistor T4 can have a dual gate structure including a lower gate electrode G4a and an upper gate electrode G4b located below and above the first initialization semiconductor layer AO4, respectively (see Figure 1 ).

[0238] In an embodiment, the pixel circuit PC can be arranged or disposed to correspond to a pixel PX of the display area DA shown in Figure 2 and Figure 1 , and can have substantially the same shape.

[0239] In an embodiment, the pixel circuit PC included in the display device 1 (see Figure 11A ) can be arranged or disposed to have a symmetrical shape with the pixel circuit PC adjacent thereto.

[0240] Hereinafter, reference will be made to Figure 11B and Figure 11AThe structure of the display apparatus according to the embodiment is described in detail according to the stacking order. In Figure 11B and Figure 4 the same reference numerals refer to the same elements as those in Figure 7 and Figure 11A . Also, Figure 11B and Figure 11A mainly describe the structure of the compensation thin film transistor T3, the first initialization thin film transistor T4, and the boost capacitor Cbt, and some components can be omitted for convenience of description.

[0241] Referring to Figure 11B and Figure 11B , the display apparatus 1 can include various insulating layers such as a buffer layer 111, a first gate insulating layer 113, a second gate insulating layer 115, a third gate insulating layer 118, a first interlayer insulating layer 117, a second interlayer insulating layer 119, a first planarization layer 121, and a second planarization layer 123.

[0242] The substrate 100 can include a glass material, a ceramic material, a metal material, or a material having a flexible or bendable characteristic. The substrate 100 can have a single layer or a multi-layer structure, and in the case of the multi-layer structure, the substrate 100 can include an inorganic layer. In the embodiment, the substrate 100 can have an organic / inorganic / organic structure.

[0243] The buffer layer 111 can increase the smoothness of the upper surface of the substrate 100, and can be formed of an oxide film such as silicon oxide (SiO x ) and / or a nitride film such as silicon nitride (SiN x ) or silicon oxynitride (SiON).

[0244] The first gate insulating layer 113 can be disposed on the buffer layer 111, and the third electrode CE3 of the boost capacitor Cbt can be disposed on the first gate insulating layer 113. The second gate insulating layer 115 can be arranged or disposed to cover or overlap the third electrode CE3 of the boost capacitor Cbt, and the lower gate electrode G3a of the compensation thin film transistor T3 and the initialization voltage line VIL can be disposed on the second gate insulating layer 115. Referring to Figure 11A , in the embodiment, the lower gate electrode G4a of the first initialization thin film transistor T4 can be disposed on the second gate insulating layer 115.

[0245] The first interlayer insulating layer 117 can be arranged or disposed to cover or overlap the lower gate electrode G3a of the compensation thin film transistor T3 and the initialization voltage line VIL, and the compensation semiconductor layer AO3, the first initialization semiconductor layer AO4, and the fourth electrode CE4 of the boost capacitor Cbt can be disposed on the first interlayer insulating layer 117. In an embodiment, the fourth electrode CE4 of the boost capacitor Cbt can extend from one of the compensation semiconductor layer AO3 and the first initialization semiconductor layer AO4.

[0246] The compensation semiconductor layer AO3 can include a compensation channel region C3, a compensation source region S3, and a compensation drain region D3, and the first initialization semiconductor layer AO4 can include a first initialization channel region C4, a first initialization source region S4, and a first initialization drain region D4.

[0247] In an embodiment, the lower gate electrode G3a of the compensation thin film transistor T3 overlaps the compensation semiconductor layer AO3, for example, can overlap the compensation channel region C3 and the compensation drain region D3. For example, the lower gate electrode G3a of the compensation thin film transistor T3 can overlap the compensation semiconductor layer AO3 by avoiding or being separated from the compensation source region S3. The lower gate electrode G3a of the compensation thin film transistor T3 can be disposed not to overlap the compensation source region S3.

[0248] The upper gate electrode G3b of the compensation thin film transistor T3 and the upper gate electrode G4b of the first initialization thin film transistor T4 can be disposed on the third gate insulating layer 118. The gate electrodes G3 and G4 can be a single layer or a multi-layer of at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. After impurities are doped into the channel regions C3 and C4 (for example, C3 and C4 of FIG. 1A), when the third gate insulating layer 118 is patterned by using the upper gate electrodes G3b and G4b as a mask, the third gate insulating layer 118 can also have a shape substantially the same as that of the upper gate electrodes G3b and G4b. Figure 10C

[0249] In an embodiment, when the first gate insulating layer 113 and the second gate insulating layer 115 are stacked on the substrate 100, the third gate insulating layer 118 can be arranged or disposed to cover or overlap the semiconductor layers AO3 and AO4.

[0250] The gate insulating layers 113, 115, and 118 can include an inorganic material including an oxide or a nitride. For example, the gate insulating layers 113, 115, and 118 can include SiO2, SiN x ​SiO2, SiN, SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0251] The thin film transistors T3 and T4 can include a second interlayer insulating layer 119 and electrode layers E3 and E4 on the second interlayer insulating layer 119, the second interlayer insulating layer 119 covering or overlapping the upper gate electrodes G3b and G4b, the source regions S3 and S4, and the drain regions D3 and D4.

[0252] The electrode layers E3 and E4 can include source electrodes electrically connected to the source regions S3 and S4 and drain electrodes electrically connected to the drain regions D3 and D4. Referring to Figure 7 , the compensation electrode layer E3 is a part of the fourth electrode layer 169, and the first initialization electrode layer E4 is a part of the third electrode layer 168.

[0253] The interlayer insulating layers 117 and 119 can include an inorganic material including an oxide or a nitride. For example, the interlayer insulating layers 117 and 119 can include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0254] The first planarization layer 121 can be disposed on the electrode layers E3 and E4, and a driving voltage line PL can be disposed on the first planarization layer 121. The second planarization layer 123 can be arranged or disposed to cover or overlap the driving voltage line PL. The planarization layer 120 can include a general-purpose polymer such as BCB, polyimide (PI), HMDSO, PMMA, and PS, a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol polymer, or a blend thereof. An organic light emitting diode OLED can be disposed on the second planarization layer 123. The organic light emitting diode OLED can include a pixel electrode 310, an intermediate layer 320 including an organic light emitting layer, and an opposite electrode 330.

[0255] Referring to Figure 9 , an edge of the pixel electrode 310 can be covered or overlap a pixel definition layer 125 on the planarization layer 120, and a central region of the pixel electrode 310 can be exposed through an opening of the pixel definition layer 125. In the spirit and scope of the present disclosure, the pixel definition layer 125 can include at least one organic insulating material selected from among polyimide, polyamide, acrylic resin, BCB, and phenol resin, and can be formed by spin coating or the like.

[0256] Referring toFigure 11A and Figure 13 According to the embodiment, the compensation thin film transistor T3 can include a compensation semiconductor layer AO3 having a compensation channel region C3, a compensation source region S3, and a compensation drain region D3, a gate electrode G3 having a lower gate electrode G3a and an upper gate electrode G3b, and a compensation electrode layer E3 positioned or disposed on or above the lower gate electrode G3a of the compensation thin film transistor T3 and the upper gate electrode G3b of the compensation thin film transistor T3. The compensation electrode layer E3 can be electrically connected to at least one of the compensation source region S3 and the compensation drain region D3.

[0257] In an embodiment, the lower gate electrode G3a of the compensation thin film transistor T3 can overlap the compensation semiconductor layer AO3, for example, can overlap the compensation channel region C3 and the compensation drain region D3. For example, the lower gate electrode G3a of the compensation thin film transistor T3 can be disposed not to overlap the compensation source region S3, and can overlap the compensation semiconductor layer AO3 by avoiding or being separated from the compensation source region S3.

[0258] In this case, since a value close to the ideal channel potential mentioned in Figure 9 can be maintained, and the lower gate electrode G3a of the compensation thin film transistor T3 can overlap the compensation channel region C3 and the compensation drain region D3, interference with an adjacent signal close to the compensation source region S3 can be reduced.

[0259] Since the area of the lower gate electrode G3a of the compensation thin film transistor T3 can be reduced to the extent that the compensation source region S3 can be avoided, an adjacent device can be arranged or disposed closer thereto. For example, the area of the pixel circuit PC can be reduced, and the resolution can be improved.

[0260] In an embodiment, a device arranged or disposed above a straight line l' extending in the second direction DR2 of Figure 9 can be moved downward by about 1 μm in the first direction DR1. As a result, the length of the first direction DR1 of each pixel circuit PC can be reduced by about 1 μm, so that more pixel circuits PC can be arranged or disposed in the thin film transistor substrate TB, resulting in high resolution.

[0261] Referring to a straight line l' extending in the second direction DR2 of Figure 11B , in a plan view, one end of the upper gate electrode G3b of the compensation thin film transistor T3 adjacent to the compensation source region S3 can coincide with one end of the lower gate electrode G3a of the compensation thin film transistor T3.

[0262] In an embodiment, the display device 1 can include a conductive layer CL arranged or disposed in the second direction DR2. The first scan line SL1 can be included as a part of the conductive layer CL. In a plan view, a gap (distance) W2a between the lower gate electrode G3a of the compensation thin film transistor T3 and the first scan line SL1 can be equal to a gap (distance) W2b between the upper gate electrode G3b of the compensation thin film transistor T3 and the first scan line SL1.

[0263] Referring to Figure 13 , the first initialization thin film transistor T4 according to the embodiment includes a first initialization semiconductor layer AO4 having a first initialization channel region C4, a first initialization source region S4, and a first initialization drain region D4, a first initialization gate electrode G4 having a lower gate electrode G4a and an upper gate electrode G4b, and a first initialization electrode layer E4 positioned or disposed on or above the lower gate electrode G4a of the first initialization thin film transistor T4 and the upper gate electrode G4b of the first initialization thin film transistor T4. The first initialization electrode layer E4 can be electrically connected to at least one of the first initialization source region S4 and the first initialization drain region D4.

[0264] In an embodiment, the lower gate electrode G4a of the first initialization thin film transistor T4 can overlap the first initialization semiconductor layer AO4, for example, can overlap the first initialization channel region C4 and the first initialization drain region D4. The first initialization semiconductor layer AO4 can include an oxide semiconductor material.

[0265] In this case, because a value close to an ideal channel potential mentioned in Figure 9 can be maintained and the lower gate electrode G4a of the first initialization thin film transistor T4 can overlap the first initialization channel region C4 and the first initialization drain region D4, interference with an adjacent signal close to the first initialization source region S4 can be reduced.

[0266] Because an area of the lower gate electrode G4a of the first initialization thin film transistor T4 can be reduced to an extent that the first initialization source region S4 can be avoided, an adjacent device can be arranged or disposed closer thereto. For example, an area of the pixel circuit PC can be reduced, and a resolution can be improved.

[0267] In an embodiment, a device arranged or disposed above a straight line l” extending in the second direction DR2 of Figure 9 can be moved downward by about 1 μm in the first direction DR1. As a result, a length of the first direction DR1 of each pixel circuit PC can be reduced by about 1 μm, so that more pixel circuits PC can be arranged or disposed in the thin film transistor substrate TB, resulting in a high resolution.

[0268] Although not shown in Figure 9 , referring to the first initialization thin film transistor T4 in the pixel circuit PC in FIG. 1, the first initialization thin film transistor T4 can include a first initialization semiconductor layer AO4 having a first initialization channel region C4, a first initialization source region S4, and a first initialization drain region D4, a first initialization gate electrode G4 having a lower gate electrode G4a and an upper gate electrode G4b, and a first initialization electrode layer E4 positioned or disposed on or above the lower gate electrode G4a of the first initialization thin film transistor T4 and the upper gate electrode G4b of the first initialization thin film transistor T4.Figure 11B and Figure 12 In the plan view, one end of the upper gate electrode G4b of the first initialization thin film transistor T4 adjacent to the first initialization source region S4 can coincide with one end of the lower gate electrode G4a of the first initialization thin film transistor T4.

[0269] As described above, the compensation thin film transistor T3 and the first initialization thin film transistor T4 can have the lower gate electrodes G3a and G4a overlapping the semiconductor layers AO3 and AO4 by avoiding or separating from the source regions S3 and S4, respectively. In this case, since the areas of the lower gate electrodes G3a and G4a can be reduced to the extent of avoiding the source regions S3 and S4, respectively, the adjacent devices can be arranged or disposed closer than when only one thin film transistor can have a lower gate electrode.

[0270] In an embodiment, each of the source regions S3 and S4 can be avoided or separated from, and the lower gate electrodes G3a and G4a can be reduced by about 1 μm, respectively. For example, the length of the first direction DR1 of each pixel circuit PC can be reduced by about 2 μm, and a higher resolution can be achieved.

[0271] Figure 9 is a schematic cross-sectional view of the display panel taken along the line IV-IV' of Figure 12 In Figure 9 , Figure 11A , Figure 11B and Figure 12 the same reference numerals indicate the same elements, and overlapping descriptions will be omitted.

[0272] Referring to Figure 13 , the drive thin film transistor T1, the first initialization thin film transistor T4, the storage capacitor Cst, and the boost capacitor Cbt, etc. can be provided on the substrate 100.

[0273] The drive thin film transistor T1 can include a drive semiconductor layer AS1 including a drive source region S1 and a drive channel region C1, and a drive gate electrode G1. The first initialization thin film transistor T4 can include a first initialization electrode layer E4 including a first initialization source electrode SE4 and a first initialization drain electrode DE4, a first initialization semiconductor layer AO4 including a first initialization source region S4, a first initialization drain region D4, and a first initialization channel region C4, and a first initialization gate electrode G4.

[0274] The storage capacitor Cst can include a first electrode CE1 and a second electrode CE2, and the boost capacitor Cbt can include a third electrode CE3 and a fourth electrode CE4. As shown, in an embodiment, the first electrode CE1 of the storage capacitor Cst can overlap with the drive gate electrode G1 of the drive thin-film transistor T1, and the fourth electrode CE4 of the boost capacitor Cbt can extend from the first initialization semiconductor layer AO4.

[0275] The lower scan line 143 included in the second scan line SL2 can be provided on the same layer as that of the second electrode CE2 of the storage capacitor Cst, and the upper scan line 153 included in the second scan line SL2 can be provided on the same layer as that of the fourth electrode CE4 of the boost capacitor Cbt.

[0276] The gate electrode G1 of the drive thin-film transistor T1 can be electrically connected to the drain region D4 of the first initialization thin-film transistor T4 through the first connection contact hole CNT1-1, the node connection line 166, and the second connection contact hole CNT1-2.

[0277] Figure 13 is a graph showing a change in channel potential according to an embodiment.

[0278] Referring to Figure 13 , the semiconductor layer can include a source region, a channel region, and a drain region. The x-axis indicates the position of a point in the semiconductor layer away from the source region, and the y-axis indicates the channel potential, e.g., energy, according to the x-axis position. By ​ It can be seen that the change in channel potential when the lower gate electrode can overlap with the semiconductor layer just with the middle of the channel region of the semiconductor layer (Ref. 1), when the lower gate electrode moves about 1 μm toward the source region (S direction), when the lower gate electrode moves about 1 μm toward the drain region (D direction), and when the lower gate electrode does not exist (Ref. 2).

[0279] In an embodiment, the lower gate electrode can overlap with the semiconductor layer by avoiding or being separated from the source region. In this case, since the change in channel potential remains the same as when the lower gate electrode overlaps with the semiconductor layer just with the middle of the channel region (Ref. 1) and when the lower gate electrode overlaps with the channel region and the drain region, interference with an adjacent signal close to the source region can be reduced. Since the width of the lower gate electrode can be reduced, an adjacent device can be positioned or disposed closer thereto, thereby improving resolution.

[0280] Although only the thin-film transistor substrate and the display device including the same have been described thus far, the present disclosure is not limited thereto. For example, a method of manufacturing the thin-film transistor substrate and the display device including the same is also within the spirit and scope of the present disclosure.

[0281] According to embodiments of the disclosure as described above, a thin film transistor substrate having improved resolution and a display apparatus including the same can be implemented. However, the scope of the disclosure is not limited to this effect.

[0282] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the following claims.

Claims

1. A thin film transistor substrate comprising: a first thin film transistor provided over a substrate, the first thin film transistor including: a first semiconductor layer including a first channel region, a first source region, and a first drain region; a first lower gate electrode provided between the substrate and the first semiconductor layer; a first upper gate electrode provided over the first semiconductor layer and overlapping with the first channel region; and a first electrode layer provided over the first upper gate electrode and electrically connected to at least one of the first source region and the first drain region, wherein the first lower gate electrode overlaps with the first channel region and the first drain region, the first upper gate electrode includes a first end adjacent to the first source region and a second end adjacent to the first drain region, the first lower gate electrode includes a first end adjacent to the first source region and a second end adjacent to the first drain region, in a plan view, the second end of the first upper gate electrode and a boundary between the first channel region and the first drain region coincide with each other, and the second end of the first upper gate electrode and the boundary between the first channel region and the first drain region are located within a region of the first lower gate electrode, a width of the first lower gate electrode in one direction is reduced, and in the plan view, the first lower gate electrode overlaps with the first semiconductor layer by avoiding or being separated from the first source region, so that the first end of the first upper gate electrode, the first end of the first lower gate electrode, and a boundary between the first channel region and the first source region coincide with each other.

2. The thin film transistor substrate according to claim 1, wherein the first lower gate electrode does not overlap with the first source region.

3. The thin film transistor substrate according to claim 1, wherein in the plan view, a distance between the first lower gate electrode and a conductive layer provided over the substrate is the same as a distance between the first upper gate electrode and the conductive layer.

4. The thin film transistor substrate according to claim 3, wherein the conductive layer is a scan line.

5. The thin film transistor substrate according to claim 1, wherein the first semiconductor layer includes a silicon semiconductor material or an oxide semiconductor material.

6. The thin film transistor substrate according to claim 1, wherein the thin film transistor substrate further comprises: a second thin film transistor provided over the substrate, the second thin film transistor including: a second semiconductor layer; a second gate electrode partially overlapping with the second semiconductor layer; and a second electrode layer provided over the second gate electrode and electrically connected to the second semiconductor layer, wherein the first semiconductor layer includes an oxide semiconductor material, and the second semiconductor layer includes a silicon semiconductor material.

7. The thin film transistor substrate according to claim 6, wherein the thin film transistor substrate further comprises: a third thin film transistor provided over the substrate, the third thin film transistor including: a third semiconductor layer including a third channel region, a third source region, and a third drain region; a third lower gate electrode provided between the substrate and the third semiconductor layer; a third upper gate electrode provided over the third semiconductor layer and overlapping with the third channel region; and a third electrode layer provided over the third upper gate electrode and electrically connected to at least one of the third source region and the third drain region, wherein the third lower gate electrode overlaps with the third channel region and the third drain region, and the third semiconductor layer includes an oxide semiconductor material.

8. The thin film transistor substrate according to claim 7, wherein The first semiconductor layer and the third semiconductor layer are integral with each other and have an isolated shape.

9. The thin film transistor substrate according to claim 7, wherein The third lower gate electrode overlaps with the third semiconductor layer and does not overlap with the third source region.

10. The thin film transistor substrate according to claim 7, wherein the third upper gate electrode includes one end adjacent to the third source region, the third lower gate electrode includes one end adjacent to the third source region, and in the plan view, the one end of the third upper gate electrode and the one end of the third lower gate electrode coincide with each other.

11. The thin film transistor substrate according to claim 7, wherein the first thin film transistor is a compensation thin film transistor, and the third thin film transistor is an initialization thin film transistor.

12. The thin film transistor substrate according to claim 6, wherein The thin film transistor substrate further includes: a boost capacitor including a lower electrode and an upper electrode, wherein the lower electrode and the second gate electrode are provided on the same layer, and the upper electrode and the first semiconductor layer are provided on the same layer.

13. The thin film transistor substrate according to claim 12, wherein, The upper electrode extends from the first semiconductor layer.

14. A display device comprising: a first thin film transistor provided over a substrate; and a display element electrically connected to the first thin film transistor, wherein the first thin film transistor includes: a first semiconductor layer including a first channel region, a first source region, and a first drain region; a first lower gate electrode provided between the substrate and the first semiconductor layer; a first upper gate electrode provided over the first semiconductor layer and overlapping with the first channel region; and a first electrode layer provided over the first upper gate electrode and electrically connected to at least one of the first source region and the first drain region, and the first lower gate electrode overlaps with the first channel region and the first drain region, the first upper gate electrode includes a first end adjacent to the first source region and a second end adjacent to the first drain region, the first lower gate electrode includes a first end adjacent to the first source region and a second end adjacent to the first drain region, in a plan view, the second end of the first upper gate electrode and a boundary between the first channel region and the first drain region coincide with each other, and the second end of the first upper gate electrode and the boundary between the first channel region and the first drain region are positioned within a region of the first lower gate electrode, a width of the first lower gate electrode in one direction is reduced, and in the plan view, the first lower gate electrode overlaps with the first semiconductor layer by avoiding or separating from the first source region, so that the first end of the first upper gate electrode, the first end of the first lower gate electrode, and a boundary between the first channel region and the first source region coincide with each other.

15. The display device of claim 14, wherein, the first lower gate electrode does not overlap with the first source region.

16. The display device of claim 14, wherein, the first semiconductor layer includes a silicon semiconductor material or an oxide semiconductor material.

17. The display device of claim 14, wherein, The display device further includes: a second thin film transistor provided over the substrate, the second thin film transistor including: a second semiconductor layer; a second gate electrode partially overlapping with the second semiconductor layer; and a second electrode layer electrically connected to at least one of the second source region and the second drain region. a second electrode layer provided over the second gate electrode and electrically connected to the second semiconductor layer, the first semiconductor layer includes an oxide semiconductor material, and the second semiconductor layer includes a silicon semiconductor material.

18. The display device of claim 17, wherein, The display device further includes: a third thin film transistor provided over the substrate, the third thin film transistor including: a third semiconductor layer including a third channel region, a third source region, and a third drain region; a third lower gate electrode provided between the substrate and the third semiconductor layer; a third upper gate electrode provided over the third semiconductor layer and overlapping with the third channel region; and a third electrode layer provided over the third upper gate electrode and electrically connected to at least one of the third source region and the third drain region, wherein the third lower gate electrode overlaps with the third channel region and the third drain region, and the third semiconductor layer includes an oxide semiconductor material.

19. The display device of claim 18, wherein, the third lower gate electrode overlaps with the third semiconductor layer and does not overlap with the third source region.

20. The display device according to claim 18, wherein the third upper gate electrode includes one end adjacent to the third source region, the third lower gate electrode includes one end adjacent to the third source region, and in the plan view, the one end of the third upper gate electrode and the one end of the third lower gate electrode coincide with each other.

21. The display device of claim 18, wherein, the first semiconductor layer and the third semiconductor layer are integral with each other and have a solitary shape.

22. The display device of claim 17, wherein, The display device further includes: a boost capacitor including a lower electrode and an upper electrode, wherein the lower electrode and the second gate electrode are provided over the same layer, and the upper electrode and the first semiconductor layer are provided over the same layer.

23. The display device of claim 17, wherein, The display device further includes: a storage capacitor including: the second gate electrode as a first electrode; and a second electrode provided over the second gate electrode, wherein the first lower gate electrode and the second electrode are provided over the same layer.

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