Tiled integrated circuit die

Abstract

This invention is entitled "Tiled integrated circuit dies." An image sensor that can be implemented using a tiled image sensor die is disclosed. The tiled image sensor die can be formed using a set of physical tiles from a reticle set through a step and repeat exposure process. The physical tiles can include a center tile that forms pixel circuitry on the image sensor die and a peripheral tile that forms non-pixel circuitry on the image sensor die. The size of each of the physical tiles can be set based on an integer multiple of a virtual unit tile. Thus, the physical tiles can have a size that is not an integer multiple of the smallest physical tile. The step and repeat exposure process can use a unit length of the virtual unit tile to correctly position the die relative to a processing tool.

Description

Background Technology

[0001] The present invention relates generally to imaging systems, and more specifically to systems and methods for optimizing the design of tiles and the partitioning of IP (intellectual property) circuit blocks in a gradation group of a stitched image sensor.

[0002] In some applications, image sensor integrated circuit dies on a wafer are formed by combining or stitching together multiple instances of selected blocks from the same set of markers (e.g., by stepping and repeatedly exposing the wafer at different locations using blocks from the same set of markers). The blocks in a set of markers are typically designed to include patterns that define one or more peripheral circuit blocks and one or more pixel blocks, where the pattern image on each block defines a corresponding (IP) circuit block for performing a specific function at a corresponding location on the image sensor die.

[0003] However, conventional systems and methods for designing blocks for gradation groups and thus dividing IP circuit blocks associated with corresponding blocks on an image sensor die can have limitations and may lead to inefficient image sensor die fabrication. For example, the size of the gradation groups and the size of each type of block relative to each other can be limited by constraints in the manufacturing process, thereby adversely limiting the specifications of the image sensor die formed by stitching these blocks together (e.g., limiting the possible pixel resolution of the formed image sensor die, especially for ultra-high resolution in large array image sensors).

[0004] The implementation plan in this paper emerged in this context. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of an exemplary electronic device having an image sensor and processing circuitry for capturing images, according to some implementation schemes.

[0006] Figure 2 This is a schematic diagram of an exemplary pixel array and associated control and readout circuitry according to some implementation schemes, the control and readout circuitry being used to control the pixel array and read out image signals from the pixel array.

[0007] Figure 3 It is a schematic diagram of four exemplary physical blocks according to some implementation schemes, which have corresponding sizes that are integer multiples of the smallest physical block.

[0008] Figure 4 It is a schematic diagram of an exemplary set of markings that can be used to form a spliced ​​integrated circuit die, according to some implementation schemes.

[0009] Figure 5A and Figure 5BIt is based on the use of some implementation schemes. Figure 4 The diagram shows two exemplary integrated circuit die layouts formed by the blocks in the calibrated group.

[0010] Figure 6 These are schematic diagrams of four exemplary physical blocks according to some implementation schemes. These exemplary physical blocks are designed based on virtual unit blocks and have corresponding sizes that are non-integer multiples of the smallest physical block.

[0011] Figure 7A and Figure 7B It is a schematic diagram of corresponding portions of two different exemplary image sensor dies formed from physical blocks from corresponding gradation groups according to some implementation schemes, each physical block being based on a virtual unit block.

[0012] Figure 8 It is based on the use of line groups with physical tiles based on virtual unit tiles in some implementation schemes (such as...) Figure 6 A schematic diagram of an exemplary integrated circuit die layout formed by the marking group. Detailed Implementation

[0013] Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices may include image sensors that collect incident light to capture images. Image sensors may include an array of image pixels. Pixels in an image sensor may include photosensitive elements, such as photodiodes that convert incident light into image signals. Image sensors may have any number (e.g., hundreds or thousands or more) of pixels. Typical image sensors may, for example, have hundreds of thousands or millions of pixels (e.g., megapixels). Image sensors may include control circuitry (e.g., circuitry for operating the image pixels) and readout circuitry for reading out image signals that correspond to the charges generated by the photosensitive elements.

[0014] Figure 1 This is a schematic diagram of an exemplary imaging system (such as an electronic device) that uses an image sensor to capture images. Figure 1The electronic device 10 may be a portable electronic device, such as a camera, cellular phone, tablet computer, webcam, camcorder, video surveillance system, vehicle imaging system, video game system with imaging capabilities, augmented reality and / or virtual reality system, unmanned aerial vehicle system (e.g., drone), industrial system, or any other desired imaging system or device for capturing digital image data. The camera module 12 (sometimes referred to as an imaging module) may be used to convert incident light into digital image data. The camera module 12 may include one or more lenses 14 and one or more corresponding image sensors 16. During image capture operation, light from the scene can be focused onto the image sensor 16 via the lens 14. The image sensor 16 may include circuitry for converting analog pixel image signals into corresponding digital image data provided to the storage and processing circuitry 18.

[0015] The storage and processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuitry, a microprocessor, a storage device such as random access memory and non-volatile memory, etc.) and may be implemented using components separate from and / or part of the camera module (e.g., circuitry forming part of an integrated circuit within a module including the image sensor 16 or associated with the image sensor 16). When the storage and processing circuitry 18 is included on an integrated circuit different from the integrated circuit of the image sensor 16, the integrated circuit having the circuitry 18 may be stacked or packaged vertically relative to the integrated circuit having the image sensor 16. The processing circuitry 18 may be used to process and store image data captured by the camera module (e.g., using an image processing engine on the processing circuitry 18, using an imaging mode selection engine on the processing circuitry 18, etc.). The processed image data may be provided to external devices (e.g., a computer, an external display, or other devices) as needed using wired and / or wireless communication paths coupled to the processing circuitry 18.

[0016] like Figure 2As shown, the image sensor 16 may include a pixel array 20 containing image sensor pixels 22 (sometimes referred to herein as image pixels or pixels) arranged in rows and columns, and control and processing circuitry 24. The array 20 may contain, for example, hundreds or thousands of rows and hundreds or thousands of columns of image sensor pixels 22. The control circuitry 24 may be coupled to row control circuitry 26 (sometimes referred to as row driver circuitry or row driver) and column readout circuitry 28 (sometimes referred to as column control circuitry, image readout circuitry, readout circuitry, processing circuitry, or column decoder circuitry). The row control circuitry 26 may receive row addresses from the control circuitry 24 and provide corresponding row control signals (such as reset control signals, anti-halo control signals, row selection control signals, charge transfer control signals, double conversion gain control signals, and readout control signals) to the pixels 22 via row control path 30. One or more wires (such as column lines 32) may be coupled to each column of pixels 22 in the array 20. The column lines 32 may be used to read out image signals from pixels 22 and to provide bias signals (e.g., bias current or bias voltage) to pixels 22. If necessary, during pixel readout operations, row control circuitry 26 can be used to select a pixel row in array 20, and the image signal generated by the image pixels 22 in that pixel row can be read along column line 32.

[0017] Column readout circuit 28 can receive image signals (e.g., analog pixel values ​​generated by pixel 22) via column lines 32. Column readout circuit 28 may include memory circuitry, amplifier circuitry or multiplier circuitry, analog-to-digital converter (ADC) circuitry, bias circuitry, latching circuitry for selectively enabling or disabling column circuitry, or other circuitry coupled to one or more pixel columns in array 20 for operating pixel 22 and for reading image signals from pixel 22. The ADC circuitry in readout circuit 28 can convert the analog pixel values ​​received from array 20 into corresponding digital pixel values ​​(sometimes referred to as digital image data or digital pixel data). Column readout circuit 28 can provide digital pixel data for pixels in one or more pixel columns to control and processing circuitry 24 and / or processor 18. Figure 1 ).

[0018] Image array 20 may also be provided with a filter array having multiple (color) filtering elements (each filtering element corresponding to a corresponding pixel), which allows a single image sensor to sample light of different colors or different wavelength groups. For example, image sensor pixels such as image pixels in array 20 may be provided with a color filter array having red, green, and blue filtering elements, which allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels arranged in a Bayer mosaic pattern.

[0019] In other suitable examples, the green pixels in the Bayer pattern may be replaced with broadband image pixels having broadband color filter elements (e.g., transparent color filter elements, yellow color filter elements, etc.), or one of the green pixels in the Bayer pattern may be replaced with an infrared (IR) image pixel formed below an IR color filter element, and / or the remaining red, green, and blue image pixels may also be sensitive to IR light (e.g., formed below a filter element that allows IR light to pass through in addition to light of its corresponding color). These examples are merely illustrative; in general, filter elements of any desired color and / or wavelength and any desired pattern may be formed above any desired number of image pixels 22.

[0020] Image sensor 16 may include an array 20 of one or more image pixels 22. The image pixels 22 may be formed in a semiconductor substrate using complementary metal-oxide-semiconductor (CMOS) technology, charge-coupled device (CCD) technology, or any other suitable photosensitive device technology. The image pixels 22 may be front-illuminated (FSI) image pixels or back-illuminated (BSI) image pixels. If desired, image sensor 16 may include an integrated circuit package or other structure in which multiple integrated circuit substrate layers or chips are stacked vertically relative to each other.

[0021] In some applications, Figure 1 and Figure 2 The image sensor 16 in the image sensor can be implemented using a mosaic image sensor die. Specifically, (e.g., using one-dimensional or two-dimensional mosaic) a mosaic image sensor die can be constructed using a small number of tiles, such as four tiles, contained in a single set of datums through a stepping and repeated exposure process (e.g., each tile in the same set can be exposed at multiple locations throughout the image sensor die).

[0022] Figure 3 These are schematic diagrams of four exemplary blocks in a traditional marking set, where the block sizes may not be optimally designed or formed. Figure 3 In the example, tiles 44, 46, 48, and 50 each have the same length in a first dimension, such as the x-axis (e.g., length X1 can be equal to length X2, the ratio of X2 to X1 is 1:1, or in other words, the integer ratio N is 1), and tiles 48 and 50 each have twice the length of tiles 44 and 46 in a second dimension, such as the y-axis (e.g., length Y2 can be twice the length Y1, the ratio of Y2 to Y1 is 2:1, or in other words, the integer ratio M is 2). Figure 3This example is merely illustrative. The dimensions of blocks 44, 46, 48, and 50 can be adjusted appropriately if needed (e.g., to make the ratio of X2 to X1 any suitable integer, and / or to make the ratio of Y2 to Y1 any suitable integer). In general, conventional marking sets may require (e.g., due to design and manufacturing requirements) that blocks have dimensions that are integer multiples of another block (e.g., length X2 is an integer multiple of length X1, and length Y2 is an integer multiple of length Y1).

[0023] However, allowing tiles to have these integer multiples of each other in size can impose limitations when forming graded sets, leading to suboptimal designs. As a concrete example, it might be desirable for the ratio of X2 to X1 to be greater than 1, since a ratio of X2 to X1 of 1 leaves some of the graded space unused, but a ratio of X2 to X1 of 2 exceeds graded size limitations (e.g., the sum of X2 and X1 could be greater than the total permissible length of the graded set along the x-axis). This results in a suboptimal design with a tile length where the ratio of X2 to X1 is 1. This, along with other problems associated with such conventional graded set designs and corresponding solutions, is described in more detail herein.

[0024] Specifically, Figure 4 This is a schematic diagram of an illustrative marker group 40 (e.g., a 2-D stitching mask group) containing four tiles 44, 46, 48, and 50. Figure 4 In the example, tile 48 (e.g., left peripheral tile and right peripheral tile) includes portions A and B, where portion B contains the circuit design of the left peripheral circuit (e.g., a circuit pattern or pattern image for exposure), and portion A contains the circuit design of the right peripheral circuit. Tile 46 (e.g., top peripheral tile and bottom peripheral tile) includes portions G and H, where portion G contains the circuit design of the bottom peripheral circuit, and portion H contains the circuit design of the top peripheral circuit. Tile 44 (e.g., corner peripheral tile) includes portions C, D, E, and F, where portion C contains the circuit design of the lower right corner peripheral circuit, portion D contains the circuit design of the lower left corner peripheral circuit, portion E contains the circuit design of the upper right corner peripheral circuit, and portion F contains the circuit design of the upper left corner peripheral circuit. Tile 50 (e.g., center tile) having portion I may contain circuitry for active pixel circuitry (e.g., Figure 2 Circuit design of pixel array 20 in the middle.

[0025] In some configurations, peripheral blocks 44, 46, and 48 may each include non-pixel circuitry (e.g., non-pixel IP), such as processing circuitry, storage circuitry, power management circuitry, system clock circuitry, and control circuitry for controlling pixel circuitry (e.g., ...). Figure 2 The control circuits 24, 26 and / or 28 in the middle), and the readout circuit for reading signals from the pixel circuit (e.g., Figure 2The readout circuit 28), pixel circuits (e.g., pixel IPs) such as reference pixels, forbidden zone (KOZ) pixels, and active pixels (e.g., implementations) Figure 2 (some portions of the pixels in array 20) and / or any other suitable circuitry. In these configurations, the center block may consist only of the active pixel circuitry that implements the active pixels (e.g., implementing...). Figure 2 (Most of the pixels in array 20). These examples are merely illustrative. Each tile may include any suitable circuitry if desired.

[0026] exist Figure 4 In the example, the marker group 40 may have marker (size) limits indicated by box 42, the marker group having a first length X along a first dimension (e.g., the x-axis) and a second length Y along a second vertical dimension (e.g., the y-axis). All tiles in the marker group 40 need to be within the marker size limits to meet processing requirements. In other words, the sum of the lengths X1 of tiles 44 and 48 and X2 of tiles 46 and 50 needs to be less than length X, and the sum of the lengths Y1 of tiles 44 and 46 and Y2 of tiles 48 and 50 needs to be less than length Y. Specifically, there may be spacing (e.g., separation) between different adjacent tiles along both the x-axis and y-axis, and there may be boundary spacing around the combined perimeter of the tiles (e.g., around the four tiles 44, 46, 48, and 50).

[0027] Furthermore, to construct a tiled image sensor die, some blocks such as peripheral circuit blocks 46 and 48 and the central pixel block 50 can be exposed multiple times (e.g., by stepping) at multiple locations on the die (e.g., by imprinting). To facilitate the stepping and imprinting processes, the sizes of blocks 44, 46, 48, and 50 can typically be constrained to integer multiples of the corresponding sizes of the other blocks, independently in both the x and y dimensions.

[0028] In other words, in this example, if tile 44 is 1 unit in the x-axis (e.g., length X1 is 1 unit), then the other tiles must be N units in the x-axis, where N is an integer (e.g., length X2 is 1 unit, 2 units, 3 units, or any other integer multiple of length X1). Similarly, in this example, if tile 44 is 1 unit in the y-axis (e.g., length Y1 is 1 unit), then the other tiles must be M units in the y-axis, where M is an integer that may be the same as or different from the integer N (e.g., length Y2 is 1 unit, 2 units, 3 units, or any other integer multiple of Y1). Figure 4In the example, tiles 44, 46, 48, and 50 each have the same size (e.g., for all four tiles in both dimensions, the ratio of tile length to tile length is 1:1), and the integer N (e.g., length X2: length X1) and the integer M (e.g., length Y2: length Y1) are both equal to 1.

[0029] Specifically, the integer multiples between the corresponding dimensions of tiles 44, 46, 48, and 50 allow machining tools (e.g., locators or stepping tools, alignment tools, exposure tools, etc.) to position each current instance of the first tile relative to a previous instance of the second tile (e.g., the same or different from the first tile) during the stepping process. In other words, based on the tile dimensions of the current and previous instances and the integer multiples between the current and previous tile instances (e.g., using integers N and / or M), the machining tool can easily calculate the current exposure position (e.g., using dead reckoning).

[0030] In some configurations, the outer patches 44, 46, and 48 may be smaller than the center patch 50. Length X1 may correspond to the left / right perimeter length in the x-axis, and length Y1 may correspond to the top / bottom perimeter length in the y-axis. Therefore, it may be desirable for the integers N and / or M (e.g., the size of the pixel patch: the size of each outer patch within the outer patches) to be large integers in these configurations, as this will maximize the pixel patch size and minimize the number of pixel patch exposures (e.g., the number of exposure steps) required on the image sensor die to satisfy a given pixel resolution.

[0031] As mentioned above, a mosaic image sensor die can be constructed by multiple exposures of individual blocks. Figure 5A and Figure 5B These are two illustrative diagrams showing the composition of... Figure 4 The marking groups shown represent two different die layouts. For example, Figure 5A The image sensor 16A may have the following die layout: three instances of the central pixel patch 50 (e.g., in a 3×1 pattern) form the majority of the pixel array 20A, and a corresponding number of peripheral patch instances (e.g., one instance of the corner patch 44, one instance of the left and right patches 48, and three instances of the top and bottom patches 46) form the non-pixel circuitry in the image sensor 16A (and optionally a portion of the pixel circuitry, such as the pixel array 20A or a portion of passive pixels). Each of the circuit blocks or patch portions A through I may be separated from each other at the stitching boundary.

[0032] For example, Figure 5BImage sensor 16B may have the following die layout: eight instances of the central pixel patch 50 (e.g., in a 4×2 pattern) form the majority of pixel array 20B, and a corresponding number of peripheral patch instances (e.g., one instance of corner patch 44, two instances of left and right patches 48, and four instances of top and bottom patches 46) form non-pixel circuitry in image sensor 16B (and optionally a portion of pixel circuitry, such as pixel array 20A or a portion of passive pixels). These examples are merely illustrative. Further details can be based on... Figure 4 The marking group 40 forms any suitable die layout.

[0033] For some applications where a satisfactory die can be formed using peripheral blocks (e.g., block 44) that are relatively smaller than the central block (e.g., block 50), setting the sizes of the different blocks to an integer ratio of the smallest peripheral block (e.g., block 40) may be sufficient to meet design requirements, because the smaller size of the peripheral blocks provides sufficient granularity (e.g., options) to form a central block (e.g., a central pixel block) of appropriate size. In other words, in these applications, optimizing the size of pixel block 50 by adjusting integers N and M relative to peripheral block 44 may be satisfactory, as integers N and M can take multiple values ​​and still meet the gamut size requirements. Specifically, giving flexibility to integers N and M allows for finding the best match for pixel resolution requirements through granularity.

[0034] However, in some applications, such as when a monolithic image sensor die with substantial functions and circuitry (e.g., power management unit (PMU), row driver circuitry, column readout circuitry and paths, sequencer circuitry, etc.) is formed within a peripheral tile, implementing these substantial functions and circuitry may require a large physical volume for the peripheral tile. This can disadvantageously limit the possible size of the center pixel tile to a very limited number, as the size of the center pixel is still required to be an integer multiple of the size of the larger peripheral tile while satisfying the datum group size limits.

[0035] In other words, including these functions and circuits in the outer tiles can thereby limit the ratio of the graph to the tiles (e.g., the aforementioned integers N and / or M) to very small integers, such as one or two. Because this constraint of small integer ratios N or M is applied to the allocation of the datum space between the center tile and the outer tiles, the center pixel tile can have a smaller size (relative to the center pixel tile in a datum group with smaller outer tiles). This results in limited optimization opportunities, making it very difficult to efficiently meet some pixel resolution requirements or pixel resolution specifications from a single datum group in a silicon-efficient manner.

[0036] In an exemplary example, it might be desirable to provide a center pixel patch with a longer first length X2 of 2 units relative to the first length X1 of 1 unit associated with the smallest outermost patch, to meet pixel resolution requirements and reduce the number of steps in stepping and repeating exposure processes. However, this may not be feasible because an integer ratio of 2 (e.g., length X2:length X1) may be too large to meet reticle size limits (e.g., the sum of lengths X2 and X1 exceeds the reticle size limit). While ratios between 1 and 2 (e.g., 1.5) can be optimized for reticle size limits, non-integer ratios are not permitted for performing conventional stepping and repeating exposure processes. Therefore, an integer ratio of 1 is inefficient and forced into use.

[0037] To alleviate these issues, the size of the (physical) tiles in the marking group can be designed based on the size of the virtual unit tile. To distinguish between these two types of tile references, the group of tiles in the marking group used for the actual patterning of the die is referred to herein as a physical tile (e.g., Figure 3 or Figure 4 (Plots 44, 46, 48, and 50). Virtual unit tiles are used only to set the size of physical tiles and perform positioning (e.g., alignment, dead reckoning, etc.) during stepping and repeated exposures against physical tiles. Specifically, using the size of virtual unit tiles to measure the size of physical tiles allows a larger percentage of the datum to be assigned to the center (pixel) tile, even when using larger peripheral tiles, because physical tiles do not actually need to have a size that is an integer multiple of the smallest physical tile (e.g., values ​​N and / or M do not need to be integers).

[0038] Figure 6 This is a schematic diagram of four exemplary physical blocks 44', 46', 48', and 50' in a single datum group. In some configurations described herein as examples, physical blocks 44', 46', 48', and 50' may have a similar combination Figure 4 The corresponding portions distributed in the manner described above include portions A', B', C', D', E', F', G', H', and I'. In other words, patch 44' can be a corner outer patch with corner portions C', D', E', and F'; patch 46' can be a top outer patch and a bottom outer patch with a top portion H' and a bottom portion G'; patch 48' can be a left outer patch and a right outer patch with a right portion B' and a left portion A'; and patch 50' can be a central patch with a central portion I'.

[0039] The size of each physical tile in these physical tiles can be set based on a virtual unit tile 60. Specifically, the virtual tile 60 may have a first length X3 along a first x-axis (sometimes referred to herein as a first unit length X3) and a second length Y3 along a second y-axis (sometimes referred to herein as a second unit length Y3). Physical tile 44' may have a first length X1 along the x-axis that is twice the first unit length X3, and may have a second length Y1 along the y-axis that is twice the second unit length Y3. Physical tile 46' may have a first length X2 along the x-axis that is three times the first unit length X3, and may have a second length Y1 along the y-axis that is twice the second unit length Y3. Physical tile 48' may have a first length X1 along the x-axis and a second length Y2 along the y-axis (e.g., each measured based on the corresponding unit length of the virtual tile). Physical tile 50' may have a first length X2 along the x-axis and a second length Y2 along the y-axis (e.g., each measured based on the corresponding unit length of the virtual tile).

[0040] As described above, each physical tile is designed to have a size that is an integer multiple of the corresponding size of the virtual unit tile. In other words, these physical tiles can be "formed" from smaller virtual unit tiles that are integer multiples of each other (e.g., the size is set based on an integer multiple of the smaller virtual unit tiles) (e.g., the size of the virtual unit tile can have an integer ratio to the size of each physical tile). This requirement can be replaced by combining... Figure 3 The more restrictive requirement is as shown in Figure 5, wherein each physical tile is designed to have a size that is an integer multiple of the corresponding size of another physical tile (e.g., the smallest physical tile).

[0041] Therefore, the relationship between the corresponding dimensions of physical blocks that are sized using virtual unit block sizes is described as an integer-to-integer ratio or integer ratio (e.g., the ratio of K to L, where K and L are both integers), or more specifically, a non-integer ratio of N to 1, where the value N is not an integer), rather than an integer ratio (e.g., the ratio of N to 1, where the value N is an integer), as combined with Figure 3 As shown in Figure 5.

[0042] exist Figure 6 In the example, along the x-axis, length X2 can be three units (e.g., three times the length X3), and length X1 can be two units. The ratio of X2 to X1 can be 3:2 or 1.5:1 (or simply 1.5). Along the y-axis, length Y2 can be five units (e.g., five times the length Y3), and length Y1 can be two units. The ratio of Y2 to Y1 can be 5:2 or 2.5:1 (or simply 2.5). Therefore, combining... Figure 3 The corresponding values ​​N and M described in Figure 5 are in Figure 6In the examples, the value can be a non-integer value or a ratio (for example, using virtual unit tiles to set the size of physical tiles).

[0043] By implementing physical blocks that have integer ratios to virtual unit blocks, physical blocks can be correlated with each other by integer ratios (e.g., non-integer multiples). This provides more flexible block sizes for efficient block partitioning, thereby enabling more efficient formation of integrated circuit dies with desired properties. This alleviates the problems caused by forming physical blocks that are integer ratios relative to each other (e.g., requiring the size of any physical block to be an integer multiple of the smallest physical block size).

[0044] As described above, virtual tiles can be defined for die exposure or patterning processes (e.g., stepping and alignment processes) without affecting the circuit design of physical tiles in the marker group. Specifically, the size of a virtual unit tile can be used for stepping and / or aligning a corresponding physical tile to expose at a corresponding location on the die (e.g., on a wafer containing the die and additional dies). In other words, the size of the virtual tile can be used to determine the location of the physical tile exposure. As an illustrative example, the wafer can be stepped in units that are integer multiples of the virtual tile unit size (e.g., integer multiples of unit lengths X3 and / or Y3) to provide corresponding alignment. This contrasts with a scenario where no virtual tiles and corresponding virtual tile unit sizes are used, where the wafer is stepped in units that are integer multiples of the entire size of the physical tile (e.g., integer multiples of lengths X1 and / or Y1 in Figure 5). Specifically, the integer multiple of the virtual tile unit length to be stepped can be indicated by the number of virtual tiles forming the corresponding physical tile to be imprinted.

[0045] For example, for a physical tile whose length in the first dimension is twice the unit length of the virtual tile in the first dimension (e.g., for a 2:1 ratio of physical tile to virtual tile length), the wafer can step by two units. Similarly, for a physical tile whose length in the first dimension is three times the unit length of the virtual tile in the first dimension (e.g., for a 3:1 ratio of physical tile to virtual tile length), the wafer can step by three units.

[0046] Figure 7A and Figure 7B These are two illustrative examples of a portion of the die layout for die 80. Figure 7A In the example, it can be based on physical tiles such as Figure 6The corner patch 44' is exposed using an exposure tool 70 at a first location on the die 80, exposing the circuit design on the patch portion 82F (corresponding to the upper left patch portion). In this example, the patch portion 82F may have the same dimensions as the virtual patch (e.g., it may have a first length X3 and a second length Y3). Subsequently, a positioner 76 (e.g., via a stepper coupled to the wafer to process multiple dies 80) can be used to move the die 80 in a direction 74 relative to the exposure tool 70. In this way, the exposure tool 70 can be positioned at a new location 72 to base the circuit design on the physical patch, such as... Figure 6 The outer patch 46' is then exposed using the exposure tool 70 at a second position on the die 80 to perform the next circuit design exposure on the patch portion 82H (corresponding to the top patch portion). Specifically, the locator 76 can perform alignment between the exposure tool 70 and the wafer based on moving the wafer and die 80 in increments of virtual patch unit length x3 (e.g., moving a total distance that is an integer multiple of the virtual patch unit length x3).

[0047] exist Figure 7A In the example, locator 76 can move the wafer relative to exposure tool 70 by a distance equal to one unit length x 3, from a first position to a second position. Subsequently, locator 76 can move the wafer relative to exposure tool 70 by a distance equal to three unit length x 3, from the second position to a third position. However, this is merely illustrative. If needed, locator 76 can move the wafer relative to exposure tool 72 by any suitable distance, depending on the physical tile size and the virtual tile size. Figure 7B Another illustrative example of how the locator 76 can move a wafer based on different die layouts is shown.

[0048] exist Figure 7B In the example, tile portion 82F may have a length along the first dimension (e.g., the x-axis) that is twice the length of the virtual tile unit x3, and tile portion 82H may have a length along the first dimension that is five times the length of the virtual tile unit x3. (To be combined with...) Figure 7A In the same manner, after the circuit design on the tile portion 82F is exposed at the first position, the locator 76 can move the wafer to perform alignment between the exposure tool 70 and the wafer at a second position, and expose the circuit design on the tile portion 82H at the second position. In this example, based on the size design of the relative virtual unit tile, the locator 76 can move the wafer a distance of twice the unit length x 3 from the first position to the second position. Subsequently, the locator 76 can move the wafer a distance of five times the unit length x 3 from the second position to the third position.

[0049] Figure 7A and Figure 7BThe examples in the text are merely illustrative. And... Figure 7A and Figure 7B In the example, alignment or stitching occurs in one dimension, and locator 76 can move (e.g., align) the wafer in the second dimension (e.g., in the y-dimension) based on virtual tile units. If needed, the exposure tool 70 can be moved instead of the wafer for alignment. Any other alignment operations can be performed during wafer fabrication based on the virtual unit tile size if required.

[0050] Figure 8 This is a schematic diagram of an exemplary die layout for an image sensor 16', which consists of a die based on... Figure 6 The virtual tiles of the type shown are formed by a group of physical tiles. Specifically, the image sensor 16' may be composed of most of the pixels forming the pixel array portion 20'. Figure 6 The image sensor 16' can also be formed from three instances of the center pixel patch 50'. The image sensor 16' can also be formed from three instances of the top peripheral patch and the bottom peripheral patch 46', two instances of the left peripheral patch and the right peripheral patch 48', and one instance of the corner peripheral patch 50'.

[0051] Specifically, by using virtual tiles to form the physical tiles in the marker group, the pixel area of ​​the pixel array 20' can be optimized. Specifically, the left outer tile portions F', B', and D' can have a length X1-1 in the x-dimensional direction, the right outer tile portions E', A', and C' can have a length X1-2 in the x-dimensional direction, and the top outer tile portion H', the bottom outer tile portion G', and the center tile portion I can have a length X2 in the x-dimensional direction. The sum of lengths X1-1 and X1-2 can be length X1( Figure 6 The ratio of X2 to X1 can be an integer-to-integer ratio (e.g., a non-integer ratio, such as the ratio of N to 1, where N is not an integer). Similarly, the top outer tile portions F', H', and E can have a length Y1-1 in the y-dimensional, the bottom outer tile portions D', G', and C' can have a length Y1-2 in the y-dimensional, and the left outer tile portion B', the right outer tile portion A', and the center tile portion I can have a length Y2 in the y-dimensional. The sum of lengths Y1-1 and Y1-2 can be a length Y1( Figure 6 The ratio of Y2 to Y1 can be an integer-to-integer ratio (e.g., a non-integer ratio of M to 1, where M is not an integer). Each of the circuit blocks or block portions A' to I' can be separated from each other at the splicing boundary.

[0052] The embodiments described herein can be implemented in a system (e.g., an imaging system, an image sensor, etc.), on processing circuitry (e.g., by executing instructions stored on a non-transitory computer-readable storage medium), on manufacturing equipment (e.g., control circuitry for a positioner, exposure tool, and / or any other processing equipment), or in any suitable manner. For example, systems and methods for forming physical tiles based on virtual tiles can form a tiled integrated circuit die, wherein (e.g., defined by tile boundaries) physical tiles are correlated with each other in integer ratios (e.g., in non-integer ratios) in the x-dimension and / or y-dimension.

[0053] The embodiments described herein can use integer relationships between constituent tiles in a gamut group for stitching to advantageously preserve desired characteristics of the manufacturing process (e.g., alignment or positioning processes) while providing finer granularity in the final physical size of each tile, thereby enabling greater flexibility in assigning functionality to different physical tiles. This can be particularly advantageous for monolithic image sensors where peripheral tiles may occupy a significant proportion of the gamut group's limited length (e.g., in the x and y dimensions). However, the examples of monolithic image sensors implementing the embodiments described herein are merely illustrative. Other types of image sensors or integrated circuit dies may also implement the embodiments described herein (e.g., be formed using the embodiments described herein) if desired.

[0054] For example, the arrangement of these monolithic image sensors or other suitable systems can limit the physical tiles to an integer multiple of the minimum physical tile size, such as having a physical tile length ratio of 1:1 or 2:1. However, the embodiments described herein enable a wider range of ratios, thus allowing greater flexibility in designing and allocating circuitry for the physical tiles. For example, in some scenarios (e.g., in...) Figure 6 In the example, if the virtual tile is 0.25 times the size of the smallest physical tile, physical tile length ratios of 4:4, 5:4, 6:4, 7:4, and 8:4 can be implemented, thus providing twice the number of options. Since there is no limit to the virtual tile size, physical tile length ratios of 5:5, 6:5, 7:5, 8:5, 9:5, and 10:5 can also be implemented for even smaller virtual tile sizes, further increasing the number of options.

[0055] As a concrete example, consider a monolithic image sensor where the peripheral IP and reference / buffer pixels result in left and right peripheral physical patch lengths of 8 mm in the x-axis and top and bottom peripheral physical patch lengths of 12 mm in the y-axis. The gamut size constraints are typically 25 mm × 32 mm, and the spacing between physical patches is 1.5 mm. This example can be assumed that the top and bottom peripheral physical patch lengths in the y-axis are aligned along the longer axis of the gamut size constraints.

[0056] In this example, if an integer ratio between physical tiles is used, the height of the outer physical tile is 12mm. As a first example, if the length ratio between a physical pixel tile and its outer physical tile is 1:1 in the y-axis, the total length in the y-axis can be determined by 12 + 12 + 1.5 (spacing) = 25.5mm. As a second example, if the length ratio between a physical pixel tile and its outer physical tile is 2:1 in the y-axis, the total length in the y-axis can be determined by 2 * 12 + 12 + 1.5 (spacing) = 37.5mm. Clearly, the length ratio M (as combined with...) Figure 4 The value mentioned above may only be the value in the following case: assuming that the total length in the y-dimensional dimension of the second example exceeds the size of the 32mm scale group (e.g., the maximum sum of the lengths of the outer physical tile and the pixel physical tile in the y-dimensional dimension must be (32-1.5) / 2 = 15.5mm).

[0057] If an integer ratio between physical tiles is used (e.g., using virtual tiles with an integer ratio relative to physical tiles), the segmentation in the y-axis between the length of the outer physical tile and the length of the pixel physical tile can be better optimized. Specifically, assuming a virtual tile length of 3mm in the y-axis and an outer physical tile length of 12mm in the y-axis, a 6:4 ratio of pixel physical tile length to outer physical tile length can be used. This results in a total length of 6*3 + 4*3 + 1.5 = 31.5mm in the y-axis, maximizing the utilization of the map group size. This method provides an outer tile length of 12mm in the y-axis and a pixel physical tile length of 18mm in the y-axis, thereby increasing the pixel physical tile size by 16% (compared to the example with the aforementioned integer ratio between physical tiles).

[0058] The systems and methods described herein enable greater flexibility in meeting requested resolutions, especially considering larger peripheral circuitry and other constraints. They also allow for greater flexibility in allocating circuitry to corresponding physical tiles, providing greater flexibility in defining granularity (e.g., resulting in a single daemon mask set serving a larger number of pixel resolutions). As a concrete example, even given certain system constraints, the systems and methods described herein can increase the number of achievable pixel rows / columns (for a given pixel resolution). In summary, the systems and methods described herein achieve flexibility in pixel resolution and implementation from a single daemon mask set.

[0059] Various implementation schemes have been described, thereby illustrating systems and methods for optimizing the design of datum groups and the partitioning of IP circuit blocks in a stitched image sensor.

[0060] For example, an image sensor can be implemented using a tiled image sensor die that is fabricated as a portion of a larger wafer containing other dies. This tiled image sensor die can be formed using a set of physical blocks from a set of markings through a stepping and repeated exposure process. Specifically, the wafer can be coupled to a locator (e.g., a stepper) that moves the wafer from one location to another relative to a processing tool (e.g., an exposure tool). At each location, the corresponding physical block can be exposed or imprinted. In this way, an image sensor die can be constructed or tiled from one or more instances of the same set of physical blocks.

[0061] In some configurations, physical blocks may include a central block forming pixel circuitry on the image sensor die and peripheral blocks (and optional pixel circuitry) forming non-pixel circuitry on the image sensor die. The size of each physical block within the physical block may be set based on an integer multiple of a virtual unit block. Specifically, a virtual unit block may have or define a first unit length along a first x-axis and a second unit length along a second y-axis. Each physical block may have a first length that is an integer multiple of the first unit length in the x-axis and a second length that is an integer multiple of the second unit length in the y-axis. By using virtual unit blocks as measurement base units for alignment and positioning during processing, physical blocks may not need to have a size that is an integer multiple of the smallest physical block (e.g., the smallest physical block does not need to be used as a measurement base unit for alignment and positioning during processing). In this way, stepping and repeated exposure processes can use the unit length of the virtual unit blocks to correctly position the die relative to the processing tool (e.g., positioning based on integer multiples of the unit length in the x-axis and / or y-axis dimensions).

[0062] According to one embodiment, a set of markers for patterning an image sensor die may include a central patch having a first patterned image associated with pixel circuitry. The central patch may have a first length along a first dimension. The set of markers may include peripheral patches having a second patterned image associated with control circuitry of the pixel circuitry. The peripheral patches may have a second length along the first dimension. The ratio of the first length of the central patch to the second length of the peripheral patches may be a non-integer ratio.

[0063] According to another implementation, the central tile may have a third length along the second dimension. The outer tiles may have a fourth length along the second dimension. The ratio of the third length of the central tile to the fourth length of the outer tiles may be a non-integer ratio.

[0064] According to another implementation, the dimensions of the central tile and the outer tiles can be set based on the same virtual unit tile that defines a unit length along the first dimension.

[0065] According to another implementation, the first length of the central tile can be an integer multiple of the unit length of the virtual unit tile.

[0066] According to another implementation, the second length of the outer block can be an integer multiple of the unit length of the virtual unit block.

[0067] According to another implementation, the central tile may have a third length along the second dimension. The outer tiles may have a fourth length along the second dimension. Virtual unit tiles may define an additional unit length along the second dimension.

[0068] According to another implementation, the third length of the central tile can be an integer multiple of the additional unit length of the virtual unit tile.

[0069] According to another implementation, the fourth length of the outer tile can be an integer multiple of the additional unit length of the virtual unit tile.

[0070] According to another implementation scheme, the ratio of the third length of the central tile to the fourth length of the outer tiles can be a non-integer ratio.

[0071] According to another implementation, the unit length of the virtual unit tile can indicate the measurement unit used for alignment when patterning and stitching image sensor dies.

[0072] According to another implementation, in the patterned mosaic image sensor die, the mosaic image sensor die can be stepped in integer multiples of the unit length of the virtual unit patch.

[0073] According to one embodiment, a method for processing a wafer having an image sensor die may include: forming a first peripheral circuit block and a second peripheral circuit block using peripheral circuit blocks in a set of markers; and forming a pixel circuit block between the first and second peripheral circuit blocks using a central pixel circuit block in the set of markers. The first and second peripheral circuit blocks may have corresponding lengths whose sum along a certain dimension is a first length. The pixel circuit block may have a second length along that dimension. The ratio of the second length to the first length may be a non-integer ratio.

[0074] According to another embodiment, forming the first peripheral circuit block and the second peripheral circuit block, as well as forming the pixel circuit block, may include using caliper groups to perform stepping and repeated exposure processes.

[0075] According to another embodiment, the first length associated with the first peripheral circuit block and the second peripheral circuit block, and the second length associated with the pixel circuit block, may be an integer multiple of the unit length associated with the virtual tile.

[0076] According to another implementation, using a set of markers to perform the stepping and repeated exposure process may include stepping the wafer based on a unit length associated with a virtual tile.

[0077] According to another implementation, stepping the wafer based on the unit length associated with the virtual tile may include stepping the wafer by a distance that is an integer multiple of the unit length associated with the virtual tile for each step in the stepping and re-exposure process.

[0078] According to another embodiment, the method may further include forming an additional pixel circuit block between a first peripheral circuit block and a second peripheral circuit block using a center pixel circuit block in a caliper group. The additional pixel circuit block may have a second length along that dimension. Forming the pixel circuit block and the additional pixel circuit block may include using the center pixel circuit block to perform a stepping and repeated exposure process.

[0079] According to another embodiment, the pixel circuit block and the additional pixel circuit block can form an image sensor pixel array of the image sensor die. The first peripheral circuit block and the second peripheral circuit block can form the control circuit of the image sensor pixel array.

[0080] According to one embodiment, a modular integrated circuit die may include multiple circuit blocks separated from each other by corresponding splicing boundaries. The multiple circuit blocks may include: a first peripheral circuit block; a second peripheral circuit block; and a central circuit block located between the first and second peripheral circuit blocks. The first and second peripheral circuit blocks may have corresponding lengths whose sum along a certain dimension equals a first length. The central circuit block may have a second length along that dimension. The ratio of the second length to the first length may be a non-integer ratio.

[0081] According to another embodiment, the central circuit block may include pixel circuitry forming an image sensor pixel array, and the first and second peripheral circuit blocks may include control circuitry for the image sensor pixel array.

[0082] If desired, embodiments of the invention described herein can be applied to forming general-purpose integrated circuit systems, such as designing and forming blocks in a set of markings and partitioning circuits, such as IP circuit blocks on an integrated circuit die in a non-imaging system. Generally, the systems and methods used to form the integrated circuit dies described herein can be implemented in any suitable imaging or non-imaging system. Those skilled in the art will understand that exemplary embodiments of the invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0083] The foregoing description is merely an illustrative representation of the principles of the present invention, and those skilled in the art can make various modifications without departing from the scope and essence of the invention. The above embodiments can be implemented individually or in any combination.

Claims

1. A marking assembly for patterning an image sensor die, the marking assembly comprising: A central patch having a first pattern image associated with a pixel circuit, the central patch having a first length along a first dimension; and The outer edge tile has a second pattern image associated with the control circuitry of the pixel circuitry, the outer edge tile has a second length along the first dimension, wherein the ratio of the first length of the center tile to the second length of the outer edge tile is a non-integer ratio, and wherein the dimensions of the center tile and the outer edge tile are set based on the same virtual unit tile defining a unit length along the first dimension.

2. The marking set according to claim 1, wherein the central patch has a third length along the second dimension, the outer patches have a fourth length along the second dimension, and wherein the ratio of the third length of the central patch to the fourth length of the outer patches is a non-integer ratio.

3. The marking group according to claim 1, wherein the first length of the central block is an integer multiple of the unit length of the virtual unit block, and wherein the second length of the outer block is an integer multiple of the unit length of the virtual unit block.

4. The grading set according to claim 1, wherein the central tile has a third length along the second dimension, the outer tiles have a fourth length along the second dimension, and the virtual unit tile defines an additional unit length along the second dimension, wherein the third length of the central tile is an integer multiple of the additional unit length of the virtual unit tile, wherein the fourth length of the outer tiles is an integer multiple of the additional unit length of the virtual unit tile, and wherein the ratio of the third length of the central tile to the fourth length of the outer tiles is a non-integer ratio.

5. A method for processing a wafer having an image sensor die, the method comprising: A first peripheral circuit block and a second peripheral circuit block are formed by using peripheral circuit blocks in a gradation group, wherein the first peripheral circuit block and the second peripheral circuit block have corresponding lengths whose sum along a first dimension is a first length; as well as A pixel circuit block is formed between the first peripheral circuit block and the second peripheral circuit block by using a center pixel circuit block in the gradation group, wherein the pixel circuit block has a second length along the first dimension, wherein the ratio of the second length to the first length is a non-integer ratio, and wherein the first length associated with the first peripheral circuit block and the second peripheral circuit block and the second length associated with the pixel circuit block are integer multiples of the unit length associated with the virtual tile.

6. The method of claim 5, wherein forming the first peripheral circuit block and the second peripheral circuit block and forming the pixel circuit block includes using the reticle group to perform a stepping and repeated exposure process.

7. The method of claim 6, wherein using the set of markers to perform the stepping and re-exposure process comprises stepping the wafer based on the unit length associated with the virtual patch, and wherein stepping the wafer based on the unit length associated with the virtual patch comprises, for each step in the stepping and re-exposure process, stepping the wafer by a distance that is an integer multiple of the unit length associated with the virtual patch.

8. The method according to claim 5, further comprising: An additional pixel circuit block is formed between the first peripheral circuit block and the second peripheral circuit block using the center pixel circuit block in the datum group, wherein the additional pixel circuit block has a second length along the first dimension, wherein forming the pixel circuit block and the additional pixel circuit block includes using the center pixel circuit block to perform a stepping and repeated exposure process, wherein the pixel circuit block and the additional pixel circuit block form an image sensor pixel array for the image sensor die, and wherein the first peripheral circuit block and the second peripheral circuit block form control circuitry for the image sensor pixel array.

9. A modular integrated circuit die, the modular integrated circuit die comprising: Multiple circuit blocks, separated from each other by corresponding splicing boundaries, the multiple circuit blocks including: First peripheral circuit block; A second peripheral circuit block, wherein the first peripheral circuit block and the second peripheral circuit block are formed on opposite sides of the spliced ​​integrated circuit die, and wherein the first peripheral circuit block and the second peripheral circuit block have corresponding lengths whose sum along a first dimension is a first length; and A central circuit block located between a first peripheral circuit block and a second peripheral circuit block, wherein the central circuit block has a second length along the first dimension, wherein the ratio of the second length to the first length is a non-integer ratio, and wherein the dimensions of the central circuit block, the first peripheral circuit block, and the second peripheral circuit block are set based on the same virtual unit tile that defines a unit length along the first dimension.

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