Nano-sheet field effect transistor device and method for forming the same

Abstract

The present disclosure relates to a nanosheet field effect transistor device and a method of forming the same. A semiconductor device includes a fin protruding above a substrate; source / drain regions over the fin; a nanosheet between the source / drain regions, wherein the nanosheet includes a first semiconductor material; internal spacers between the nanosheets and at opposite ends of the nanosheets, wherein there is an air gap between each internal spacer and a corresponding one of the source / drain regions of the source / drain regions; and a gate structure over the fin and between the source / drain regions.

Description

Technical Field

[0001] The present disclosure generally relates to nanosheet field effect transistor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that should be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a fin protruding above a substrate; a source / drain region over the fin; a nanosheet between the source / drain regions, wherein the nanosheet comprises a first semiconductor material; an internal spacer between the nanosheets and at opposite ends of the nanosheets, wherein there is an air gap between each internal spacer and a corresponding source / drain region in the source / drain regions; and a gate structure over the fin and between the source / drain regions.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a fin protruding above a substrate; a gate structure over the fin; source / drain regions over the fin and on opposite sides of the gate structure; a first channel layer and a second channel layer disposed between the source / drain regions and parallel to each other, wherein the gate structure surrounds the first channel layer and the second channel layer; and an internal spacer disposed between an end of the first channel layer and an end of the second channel layer, wherein there is an air gap between the internal spacer and the source / drain regions.

[0006] According to another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, the method comprising: forming a dummy gate structure over a nanostructure and over a fin, the nanostructure covering the fin, the fin protruding above the substrate, the nanostructure comprising alternating layers of a first semiconductor material and a second semiconductor material; forming an opening in the nanostructure on opposite sides of the dummy gate structure, the opening exposing ends of the first semiconductor material and the second semiconductor material; recessing the exposed ends of the first semiconductor material to form grooves; forming dummy internal spacers in the grooves and forming a material layer over the dummy internal spacers in the grooves; after forming the material layer, forming source / drain regions in the openings; after forming the source / drain regions, removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material disposed under the dummy gate structure; removing the exposed first semiconductor material and the dummy internal spacers, wherein the second semiconductor material remains and forms a plurality of nanosheets, wherein the material layer is exposed after removing the dummy internal spacers; and forming internal spacers between the source / drain regions at opposite ends of the plurality of nanosheets, wherein each spacer in the internal spacers seals an air gap between each internal spacer and the material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a nanosheet field effect transistor (NSFET) device in accordance with some embodiments is shown in a three-dimensional view.

[0009] Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B and Figures 6 - 17 are cross-sectional views of a nanosheet field effect transistor device in accordance with embodiments at various stages of manufacture.

[0010] Figure 18 and 19 are cross-sectional views of a nanosheet field effect transistor device in accordance with another embodiment at a certain stage of manufacture.

[0011] Figure 20 is a flowchart of a method of forming a semiconductor device in accordance with some embodiments. Detailed Implementation Modes

[0012] Numerous different embodiments or examples are provided below for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "under", "below", "beneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, like or similar reference numerals in different figures refer to the same or similar components formed of the same or similar material(s) by the same or similar process(es).

[0014] According to some embodiments, during the formation of a nanosheet field-effect transistor (NSFET) device, dummy spacers are formed between the nanosheets, and a material layer (which can be a semiconductor material layer or a dielectric material layer) is formed over the dummy spacers. Subsequently, the dummy spacers are removed during the replacement gate process, and internal spacers are formed to replace the dummy internal spacers. The internal spacers seal the air gap between the internal spacers and the material layer. The air gap advantageously reduces the k value and decreases the parasitic capacitance of the formed device.

[0015] Figure 1An example of a nanosheet field-effect transistor (NSFET) device according to some embodiments is shown in a three-dimensional view. The NSFET device includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed over the fin, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanosheets 54 are formed over the fin 90 and between the source / drain regions 112. Isolation regions 96 are formed on opposite sides of the fin 90. A gate dielectric layer 120 is formed around the nanosheets 54. The gate electrode 122 is located over and around the gate dielectric layer 120.

[0016] Figure 1 Also shown are reference cross-sections used in the subsequent figures. Cross-section A-A is along the longitudinal axis of the gate electrode 122 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 112 of the NSFET device. Cross-section B-B is perpendicular to cross-section A-A, along the longitudinal axis of the fin, and in the direction of current flow between the source / drain regions 112 of the NSFET device, for example. For clarity, the subsequent figures refer to these reference cross-sections.

[0017] Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B and Figures 6 - 17 are cross-sectional views of a nanosheet field-effect transistor (NSFET) device 100 at various stages of fabrication according to an embodiment.

[0018] In Figure 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate that is typically a silicon substrate or a glass substrate. Other substrates (e.g., multi-layer or gradient substrates) can also be used. In some embodiments, the semiconductor material of the substrate 50 includes silicon; germanium; compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP); or combinations thereof.

[0019] A multi-layer stack 64 is formed on the substrate 50. The multi-layer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. InFigure 2 In it, the layers formed of the first semiconductor material 52 are labeled 52A, 52B, 52C, and 52D, and the layers formed of the second semiconductor material 54 are labeled 54A, 54B, 54C, and 54D. Figure 2 The number of layers formed of the first semiconductor material and the second semiconductor material shown is merely a non-limiting example. Other numbers of layers are possible and are fully intended to be included within the scope of the present disclosure.

[0020] In some embodiments, the first semiconductor material 52 is an epitaxial material (such as silicon germanium (Si x Ge 1-x , where x can range from 0 to 1) suitable for forming a channel region of, for example, a p-type FET, and the second semiconductor material 54 is an epitaxial material (such as silicon) suitable for forming a channel region of an n-type FET. The multi-layer stack 64 (which may also be referred to as an epitaxial material stack) can be patterned in a subsequent process to form the channel region of the NSFET. In particular, the multi-layer stack 64 will be patterned to form horizontal nanosheets, and the channel region of the resulting NSFET includes a plurality of horizontal nanosheets.

[0021] The multi-layer stack 64 can be formed by an epitaxial growth process that can be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber is periodically exposed to a first set of precursors for selectively growing the first semiconductor material 52, and then to a second set of precursors for selectively growing the second semiconductor material 54. The first set of precursors includes precursors for the first semiconductor material (such as silicon germanium), and the second set of precursors includes precursors for the second semiconductor material (such as silicon). In some embodiments, the first set of precursors includes a silicon precursor (such as silane) and a germanium precursor (such as germane), and the second set of precursors includes a silicon precursor but omits the germanium precursor. Thus, the epitaxial growth process can include continuously flowing a silicon precursor into the growth chamber, and then cycling: (1) flowing a germanium precursor into the growth chamber when growing the first semiconductor material 52; and (2) prohibiting the germanium precursor from flowing into the growth chamber when growing the second semiconductor material 54. The periodic exposure can be repeated until a target number of layers is formed.

[0022] Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B and Figures 6 - 17 are cross-sectional views of the NSFET device 100 according to an embodiment at a subsequent stage of manufacturing. Figure 3A 、 Figure 4A 、 Figure 5A and Figures 6 - 16 are cross-sectional views along section B-B in Figure 1 .Figure 3B , Figure 4B and Figure 5B are cross-sectional views along cross-section A-A in Figure 1 . Figure 17 is an enlarged view of a portion of the NSFET device 100 shown in Figure 16 . Although one fin and one gate structure are shown as non-limiting examples in the figure, it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0023] In Figure 3A and Figure 3B , the fin structure 91 is formed to protrude above the substrate 50. The fin structure 91 includes a semiconductor fin 90 and a nanostructure 92 covering the semiconductor fin 90. The nanostructure 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively.

[0024] The fin structure 91 can be patterned by any suitable method. For example, one or more lithography processes (including double-patterning or multi-patterning processes) can be used to pattern the fin structure 91. Generally, double-patterning or multi-patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns with, for example, pitches smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can then be used to pattern, for example, the fin structure 91.

[0025] In some embodiments, the remaining spacers are used to pattern a mask 94, and then the mask 94 is used to pattern the fin structure 91. The mask 94 can be a single-layer mask or can be a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be formed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to appropriate techniques. The first mask layer 94A and the second mask layer 94B are different materials with high etch selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. The mask 94 can be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. Then, the mask 94 can be used as an etch mask to etch the substrate 50 and the multilayer stack 64. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. In some embodiments, the etching is an anisotropic etching process. As Figure 3A and Figure 3BAs shown, after the etching process, the patterned multi-layer stack 64 forms nanostructures 92, and the patterned substrate 50 forms semiconductor fins 90. Thus, in the illustrated embodiment, the nanostructures 92 also include alternating layers of a first semiconductor material 52 and a second semiconductor material 54, and the semiconductor fins 90 are formed of the same material as the substrate 50 (e.g., silicon).

[0026] Next, in Figure 4A and Figure 4B shallow trench isolation (STI) regions 96 are formed over the substrate 50 and on opposite sides of the fin structures 91. As an example of forming the STI regions 96, an insulating material can be formed over the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc. or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), etc. or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by the FCVD process. An annealing process can be performed after forming the insulating material.

[0027] In an embodiment, the insulating material is formed such that excess insulating material covers the fin structures 91. In some embodiments, a liner is first formed along the surfaces of the substrate 50 and the fin structures 91, and a filling material such as those discussed above is formed over the liner. In some embodiments, the liner is omitted.

[0028] Next, a removal process is applied to the insulating material to remove the excess insulating material over the fin structure 91. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc. can be utilized. The planarization process exposes the nanostructure 92 such that after the planarization process is completed, the top surface of the nanostructure 92 and the insulating material are flush. Next, the insulating material is recessed to form the STI region 96. The insulating material is recessed such that the nanostructure 92 protrudes between adjacent STI regions 96. The top of the semiconductor fin 90 can also protrude between adjacent STI regions 96. Additionally, the top surface of the STI region 96 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI region 96 can be formed to be flat, convex, and / or concave by appropriate etching. An acceptable etching process can be used to recess the STI region 96, for example, an etching process selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the materials of the semiconductor fin 90 and the nanostructure 92). For example, chemical oxide removal using a suitable etchant (e.g., dilute hydrofluoric acid (dHF)) can be used.

[0029] Still referring to Figure 4A and Figure 4B , a dummy dielectric layer 97 is formed over the nanostructure 92 and over the STI region 96. The dummy dielectric layer 97 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. In an embodiment, a silicon layer is conformally formed over the nanostructure 92 and over the upper surface of the STI region 96, and a thermal oxidation process is performed to convert the deposited silicon layer into an oxide layer as the dummy dielectric layer 97.

[0030] Next, in Figure 5A and Figure 5B , a dummy gate 102 is formed over the fin 90 and over the nanostructure 92. To form the dummy gate 102, a dummy gate layer can be formed over the dummy dielectric layer 97. The dummy gate layer can be deposited over the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be a conductive material and can be selected from the group including amorphous silicon, polysilicon, poly-silicon germanium (poly-SiGe), etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials having a high etch selectivity with respect to the isolation region 96.

[0031] Then, a mask 104 is formed over the dummy gate layer. The mask 104 can be formed of silicon nitride, silicon oxynitride, a combination thereof, etc., and can be patterned using acceptable lithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). Then, the pattern of the mask 104 is transferred to the dummy gate layer by acceptable etching techniques to form the dummy gate 102, and then the pattern of the mask 104 is transferred to the dummy dielectric layer by acceptable etching techniques to form the dummy gate dielectric 97. The dummy gate 102 covers the respective channel regions of the nanostructure 92. The pattern of the mask 104 can be used to separate the dummy gate 102 from adjacent dummy gate entities. The dummy gate 102 can also have a length direction that is substantially perpendicular to the length direction of the fin 90. In some embodiments, the dummy gate 102 and the dummy gate dielectric 97 are collectively referred to as the dummy gate structure.

[0032] Next, a gate spacer layer 107 is formed by conformally depositing an insulating material over the nanostructure 92, the STI region 96, and the dummy gate 102. The insulating material can be silicon nitride, silicon carbonitride, a combination thereof, etc. In some embodiments, the gate spacer layer 107 includes a plurality of sub-layers. For example, a first sub-layer 108 (sometimes referred to as a gate seal spacer layer) can be formed by thermal oxidation or deposition, and a second sub-layer 109 (sometimes referred to as a main gate spacer layer) can be conformally deposited over the first sub-layer 108.

[0033] Figure 5B A cross-sectional view of the NSFET device 100 in Figure 5A is shown, but along the cross-section F-F in Figure 5A . Figure 5A The cross-section F-F in Figure 1 corresponds to the cross-section A-A in

[0034] Next, in Figure 6 , the gate spacer layer 107 is etched by an anisotropic etching process to form the gate spacer 107. The anisotropic etching process can remove the horizontal portions of the gate spacer layer 107 (e.g., the portions over the STI region 96 and the dummy gate 102), and the remaining vertical portions of the gate spacer layer 107 (e.g., along the sidewalls of the dummy gate 102 and the dummy gate dielectric 97) form the gate spacer layer 107.

[0035] After the gate spacers 107 are formed, implantation for lightly doped source / drain (LDD) regions (not shown) can be performed. Impurities of an appropriate type (e.g., p-type or n-type) can be implanted into the exposed nanostructures 92 and / or the semiconductor fins 90. The n-type impurities can be any suitable n-type impurities such as phosphorus, arsenic, antimony, etc., and the p-type impurities can be any suitable p-type impurities such as boron, BF2, indium, etc. The lightly doped source / drain regions can have an impurity concentration of about 10 15 cm -3 to about 10 16 cm -3 . An annealing process can be used to activate the implanted impurities.

[0036] Next, in Figure 7 , an opening 110 (which can also be referred to as a recess) is formed in the nanostructure 92. The opening 110 can extend through the nanostructure 92 and into the semiconductor fin 90. The opening 110 can be formed by any acceptable etching technique, using, for example, the dummy gate 102 as an etching mask. The opening 110 exposes the ends of the first semiconductor material 52 and the ends of the second semiconductor material 54.

[0037] Next, in Figure 8 , after the opening 110 is formed, a selective etching process (e.g., a wet etching process using an etching chemical) is performed to recess the ends of the first semiconductor material 52 exposed by the opening 110, while substantially not removing the second semiconductor material 54. After the selective etching process, a recess 52R is formed at the location where the removed ends of the first semiconductor material 52 were located.

[0038] Next, in Figure 9 , a dummy inner spacer layer 55 is formed (e.g., conformally) in the opening 110. The dummy inner spacer layer 55 lines the sidewalls and the bottom of the opening 110. The dummy inner spacer layer 55 also lines the surface of the recess 52R. In the illustrated embodiment, the thickness of the dummy inner spacer layer 55 in the recess 52R is greater than the thickness of the dummy inner spacer layer 55 disposed outside the recess 52R (e.g., along the sidewalls of the opening 110). The greater thickness of the dummy inner spacer layer 55 in the recess 52R may be due to a faster deposition / accumulation rate of the material in the small / narrow space (e.g., inside the recess 52R).

[0039] In some embodiments, the dummy internal spacer layer 55 is formed of a suitable dielectric material such as silicon oxide and can be formed by a suitable deposition method such as ALD, PVD, CVD, etc. The material of the dummy internal spacer layer 55 can be selected to have the same or similar etching rate as the first semiconductor material 52, such that in a subsequent etching process for removing the first semiconductor material 52, the dummy internal spacer layer 55 (formed by etching the internal spacer layer 55) and the first semiconductor material 52 can be removed by the same etching process.

[0040] Next, in Figure 10 , an etching process is performed to remove the portion of the dummy internal spacer layer 55 located outside the groove 52R. The remaining portion of the dummy internal spacer layer 55 (e.g., the portion disposed inside the groove 52R) forms the dummy internal spacer layer 55. In an embodiment, the etching process is a wet etching process using a suitable etchant such as dilute hydrofluoric acid (dHF). The wet etching process can be a timed process such that the portion of the dummy internal spacer layer 55 disposed outside the groove 52R is removed while the (thicker) portion of the dummy internal spacer layer 55 inside the groove 52R is retained to form the dummy internal spacer 55.

[0041] Next, in Figure 11 , a material layer 56 is formed over the dummy internal spacer 55 in the groove 52R. In an Figure 11 example, the material layer 56 is a semiconductor material (e.g., silicon) formed by a suitable formation method such as an epitaxial process. In the illustrated embodiment, the material layer 56 and the second semiconductor material 54 are formed of the same material (e.g., silicon), but the material layer 56 can also be formed of a material different from the second semiconductor material 54.

[0042] In an embodiment, to form the material layer 56, an epitaxial silicon layer is conformally formed in the opening 110 and the groove 52R. Then an etching process (e.g., an anisotropic etching process) is performed to remove the portion of the epitaxial silicon layer disposed outside the groove 52R and retain the (thicker) portion of the epitaxial silicon layer inside the groove 52R, thereby forming the material layer 56. As Figure 11 shown, the material layer 56 includes a plurality of segments, where each segment is disposed over (e.g., in contact with) a corresponding dummy internal spacer 55. Using a semiconductor material (e.g., silicon) as the material layer 56 facilitates the formation of the source / drain regions 112 in a subsequent process. In an Figure 11 example, the material layer 56 and the dummy internal spacer 55 do not completely fill the groove 52R, and as a result, the subsequently formed source / drain regions 112 have a plurality of protrusions (see 112P in Figure 12 ) that extend into (e.g., fill) the remaining space of the groove 52R.

[0043] Next, in Figure 12 , source / drain regions 112 are formed in the opening 110. As Figure 12 shown, the source / drain regions 112 fill the opening 110 and have a plurality of protrusions 112P that fill the grooves 52R in the first semiconductor material 52. In the illustrated embodiment, the source / drain regions 112 are formed of (one or more) epitaxial materials and, thus, may also be referred to as epitaxial source / drain regions 112. In some embodiments, the epitaxial source / drain regions 112 are formed in the opening 110 to apply stress in the corresponding channel regions of the formed NSFET devices, thereby improving performance. The epitaxial source / drain regions 112 are formed such that the dummy gate 102 is disposed between adjacent pairs of the epitaxial source / drain regions 112. In some embodiments, the gate spacers 107 are used to separate the epitaxial source / drain regions 112 from the dummy gate 102 by an appropriate lateral distance such that the epitaxial source / drain regions 112 do not short-circuit the gates of the subsequently formed NSFET devices.

[0044] The epitaxial source / drain regions 112 grow epitaxially in the opening 110. The epitaxial source / drain regions 112 may include, for example, any acceptable material suitable for n-type or p-type devices. For example, when forming an n-type device, the epitaxial source / drain regions 112 may include materials that apply tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type device, the epitaxial source / drain regions 112 may include materials that apply compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 112 may have a surface that protrudes from the corresponding surfaces of the fins and may have facets.

[0045] The epitaxial source / drain regions 112 and / or the fins may be implanted with dopants to form the source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by an annealing process. The impurity concentration of the source / drain regions may be between about 10 19 cm -3 and about 10 21 cm -3 . The n-type and / or p-type impurities for the source / drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source / drain regions 112 may be in-situ doped during growth.

[0046] As a result of the epitaxial process for forming the epitaxial source / drain regions 112, the upper surface of the epitaxial source / drain regions 112 has facets that extend laterally outward beyond the sidewalls of the fins 90. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 112 disposed over adjacent fins remain separated. In other embodiments, these facets cause adjacent epitaxial source / drain regions 112 disposed over adjacent fins of the same NSFET to merge.

[0047] Next, in Figure 13 , a contact etch stop layer (CESL) 116 is formed (e.g., conformally) over the source / drain regions 112 and over the dummy gate 102, and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having an etch rate different from that of the first ILD 114 and may be formed of silicon nitride using PECVD, but other dielectric materials (e.g., silicon oxide, silicon oxynitride, combinations thereof, etc.) and alternative techniques for forming the CESL 116 (e.g., low pressure CVD (LPCVD), PVD, etc.) may alternatively be used.

[0048] The first ILD 114 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials for the first ILD 114 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0049] Next, the dummy gate 102 is removed. To remove the dummy gate 102, a planarization process such as CMP is performed to make the top surfaces of the first ILD 114 and the CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacers 107. The planarization process may also remove the mask 104 on the dummy gate 102 (see Figure 5A )(if the mask 104 has not already been removed by the anisotropic etch process to form the gate spacers 107), as well as portions of the gate spacers 107 along the sidewalls of the mask 104. After the planarization process, the top surfaces of the dummy gate 102, the gate spacers 107, and the first ILD 114 are flush. Thus, the top surface of the dummy gate 102 is exposed through the first ILD 114.

[0050] After the planarization process, the dummy gate 102 is removed in one or more etching steps such that a groove 103 is formed between the gate spacers 107. In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 102 without etching the first ILD 114 or the gate spacers 107. The groove 103 exposes the channel region of the NSFET. The channel region is disposed between adjacent pairs of the epitaxial source / drain regions 112. During the removal of the dummy gate 102, the dummy gate dielectric 97 may be used as an etch stop layer when etching the dummy gate 102. Then the dummy gate dielectric 97 may be removed after the removal of the dummy gate 102. After the removal of the dummy gate 102, the first semiconductor material 52 and the second semiconductor material 54 disposed below the dummy gate 102 are exposed through the groove 103.

[0051] Next, the first semiconductor material 52 is removed to release the second semiconductor material 54. After the removal of the first semiconductor material 52, the second semiconductor material 54 forms a plurality of nanosheets 54 that extend horizontally (e.g., parallel to the main upper surface of the substrate 50). The nanosheets 54 may collectively form the channel region or channel layer of the formed NSFET device 100. As Figure 13 shown, a gap 53 (e.g., an empty space) is formed between the nanosheets 54 by removing the first semiconductor material 52. In some embodiments, the nanosheets 54 may also be referred to as nanowires, and the NSFET device 100 may also be referred to as a gate-all-around (GAA) device.

[0052] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to the first semiconductor material 52 (e.g., having a higher etching rate) such that the first semiconductor material 52 is removed with substantially no erosion of the second semiconductor material 54. In an embodiment, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process may be performed using an etching gas and optionally a carrier gas, where the etching gas includes F2 and HF, and the carrier gas may be an inert gas (e.g., Ar, He, N2, combinations thereof, etc.).

[0053] In some embodiments, the dummy inner spacer 55 is also removed by this etching process, thereby removing the first semiconductor material 52. In other embodiments, after the removal of the first semiconductor material 52, an additional etching process is performed to remove (e.g., selectively remove) the dummy inner spacer 55. After the removal of the dummy inner spacer 55, a material layer 56 (e.g., silicon) is exposed in the gap 53.

[0054] Next, in Figure 14 an internal spacer layer 131 is formed (e.g., conformally) in the groove 103 and around the nanosheet 54. In some embodiments, the internal spacer layer 131 is formed of a suitable dielectric material. Examples of materials for the internal spacer layer 131 include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), silicon dioxide (SiO2), etc., formed by suitable deposition methods (e.g., ALD, PVD, CVD, etc.).

[0055] As Figure 14 shown, in the region 132 near the end of the nanosheet 54, due to the protrusions 112P of the source / drain regions 112 and the material layer 56 over the protrusions 112P, a small space (see label 133) is formed. This small space makes it easier to be sealed by the internal spacer layer 131 to form an air gap 133. An enlarged view of the region 132 is shown in Figure 17 . Details of the air gap 133 are discussed below. In some embodiments, due to the faster deposition / accumulation rate at the small / narrow space, the thickness of the portion of the internal spacer layer 131 in the region 132 (e.g., the portion in contact with the material layer 56) is greater than the thickness of other portions of the internal spacer layer.

[0056] Next, in Figure 15 an etching process is performed to remove a portion of the internal spacer layer 131. The etching process can be a wet etching process performed using a suitable etchant such as H3PO4. The etching process can be a timed process such that the portion of the internal spacer layer 131 outside the region 132 (e.g., the middle portion around the nanosheet 54) is completely removed, while the remaining portion of the internal spacer layer 131 within the region 132 (e.g., the portion in contact with the material layer 56 and sealing the air gap 133) forms an internal spacer 131. As Figure 15 shown, each internal spacer 131 extends continuously between two adjacent nanosheets 54 or between the bottommost nanosheet 54 and the fin 90 and seals the air gap 133.

[0057] Next, in Figure 16In [the figure], a gate dielectric layer 120 is formed (e.g., conformally) in the groove 103. The gate dielectric layer 120 wraps around the nanosheet 54, lines the sidewalls of the first sub-layer 108 of the gate spacer, and extends along the upper surface and sidewalls of the fin 90. According to some embodiments, the gate dielectric layer 120 includes silicon oxide, silicon nitride, or a multi-layer thereof. In some embodiments, the gate dielectric layer 120 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 120 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb or combinations thereof. The method of forming the gate dielectric layer 120 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0058] Next, gate electrode material (e.g., a conductive material) is formed in the groove 103 to form the gate electrode 122. The gate electrode 122 fills the remaining portion of the groove 103. The gate electrode 122 can be made of a metal material (such as Cu, Al, W, etc., combinations thereof, or multi-layers thereof) and can be formed by, for example, electroplating, electroless plating, or other suitable methods. After filling the gate electrode 122, a planarization process such as CMP can be performed to remove the excess portions of the materials of the gate dielectric layer 120 and the gate electrode 122 that are above the top surface of the first ILD 114. The material of the gate electrode 122 and the remaining portion of the gate dielectric layer 120 thus form the replacement gate of the resulting NSFET device 100. The gate electrode 122 and the corresponding gate dielectric layer 120 can be collectively referred to as the gate stack 123, the replacement gate structure 123, or the metal gate structure 123. Each gate stack 123 extends over and around the corresponding nanosheet 54.

[0059] Although the gate electrode 122 is shown as a single layer in the Figure 16 example, those skilled in the art will readily understand that the gate electrode 122 can have a multi-layer structure and can include multiple layers, such as a barrier layer, a work function layer, a seed layer, and a fill metal.

[0060] For example, a barrier layer can be conformally formed over the gate dielectric layer 120. The barrier layer can include a conductive material such as titanium nitride, but optionally other materials such as tantalum nitride, titanium, tantalum, etc. can also be used. A work function layer can be formed over the barrier layer. Exemplary p-type work function materials (which can also be referred to as p-type work function metals) include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function materials (which can also be referred to as n-type work function metals) include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer. Thus, the work function layer is selected to adjust its work function value such that a target threshold voltage V is achieved in the device to be formed TH 。

[0061] Figure 17 is Figure 16 an enlarged view of region 132 in Figure 17 . As shown in Figure 17 , the internal spacer 131 seals the air gap 133, which is disposed between the internal spacer 131 and the material layer 56 and between two adjacent nanosheets 54. The air gap 133 can include an upper portion 133U over the protrusion 112P of the source / drain region 112 and a lower portion 133L under the protrusion 112P. In some embodiments, the upper portion 133U and the lower portion 133L of the air gap 133 are two independent sealed spaces. In some embodiments, the upper portion 133U and the lower portion 133L have similar shapes (e.g., substantially mirror symmetric about the horizontal central axis 112C of the protrusion 112P in Figure 17 ). In the example of Figure 17 , the upper portion 133U (or the lower portion 133L) of the air gap 133 has a width W between the internal spacer 131 and the material layer 56, where the width W continuously increases from the center of two adjacent nanosheets 54 towards one of the two adjacent nanosheets 54 along the Figure 17 's vertical direction. Further, the upper portion 133U (or the lower portion 133L) of the air gap 133 has a height H, which includes a first value H1 measured between the internal spacer 131 and the material layer 56 and has a second value H2 measured between the nanosheet 54 and the material layer 56, where H1 continuously increases from left to right along the Figure 17 's horizontal direction, and H2 continuously decreases from left to right along the Figure 17 's horizontal direction. In Figure 17In [the figure], the internal spacer 131 has a surface 131S1 facing and contacting the gate stack 123, and has a surface 131S2 facing the air gap 133. The material layer 56 may extend into the surface 131S2, as Figure 17 shown. The surfaces 131S1 and 131S2 are curved surfaces. When looking along a first direction from the internal spacer 131 towards the gate stack 123, the surface 131S1 is concave, while the surface 131S2 is convex; when looking along a second direction opposite to the first direction, the surface 131S1 is convex, while the surface 131S2 is concave. In some embodiments, the distance S between adjacent nanosheets 54 is between about 5 nm and about 20 nm, the distance D between the source / drain region 112 and the surface 131S1 of the internal spacer layer 131 is between about 5 nm and about 15 nm, and the thickness T of the material layer 56 is between about 2 nm and about 7 nm. In some embodiments, the height H of the air gap 133 (e.g., 133U or 133L) is between about one-fourth and about one-half of the distance S (e.g., 0.25S < H ≤ 0.5S). In some embodiments, the width W of the air gap 133 is between about D - T and about D - 0.5T (e.g., D - T ≤ W < D - 0.5T).

[0062] In some embodiments, the air gap 133 reduces the k value (e.g., the average k value) of the dielectric material near the gate stack 123, thereby improving device performance by reducing the parasitic capacitance of the NSFET device 100.

[0063] As can be readily understood by those of ordinary skill in the art, additional processes may be performed to complete the fabrication of the NSFET device 100, and thus will not be elaborated herein. For example, a second ILD may be deposited on top of the first ILD 114. Additionally, gate contacts and source / drain contacts may be formed through the second ILD and / or the first ILD 114 to be electrically coupled to the gate electrode 122 and the source / drain region 112, respectively.

[0064] Figure 18 is a cross-sectional view of a nanosheet field-effect transistor device 100A at a certain manufacturing stage according to another embodiment. The NSFET device 100A is similar to Figure 16 the NSFET device 100, but Figure 16 the material layer (e.g., the semiconductor layer) [of the NSFET device 100] is replaced with a material layer 57, which is a dielectric material layer. The same or similar processes (e.g., a deposition process followed by an etching process) as discussed above with reference to Figure 11 the material layer 56 can be used to form the material layer 57. After forming the material layer 57, the same or similar processes as Figures 12 - 16 shown can be performed to form Figure 18The nanosheet field-effect transistor device 100A. In some embodiments, the material of the material layer 57 is the same as the material of the internal spacer 131, such as silicon nitride. In other embodiments, the material of the material layer 57 is a dielectric material different from the dielectric material of the internal spacer 131.

[0065] Figure 19 is Figure 18 An enlarged view of the region 132 in. As Figure 19 shown, the internal spacer 131 seals the air gap 133, and the air gap 133 is arranged between the material layer 57 and the internal spacer 131 and between two adjacent nanosheets 54. Details of the air gap 133 (such as shape and size) are the same as or similar to those of Figure 17 those, and thus will not be repeated here.

[0066] Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, depending on the type of device being formed (e.g., an n-type or p-type device), the second semiconductor material 54 can be removed, and the first semiconductor material 52 can be retained to form nanosheets to be used as the channel region of the formed NSFET device. As will be readily understood by those of ordinary skill in the art, in embodiments where the first semiconductor material 52 is retained to form nanosheets, the internal spacer is formed near the end of the second semiconductor material 54.

[0067] The embodiments can achieve advantages. The disclosed method or structure reduces the parasitic capacitance of the NSFET device by forming an air gap between the internal spacer and the source / drain region 112. In addition, the epitaxial growth of the source / drain region 112 is facilitated by using a semiconductor material (e.g., silicon) as the material layer 56.

[0068] Figure 20 A flowchart of a method 1000 for manufacturing a semiconductor device according to some embodiments is shown. It should be understood that Figure 20 the illustrated embodiment methods are merely examples of many possible embodiment methods. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. For example, the various steps shown as Figure 20 such can be added, removed, replaced, rearranged, or repeated.

[0069] Referring to Figure 20, in step 1010, a dummy gate structure is formed over the nanostructure and over the fin, the nanostructure covering the fin, the fin protruding above the substrate, and the nanostructure including alternating layers of a first semiconductor material and a second semiconductor material. In step 1020, an opening is formed in the nanostructure on the opposite side of the dummy gate structure, the opening exposing ends of the first semiconductor material and the second semiconductor material. In step 1030, the exposed ends of the first semiconductor material are recessed to form grooves. In step 1040, dummy inner spacers are formed in the grooves, and a material layer is formed over the dummy inner spacers in the grooves. In step 1050, after forming the material layer, source / drain regions are formed in the opening. In step 1060, after forming the source / drain regions, the dummy gate structure is removed to expose the first semiconductor material and the second semiconductor material disposed under the dummy gate structure. In step 1070, the exposed first semiconductor material and the dummy inner spacers are removed, wherein the second semiconductor material remains and forms a plurality of nanosheets, and the material layer is exposed after removing the dummy inner spacers. In step 1080, inner spacers are formed between opposite ends of the plurality of nanosheets, between the source / drain regions, wherein each inner spacer seals an air gap between each inner spacer and the material layer.

[0070] In one embodiment, a semiconductor device includes: a fin protruding above a substrate; source / drain regions over the fin; nanosheets between the source / drain regions, wherein the nanosheets include a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, wherein there is an air gap between each inner spacer and a corresponding one of the source / drain regions of the source / drain regions; and a gate structure over the fin and between the source / drain regions. In an embodiment, the nanosheets are parallel to each other and parallel to a major upper surface of the substrate. In an embodiment, the semiconductor device further includes a material layer between each inner spacer and a corresponding source / drain region, wherein the air gap is between each inner spacer and the material layer. In an embodiment, the material layer is a layer of a second semiconductor material. In an embodiment, the first semiconductor material is the same as the second semiconductor material. In an embodiment, the source / drain regions have a plurality of protrusions extending between the nanosheets toward the inner spacers, wherein the material layer extends conformally over the plurality of protrusions. In an embodiment, the material layer is a layer of a first dielectric material, and the inner spacers include a second dielectric material. In an embodiment, the first dielectric material is the same as the second dielectric material. In an embodiment, the air gap is sealed between each inner spacer and a corresponding source / drain region and in a space between adjacent nanosheets. In an embodiment, each inner spacer has a concave surface facing the gate structure.

[0071] In an embodiment, a semiconductor device includes: a fin protruding above a substrate; a gate structure over the fin; source / drain regions over the fin and on opposite sides of the gate structure; a first channel layer and a second channel layer disposed between the source / drain regions and parallel to each other, wherein the gate structure surrounds the first channel layer and the second channel layer; an internal spacer disposed between an end of the first channel layer and an end of the second channel layer, wherein there is an air gap between the internal spacer and the source / drain region. In an embodiment, the semiconductor device further includes a material layer between the internal spacer and the source / drain region, wherein the air gap is between the internal spacer and the material layer. In an embodiment, the material layer is a semiconductor layer. In an embodiment, the material layer is a dielectric layer. In an embodiment, the internal spacer and the material layer comprise the same dielectric material. In an embodiment, each internal spacer has a first concave surface facing the gate structure and a second concave surface facing the source / drain region.

[0072] In an embodiment, a method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure and over a fin, the nanostructure covering the fin, the fin protruding above a substrate, the nanostructure including alternating layers of a first semiconductor material and a second semiconductor material; forming an opening in the nanostructure on opposite sides of the dummy gate structure, the opening exposing ends of the first semiconductor material and the second semiconductor material; recessing the exposed ends of the first semiconductor material to form a groove; forming a dummy internal spacer in the groove and forming a material layer over the dummy internal spacer in the groove; after forming the material layer, forming source / drain regions in the opening; after forming the source / drain regions, removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material disposed under the dummy gate structure; removing the exposed first semiconductor material and the dummy internal spacer, wherein the second semiconductor material remains and forms a plurality of nanosheets, wherein the material layer is exposed after removing the dummy internal spacer; and forming internal spacers between the source / drain regions at opposite ends of the plurality of nanosheets, wherein each internal spacer seals an air gap between each internal spacer and the material layer. In an embodiment, the method further includes, after forming the internal spacers, forming a replacement gate structure surrounding the plurality of nanosheets. In an embodiment, forming the material layer includes forming the material layer using a semiconductor material. In an embodiment, forming the material layer includes forming the material layer using a dielectric material.

[0073] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0074] Example 1. A semiconductor device, comprising: fins protruding above a substrate; source / drain regions over the fins; nanosheets between the source / drain regions, wherein the nanosheets comprise a first semiconductor material; internal spacers between the nanosheets and at opposite ends of the nanosheets, wherein there is an air gap between each of the internal spacers and a corresponding one of the source / drain regions in the source / drain regions; and a gate structure over the fins and between the source / drain regions.

[0075] Example 2. The semiconductor device according to Example 1, wherein the nanosheets are parallel to each other and parallel to a main upper surface of the substrate.

[0076] Example 3. The semiconductor device according to Example 1, further comprising: a material layer between each of the internal spacers and the corresponding source / drain region, wherein the air gap is between each of the internal spacers and the material layer.

[0077] Example 4. The semiconductor device according to Example 3, wherein the material layer is a layer of a second semiconductor material.

[0078] Example 5. The semiconductor device according to Example 4, wherein the first semiconductor material is the same as the second semiconductor material.

[0079] Example 6. The semiconductor device according to Example 5, wherein the source / drain regions have a plurality of protrusions extending between the nanosheets and toward the internal spacers, wherein the material layer extends conformally over the plurality of protrusions.

[0080] Example 7. The semiconductor device according to Example 3, wherein the material layer is a layer of a first dielectric material, and the internal spacers comprise a second dielectric material.

[0081] Example 8. The semiconductor device according to Example 7, wherein the first dielectric material is the same as the second dielectric material.

[0082] Example 9. The semiconductor device according to Example 1, wherein the air gap is sealed between each of the inner spacers and the corresponding source / drain region and in the space between adjacent nanosheets in the nanosheet.

[0083] Example 10. The semiconductor device according to Example 1, wherein each of the inner spacers has a concave surface facing the gate structure.

[0084] Example 11. A semiconductor device, comprising: a fin protruding above a substrate; a gate structure above the fin; source / drain regions above the fin on opposite sides of the gate structure; a first channel layer and a second channel layer disposed between the source / drain regions and parallel to each other, wherein the gate structure surrounds the first channel layer and the second channel layer; and inner spacers disposed between an end of the first channel layer and an end of the second channel layer, wherein an air gap exists between the inner spacers and the source / drain regions.

[0085] Example 12. The semiconductor device according to Example 11, further comprising: a material layer between the inner spacers and the source / drain regions, wherein the air gap is between the inner spacers and the material layer.

[0086] Example 13. The semiconductor device according to Example 12, wherein the material layer is a semiconductor layer.

[0087] Example 14. The semiconductor device according to Example 12, wherein the material layer is a dielectric layer.

[0088] Example 15. The semiconductor device according to Example 14, wherein the inner spacers and the material layer comprise the same dielectric material.

[0089] Example 16. The semiconductor device according to Example 11, wherein each of the inner spacers has a first concave surface facing the gate structure and a second concave surface facing the source / drain region.

[0090] Example 17. A method of forming a semiconductor device, the method comprising: forming a dummy gate structure over a nanostructure and over a fin, the nanostructure covering the fin, the fin protruding above the substrate, the nanostructure comprising alternating layers of a first semiconductor material and a second semiconductor material; forming an opening in the nanostructure on opposite sides of the dummy gate structure, the opening exposing ends of the first semiconductor material and the second semiconductor material; recessing the exposed ends of the first semiconductor material to form grooves; forming dummy inner spacers in the grooves and forming a material layer over the dummy inner spacers in the grooves; after forming the material layer, forming source / drain regions in the opening; after forming the source / drain regions, removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material disposed below the dummy gate structure; removing the exposed first semiconductor material and the dummy inner spacers, wherein the second semiconductor material remains and forms a plurality of nanosheets, wherein the material layer is exposed after removing the dummy inner spacers; and forming inner spacers between the source / drain regions at opposite ends of the plurality of nanosheets, wherein each of the inner spacers seals an air gap between each inner spacer and the material layer.

[0091] Example 18. The method according to Example 17, further comprising: after forming the inner spacers, forming a replacement gate structure around the plurality of nanosheets.

[0092] Example 19. The method according to Example 17, wherein forming the material layer comprises: forming the material layer using a semiconductor material.

[0093] Example 20. The method according to Example 17, wherein forming the material layer comprises: forming the material layer using a dielectric material.

Claims

1. A semiconductor device, comprising: a fin protruding above a substrate; a source / drain region above the fin; nanosheets between the source / drain regions, wherein the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, wherein there is an air gap between each inner spacer and a corresponding source / drain region in the source / drain regions; and a gate structure above the fin and between the source / drain regions, and a material layer between each inner spacer and the corresponding source / drain region, wherein the air gap is between each inner spacer and the material layer, wherein the source / drain regions have a plurality of protrusions extending between the nanosheets towards the inner spacers, wherein the material layer conformally extends over the plurality of protrusions, wherein each inner spacer has a first concave surface facing the gate structure and a second concave surface facing the source / drain region.

2. The semiconductor device according to claim 1, wherein, The nanosheets are parallel to each other and parallel to a main upper surface of the substrate.

3. The semiconductor device according to claim 1, wherein The material layer is a layer of a second semiconductor material.

4. The semiconductor device according to claim 3, wherein, The first semiconductor material is the same as the second semiconductor material.

5. The semiconductor device according to claim 1, wherein, The material layer is a layer of a first dielectric material, and the inner spacers comprise a second dielectric material.

6. The semiconductor device according to claim 5, wherein, The first dielectric material is the same as the second dielectric material.

7. The semiconductor device according to claim 1, wherein, The air gap is sealed between each inner spacer and the corresponding source / drain region and in a space between adjacent nanosheets in the nanosheets.

8. A semiconductor device, comprising: a fin protruding above a substrate; a gate structure above the fin; source / drain regions above the fin, on opposite sides of the gate structure; a first channel layer and a second channel layer arranged between the source / drain regions and parallel to each other, wherein the gate structure surrounds the first channel layer and the second channel layer; and inner spacers arranged between an end of the first channel layer and an end of the second channel layer, wherein there is an air gap between the inner spacers and the source / drain regions, and a material layer between the inner spacers and the source / drain regions, wherein the air gap is between the inner spacers and the material layer, wherein the source / drain regions have a plurality of protrusions extending between the first channel layer and the second channel layer towards the inner spacers, wherein the material layer conformally extends over the plurality of protrusions, wherein each inner spacer has a first concave surface facing the gate structure and a second concave surface facing the source / drain region.

9. The semiconductor device according to claim 8, wherein, The material layer is a semiconductor layer.

10. The semiconductor device according to claim 8, wherein, The material layer is a dielectric layer.

11. The semiconductor device according to claim 10, wherein, The inner spacers and the material layer comprise the same dielectric material.

12. A method of forming a semiconductor device, the method comprising: A dummy gate structure is formed over the nanostructure and over the fin, the nanostructure covering the fin, the fin protruding above a substrate, the nanostructure including alternating layers of a first semiconductor material and a second semiconductor material; An opening is formed in the nanostructure on opposite sides of the dummy gate structure, the opening exposing ends of the first semiconductor material and ends of the second semiconductor material; The exposed ends of the first semiconductor material are recessed to form grooves; A dummy inner spacer is formed in the grooves, and a material layer is formed over the dummy inner spacer in the grooves; After forming the material layer, source / drain regions are formed in the opening; After forming the source / drain regions, the dummy gate structure is removed to expose the first semiconductor material and the second semiconductor material disposed under the dummy gate structure; The exposed first semiconductor material and the dummy inner spacer are removed, wherein the second semiconductor material remains and forms a plurality of nanosheets, and wherein the material layer is exposed after removing the dummy inner spacer; and Internal spacers are formed between the source / drain regions at opposite ends of the plurality of nanosheets, wherein each of the internal spacers seals an air gap between each internal spacer and the material layer, wherein the source / drain regions have a plurality of protrusions extending between the first semiconductor material and the second semiconductor material toward the internal spacers, wherein the material layer conformally extends over the plurality of protrusions, and each of the internal spacers has a first concave surface facing the gate structure and a second concave surface facing the source / drain regions.

13. The method according to claim 12 further comprises: After forming the internal spacers, a replacement gate structure is formed around the plurality of nanosheets.

14. The method according to claim 12, wherein, Forming the material layer includes: forming the material layer using a semiconductor material.

15. The method according to claim 12, wherein, Forming the material layer includes: forming the material layer using a dielectric material.

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