Error correction circuit for semiconductor memory device and semiconductor memory device

Abstract

An error correction circuit for a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates parity data based on main data using an error correction code represented by a generator matrix, and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device, generates different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when there is one in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0005703 filed on January 16, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to memory devices, and more particularly, to error correction circuits of semiconductor memory devices. Background Art

[0004] Semiconductor memory devices can be classified into non-volatile memory devices such as flash memory devices and volatile memory devices such as dynamic random access memory (DRAM) devices. Due to their high-speed operation and cost-effectiveness, DRAM devices are commonly used for system memory. As the manufacturing design rules of DRAM devices continue to decrease, bit errors of memory cells in DRAM devices may increase, and the yield of DRAM devices may decrease. Summary of the Invention

[0005] Some example embodiments of the present disclosure provide an error correction circuit of a semiconductor memory device that may enhance performance and reliability.

[0006] Some example embodiments of the present disclosure provide semiconductor memory devices with enhanced performance and reliability.

[0007] According to some example embodiments, an error correction circuit of a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates parity data based on main data using an error correction code represented by a generator matrix, and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device, generates different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when there is a single bit error in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page.

[0008] According to some example embodiments, a semiconductor memory device includes a memory cell array, an error correction circuit, and a control logic circuit. The memory cell array includes a plurality of volatile memory cells connected to word lines and bit lines. The error correction circuit generates parity data based on main data using an ECC represented by a generator matrix, and stores a codeword including the main data and the parity data in a target page of the memory cell array. Based on an address provided from outside the semiconductor memory device, the error correction circuit reads the codeword from the target page as a read codeword to generate a different syndrome based on the read codeword and a parity check matrix, the parity check matrix being based on the ECC. The different syndromes are applied to the main data in the read codeword to correct a single bit error when the main data exists, or to correct two bit errors when two adjacent memory cells in the target page occur. The control logic circuit controls the error correction circuit based on a command from outside the semiconductor memory device and the address.

[0009] According to some example embodiments, a semiconductor memory device includes a memory cell array, an error correction circuit, and a control logic circuit. The memory cell array includes a plurality of volatile memory cells connected to word lines and bit lines. The error correction circuit generates parity data based on main data using an ECC represented by a generator matrix, and stores a codeword including the main data and the parity data in a target page of the memory cell array. The device reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device to generate different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the ECC. The device applies the different syndromes to the main data in the read codeword to correct a single bit error if one exists in the main data, or to correct two bit errors if two bit errors occur in two adjacent memory cells in the target page. The control logic circuit controls the error correction circuit based on a command provided from outside the semiconductor memory device and the address. The error correction circuit includes an ECC decoder that generates the different syndromes based on the parity check matrix based on the ECC. The ECC decoder generates a first sub-check matrix and a second sub-check matrix, and applies one of the first sub-check matrix and the second sub-check matrix to the read codeword based on a least significant bit of a row address in the address to generate at least one syndrome to correct the two bit errors.

[0010] According to some example embodiments, an error correction circuit and a semiconductor memory device including the same may correct single-bit errors and double-bit errors by applying different syndromes to the single-bit errors and double-bit errors using an ECC-based parity check matrix, thereby improving error correction efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating a storage system according to some example embodiments.

[0013] Figure 2 shows a method according to some example embodiments Figure 1 The main data corresponding to multiple burst lengths in the storage system.

[0014] Figure 3 is a diagram illustrating a method according to some example embodiments Figure 1 A block diagram of an example of a storage controller in FIG.

[0015] Figure 4 is a diagram illustrating a method according to some example embodiments Figure 3 A block diagram of an example of an ECC decoder in FIG.

[0016] Figure 5 is a diagram illustrating some example embodiments according to the present disclosure Figure 1 Block diagram of a semiconductor memory device in FIG.

[0017] Figure 6 According to some example embodiments Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0018] Figure 7 According to some example embodiments Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0019] Figure 8 According to some example embodiments Figure 7 A portion of a first memory bank array.

[0020] Figure 9 Shows the write operation Figure 5 A portion of a semiconductor memory device.

[0021] Figure 10 Shows the read operation Figure 5 A portion of a semiconductor memory device.

[0022] Figure 11 is a diagram illustrating a method according to some example embodiments Figure 5 A block diagram of an example of an error correction circuit in a semiconductor memory device.

[0023] Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D Examples of error bits in a data pattern stored in a sub-array block according to the least significant bit of a row address are respectively shown.

[0024] Figure 13 is a diagram illustrating a method according to some example embodiments Figure 11 Block diagram of the ECC decoder in the error correction circuit.

[0025] Figure 14 According to some example embodiments Figure 11 The relationship between the first ECC and parity bits used in the error correction circuit.

[0026] Figure 15 According to some example embodiments Figure 14 Example of the first ECC in .

[0027] Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D and Figure 16E Shown Figure 15 Example of a parity check matrix.

[0028] Figure 17A and Figure 17B An example of a first sub-check matrix generated by using a parity check matrix is ​​shown.

[0029] Figure 18A and Figure 18B An example of a second sub-check matrix generated by using a parity check matrix is ​​shown.

[0030] Figure 19A is a diagram illustrating a method according to some example embodiments Figure 13 Block diagram of the syndrome generation circuit in the ECC decoder.

[0031] Figure 19B is a diagram illustrating a method according to some example embodiments Figure 13 Block diagram of the selection circuit in the ECC decoder.

[0032] Figure 20 is a diagram illustrating a method according to some example embodiments Figure 13 Block diagram of the first corrector in the ECC decoder.

[0033] Figure 21is a flowchart illustrating a method of operating a semiconductor memory device according to some example embodiments.

[0034] Figure 22 is a block diagram illustrating a semiconductor memory device according to some example embodiments.

[0035] Figure 23 According to some example embodiments, Figure 22 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0036] Figure 24 is a diagram illustrating a semiconductor package including a stacked memory device according to some example embodiments. DETAILED DESCRIPTION

[0037] Hereinafter, example embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0038] Figure 1 is a block diagram illustrating a storage system according to an example embodiment of the present disclosure.

[0039] Reference Figure 1 , the memory system 20 may include a memory controller 100 (eg, an external memory controller) and a semiconductor memory device 200 .

[0040] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 may write data into the semiconductor memory device 200 or read data from the semiconductor memory device 200 in response to a request from the host.

[0041] In addition, the memory controller 100 may issue an operation command to the semiconductor memory device 200 to control the semiconductor memory device 200 .

[0042] In an example embodiment, the semiconductor memory device 200 is a memory device including a plurality of dynamic (volatile) memory cells, such as a dynamic random access memory (DRAM), a DDR5 (double data rate) synchronous DRAM (SDRAM), a DDR6 (double data rate) synchronous DRAM (SDRAM), or a stacked memory device. An example of a stacked memory device in some embodiments is a high bandwidth memory (HBM).

[0043] The memory controller 100 sends a command CMD and an address (signal) ADDR to the semiconductor memory device 200 and exchanges main data MD with the semiconductor memory device 200. Figure 1Although not shown, the memory controller 100 may transmit a clock signal to the semiconductor memory device 200 .

[0044] The memory controller 100 may include an error correction circuit 130. As described below, the semiconductor memory device 200 may include an error correction circuit 400, and thus the error correction circuit 130 in the memory controller 100 may be referred to as a second error correction circuit. The error correction circuit 130 may generate parity data based on the main data MD to be transmitted to the semiconductor memory device 200. The error correction circuit 130 may store the parity data, may generate a check bit based on the main data MD when receiving the main data MD from the semiconductor memory device 200, and may correct an error bit in the main data MD received from the semiconductor memory device 200 based on a comparison between the parity data and the check bit.

[0045] The semiconductor memory device 200 includes a memory cell array (MCA) 300 that stores main data MD, an error correction circuit 400, and a control logic circuit 210. Since the error correction circuit 130 in the memory controller 100 can be referred to as a second error correction circuit as described above, the error correction circuit 400 can be referred to as a first error correction circuit. The memory cell array 300 includes a plurality of sub-array blocks arranged along a first direction and a second direction intersecting the first direction. For example, the sub-array blocks can be arranged in a three-dimensional configuration in which the first direction is perpendicular to a second plane including the second direction, and the second direction is perpendicular to the first plane including the first direction.

[0046] The generator matrix can represent the ECC as a structure / data format in the form of a matrix. The generator matrix may include, for example, a plurality of column vectors, and the column vectors may be divided into groups. The error correction circuit 400 may use the ECC represented by the generator matrix to generate parity data. The group of column vectors of the generator matrix may include, for example, a plurality of code groups corresponding to sub-data units of the main data MD and parity data. The error correction circuit 400 may generate parity data by performing ECC encoding on the main data MD, and may use the parity data to detect and / or correct at least one erroneous bit in the main data MD read from the memory cell array 300 by performing ECC decoding on the main data MD.

[0047] The error correction circuit 400 may include an ECC decoder. The ECC decoder in the error correction circuit 400 may be configured to read data (e.g., a codeword) from a target page in the memory cell array 300. The ECC decoder in the error correction circuit 400 may be configured to read the codeword from the target page of the memory cell array 300 based on an address provided from outside the semiconductor memory device 200 to generate at least one syndrome. A syndrome is an indication of whether an error has occurred in the read codeword and is typically displayed when the syndrome calculation produces a non-zero result, which indicates, for example, a difference between the original main data MD in the codeword to be stored and the main data in the read codeword. The ECC decoder may generate a syndrome based on the data (e.g., a codeword) read from the memory cell array 300 and may correct at least one erroneous bit in the read data based on the syndrome by applying different syndromes to a single-bit error in the read data (when a single-bit error exists in the read data) and a double-bit error occurring in two adjacent memory cells in the target page (when a double-bit error occurs in two adjacent memory cells in the target page). The ECC decoder can generate different syndromes using the ECC-based parity check matrix. Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D and Figure 16E The parity check matrix may include a plurality of code groups corresponding to a plurality of sub-data units and a code group corresponding to parity bits.

[0048] The main data MD includes a plurality of data bits, and the plurality of data bits may be divided into a plurality of sub-data units. The ECC may include a plurality of column vectors divided into a plurality of code groups corresponding to the sub-data units and parity data.

[0049] The semiconductor memory device 200 can perform a burst operation. In this document, a burst operation refers to an operation of writing or reading a large amount of data by sequentially increasing or decreasing an initial address provided from the memory controller 100. The basic unit of a burst operation may be referred to as a burst length BL. In an example embodiment, the burst length BL refers to the number of operations of continuously reading or writing data by sequentially increasing or decreasing an initial address. Figure 1 The main data MD in the storage system 20 may correspond to multiple burst lengths.

[0050] Figure 2 shows a method according to some example embodiments Figure 1 The main data corresponding to multiple burst lengths in the storage system.

[0051] Reference Figure 2, main data MD corresponding to a plurality of burst lengths is input to or output from the semiconductor memory device 200. The main data MD includes data segments MD_SG1 to MD_SGt (t is a natural number equal to or greater than 8), each data segment corresponding to one of the plurality of burst lengths. Figure 2 It is assumed that the burst length is 8. However, example embodiments are not limited thereto. Main data MD corresponding to a plurality of burst lengths may be stored in the memory cell array 300 of the semiconductor memory device 200 .

[0052] Figure 3 is a diagram illustrating a method according to some example embodiments Figure 1 A block diagram of an example of a storage controller in FIG.

[0053] Reference Figure 3 , the memory controller 100 may include a CPU (Central Processing Unit) 110, a data buffer 120, an error correction circuit 130, a command buffer 180, and an address buffer 190. The error correction circuit 130 may include a parity generator 140, a buffer 145, a memory 150 storing a second ECC (ECC2) 155, and an ECC decoder 160.

[0054] The CPU 110 receives a request REQ and data DTA from the host, and provides the data DTA to the data buffer 120 and the parity generator 140 .

[0055] The data buffer 120 buffers the data DTA to provide the first main data MD1 to the semiconductor memory device 200 .

[0056] The parity generator 140 is connected to the memory 150 , performs ECC encoding on the data DTA using the second ECC 155 to generate systematic parity data PRTc, and stores the systematic parity data PRTc in the buffer 145 .

[0057] In a read operation of the semiconductor memory device 200, the ECC decoder 160 receives the second main data MD2 from the semiconductor memory device 200. The ECC decoder 160 performs ECC decoding on the second main data MD2 by using the second ECC 155 and the system parity data PRTc, and may provide corrected main data C_MD2 to the CPU 110. The CPU 110 provides the corrected main data C_MD2 to the host.

[0058] The command (CMD) buffer 180 stores a command CMD corresponding to the request REQ and transmits the command CMD to the semiconductor memory device 200 under the control of the CPU 110. The address buffer 190 stores an address ADDR and transmits the address ADDR to the semiconductor memory device 200 under the control of the CPU 110.

[0059] Figure 4 is a diagram illustrating a method according to some example embodiments Figure 3 A block diagram of an example of an ECC decoder in FIG.

[0060] Reference Figure 4 , the ECC decoder 160 may include a check bit generator 161 , a syndrome generator 163 and a data corrector 165 .

[0061] The parity generator 161 receives the second main data MD2 and generates a parity CHBc corresponding to the second main data MD2 using the second ECC 155 .

[0062] The syndrome generator 163 compares the systematic parity data PRTc with the check bits CHBc based on the sign to generate syndrome data SDRc. The syndrome data SDRc indicates whether the second main data MD2 includes at least one error bit and the position of the at least one error bit.

[0063] The data corrector 165 receives the second main data MD2 and corrects at least one error bit in the second main data MD2 based on the syndrome data SDRc to output corrected main data C_MD2.

[0064] Figure 5 is a diagram illustrating some example embodiments according to the present disclosure Figure 1 Block diagram of a semiconductor memory device in FIG.

[0065] Reference Figure 5 The semiconductor memory device 200 includes a control logic circuit 210, an address register 220, a bank control logic 230, a row address multiplexer (RA MUX) 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an I / O gating circuit 290 (input / output gating circuit), a data I / O buffer 295 (data input / output buffer), a refresh counter 245 and an error correction circuit 400.

[0066] The memory cell array 300 includes first to eighth memory bank arrays 310 to 380. The row decoder 260 includes first to eighth memory bank row decoders 260a to 260h coupled to the first to eighth memory bank arrays 310 to 380, respectively. The column decoder 270 includes first to eighth memory bank column decoders 270a to 270h coupled to the first to eighth memory bank arrays 310 to 380, respectively. The sense amplifier unit 285 includes first to eighth memory bank sense amplifiers 285a to 285h coupled to the first to eighth memory bank arrays 310 to 380, respectively. The first to eighth memory bank arrays 310 to 380, the first to eighth memory bank row decoders 260a to 260h, the first to eighth memory bank column decoders 270a to 270h, and the first to eighth memory bank sense amplifiers 285a to 285h may form first to eighth memory banks. In addition, each of the first to eighth memory bank arrays 310 ˜ 380 may be divided into a plurality of sub-array blocks arranged along first and second directions (eg, horizontal and vertical directions; or eg, depth and vertical directions).

[0067] Each of the first to eighth memory bank arrays 310 ˜ 380 includes a plurality of memory cells MC coupled to word lines WL and bit lines BTL.

[0068] Despite Figure 5 , the semiconductor memory device 200 is shown to include eight memory banks, but example embodiments of the present disclosure are not limited thereto, and the semiconductor memory device 200 may include any number of memory banks.

[0069] The control logic circuit 210 receives a command CMD from the memory controller 100. The address register 220 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100.

[0070] The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 , provide the received row address ROW_ADDR to the row address multiplexer 240 , and provide the received column address COL_ADDR to the column address latch 250 .

[0071] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. A bank row decoder corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders 260a-260h may be activated in response to the bank control signal, and a bank column decoder corresponding to the bank address BANK_ADDR among the first to eighth bank column decoders 270a-270h may be activated in response to the bank control signal.

[0072] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output one of the row address ROW_ADDR and the refresh row address REF_ADDR. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a-260h.

[0073] The activated bank row decoder among the first to eighth bank row decoders 260a-260h may decode the row address RA output from the row address multiplexer 240 and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0074] The column address latch 250 may receive a column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In an example embodiment, in burst mode, the column address latch 250 may generate column addresses that increment starting from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column addresses to the first to eighth bank column decoders 270a-270h.

[0075] The activated bank column decoder among the first to eighth bank column decoders 270a to 270h may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR received from the column address latch 250. Alternatively, the activated bank column decoder among the first to eighth bank column decoders 270a to 270h may control the I / O gating circuit 290 to output data corresponding to the mapped column address MCA.

[0076] The I / O gating circuit 290 includes a circuit for gating input / output data. The I / O gating circuit 290 also includes a read data latch for storing data output from the first to eighth memory bank arrays 310-380, and a write driver for writing data into the first to eighth memory bank arrays 310-380.

[0077] The codeword CW to be read from one of the first to eighth memory bank arrays 310-380 can be sensed by a sense amplifier coupled to the one memory bank array from which the codeword is to be read and can be stored in a read data latch. The codeword CW stored in the read data latch is ECC-decoded by the error correction circuit 400 and can be provided to the memory controller 100 via the data I / O buffer 295.

[0078] Data (or main data) MD to be written into one of the first to eighth bank arrays 310 ˜ 380 may be provided from the memory controller 100 to the data I / O buffer 295 . The main data MD is provided to the error correction circuit 400 .

[0079] The error correction circuit 400 performs ECC encoding on the main data MD to generate parity data and provides a codeword CW including the main data MD and the parity data to the I / O gating circuit 290. The control logic circuit 210 is configured to control the I / O gating circuit 290 so that the sub-data units of the main data MD and the parity data are stored in a target sub-array block among the sub-array blocks. The I / O gating circuit 290 can store the main data MD and the parity data in the target page based on a first control signal CTL1 from the control logic circuit 210. In addition, the error correction circuit 400 performs ECC decoding on the main data read from the target page based on the parity data read from the target page.

[0080] When the error correction circuit 400 performs ECC encoding and ECC decoding, the error correction circuit 400 can use a first ECC represented by a generator matrix. For example, the data structure / data format of the first ECC can be a generator matrix. The first ECC can include multiple column vectors corresponding to the data bits of the data (or main data) MD and the parity bits of the parity data, and these column vectors can be divided into multiple code groups corresponding to multiple sub-data units and parity data. The data bits can be divided into multiple sub-data units.

[0081] The error correction circuit 400 reads a codeword CW from a target page to generate at least one syndrome, and corrects at least one erroneous bit in the read codeword by applying different syndromes to single-bit errors and double-bit errors in the read codeword. When two-bit errors in the read codeword occur in two adjacent memory cells in the target page, the error correction circuit corrects the two-bit errors in the read codeword. The error correction circuit 400 generates different syndromes using a parity check matrix based on the first ECC.

[0082] Therefore, the error correction circuit 400 can correct a single-bit error or a double-bit error in the main data.

[0083] The control logic circuit 210 can control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 can generate a control signal for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100, and a mode register 212 that sets an operation mode of the semiconductor memory device 200. That is, the control logic circuit 210 is configured to control the semiconductor memory device 200 based on the command CMD and address received from outside the semiconductor memory device 200. More specifically, the control logic circuit 210 is configured to control elements of the semiconductor memory device 200 (e.g., the error correction circuit 400) based on the command and address received from outside the semiconductor memory device 200.

[0084] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 may generate a first control signal CTL1 for controlling the I / O gating circuit 290 and a second control signal CTL2 for controlling the error correction circuit 400.

[0085] Figure 6 According to some example embodiments Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0086] Reference Figure 6 The first memory bank array 310 includes a plurality of word lines WL1-WLm (where m is a natural number greater than 2), a plurality of bit lines BTL1-BTLn (where n is a natural number greater than 2), and a plurality of memory cells MC disposed at intersections between the word lines WL1-WLm and the bit lines BTLz1-BTLn. Each memory cell MC includes an access (cell) transistor coupled to one of the word lines WL1-WLm and one of the bit lines BTL1-BTLn, and a storage (cell) capacitor coupled to the cell transistor. In other words, each memory cell MC has a DRAM cell structure.

[0087] Figure 7 According to some example embodiments Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0088] Reference Figure 7In the first memory bank array 310, I sub-array blocks SCB may be arranged in the second direction D2, and J sub-array blocks SCB may be arranged in the first direction D1 substantially perpendicular to the second direction D2. I and J represent the number of sub-array blocks SCB in the second direction and the first direction, respectively, and are natural numbers greater than 2. A plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the bit lines and word lines are arranged in each sub-array block SCB.

[0089] I+1 sub-word line driver regions SWB may be arranged between sub-array blocks SCB along the second direction and on each side of each sub-array block SCB along the second direction D2. Sub-word line drivers may be provided in the sub-word line driver regions SWB. J+1 bit line sense amplifier regions BLSAB may be arranged, for example, between sub-array blocks SCB along the first direction D1 and above and below each sub-array block SCB along the first direction D1. Bit line sense amplifiers for sensing data stored in memory cells may be provided in the bit line sense amplifier regions BLSAB.

[0090] A plurality of junction regions CONJ may be provided adjacent to the sub-word line driver region SWB and the bit line sense amplifier region BLSAB. A voltage generator is provided in each junction region CONJ. Figure 8 A portion 390 of the first memory bank array 310 is depicted.

[0091] Figure 8 According to some example embodiments Figure 7 A portion of a first memory bank array.

[0092] Reference Figure 7 and Figure 8 In the portion 390 of the first bank array 310, a sub-array block SCB, two bit line sense amplifier regions BLSAB, two sub-word line driver regions SWB, and four coupling regions CONJ are provided.

[0093] The sub-array block SCB includes a plurality of word lines WL1-WL4 extending in the row direction (second direction D2) and a plurality of bit line pairs BTL1-BTLB1 and BTL2-BTLB2 extending in the column direction (first direction D1). The sub-array block SCB includes a plurality of memory cells MC arranged at the intersections of the word lines WL1-WL4 and the bit line pairs BTL1-BTLB1 and BTL2-BTLB2.

[0094] Reference Figure 8The sub-word line driver region SWB includes a plurality of sub-word line drivers (SWDs) 551, 552, 553, and 554 that drive word lines WL1 to WL4, respectively. The sub-word line drivers 551 and 552 can be disposed in the sub-word line driver region SWB located on the left side of the sub-array block SCB (in this example). Furthermore, the sub-word line drivers 553 and 554 can be disposed in the sub-word line driver region SWB located on the right side of the sub-array block SCB (in this example).

[0095] The bit line sense amplifier region BLSAB includes a bit line sense amplifier (BLSA) 560 and a bit line sense amplifier 570 coupled to the bit line pairs BTL1-BTLB1 and BTL2-BTLB2, as well as a local sense amplifier (LSA) circuit 580 and a local sense amplifier circuit 590. The bit line sense amplifier 560 can sense and amplify the voltage difference between the bit line pair BTL1 and BTLB1 to provide the amplified voltage difference to the local I / O line pair LIO1 and LIOB1.

[0096] Local sense amplifier circuit 580 controls the connection between local I / O line pair LIO1 and LIOB1 and global I / O line pair GIO1 and GIOB1. Local sense amplifier circuit 590 controls the connection between local I / O line pair LIO2 and LIOB2 and global I / O line pair GIO2 and GIOB2.

[0097] like Figure 8 As shown, the bit line sense amplifier 570 and the bit line sense amplifier 560 can be alternately arranged in the upper and lower parts of the sub-array block SCB. The junction area CONJ is adjacent to the bit line sense amplifier area BLSAB and the sub word line driver area SWB. The junction area CONJ is also arranged in Figure 8 A plurality of voltage generators (VG) 510, 520, 530, and 540 may be disposed in the coupling region CONJ, respectively.

[0098] Figure 9 Shows the write operation Figure 5 A portion of a semiconductor memory device.

[0099] exist Figure 9 , a control logic circuit 210, a first memory bank array 310, an I / O gating circuit 290, and an error correction circuit 400 are shown.

[0100] Reference Figure 9 , the first memory bank array 310 includes a normal cell array NCA and a redundancy cell array RCA.

[0101] The normal cell array (NCA) includes a plurality of first memory blocks (MB0-MB15) (i.e., 311-313), and the redundant cell array (RCA) includes at least a second memory block (314). The first memory blocks (311-313) determine or are used to determine the storage capacity of the semiconductor memory device (200). The second memory block (314) is used for ECC and / or redundancy repair. Because the second memory blocks (314) used for ECC and / or redundancy repair are used for ECC, data line repair, and block repair to repair "defective" cells generated in the first memory blocks (311-313), the second memory blocks (314) are also referred to as EDB blocks. In each of the first memory blocks (311-313), a plurality of first memory cells are arranged in rows and columns. In the second memory block (314), a plurality of second memory cells are arranged in rows and columns. The first memory cells connected to the intersection of the word line (WL) and the bit line (BTL) may be dynamic memory cells. The second memory cells connected to the intersection of the word line (WL) and the bit line (RBTL) may be dynamic memory cells. The first storage blocks 311-313 and the second storage block 314 can both be Figure 7 The SCB stands for Sub-Array Block.

[0102] The I / O gating circuit 290 includes a plurality of switch circuits 291 a ˜ 291 d connected to the first memory blocks 311 ˜ 313 and the second memory block 314 , respectively.

[0103] The error correction circuit 400 can be connected to the switch circuits 291a-291d via the first data line GIO and the second data line EDBIO. The control logic circuit 210 can receive a command CMD and an address ADDR, and can decode the command CMD to generate a first control signal CTL1 for controlling the switch circuits 291a-291d and a second control signal CTL2 for controlling the error correction circuit 400.

[0104] When the command CMD is a write command, the control logic circuit 210 provides the second control signal CTL2 to the error correction circuit 400. The error correction circuit 400 performs ECC encoding on the main data MD to generate parity data associated with the main data MD, and provides the codeword CW including the main data MD and the parity data to the I / O gating circuit 290. The control logic circuit 210 provides the first control signal CTL1 to the I / O gating circuit 290 so that the codeword CW will be stored in a subpage of the target page in the first memory bank array 310.

[0105] Figure 10 Shows the read operation Figure 5 A portion of a semiconductor memory device.

[0106] Reference Figure 10When the command CMD is a read command (second command) specifying a read operation, the control logic circuit 210 provides the first control signal CTL1 to the I / O gating circuit 290, so that the (read) code word RCW stored in the sub-page of the target page in the first memory bank array 310 is provided to the error correction circuit 400.

[0107] The error correction circuit 400 performs ECC decoding on the read codeword RCW to correct a single-bit error or a double-bit error in the read codeword RCW by applying different syndromes to the single-bit error and the double-bit error, and outputs corrected main data C_MD.

[0108] Figure 11 is a diagram illustrating a method according to some example embodiments Figure 5 A block diagram of an example of an error correction circuit in a semiconductor memory device.

[0109] Reference Figure 11 , the error correction circuit 400 includes an ECC memory 410 , an ECC encoder 420 and an ECC decoder 430 .

[0110] The ECC memory 410 stores a first ECC (ECC1) 415. The first ECC 415 can be represented by a generator matrix. For example, the data format / structure of the first ECC 415 can be a generator matrix. The first ECC 415 can include a plurality of column vectors corresponding to data bits in the main data (e.g., MD) and parity data.

[0111] The ECC encoder 420 is connected to the ECC memory 410 and may perform ECC encoding on the main data MD using the first ECC 415 stored in the ECC memory 410 to generate parity data PRT in a write operation of the semiconductor memory device 200. The ECC encoder 420 may provide a codeword CW including the main data MD and the parity data PRT to the I / O gating circuit 290.

[0112] The ECC decoder 430 is connected to the ECC memory 410, can receive the codeword CW including the main data MD and the parity data PRT, can use the first ECC 415 to perform ECC decoding on the main data MD based on the parity data PRT to correct and / or detect error bits in the main data MD, and can output the corrected main data C_MD.

[0113] Although the reference Figure 11 It is described that the ECC memory 410 is coupled to the ECC encoder 420 and the ECC decoder 430 , but in example embodiments, the ECC memory 410 may be implemented using exclusive OR gates within the ECC encoder 420 and the ECC decoder 430 .

[0114] Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D Examples of error bits in a data pattern stored in a sub-array block according to the least significant bit (LSB) of a row address are respectively shown.

[0115] Figure 12A and Figure 12C The occurrence of a single bit error in the data pattern is respectively shown. Figure 12B and Figure 12D It is shown that two bit errors occur in two adjacent memory cells.

[0116] exist Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D In the figure, X represents an error bit.

[0117] Reference Figure 12A , the LSB of the row address is low, so that the row address designates a target page coupled to an even word line, and the memory cell designated by CINX 2 (cell index) includes a single bit error. Figure 12B , the LSB of the row address is low level, and both memory cells designated by CINX 5 and CINX 6 include error bits. That is, two bit errors occur in the adjacent two memory cells designated by CINX 5 and CINX 6. Figure 12B In the example, two bit errors do not occur in adjacent two storage cells designated by, for example, CINX 2 and CINX 3, CINX 4 and CINX 5, and CINX 6 and CINX 7, or there is only a small possibility that two bit errors occur.

[0118] Reference Figure 12C , the LSB of the row address is high, so that the row address designates a target page coupled to an odd word line, and the memory cell designated by CINX 4 includes a single bit error. Figure 12D , the LSB of the row address is high level, and the memory cells designated by CINX 4 and CINX 5 both include error bits. That is, two bit errors occur in the adjacent two memory cells designated by CINX 4 and CINX 5. Figure 12D In the example, two bit errors do not occur in adjacent two storage cells designated by, for example, CINX 1 and CINX 2, CINX 3 and CINX 4, CINX 5 and CINX 6, and CINX 7 and CINX 8, or there is only a small possibility that two bit errors occur.

[0119] like Figure 12B and Figure 12DAs shown, in most pairs of adjacent memory cells, there is no double-bit error or only a small probability of a double-bit error. The structure of the memory cells in the target page may be different based on the LSB of the row address, which may result in the occurrence or non-occurrence of a double-bit error in two adjacent memory cells.

[0120] Figure 13 is a diagram illustrating a method according to some example embodiments Figure 11 Block diagram of the ECC decoder in the error correction circuit.

[0121] Reference Figure 13 , the ECC decoder 430 includes a syndrome generation circuit 440 , a first corrector 470 , a second corrector 475 , a third corrector 480 , and a selection circuit 490 .

[0122] The syndrome generation circuit 440 generates the first syndrome SDR1, the second syndrome SDR2, and the third syndrome SDR3 based on the parity check matrix HS and the read codeword CW. The syndrome generation circuit 440 generates the selection signal SS based on the LSB LSB_RA of the row address, the first syndrome SDR1, and one of the second syndrome SDR2 and the third syndrome SDR3.

[0123] The first corrector 470 corrects a single-bit error in the main data MD based on the first syndrome SDR1 to provide first output data DOUT1. The second corrector 475 corrects two-bit errors in the main data MD based on the second syndrome SDR2 in response to the LSB LSB_RA of the row address being low to provide second output data DOUT2. The third corrector 480 corrects two-bit errors in the main data MD based on the third syndrome SDR3 in response to the LSB LSB_RA of the row address being high to provide third output data DOUT3.

[0124] The selection circuit 490 receives the main data MD, the first output data DOUT1, the second output data DOUT2 and the third output data DOUT3, and selects one of the main data MD, the first output data DOUT1, the second output data DOUT2 and the third output data DOUT3 based on the selection signal SS and the LSB LSB_RA of the row address to output the corrected main data C_MD or the main data MD.

[0125] Figure 14 According to some example embodiments Figure 11 The relationship between the first ECC and parity bits used in the error correction circuit.

[0126] exist Figure 14In FIG, it is assumed that the main data MD includes a plurality of sub-data units SDU1 to SDUx, and the parity data PRT includes 8 parity bits PB1 to PB8. Figure 14 In , assume that x is a natural number equal to or greater than eight.

[0127] Reference Figure 14 The first ECC 415 may be divided into a plurality of code groups CG1-CGx and PCG corresponding to a plurality of sub-data units SDU1-SDUx and parity data PRT. The code group PCG may include a plurality of column vectors PV1-PV8 corresponding to parity bits PB1-PB8 of the parity data PRT.

[0128] Figure 15 According to some example embodiments Figure 14 Example of the first ECC in .

[0129] exist Figure 15 In the example, it is assumed that the main data MD includes 128 data bits d1 to d128, and the parity bits PB1 to PB8 correspond to the data bits d129 to d136. Figure 14 Here x is 16.

[0130] Reference Figure 15 , the data bits d1-d128 of the main data MD may be divided into first to sixteenth sub-data units SDU1-SDU16. The first to sixteenth sub-data units SDU1-SDU16 each include 8 data bits.

[0131] The first ECC 415 (ie, Figure 13 The mentioned parity check matrix HS) includes first to sixteenth code groups CG1-CG16 corresponding to the first to sixteenth sub-data units SDU1-SDU16 and a code group PCG corresponding to parity bits PB1-PB8.

[0132] Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D and Figure 16E Shown Figure 15 Example of a parity check matrix.

[0133] Reference Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D and Figure 16E , the parity check matrix HS includes first to sixteenth code groups CG1 ˜ CG16 corresponding to first to sixteenth sub-data units SDU1 ˜ SDU16 and code groups PCG corresponding to parity bits PB1 ˜ PB8 .

[0134] The first to sixteenth code groups CG1~CG16 include column vectors CV11~CV18, CV21~CV28, CV31~CV38, CV41~CV48, CV51~CV58, CV61~CV68, CV71~CV78, CV81~CV88, CV91~CV98, CV101~CV108, CV111~CV118, CV121~CV128, CV131~CV138, CV141~CV148, CV151~CV158 and CV161~CV168, and code group PCG includes column vectors PV1~PV8.

[0135] Column vectors CV11 to CV18 correspond to data bits d1 to d8. Column vectors CV21 to CV28 correspond to data bits d9 to d16. Column vectors CV31 to CV38 correspond to data bits d17 to d24. Column vectors CV41 to CV48 correspond to data bits d25 to d32. Column vectors PV1 to PV8 correspond to data bits d129 to d136.

[0136] Figure 13 The syndrome generation circuit 440 in the parity check matrix HS can generate a first sub-check matrix ( Figure 19A HS1 in) and the second sub-check matrix ( Figure 19A HS2 in the

[0137] Figure 17A and Figure 17B An example of a first sub-check matrix generated by using a parity check matrix is ​​shown.

[0138] The syndrome generation circuit 440 in the ECC decoder 430 can generate a first sub-check matrix ( ) to be applied when the target page is coupled to an even word line by using the column vectors CV11 to CV168 and PV1 to PV8 of the parity check matrix HS. Figure 19A HS1 in the

[0139] Reference Figure 17A and Figure 17B , the syndrome generation circuit 440 can be Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D and Figure 16EAn XOR operation is performed on the adjacent (2i-1)th column vector and (2i)th column vector among the column vectors CV11-CV168 and PV1-PV8 in the first sub-check matrix HS1. Here, i is one of 1 to k, and k is the number of data bits in each of the sub-data units SDU1-SDU16 and the parity data PRT. The first sub-check matrix HS1 may include even-numbered column vectors eCV1-eCV68.

[0140] For example, the syndrome generation circuit 440 may generate an even column vector eCV1 by performing an exclusive OR operation on column vectors CV11 and CV12 , and may generate an even column vector eCV2 by performing an exclusive OR operation on column vectors CV13 and CV14 .

[0141] Figure 18A and Figure 18B An example of a second sub-check matrix generated by using a parity check matrix is ​​shown.

[0142] The syndrome generation circuit 440 in the ECC decoder 430 can generate a second sub-check matrix ( ) to be applied when the target page is coupled to an odd word line by using the column vectors CV11 to CV168 and PV1 to PV8 of the parity check matrix HS. Figure 19A HS2 in the

[0143] Reference Figure 18A and Figure 18B , the syndrome generation circuit 440 can be Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D and Figure 16E The column vectors CV11-CV168 and the adjacent (2i)th column vector and (2i+1)th column vector among PV1-PV8 are XORed to generate the second sub-check matrix HS2. The second sub-check matrix HS2 may include odd column vectors oCV1-oCV51.

[0144] For example, the syndrome generation circuit 440 may generate an odd column vector oCV1 by performing an exclusive OR operation on column vectors CV12 and CV13 , and may generate an odd column vector oCV2 by performing an exclusive OR operation on column vectors CV14 and CV15 .

[0145] Figure 19A is a diagram illustrating a method according to some example embodiments Figure 13 Block diagram of the syndrome generation circuit in the ECC decoder.

[0146] Reference Figure 19AThe syndrome generation circuit 440 may include a first syndrome generator 445 , a sub-check matrix generator 450 , a second syndrome generator 460 , a third syndrome generator 465 , a multiplexer (MUX) 467 , and a selection signal generator (SS generator) 468 .

[0147] The first syndrome generator 445 may generate the first syndrome SDR1 by applying the parity check matrix HS to the read codeword CW. The sub-check matrix generator 450 may generate the first syndrome SDR1 based on the first part of the parity check matrix HS as shown in FIG. Figure 17A and Figure 17B The first sub-check matrix HS1 can be generated based on the second part of the parity check matrix HS as shown in FIG. Figure 18A and Figure 18B The second sub-check matrix HS2.

[0148] The second syndrome generator 460 can generate a second syndrome SDR2 by applying the first sub-check matrix HS1 to the read codeword CW. The third syndrome generator 465 can generate a third syndrome SDR3 by applying the second sub-check matrix HS2 to the read codeword CW. The third syndrome generator 465 can apply the second sub-check matrix HS2 to the read codeword in response to the LSB of the row address being an even number. That is, the third syndrome generator 465 can apply the second sub-check matrix HS2 to the read codeword based on the LSB of the row address being at a low level, so that the row address specifies a target page coupled to an even wordline.

[0149] The multiplexer 467 may receive the second syndrome SDR2 and the third syndrome SDR3 and may select one of the second syndrome SDR2 and the third syndrome SDR3 based on the LSB LSB_RA of the row address. The selection signal generator 468 may receive the first syndrome SDR1 and the output of the multiplexer 467 and may generate a selection signal SS based on the logic levels of the first syndrome SDR1 and one of the second syndrome SDR2 and the third syndrome SDR3.

[0150] If the first ECC 415 corresponds to a single error correction (SEC) code, the first syndrome SDR1 and the second syndrome SDR2 cannot have non-zero values ​​at the same time, and the first syndrome SDR1 and the third syndrome SDR3 cannot have non-zero values ​​at the same time. Therefore, when the read codeword CW includes a single bit error, one of the second syndrome SDR2 and the third syndrome SDR3 has a non-zero value.

[0151] In addition, when the read codeword CW does not include (one or more) errors, the first syndrome SDR1 and the second syndrome SDR2 both have non-zero values, or the first syndrome SDR1 and the third syndrome SDR3 both have non-zero values. Therefore, according to the above description, the selection signal generator 468 can determine the logic level of the selection signal SS based on the values ​​of the first syndrome SDR1, the second syndrome SDR2, and the third syndrome.

[0152] Figure 19B is a diagram illustrating a method according to some example embodiments Figure 13 Block diagram of the selection circuit in the ECC decoder.

[0153] Reference Figure 19B , the selection circuit 490 may include a first multiplexer 491 and a second multiplexer 493 .

[0154] The first multiplexer 491 receives the second and third output data DOUT2 and DOUT3 and selects one of the second and third output data DOUT2 and DOUT3 in response to the LSB LSB_RA of the row address.

[0155] When the target page is coupled to an even word line, first multiplexer 491 provides second output data DOUT2. When the target page is coupled to an odd word line, first multiplexer 491 provides third output data DOUT3. Second multiplexer 493 receives main data MD, first output data DOUT1, and the output of first multiplexer 491, selects one of main data MD, first output data DOUT1, and the output of first multiplexer 491 in response to a select signal SS, and outputs the selected one as main data MD or corrected main data C_MD.

[0156] Figure 20 is a diagram illustrating a method according to some example embodiments Figure 13 Block diagram of the first corrector in the ECC decoder.

[0157] Reference Figure 20 , the first corrector 470 may include an error locator polynomial calculator (ELP calculator) 471 , an error locator calculator (EL calculator) 472 , and a data corrector 473 .

[0158] The error locator polynomial calculator 471 may calculate coefficients ELP of the error locator polynomial based on the first syndrome SDR1 and provide the coefficients ELP of the error locator polynomial to the error locator calculator 472. The error locator calculator 472 may calculate error locations based on the coefficients ELP of the error locator polynomial and provide an error location signal ELS indicating the location(s) of the error(s) to the data corrector 473. The data corrector 473 may correct a single bit error in the main data MD based on the error location signal ELS and provide first output data DOUT1.

[0159] Figure 21 is a flowchart illustrating a method of operating a semiconductor memory device according to some example embodiments.

[0160] Reference Figures 5 to 21 , in the method of operating the semiconductor memory device 200 including the memory cell array 300, the error correction circuit 400 generates parity data PRT based on the main data MD by using the first ECC 415 (S110).

[0161] The first ECC 415 may be represented by a generator matrix, may include a plurality of column vectors, and the column vectors may be divided into a plurality of code groups PRT corresponding to sub-data units of the main data MD and parity data.

[0162] The error correction circuit 400 stores the main data MD and the parity data PRT in the target page of the memory cell array 300 via the I / O gating circuit 290 ( S130 ).

[0163] The error correction circuit 400 reads the main data MD and the parity data PRT from the target page of the memory cell array 300 via the I / O gating circuit 290 ( S150 ).

[0164] The error correction circuit 400 generates a first syndrome SDR1 , a second syndrome SDR2 , and a third syndrome SDR3 based on the main data MD and the parity data PRT by using the first ECC 415 ( S170 ).

[0165] The error correction circuit 400 corrects a one-bit error in the main data MD or two-bit errors occurring in two adjacent memory cells of the main data MD by using the first syndrome SDR1 or one of the second syndrome SDR2 and the third syndrome SDR3 selected based on the LSB of the row address of the designated target page (S190).

[0166] Therefore, the error correction circuit and the semiconductor memory device including the same can correct single-bit errors and double-bit errors by applying different syndromes to the single-bit errors and double-bit errors using an ECC-based parity check matrix, and thus can improve error correction efficiency.

[0167] Figure 22 is a block diagram illustrating a semiconductor memory device according to some example embodiments.

[0168] Reference Figure 22 , the semiconductor memory device 600 may include one or more buffer dies 610 and a stack die 620 that provide soft error analysis and correction functions in a stacked chip structure.

[0169] Group die 620 may be a high bandwidth memory (HBM).

[0170] The group die 620 may include a plurality of memory dies 620 - 1 to 620 - u (u is a natural number greater than 2) stacked on one or more buffer dies 610 and transmitting data through a plurality of through silicon via (TSV) lines.

[0171] Each of the memory dies 620-1 to 620u may include a cell core 622 and an ECC circuit 624, and the cell core 622 may include a memory cell array including a plurality of sub-array blocks arranged along a first direction and a second direction. The ECC circuit 624 may be referred to as an error correction circuit and may be implemented as Figure 11 Therefore, the ECC circuit 624 can correct single-bit errors and double-bit errors by applying different syndromes to the single-bit errors and double-bit errors using one parity check matrix based on ECC, thereby improving error correction efficiency.

[0172] The buffer die 610 may include a path ECC circuit 612 that, when a transmission error is detected in transmission data received through the TSV line, uses the transmission parity bits to correct the transmission error and generate error-corrected data. The path ECC circuit 612 may be referred to as a path error correction circuit.

[0173] The semiconductor memory device 600 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals through TSV lines, which may also be referred to as through electrodes.

[0174] Transmission errors that occur in transmitted data may be caused by noise that occurs at the TSV lines. Because data failures caused by noise that occurs at the TSV lines can be distinguished from data failures caused by erroneous operation of the memory die, they can be considered soft data failures (or soft errors). Soft data failures may be caused by transmission failures along the transmission path and can be detected and corrected through ECC operations.

[0175] Through the above description, the data TSV line group 632 formed at one memory die 620 - u may include 128 TSV lines L1 to Lu, and the parity TSV line group 634 may include TSV lines L10 to Lv.

[0176] The TSV lines L1 to Lu of the data TSV line group 632 and the parity TSV lines L10 to Lv of the parity TSV line group 634 may be connected to micro bumps MCB correspondingly formed between the memory dies 620 - 1 to 620 - u.

[0177] Each of the memory dies 620 - 1 to 620 - u may include a DRAM cell, each of which includes at least one access transistor and one storage capacitor.

[0178] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a memory controller through a data bus B10. The buffer chip 610 may be connected to the memory controller through the data bus B10.

[0179] The path ECC circuit 612 may determine whether a transmission error occurs in transmission data received through the data TSV line group 632 based on the transmission parity bits received through the parity TSV line group 634 .

[0180] When a transmission error is detected, the path ECC circuit 612 may correct the transmission error on the transmission data using the transmission parity bit. When the transmission error is uncorrectable, the path ECC circuit 612 may output information indicating that an uncorrectable data error has occurred.

[0181] exist Figure 22 In the context of the above embodiments, it is possible to Figure 5 The data I / O buffer 295 shown includes a buffer die 610 and a group die 620. The error correction circuit 400 may be configured to generate transmission parity data based on transmission data to be transmitted to the buffer die 610. As described above, the buffer die 610 may include a path ECC circuit 612. When a transmission error is detected in the transmission data received through the TSV line, the path ECC circuit 612 corrects the transmission error using the transmission parity bit and generates error-corrected data.

[0182] Figure 23 According to some example embodiments, Figure 22 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0183] Figure 23 A 3D chip structure 700 is shown where the host and HBM are directly connected without an interposer.

[0184] Reference Figure 23 , a host die 710 such as a system on chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU) can be placed on a printed circuit board (PCB) 720 using flip chip bumps FB. Memory dies D11 to D14 can be stacked on the host die 710 to implement an HBM structure as Figure 22 The memory die in the group of die 620. Figure 23 In, omitted Figure 22 However, the buffer die 610 or the logic die may be provided between the memory die D11 and the host die 710.

[0185] In order to implement the HBM structure as a memory die in the group die 620, TSV lines can be formed at the memory dies D11 and D14. The TSV lines can be electrically connected to the microbumps MCB placed between the memory dies. In addition, each of the memory dies D11 to D14 may include a Figure 11 The error correction circuit 400 is an error correction circuit.

[0186] Figure 24 is a diagram illustrating a semiconductor package including a stacked memory device according to some example embodiments.

[0187] Reference Figure 24 , the semiconductor package 900 may include one or more stacked memory devices 910 and a GPU (Graphics Processing Unit) 920 , and the GPU 920 includes a memory controller (CONT) 925 .

[0188] The stacked memory device 910 and the GPU 920 may be mounted on an interposer 930, and the interposer on which the stacked memory device 910 and the GPU 920 are mounted may be mounted on a package substrate 940. The memory controller 925 may be configured as Figure 1 The storage controller 100 in FIG.

[0189] Each stacked memory device 910 can be implemented in various forms and can be a high-bandwidth memory (HBM) memory device stacked with multiple layers. Therefore, each stacked memory device 910 can include a buffer die and multiple memory dies, and each of the multiple memory dies can include a memory cell array and an error correction circuit.

[0190] A plurality of stacked memory devices 910 may be mounted on the interposer 930, and the GPU 920 may communicate with the plurality of stacked memory devices 910. For example, the stacked memory device 910 and the GPU 920 may each include a physical area, and communication may be performed between the stacked memory device 910 and the GPU 920 through the physical area.

[0191] As described above, according to example embodiments, an error correction circuit and a semiconductor memory device including the same can correct single-bit errors and double-bit errors by applying different syndromes to the single-bit errors and double-bit errors using an ECC-based parity check matrix, and thus can improve error correction efficiency.

[0192] Example embodiments of the present disclosure may be applied to semiconductor memory devices and memory systems employing the ECC described herein.

[0193] While the present disclosure has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. An error correction circuit for a semiconductor memory device, comprising: an error correction code encoder configured to generate parity data based on main data using an error correction code represented by a generator matrix, and configured to store a codeword including the main data and the parity data in a target page of a memory cell array; as well as An error correction code decoder, the error correction code decoder being configured to: reading the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device to generate different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the error correction code; and applying the different syndromes to the main data in the read codeword to correct a single bit error when a single bit error exists in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page, The error correction code decoder is further configured to generate a first sub-check matrix and a second sub-check matrix, and apply one of the first sub-check matrix and the second sub-check matrix to the read codeword based on the least significant bit of the row address in the address, and generate at least one syndrome to correct the two bit errors.

2. The error correction circuit according to claim 1, wherein The error correction code decoder is further configured to, in response to a least significant bit of a row address in the address being at a low level, generate a first syndrome by applying the parity check matrix to the read codeword, and generate a second syndrome by applying the first sub-check matrix to the read codeword, the first sub-check matrix being generated based on the parity check matrix.

3. The error correction circuit according to claim 2, wherein: The error correction code decoder is further configured to: correcting the single bit error in the primary data based on the first syndrome; and The two bit errors in the main data are corrected based on the second syndrome.

4. The error correction circuit according to claim 1, wherein The error correction code decoder is further configured to: In response to a least significant bit of a row address in the address being at a high level, generating a first syndrome by applying the parity check matrix to the read codeword, and generating a second syndrome by applying the first sub-check matrix to the read codeword, the first sub-check matrix being generated based on the parity check matrix, and In response to the least significant bit of the row address being an even number, applying the second sub-check matrix to the read codeword to generate a third syndrome, the second sub-check matrix being different from the first sub-check matrix.

5. The error correction circuit according to claim 4, wherein: The error correction code decoder is further configured to: correcting the single bit error in the primary data based on the first syndrome; and The two bit errors in the main data are corrected based on the third syndrome.

6. The error correction circuit according to claim 1, wherein The main data includes a plurality of data bits divided into a plurality of sub-data units; and The parity check matrix includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub-data units and the parity check data.

7. The error correction circuit according to claim 6, wherein: The error correction code decoder is further configured to: generating the first sub-check matrix by performing an exclusive OR operation on a 2i-1th column vector and a 2ith column vector among the plurality of column vectors, where i is one of 1 to k, and k is the number of data bits in each of the sub-data unit and the parity data; and In response to a least significant bit of a row address in the address being at a low level, the first sub-check matrix is ​​applied to the main data in the read codeword.

8. The error correction circuit according to claim 6, wherein: The error correction code decoder is further configured to: generating the second sub-check matrix by performing an exclusive OR operation on a 2i-th column vector and a 2i+1-th column vector among the plurality of column vectors, where i is one of 1 to k, and k is the number of data bits in each of the sub-data unit and the parity data; and In response to a least significant bit of a row address in the address being at a high level, applying the second sub-check matrix to the main data in the read codeword.

9. The error correction circuit according to claim 1, wherein: The error correction code decoder comprises: a syndrome generation circuit configured to generate a first syndrome, a second syndrome, and a third syndrome based on the parity check matrix and the read codeword, and to generate a selection signal based on the first syndrome, a least significant bit of a row address in the address, and one of the second syndrome and the third syndrome; a first corrector configured to correct the single bit error in the primary data based on the first syndrome to provide first output data; a second corrector configured to correct the two bit errors in the main data based on the second syndrome in response to the least significant bit of the row address being at a low level, so as to provide second output data; a third corrector configured to correct the two bit errors in the main data based on the third syndrome in response to the least significant bit of the row address being at a high level, so as to provide third output data; and A selection circuit is configured to select one of the main data, the first output data, the second output data, and the third output data in response to the selection signal and the least significant bit of the row address to provide corrected main data or the main data.

10. The error correction circuit according to claim 9, wherein: The syndrome generation circuit comprises: a first syndrome generator configured to generate the first syndrome by applying the parity check matrix to the read codeword; a sub-check matrix generator configured to generate the first sub-check matrix based on a first portion of the parity check matrix, and configured to generate the second sub-check matrix based on a second portion of the parity check matrix; a second syndrome generator configured to generate the second syndrome by applying the first sub-check matrix to the read codeword; a third syndrome generator configured to generate the third syndrome by applying the second sub-check matrix to the read codeword; a multiplexer configured to select one of the second syndrome and the third syndrome based on the least significant bit of the row address; and A selection signal generator is configured to generate the selection signal based on the first syndrome and an output of the multiplexer.

11. A semiconductor memory device comprising: a memory cell array comprising a plurality of volatile memory cells connected to word lines and bit lines; an error correction circuit configured to generate parity data based on main data using an error correction code represented by a generator matrix, and store a codeword including the main data and the parity data in a target page of the memory cell array; Reading the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device to generate different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the error correction code; and applying the different syndromes to the main data in the read codeword to correct a single bit error when a single bit error exists in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page; as well as a control logic circuit configured to control the error correction circuit based on a command from outside the semiconductor memory device and the address, The error correction circuit is further configured to generate a first sub-check matrix and a second sub-check matrix, and apply one of the first sub-check matrix and the second sub-check matrix to the read codeword based on the least significant bit of the row address in the address, and generate at least one syndrome to correct the two bit errors.

12. The semiconductor memory device according to claim 11, wherein The error correction circuit includes an error correction code decoder configured to apply the different syndromes to the single bit error and the two bit errors based on the read codeword; The error correction code decoder is further configured to, in response to a least significant bit of a row address in the address being at a low level, generate a first syndrome by applying the parity check matrix to the read codeword, and generate a second syndrome by applying the first sub-check matrix to the read codeword, wherein the first sub-check matrix is ​​generated based on the parity check matrix; and The error correction code decoder is further configured to, in response to the least significant bit of the row address being at a high level, generate a third syndrome by applying the second sub-check matrix to the read codeword, wherein the second sub-check matrix is ​​generated based on the parity check matrix, and the second sub-check matrix is ​​different from the first sub-check matrix.

13. The semiconductor memory device according to claim 12, wherein The error correction code decoder is further configured to: correcting the single bit error in the primary data based on the first syndrome; and The two bit errors in the main data are corrected by using one of the second syndrome and the third syndrome based on the least significant bit of the row address.

14. The semiconductor memory device according to claim 11, wherein The memory cell array includes a plurality of sub-array blocks arranged along a first direction and a second direction crossing the first direction; The main data includes a plurality of data bits divided into a plurality of sub-data units; The semiconductor memory device further includes an input / output gating circuit connected between the memory cell array and the error correction circuit; and The control logic circuit is further configured to control the input / output gating circuit so that the sub-data unit and the parity data are stored in a target sub-array block among the sub-array blocks.

15. The semiconductor memory device according to claim 14, wherein The parity check matrix includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub-data units and the parity check data; The error correction circuit includes an error correction code decoder configured to apply the different syndromes to the single bit error and the two bit errors based on the read codeword; The error correction code decoder is further configured to: generating the first sub-check matrix by performing an exclusive OR operation on a 2i-1th column vector and a 2ith column vector among the plurality of column vectors, where i is one of 1 to k, and k is the number of data bits in each of the sub-data unit and the parity data; and In response to a least significant bit of a row address in the address being at a low level, the first sub-check matrix is ​​applied to the main data in the read codeword.

16. The semiconductor memory device according to claim 14, wherein The parity check matrix includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub-data units and the parity check data; The error correction circuit includes an error correction code decoder configured to apply the different syndromes to the single bit error and the two bit errors based on the read codeword; The error correction code decoder is further configured to: generating the second sub-check matrix by performing an exclusive OR operation on a 2i-th column vector and a 2i+1-th column vector among the plurality of column vectors, where i is one of 1 to k and k is the number of data bits in each of the sub-data unit and the parity data; and In response to a least significant bit of a row address in the address being at a high level, applying the second sub-check matrix to the main data in the read codeword.

17. The semiconductor memory device according to claim 11, in, The error correction circuit includes an error correction code decoder configured to apply the different syndromes to the single bit error and the two bit errors based on the read codeword; Wherein, the error correction code decoder comprises: a syndrome generation circuit configured to generate a first syndrome, a second syndrome, and a third syndrome based on the parity check matrix and the read codeword, and to generate a selection signal based on the first syndrome, a least significant bit of a row address in the address, and one of the second syndrome and the third syndrome; a first corrector configured to correct the single bit error in the primary data based on the first syndrome to provide first output data; a second corrector configured to correct the two bit errors in the main data based on the second syndrome in response to the least significant bit of the row address being at a low level, so as to provide second output data; a third corrector configured to correct the two bit errors in the main data based on the third syndrome in response to the least significant bit of the row address being at a high level, so as to provide third output data; and A selection circuit is configured to select one of the main data, the first output data, the second output data, and the third output data in response to the selection signal and the least significant bit of the row address to provide corrected main data or the main data.

18. The semiconductor memory device according to claim 11, comprising: at least one buffer die; as well as a plurality of memory dies stacked on the at least one buffer die and transmitting data through a plurality of silicon through routes, and At least one memory die among the plurality of memory dies comprises the memory cell array and the error correction circuit.

19. The semiconductor memory device according to claim 18, wherein The error correction circuit is configured to generate transmit parity data based on transmit data to be transmitted to the at least one buffer die; and The at least one buffer die includes a path error correction circuit configured to correct a transmission error included in data transmitted through the through-silicon route based on the transmission parity data.

20. A semiconductor memory device comprising: a memory cell array comprising a plurality of volatile memory cells connected to word lines and bit lines; an error correction circuit configured to generate parity data based on main data using an error correction code represented by a generator matrix, and store a codeword including the main data and the parity data in a target page of the memory cell array; Reading the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device to generate different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the error correction code; and applying the different syndromes to the main data in the read codeword to correct a single bit error when a single bit error exists in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page; as well as a control logic circuit configured to control the error correction circuit based on a command from outside the semiconductor memory device and the address, The error correction circuit includes an error correction code decoder configured to generate the different syndromes based on the parity check matrix, and The error correction code decoder is configured to generate a first sub-check matrix and a second sub-check matrix, and is configured to apply one of the first sub-check matrix and the second sub-check matrix to the read codeword based on the least significant bit of the row address in the address, and generate at least one syndrome to correct the two bit errors.

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