Connection structure and forming method thereof

Abstract

The present disclosure relates to a connection structure and a method for forming the same. A connection structure includes: a first dielectric layer disposed on a substrate and a conductive feature; a doped dielectric layer disposed on the first dielectric layer; a first metal portion disposed in the first dielectric layer and in contact with the conductive feature; and a doped metal portion disposed on the first metal portion. The first metal portion and the doped metal portion include the same noble metal material. The doped dielectric layer and the doped metal portion include the same dopant.

Description

Technical Field

[0001] The present disclosure relates to connection structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have enabled successive generations of ICs to continue to improve. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. Thus, there exists a challenge to form reliable semiconductor devices having increasingly smaller dimensions. Summary of the invention

[0005] According to one aspect of the present disclosure, a connection structure is provided, comprising: a first dielectric layer disposed on a conductive feature; a doped dielectric layer disposed on the first dielectric layer; and a metal feature disposed in the first dielectric layer and the doped dielectric layer, wherein the doped dielectric layer applies compressive stress to the metal feature, wherein the metal feature contacts the conductive feature, the doped dielectric layer and the first dielectric layer, wherein a top surface of the metal feature is aligned with a top surface of the doped dielectric layer, wherein the first dielectric layer comprises a first dielectric material, and at least a portion of the doped dielectric layer comprises a second dielectric material different from the first dielectric material.

[0006] According to another aspect of the present disclosure, a connection structure is provided, comprising: a first dielectric layer disposed above a conductive feature; a doped dielectric layer disposed above the first dielectric layer; a metal portion disposed in the first dielectric layer and the doped dielectric layer; and a doped metal portion disposed above the metal portion, wherein the doped dielectric layer applies compressive stress to the doped metal portion, a top surface of the doped metal portion is aligned with a top surface of the doped dielectric layer, a bottom surface of the doped metal portion is higher than a bottom surface of the doped dielectric layer, the first dielectric layer comprises a first dielectric material, and at least a portion of the doped dielectric layer comprises a second dielectric material different from the first dielectric material.

[0007] According to another aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a dielectric structure over a conductive feature, wherein the dielectric structure comprises an opening exposing a portion of the conductive feature; filling the opening with a metal layer; forming a doped metal portion in the metal layer, and forming a doped dielectric layer in the dielectric structure, wherein the doped dielectric layer comprises a compressive stress layer for the doped metal portion, a top surface of the doped metal portion is separated from a top surface of the metal layer, wherein a top surface of the doped dielectric layer is separated from a top surface of the dielectric structure; and removing at least a portion of the metal layer and at least a portion of the dielectric structure to form a connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 It is a partial cross-sectional view of a semiconductor structure.

[0010] Figure 2 is a flow chart of a method for forming a connection structure according to various aspects of the present disclosure.

[0011] FIG. 3A to FIG. 3F is a schematic diagram illustrating various stages in a method for forming a connection structure according to aspects of one or more embodiments of the present disclosure.

[0012] Figure 4 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0013] Figure 5 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0014] FIG. 6A to FIG. 6D is a schematic diagram illustrating various stages in a method for forming a connection structure according to aspects of one or more embodiments of the present disclosure.

[0015] Figure 7 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0016] Figure 8 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0017] Fig. 9is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0018] Fig.10 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0019] Fig.11 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0020] Fig.12 is a flow chart of a method for forming a connection structure according to various aspects of the present disclosure.

[0021] FIG. 13A to FIG. 13E is a schematic diagram illustrating various stages in a method for forming a connection structure according to aspects of one or more embodiments of the present disclosure.

[0022] Fig.14 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0023] Fig.15 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0024] Fig.16 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0025] Fig.17 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure.

[0026] Fig.18 is a schematic diagram showing a connection structure of aspects according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for realizing different features of the subject matter provided. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0029] As used herein, terms such as "first", "second", and "third" describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. When used herein, terms such as "first", "second", and "third" do not imply a sequence or order unless the context clearly indicates.

[0030] The IC manufacturing process flow can generally be divided into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). FEOL generally includes industries related to the manufacture of IC devices (e.g., transistors). For example, the FEOL process may include the formation of the following items: an isolation structure for isolating the IC device, a gate structure forming a transistor, and a source and drain structure (also referred to as a source / drain structure). MEOL generally includes processes related to the manufacture of a connection structure (also referred to as a contact or plug) connected to a conductive feature (or conductive region) of the IC device. For example, the MEOL process may include the formation of a connection structure connected to a gate structure, and a connection structure connected to a source / drain structure. BEOL generally includes processes related to the manufacture of a multi-layer interconnect (MLI) structure that electrically connects the IC device and the connection structure manufactured by the FEOL and MEOL. Therefore, the operation of the IC device can be achieved. As described above, the shrinking process increases the complexity of processing and manufacturing ICs. For example, in some comparative methods, ruthenium (Ru) having low resistivity is used to form a connection structure formed by MEOL in order to reduce plug contact resistance, but as IC feature sizes continue to shrink and connection structures become more compact, Ru-containing connection structures have brought challenges in terms of yield and cost.

[0031] Embodiments such as those described herein provide a connection structure and a method for forming a connection structure to mitigate bottom metal loss problems that may occur due to diffusion of metal from a lower metal layer during annealing. In some embodiments, ion implantation is performed after depositing the metal layer to form a barrier layer within the conductive material. In some embodiments, the ions implanted into the conductive material are bonded to the conductive material to form a diffusion barrier layer so that metal diffusion can be hindered or reduced by the diffusion barrier layer. Therefore, the bottom metal loss problem caused by metal diffusion can be mitigated or reduced.

[0032] Figure 1 is a partial cross-sectional view of part or all of a semiconductor structure 100 according to various aspects of some embodiments. The semiconductor structure 100 may be included in a microprocessor, a memory, and / or another IC device. In some embodiments, the semiconductor structure 100 is part of an IC chip, a system on a chip (SoC), or a part of a system on a chip (SoC), which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The transistors may be planar transistors or multi-gate transistors, such as fin FETs (FinFETs). For clarity, the schematic diagram has been simplified. Figure 1 , to better illustrate features of some embodiments. Additional features may be added to the semiconductor structure 100 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor structure 100 .

[0033] In some embodiments, the semiconductor structure 100 includes a substrate (e.g., a wafer) 102. In some embodiments, the substrate 102 includes silicon. Alternatively or additionally, the substrate 102 includes another elemental semiconductor, for example, germanium; a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); an alloy semiconductor (e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof). In some implementations, the substrate 102 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some implementations, the substrate 102 is a semiconductor-on-insulator substrate, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. The substrate 102 may include various doped regions (not shown) configured according to the design requirements of the device, such as a p-type doped region, an n-type doped region, or a combination thereof. The p-type doped region (e.g., a p-type well) includes a p-type dopant, such as boron, indium, another p-type dopant, or a combination thereof. The n-type doped region (e.g., an n-type well) includes an n-type dopant, such as phosphorus, arsenic, another n-type dopant, or a combination thereof. In some implementations, the substrate 102 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. For example, various doped regions may be formed directly on and / or in the substrate 102, thereby providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. An ion implantation process, a diffusion process, and / or another suitable doping process may be performed to form the various doped regions.

[0034] Isolators (not shown) may be formed on and / or in the substrate 102 to electrically isolate various regions of the semiconductor structure 100, such as various device regions. For example, the isolation members may define active device regions and / or passive device regions and electrically isolate them from each other. The isolation members may include silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material, or a combination thereof. The isolation features may include different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure.

[0035] Various gate structures (e.g., gate structures 110, 112, and 114) may be disposed over substrate 102. In some embodiments, one or more gate structures 110, 112, and 114 may be between a source region and a drain region, wherein a channel region is defined between the source region and the drain region. In some embodiments, gate structures 110, 112, and 114 are formed over the fin structure. In some embodiments, gate structures 110, 112, and 114 include a metal gate structure. In some embodiments, the metal gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer may be disposed over substrate 102, and the gate electrode is disposed on the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-k dielectric material, another suitable dielectric material, or a combination thereof. A high-k dielectric material generally refers to a dielectric material having a high dielectric constant, such as a dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, another suitable component, or a combination thereof. In some embodiments, the gate dielectric layer includes a multilayer structure, such as an interfacial layer (IL) including, for example, silicon oxide, and a high-k dielectric layer including, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, another suitable high-k dielectric material, or a combination thereof.

[0036] The gate electrode includes a conductive material. In some implementations, the gate electrode includes multiple layers, such as one or more work function metal layers and a gap filling metal layer. The work function metal layer includes a conductive material adjusted to have a desired work function (e.g., n-type work function or p-type work function), such as an n-type work function material and / or a p-type work function material. P-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, and combinations thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, and combinations thereof. The gap filling metal layer may include a suitable conductive material, such as Al, W, and / or Cu.

[0037] The gate structures 110, 112, and 114 may further include a spacer 116 disposed adjacent to the gate structures 110, 112, and 114 (e.g., along the sidewalls of the gate structures 110, 112, and 114). The spacer 116 may be formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some embodiments, the spacer 116 may include a multilayer structure, for example, a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, biasing spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the gate structures 110, 112, and 114.

[0038] Implantation, diffusion, and / or annealing processes may be performed to form lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in the substrate 102 before and / or after forming the spacers 116 .

[0039] In some embodiments, the source / drain region S / D of the device may include an epitaxial structure 118. For example, a semiconductor material is epitaxially grown on the substrate 102, thereby forming an epitaxial source / drain structure 118 above the source region and the drain region of the substrate 102. Therefore, the gate structure 110, the epitaxial source / drain structure 118, and the channel region defined between the epitaxial source / drain structure 118 form a device such as a transistor. In some embodiments, the epitaxial source / drain structure 180 may surround the source / drain region of the fin structure. In some embodiments, the epitaxial source / drain structure 180 may replace a portion of the fin structure. The epitaxial source / drain structure 180 is doped with an n-type dopant and / or a p-type dopant. In some embodiments, where the transistor is configured as an n-type device (e.g., having an n-channel), the epitaxial source / drain structure 180 may include a silicon-containing epitaxial layer or a silicon-carbon-containing epitaxial layer doped with phosphorus, another n-type dopant, or a combination thereof (e.g., forming a Si:P epitaxial layer or a Si:C:P epitaxial layer). In alternative embodiments, where the transistor is configured as a p-type device (e.g., having a p-channel), the epitaxial source / drain structure 180 may include an epitaxial layer containing silicon and germanium doped with boron, another p-type dopant, or a combination thereof (e.g., forming a Si:Ge:B epitaxial layer). In some embodiments, the epitaxial source / drain structure 180 includes materials and / or dopants that achieve a desired tensile stress and / or compressive stress in the channel region.

[0040] like Figure 1As shown, a plurality of dielectric layers 120 and 122 may be disposed on substrate 102. Dielectric layers 120 and 122 may each include one or more layers of dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, another suitable dielectric material, or a combination thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, Black (Applied Materials, Santa Clara, CA), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, SILK (The Dow Chemical Company, Midland, MI), polyimide, other low-k dielectric materials, and combinations thereof. Figure 1 As shown, dielectric layer 120 may cover source / drain regions S / D, spacers 116, and gate structures 110, 112, and 114. In some embodiments, dielectric layer 120 may be referred to as an interlayer dielectric (ILD) layer. In some embodiments, dielectric layer 122 may be referred to as an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer.

[0041] In some embodiments, Figure 1 As shown, one or more connection structures 130, 132 may be formed over the source / drain regions S / D and the gate structure 110. The connection structure 130 is disposed on the gate structure 110 so that the gate structure 110 may be connected to a back-end-of-line (BEOL) interconnect (not shown) through the connection structure 130. The connection structure 132 may be referred to as a metal-to-drain (MD) contact, which generally refers to a contact to the source / drain region S / D. Figure 1 As shown, the connection structures 132 can be respectively disposed on the epitaxial source / drain structures 118, so that the epitaxial source / drain structures 118 can be connected to the BEOL interconnection through the connection structures 132. Therefore, the FEOL structure can be electrically connected to the BEOL interconnection through the connection structures 130, 132, and the connection structures 130, 132 can also be referred to as MEOL interconnection structures.

[0042] Still reference Figure 1, connection structures 140, 142 may be formed on connection structures 130, 132, and conductive features 150 may be formed on connection structures 140, 142. Connection structures 140, 142 electrically connect connection structures 130, 132 to conductive features 150. In some embodiments, in the BEOL interconnect, connection structures 140, 142 are referred to as vias (V), and conductive features 150 are referred to as metal lines (M). In some embodiments, the BEOL interconnect includes a dielectric stack (including dielectric layers 120 and 122), and vias and metal lines are formed in the dielectric stack.

[0043] Figure 2 1 is a flow chart representing a method for forming a connection structure 10 according to various aspects of the present disclosure. In some embodiments, the method for forming the connection structure 10 includes a number of operations (11, 12, 13, and 14). The method for forming the connection structure 10 will be further described according to one or more embodiments. It should be noted that the operations of the method for forming the connection structure 10 can be rearranged or otherwise modified within the scope of various aspects. It should also be noted that additional processes can be provided before, during, and after the method 10, and only some other processes are briefly described herein. In some embodiments, the method for forming the connection structure 10 can be used to form the connection structures 130, 132 in a MEOL structure. In other embodiments, the method for forming the connection structure 10 can be used to form the connection structures 140, 142 in a BEOL interconnect.

[0044] FIG. 3A to FIG. 3F 1 is a schematic diagram showing various stages in a method for forming a connection structure 10 according to aspects of one or more embodiments of the present disclosure. In some embodiments, a substrate 200 may be received. The substrate 200 may be Figure 1 The substrate 102 is shown, but the present disclosure is not limited thereto. In some embodiments, the substrate 200 may include a semiconductor device, such as Figure 1 The transistor shown in FIG. 1 is a transistor shown in FIG. 2 , but the present disclosure is not limited thereto. Figure 3A As shown, substrate 200 may include conductive features 202 disposed therein. In some embodiments, conductive features 202 may be similar to Figure 1 1 or FEOL features of the metal gate 110 or source / drain regions S / D depicted in FIG. In some embodiments, the conductive features 202 may be MEOL features, such as those similar to Figure 1 130, 132. In addition, substrate 200 may include one or more dielectric layers. For example, in some embodiments, conductive feature 202 may be a BEOL feature, such as formed on Figure 1 1. Cobalt-containing lines of metal line (M) features 150 in the dielectric layer depicted in FIG.

[0045] In operation 11, a dielectric structure 210 is formed over the substrate 200 and the conductive features 202. In some embodiments, the dielectric structure 210 may include a single layer. In some embodiments, the dielectric structure 210 may include a multi-layer structure. For example, Figure 3A As shown, the dielectric structure 210 may include at least a first dielectric layer 212 and a second dielectric layer 214 sequentially stacked on the substrate 200 and the conductive feature 202. The first dielectric layer 212 and the second dielectric layer 214 may include different dielectric materials. For example, the first dielectric layer 212 may be a contact etch stop layer (CESL), and the second dielectric layer may be an ILD layer or an IMD layer. In some embodiments, the CESL may include silicon nitride, silicon oxynitride, etc. The ILD layer or the IMD layer may include materials as described above.

[0046] Still reference Figure 3A , in operation 11, an opening 215 may be formed in the dielectric structure 210. In some embodiments, the opening 215 passes through the dielectric structure 210 from the top surface 210t of the dielectric structure 210 to the bottom of the dielectric structure 210. Thus, a portion of the conductive feature 202 is exposed through the opening 215. The opening 215 may be formed using a photolithography process using a masking technique and an anisotropic etching operation (e.g., plasma etching or reactive ion etching), but the present disclosure is not limited thereto.

[0047] refer to Figure 3B In operation 12, a metal layer 220 such as a noble metal layer may be formed to fill the opening 215, but the present disclosure is not limited thereto. The noble metal layer may include rhenium (Re), rhodium (Rh), and ruthenium (Ru). The metal layer 220 extends from the top surface 210t of the dielectric structure 210 to the bottom of the dielectric structure 210. The metal layer 220 passes through the second dielectric layer 214 and the first dielectric layer 212 and contacts the exposed portion of the conductive feature 202. In addition, the metal layer 220 covers the top surface 210t of the dielectric structure 210.

[0048] It should be noted that in some embodiments, metal layer 220 may be formed without a liner, barrier layer, seed layer, or any intermediate layer. Thus, in such embodiments, metal layer 220 may contact dielectric structure 210, but the disclosure is not limited thereto.

[0049] refer to Figure 3CIn operation 13, a doped metal portion 222 is formed in the metal layer 220, and a doped dielectric layer 216 is formed in the dielectric structure 210. In some embodiments, the doped metal portion 222 and the doped dielectric layer 216 include the same dopant, and the dopant may include germanium (Ge), silicon (Si), argon (Ar), xenon (Xe), or nitrogen (N), but the present disclosure is not limited thereto. The formation of the doped metal portion 222 and the doped dielectric layer 216 includes ion implantation. In some embodiments, the dose of the ion implantation may be about 1E13 cm -2 to about 1E16cm -2 The ion implantation angle may be between about 0 degrees and about 60 degrees, and the ion implantation temperature may be between about -100° C. and about 500° C. In some embodiments, the concentration of the dopant in the doped dielectric layer 216 may be between about 1E19 atoms / cm 3 to about 1E12 atoms / cm 3 In some embodiments, the concentration of the dopant in the doped metal portion 222 may be between about 1E19 atoms / cm 3 to about 1E12 atoms / cm 3 However, the present disclosure is not limited thereto.

[0050] In some embodiments, the top surface of the doped metal portion 222 is separated from the top surface of the metal layer 220, and the top surface of the doped dielectric layer 216 is separated from the top surface of the dielectric structure 210 (e.g., the top surface of the second dielectric layer 214). In some embodiments, by adjusting the implantation energy of the ion implantation, the doped dielectric layer 216 can be completely formed within the second dielectric layer 214. In some embodiments, the bottom surface of the doped dielectric layer 216 is separated from the substrate 200 by a portion of the second dielectric layer 214 and the first dielectric layer 212. In addition, the bottom surface of the doped dielectric layer 216 is in contact with the second dielectric layer 214. The bottom surface of the doped metal portion 222 is separated from the conductive feature 202, so that the resistance of the conductive feature 202 will not be affected by the dopant. In addition, the bottom surface of the doped metal portion 222 and the bottom surface of the doped dielectric layer 216 can be aligned with each other, but the present disclosure is not limited thereto. The distribution of the dopant in the doped metal portion 222 and in the doped dielectric layer 216 is as shown in FIG. Figure 3C . In some embodiments, the peak of the distribution curve may be near the middle of the doped metal portion 222 and the middle of the doped dielectric layer 216, but the present disclosure is not limited thereto. In some embodiments, the thickness of the doped metal portion 222 is less than the thickness of the metal layer 220, and the thickness of the doped dielectric layer 216 is less than the thickness of the dielectric structure 210. In some embodiments, the thickness of the doped dielectric layer 216 is less than the thickness of the second dielectric layer 214.

[0051] refer to Figure 3D In some embodiments, an annealing in a range from about 100° C. to about 500° C. is performed to improve gap filling results, reduce plug resistance, and improve interface quality. The pressure for annealing may be in a range from about 100 mTorr to about 760 mTorr, but the present disclosure is not limited thereto. The process duration of the annealing may be in a range from about 10 minutes to about 120 minutes, but the present disclosure is not limited thereto. In addition, gases such as nitrogen (N2), hydrogen (H2), helium (He), and / or argon (Ar) may be used in the annealing. During the annealing, metal diffusion may occur, and metal ions may move from the conductive feature 202 to the upper portion of the metal layer 220 along the interface between the dielectric structure 210 and the metal layer 220. It should be noted that because the volume of the dopant (e.g., Ge) is larger than the volume of the dielectric material of the doped dielectric layer 216, compressive stress is generated from the doped dielectric layer 216 due to the presence of a larger volume of the dopant, as shown by the arrows along the opposite sidewalls of the doped metal portion 222. In some embodiments, doped dielectric layer 216 may be referred to as a compressive stress layer. In addition, compressive stress helps prevent or reduce metal diffusion along the interface between dielectric structure 210 and metal layer 220, such as Figure 3D As shown by the “X” in the figure and the upward arrow. Therefore, the metal loss problem can be alleviated or reduced.

[0052] refer to Figure 3E In operation 14, a portion of the metal layer 220 is removed to expose and / or recess the top surface 210t of the dielectric structure 210 and form a connection structure 240. In some embodiments, in operation 14, a portion of the doped metal portion 222 and a portion of the doped dielectric layer 216 may be removed. In some embodiments, the removal of the portion of the metal layer 220, the portion of the doped metal portion 222, and the portion of the doped dielectric layer 216 may be performed using a chemical mechanical polishing (CMP) operation.

[0053] refer to Figure 3F In some embodiments, another dielectric structure 250 may be formed over the dielectric structure 210 and the connection structure 240. Another conductive feature 260 may be formed in the dielectric structure 250. The conductive feature 260 may be coupled to the connection structure 240. In some embodiments, the conductive feature 260 may be referred to as Figure 1 In some embodiments, the conductive feature 260 may be referred to as Figure 1 The metal wire 150 in.

[0054] Thus, a connection structure 240 is obtained. The connection structure 240 includes: a first dielectric layer 212 disposed on the conductive feature 202; a second dielectric layer 214 disposed on the first dielectric layer 212; a doped dielectric layer 216 disposed on the first dielectric layer 212 and the second dielectric layer 214; a metal layer 220 used as a metal portion disposed in the first dielectric layer 212 and the second dielectric layer 214; and a doped metal portion 222 located on the metal portion 220. The second dielectric layer 214 is located between the doped dielectric layer 216 and the first dielectric layer 212. Figure 3E As shown, metal portion 220 contacts conductive feature 202, first dielectric layer 212, and second dielectric layer 214, while doped metal portion 222 contacts doped dielectric layer 216. A top surface of doped metal portion 222 is aligned with a top surface of doped dielectric layer 216.

[0055] Furthermore, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222. In some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed below the top surface of the doped dielectric layer 216, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed at the top surface of the doped dielectric layer 216.

[0056] In such an embodiment, metal portion 220 and doped metal portion 222 include the same metal material, and doped dielectric layer 216 and second dielectric layer 214 include the same dielectric material. Additionally, doped metal portion 222 and doped dielectric layer 216 include the same dopant.

[0057] Figure 4 It is a schematic diagram showing the connection structure of various aspects according to different embodiments of the present disclosure. It should be understood that Figure 4 and Figure 3F Like elements in the present invention are represented by like reference numerals, and repeated details may be omitted for the sake of brevity.

[0058] It should be noted that the depth or position of forming the doped metal portion 222 and the doped dielectric layer 216 can be determined by the implantation energy of the ion implantation. In some embodiments, by adjusting the implantation energy, the bottom surface of the doped dielectric layer 216 can be formed to contact the first dielectric layer 212, such as Figure 4In addition, the bottom surface of the doped dielectric layer 216 and the bottom surface of the doped metal portion 222 may be aligned, but the present disclosure is not limited thereto.

[0059] Furthermore, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222. In some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed below the top surface of the doped dielectric layer 216, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed at the top surface of the doped dielectric layer 216.

[0060] refer to Figure 5 In some embodiments, by adjusting the injection energy, Figure 3F and Figure 4 The doped dielectric layer 216 and the doped metal portion 222 are formed deeper than the depth shown in FIG. For example, the doped dielectric layer 216 can be formed by implanting dopants into the first dielectric layer 212 and the second dielectric layer 214. Therefore, the doped dielectric layer 216 can include two portions. Figure 5 As shown, the doped dielectric layer 216 may include a first portion 216 - 1 including a first dielectric material that is the same as the dielectric material of the first dielectric layer 212 and a second portion 216 - 2 including a second dielectric material that is the same as the dielectric material of the second dielectric layer 214 .

[0061] In addition, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222. In some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed below the top surface of the second portion 216-2 of the doped dielectric layer 216, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed at the top surface of the second portion 216-2 of the doped dielectric layer 216.

[0062] FIG. 6A to FIG. 11 1 is a schematic diagram showing various stages in a method 10 for forming a connection structure according to various aspects of various embodiments of the present disclosure. It should be understood that FIG. 6A to FIG. 11 as well as FIG. 3A to FIG. 3F Like elements in the present invention are represented by like reference numerals, and repeated details may be omitted for the sake of brevity.

[0063] In some embodiments, a substrate 200 may be received. Fig. 6A As shown, substrate 200 may include conductive features 202 disposed therein. In operation 11, a dielectric structure 210 is formed over substrate 200 and conductive features 202, and an opening may be formed in dielectric structure 210. In operation 12, a metal layer 220 such as a noble metal layer may be formed to fill the opening. Fig. 6A As shown, the metal layer 220 extends from the top surface 210t of the dielectric structure 210 to the bottom of the dielectric structure 210. The metal layer 220 passes through the second dielectric layer 214 and the first dielectric layer 212 to contact the exposed portion of the conductive feature 202. In addition, the metal layer 220 covers the top surface 210t of the dielectric structure 210. As described above, in some embodiments, the metal layer 220 can be formed without a liner, a barrier layer, a seed layer, or any intermediate layer. Therefore, in such an embodiment, the metal layer 220 can be in contact with the dielectric structure 210, but the present disclosure is not limited thereto.

[0064] Still reference Fig. 6A , in operation 13, a doped metal portion 222 is formed in the metal layer 220, and a doped dielectric layer 216 is formed in the dielectric structure 210. In some embodiments, the formation of the doped metal portion 222 and the doped dielectric layer 216 includes ion implantation. The dopant, dose, angle, and temperature used in the ion implantation can be similar to the dopant, dose, angle, and temperature described above; therefore, the details are omitted for the sake of brevity. It should be noted that the depth of the location where the doped metal portion 222 and the doped dielectric layer 216 are formed can be determined by the implantation energy of the ion implantation. For example, by adjusting the implantation energy, the bottom surface of the doped dielectric layer 216 can be formed to contact the second dielectric layer 214 (such as FIG. 6A to FIG. 6D and Figure 7 ), contacting the top surface of the first dielectric layer 212 (as shown Figure 8 and Fig. 9 ), or below the top surface of the first dielectric layer 212 (as shown in Fig.10 and Fig.11 shown).

[0065] In some embodiments, since the density of dielectric materials is less than that of metal materials, the dopant in dielectric structure 214 can penetrate deeper than the dopant in metal layer 220. Therefore, the bottom surface of doped dielectric layer 216 can be lower than the bottom surface of doped metal portion 222, such as Fig. 6A , Figure 7 , Fig. 9 and Fig.11 For example, in some embodiments, the depth of the bottom surface of doped dielectric layer 216 may be about 40 nanometers lower than the top surface of doped dielectric layer 216. In some embodiments, the depth of the bottom surface of doped dielectric layer 216 may be about 40 nanometers to about 90 nanometers lower than the top surface of doped dielectric layer 216. In some embodiments, the depth of the bottom surface of doped metal portion 222 may be about 0 nanometers to about 40 nanometers lower than the top surface of doped metal portion 222.

[0066] refer to Figure 6B In some embodiments, annealing is performed to improve gap filling results, reduce plug resistance, and improve interface quality. During annealing, metal diffusion may occur, and metal ions may move from conductive feature 202 to the upper portion of metal layer 220 along the interface between dielectric structure 210 and metal layer 220. As described above, the dopant in doped dielectric layer 216 causes doped dielectric layer 216 to function as a compressive stress layer. Figure 6B As shown, the compressive stress from the doped dielectric layer 216 helps to prevent metal diffusion. Therefore, the metal loss problem can be alleviated or reduced.

[0067] refer to Figure 6C In operation 14, a portion of the metal layer 220 is removed to expose or recess the top surface 210t of the dielectric structure 210 and form a connection structure 240. In some embodiments, the doped metal portion 222 may be completely removed, but the present disclosure is not limited thereto. In some embodiments, a portion of the dielectric structure 210, such as a portion of the doped dielectric layer 216, may be removed in operation 14. In some embodiments, the removal of the portion of the metal layer 220, the doped metal portion 222, and the portion of the dielectric structure 210 may be performed using a CMP operation.

[0068] refer to Fig.6D In some embodiments, another dielectric structure 250 may be formed over the dielectric structure 210 and the connection structure 240. Another conductive feature 260 may be formed in the dielectric structure 250. The conductive feature 260 may be coupled to the connection structure 240. In some embodiments, the conductive feature 260 may be referred to as Figure 1 In some embodiments, the conductive feature 260 may be referred to as Figure 1 The metal wire 150 in.

[0069] Furthermore, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222. In some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed below the top surface of the doped dielectric layer 216, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed at the top surface of the doped dielectric layer 216.

[0070] Thus, a connection structure 240 is obtained. Figure 6C As shown, the connection structure 240 includes a dielectric structure 210, which includes a first dielectric layer 212 on the substrate 200 and the conductive feature 202, a second dielectric layer 214 on the first dielectric layer 212, a doped dielectric layer 216 on the second dielectric layer 214, and a metal layer 220 disposed on the conductive feature 202 and referred to as a metal portion. Figure 6C As shown, metal portion 220 contacts conductive feature 202, first dielectric layer 212, second dielectric layer 214, and doped dielectric layer 216. A top surface of metal portion 220 is aligned with a top surface of doped dielectric layer 216. Additionally, metal portion 220 may be free of dopants. In such an embodiment, a bottom surface of doped dielectric layer 216 contacts second dielectric layer 214. In such an embodiment, doped dielectric layer 216 and second dielectric layer 214 include the same dielectric material.

[0071] refer to Figure 7 In operation 14, in some embodiments, portions of the metal layer 220 and portions of the doped metal portion 222 are removed to expose the top surface 210t of the dielectric structure 210 and form the connection structure 240. In such an embodiment, the top surface of the doped metal portion 222 is aligned with the top surface of the doped dielectric layer 216, but the bottom surface of the doped metal portion 222 is higher than the bottom surface of the doped dielectric layer 216.

[0072] refer to Figure 8 and Fig. 9As described above, by adjusting the implantation energy of the ion implantation, the doped dielectric layer 216 can be formed to contact the first dielectric layer 212. In such an embodiment, the bottom surface of the doped dielectric layer 216 is in contact with the first dielectric layer 212. In addition, the doped dielectric layer 216 and the first dielectric layer 212 include different dielectric materials. By adjusting the planarization operation, the doped metal portion 222 can be completely removed. Therefore, the metal portion 220 can be free of dopants, such as Figure 8 In other embodiments, as shown in Fig. 9 As shown, the doped metal portion 222 may be partially removed.

[0073] As described above, by completely or partially removing the doped metal portion 222, the top surface of the doped dielectric layer 216 can be aligned with the top surface of the metal portion 220, such as Figure 8 Alternatively, the top surface of the doped dielectric layer 216 may be aligned with the top surface of the doped metal portion 222, as shown. Fig. 9 shown.

[0074] Furthermore, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222. In some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed below the top surface of the doped dielectric layer 216, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed at the top surface of the doped dielectric layer 216.

[0075] refer to Fig.10 and Fig.11 As described above, by adjusting the implantation energy of the ion implantation, the doped dielectric layer 216 can be formed even deeper, so that the doped dielectric layer 216 can include two parts. Fig.10 and Fig.11 As shown, the doped dielectric layer 216 may include a first portion 216-1 having the same dielectric material as the first dielectric layer 212, and a second portion 216-2 having the same dielectric material as the second dielectric layer 214. In such an embodiment, the bottom surface of the doped dielectric layer 216 is in contact with the first dielectric layer 212. As described above, by adjusting the planarization operation, the doped metal portion 222 may be completely removed. Therefore, the metal portion 220 may be free of dopants, such as Fig.10 In other embodiments, the doped metal portion 222 may be partially removed, such as Fig.11 shown.

[0076] As described above, by completely or partially removing the doped metal portion 222, the top surface of the doped dielectric layer 216 can be aligned with the top surface of the metal portion 220, such as Fig.10 As shown, or may be aligned with the top surface of the doped metal portion 222, as shown Fig.11 shown.

[0077] In addition, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed below the top surface of the doped metal portion 222, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped metal portion 222 may be observed at the top surface of the doped metal portion 222. In some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed below the top surface of the second portion 216-2 of the doped dielectric layer 216, but the present disclosure is not limited thereto. For example, in some embodiments, a peak of the profile of the dopant in the doped dielectric layer 216 may be observed at the top surface of the second portion 216-2 of the doped dielectric layer 216.

[0078] refer to Figures 7 to 11 In some embodiments, another dielectric structure 250 may be formed over the dielectric structure 210 and the connection structure 240. Another conductive feature 260 may be formed in the dielectric structure 250. The conductive feature 260 may be coupled to the connection structure 240. In some embodiments, the conductive feature 260 may be referred to as Figure 1 In some embodiments, the conductive feature 260 may be referred to as Figure 1 The metal wire 150 in.

[0079] According to the method 10 for forming a connection structure, a doped metal portion 222 and a doped dielectric layer 216 may be formed before removing a portion of the metal layer 220 and a portion of the dielectric structure 210. The doped dielectric layer 216 provides compressive stress, so that metal diffusion along the interface between the metal layer 220 and the dielectric structure 210 may be prevented or reduced, and the metal loss problem may be alleviated or reduced.

[0080] Fig.1230 is a flow chart representing a method 30 for forming a connection structure according to various aspects of the present disclosure. In some embodiments, the method 30 for forming a connection structure includes a plurality of operations (31, 32, 33, and 34). The method 30 for forming a connection structure will be further described according to one or more embodiments. It should be noted that the operations of the method 30 for forming a connection structure can be rearranged or otherwise modified within the scope of various aspects. It should also be noted that additional processes can be provided before, during, and after the method 30, and some other processes may only be briefly described herein.

[0081] FIG. 13A to FIG. 18 is a schematic diagram showing various stages in a method 30 for forming a connection structure according to aspects of one or more embodiments of the present disclosure. It should be noted that FIG. 3A to FIG. 3F and FIG. 13A to FIG. 13E The same elements in the drawings may include the same materials, and repeated details may be omitted for brevity. In some embodiments, a substrate 400 may be received. The substrate 400 may be Figure 1 The substrate 102 is shown, but the present disclosure is not limited thereto. In some embodiments, the substrate 400 may include a semiconductor device, such as Figure 1 The transistor shown in FIG. 1 is a transistor shown in FIG. 2 , but the present disclosure is not limited thereto. Fig.13A As shown, substrate 400 may include conductive features 402 disposed therein. In some embodiments, conductive features 402 may be similar to Figure 1 1 or the FEOL features of the metal gate 110 or source / drain regions S / D shown in FIG. In some embodiments, the conductive features 402 may be MEOL features, such as those similar to Figure 1 130, 132. In other embodiments, the conductive feature 402 may be a BEOL feature, such as Figure 1 The metal line (M) feature 150 depicted in FIG.

[0082] In operation 31, a dielectric structure 410 is formed over substrate 400 and conductive features 402. In some embodiments, dielectric structure 410 may include a single layer. In some embodiments, dielectric structure 410 may include a multi-layer structure. For example, Fig.13A As shown, dielectric structure 410 may include at least first dielectric layer 412 and second dielectric layer 414 sequentially stacked over substrate 400 and conductive feature 402. First dielectric layer 412 and second dielectric layer 414 may include different dielectric materials.

[0083] In operation 31, an opening may be formed in dielectric structure 410. In some embodiments, the opening passes through dielectric structure 410 from top surface 410t to the bottom of dielectric structure 410. Thus, a portion of conductive feature 402 is exposed through the opening.

[0084] Still reference Fig.13A , in operation 32, a metal layer 420 (e.g., a noble metal layer) may be formed to fill the opening. The metal layer 420 extends from the top surface 410t of the dielectric structure 410 to the bottom of the dielectric structure 410. The metal layer 420 passes through the second dielectric layer 414 and the first dielectric layer 412 to contact the exposed portion of the conductive feature 402. In addition, the metal layer 420 covers the top surface 410t of the dielectric structure 410. It should be noted that in some embodiments, the metal layer 420 may be formed without a liner, a barrier layer, a seed layer, or any intermediate layer. Therefore, in such an embodiment, the metal layer 420 may be in contact with the dielectric structure 410, but the present disclosure is not limited thereto.

[0085] refer to Fig. 13B In operation 33, a portion of the metal layer 420 is removed to expose the top surface 410t of the dielectric structure 410 and form a connection structure 440. In some embodiments, a portion of the dielectric structure 410, such as a portion of the second dielectric layer 414, may be removed in operation 33. In some embodiments, the removal of the portion of the metal layer 420 and the portion of the dielectric structure 410 may be performed using a CMP operation.

[0086] refer to Fig. 13C In operation 34, a doped metal portion 422 is formed in the metal layer 420, and a doped dielectric layer 416 is formed in the second dielectric layer 414 of the dielectric structure 410. In some embodiments, the doped metal portion 422 and the doped dielectric layer 416 are aligned with each other, but the present disclosure is not limited thereto. In some embodiments, the doped metal portion 422 and the doped dielectric layer 416 include dopants such as germanium (Ge), silicon (Si), argon (Ar), xenon (Xe), or nitrogen (N), but the present disclosure is not limited thereto. In some embodiments, the formation of the doped metal portion 422 and the doped dielectric layer 416 includes ion implantation. The dose of the ion implantation may be about 1E13 cm -2 to about 1E16cm -2 The angle of the ion implantation may be between about 0 degrees and about 60 degrees. In some embodiments, the temperature of the ion implantation may be between about -100°C and about 500°C. In some embodiments, the concentration of the dopant in the doped dielectric layer 416 may be between about 1E19 atoms / cm 3 to about 1E12 atoms / cm 3In some embodiments, the concentration of the dopant in the doped metal portion 422 may be between about 1E19 atoms / cm 3 to about 1E12 atoms / cm 3 However, the present disclosure is not limited thereto.

[0087] It should be noted that the depth or position of forming the doped metal portion 422 and the doped dielectric layer 416 can be determined by the implantation energy of the ion implantation. For example, by adjusting the implantation energy, the bottom surface of the doped dielectric layer 416 can be formed to contact the second dielectric layer 414 (eg, Fig. 13C and Fig.14 ), contacting the top surface of the first dielectric layer 412 (as shown Fig.15 and Fig.16 ), or below the top surface of the first dielectric layer 412 (as shown Fig.17 and Fig.18 In some embodiments, as shown Fig. 13C As shown, the top surface of the doped metal portion 422 and the top surface of the doped dielectric layer 416 are exposed. However, it should be noted that by controlling or adjusting the implantation energy of the ion implantation, the doped metal portion 422 is separated from the conductive feature 402. In some comparative methods, when the doped metal portion 422 contacts the conductive feature 402, the resistance of the conductive feature 402 may be negatively affected.

[0088] refer to Fig.13D In some embodiments, an annealing in a range from about 100° C. to about 500° C. is performed to improve gap filling results, reduce plug resistance, and improve interface quality. During the annealing, metal diffusion may occur, and metal ions may move from the conductive feature 402 to the upper portion of the metal layer 420 along the interface between the dielectric structure 410 and the metal layer 420. As described above, the dopant in the doped dielectric layer 416 causes the doped dielectric layer 416 to function as a compressive stress layer. Fig.13D As shown, compressive stress from doped dielectric layer 416, as indicated by opposing arrows along the sidewalls of doped metal portion 422, helps prevent or reduce metal diffusion, as indicated by the "X" and upward arrows. Thus, metal loss issues may be mitigated or reduced.

[0089] refer to Fig.13E In some embodiments, another dielectric structure 450 may be formed over dielectric structure 410 and connection structure 440. Another conductive feature 460 may be formed in dielectric structure 450. Conductive feature 460 may be coupled to connection structure 440. In some embodiments, conductive feature 460 may be referred to as Figure 1 In some embodiments, the conductive feature 460 may be referred to as Figure 1 The metal wire 150 in.

[0090] Thus, a connection structure 440 is obtained. Fig.13D As shown, the connection structure 440 includes: a first dielectric layer 412 on the substrate 400 and the conductive feature 402, a second dielectric layer 414 on the first dielectric layer 412, a doped dielectric layer 416 on the second dielectric layer 414, a metal layer 420 disposed on the conductive feature 402 and referred to as a metal portion, and a doped metal portion 422 on the metal portion 420. Fig.13D As shown, metal portion 420 contacts conductive feature 402, first dielectric layer 412, and second dielectric layer 414, while doped metal portion 422 contacts doped dielectric layer 416. A top surface of doped metal portion 422 is aligned with a top surface of doped dielectric layer 416. In such an embodiment, a bottom surface of doped dielectric layer 416 contacts second dielectric layer 414. Furthermore, a bottom surface of doped dielectric layer 416 and a bottom surface of doped metal portion 422 may be aligned, but the disclosure is not limited thereto.

[0091] In some embodiments, metal portion 420 and doped metal portion 422 include the same metal material. Doped dielectric layer 416 and second dielectric layer 414 include the same dielectric material. In addition, doped metal portion 422 and doped dielectric layer 416 include the same dopant.

[0092] As described above, during ion implantation, the dopant in dielectric structure 410 may penetrate deeper than the dopant in metal layer 420 because the density of dielectric material is less than that of metal material. Therefore, the bottom surface of doped dielectric layer 416 may be lower than the bottom surface of doped metal portion 422, as shown in FIG. Fig.14 shown.

[0093] Furthermore, in some embodiments, a peak of a profile of a dopant in doped metal portion 422 may be observed below the top surface of doped metal portion 422, but the disclosure is not limited thereto. For example, in some embodiments, a peak of a profile of a dopant in doped metal portion 422 may be observed at the top surface of doped metal portion 422. In some embodiments, a peak of a profile of a dopant in doped dielectric layer 416 may be observed below the top surface of doped dielectric layer 416, but the disclosure is not limited thereto. For example, in some embodiments, a peak of a profile of a dopant in doped dielectric layer 416 may be observed at the top surface of doped dielectric layer 416.

[0094] As described above, in some embodiments, by adjusting the implantation energy, the bottom surface of the doped dielectric layer 416 can be formed to contact the first dielectric layer 412, such as Fig.15 and Fig.16 In such an embodiment, the doped dielectric layer 416 and the first dielectric layer 412 may include different dielectric materials.

[0095] As described above, during ion implantation, the dopant in dielectric structure 410 may penetrate deeper than the dopant in metal layer 420 because the density of dielectric material is less than that of metal material. Therefore, the bottom surface of doped dielectric layer 416 may be lower than the bottom surface of doped metal portion 422, as shown in FIG. Fig.16 shown.

[0096] As described above, in some embodiments, the doped dielectric layer 416 may be formed by implanting dopants into the first dielectric layer 412 and the second dielectric layer 414. Therefore, the doped dielectric layer 416 may include two parts. Fig.17 and Fig.18 As shown, the doped dielectric layer 416 may include a first portion 416 - 1 including a first dielectric material that is the same as the dielectric material of the first dielectric layer 412 and a second portion 416 - 2 including a second dielectric material that is the same as the dielectric material of the second dielectric layer 414 .

[0097] As described above, during ion implantation, the dopant in dielectric structure 410 may penetrate deeper than the dopant in metal layer 420 because the density of dielectric material is less than that of metal material. Therefore, the bottom surface of doped dielectric layer 416 may be lower than the bottom surface of doped metal portion 422, as shown in FIG. Fig.18 shown.

[0098] In addition, reference Figures 14 to 18 In some embodiments, another dielectric structure 450 may be formed over dielectric structure 410 and connection structure 440. Another conductive feature 460 may be formed in dielectric structure 450. Conductive feature 460 may be coupled to connection structure 440. In some embodiments, conductive feature 460 may be referred to as Figure 1 In some embodiments, the conductive feature 460 may be referred to as Figure 1 The metal wire 150 in.

[0099] According to the method 30 for forming a connection structure, a doped metal portion 422 and a doped dielectric layer 416 may be formed after removing a portion of the metal layer 420 and a portion of the second dielectric layer 414. The doped dielectric layer 416 provides compressive stress, so that metal diffusion may be prevented, and the metal loss problem may be mitigated. As described above, although the depth and position of the doped dielectric layer 416 and the doped metal portion 422 may be determined by adjusting the implantation energy, it should be noted that the bottom surface of the doped metal portion 422 is formed to be separated from the conductive feature 402, and the bottom surface of the doped dielectric layer 416 is formed to be separated from the substrate 400, so as to prevent a negative impact on the resistance of the conductive feature 402 and the resistance of the substrate 400.

[0100] In summary, the present disclosure therefore provides a connection structure and a method for forming a connection structure to mitigate the bottom metal loss problem. In some embodiments, ion implantation is performed after the deposition of the metal layer to form a doped dielectric layer that serves as a compressive stress layer that provides compressive stress, and the compressive stress helps to prevent metal diffusion. Therefore, the bottom metal loss problem caused by metal diffusion can be mitigated.

[0101] In some embodiments, a connection structure is provided. The connection structure includes: a first dielectric layer, which is disposed on a conductive feature; a doped dielectric layer, which is disposed on the first dielectric layer; and a metal portion, which is disposed in the first dielectric layer and the doped dielectric layer. In some embodiments, the doped dielectric layer includes a compressive stress on the metal portion. In some embodiments, the metal portion contacts the conductive feature, the doped dielectric layer, and the first dielectric layer. In some embodiments, a top surface of the metal portion is aligned with a top surface of the doped dielectric layer. In some embodiments, the first dielectric layer includes a first dielectric material, and at least a portion of the doped dielectric layer includes a second dielectric material different from the first dielectric material.

[0102] In some embodiments, a connection structure is provided. The connection structure includes: a first dielectric layer disposed on a conductive feature; a doped dielectric layer disposed on the first dielectric layer; a metal portion disposed in the first dielectric layer and the doped dielectric layer; and a doped metal portion disposed on the metal portion. In some embodiments, the doped dielectric layer includes a compressive stress for the doped metal portion. In some embodiments, a top surface of the doped metal portion and a top surface of the doped dielectric layer are aligned. In some embodiments, a bottom surface of the doped metal portion is higher than a bottom surface of the doped dielectric layer. In some embodiments, the first dielectric layer includes a first dielectric material, and at least a portion of the doped dielectric layer includes a second dielectric material different from the first dielectric material.

[0103] In some embodiments, a method for forming a connection structure is provided. The method includes the following operations. A dielectric structure is formed over a conductive feature. The dielectric structure includes an opening that exposes a portion of the conductive feature. The opening is filled with a metal layer. A doped metal portion is formed in the metal layer, and a doped dielectric layer is formed in the dielectric structure. In some embodiments, the doped dielectric layer includes a compressive stress on the doped metal portion. In some embodiments, a top surface of the doped metal portion is separated from a top surface of the metal layer, and a top surface of the dielectric layer is separated from a top surface of the dielectric structure. A portion of the metal layer and a portion of the dielectric structure are removed to form the connection structure.

[0104] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0105] Example 1. A connection structure comprising: a first dielectric layer disposed on a conductive feature; a doped dielectric layer disposed on the first dielectric layer; and a metal feature disposed in the first dielectric layer and the doped dielectric layer, wherein the doped dielectric layer applies compressive stress to the metal feature, wherein the metal feature contacts the conductive feature, the doped dielectric layer and the first dielectric layer, wherein a top surface of the metal feature and a top surface of the doped dielectric layer are aligned, wherein the first dielectric layer comprises a first dielectric material and at least a portion of the doped dielectric layer comprises a second dielectric material different from the first dielectric material.

[0106] Example 2. The connection structure of Example 1, wherein the metal feature comprises a precious metal material.

[0107] Example 3. The connection structure according to Example 1, wherein the doped dielectric layer includes a dopant, wherein the dopant includes germanium Ge, silicon Si, argon Ar, xenon Xe or nitrogen N.

[0108] Example 4. The connection structure of Example 1, wherein a bottom surface of the doped dielectric layer is in contact with the first dielectric layer.

[0109] Example 5. The connection structure according to Example 1 further includes: a second dielectric layer, arranged on the first dielectric layer, wherein the second dielectric layer includes the second dielectric material, and wherein the second dielectric layer does not have the dopant of the doped dielectric layer.

[0110] Example 6. The connection structure of Example 5, wherein the second dielectric layer is disposed between the doped dielectric layer and the first dielectric layer.

[0111] Example 7. The connection structure of Example 1, wherein the doped dielectric layer comprises: a first portion comprising the first dielectric material; and a second portion comprising the second dielectric material.

[0112] Example 8. A connection structure, comprising: a first dielectric layer, disposed on a conductive feature; a doped dielectric layer, disposed on the first dielectric layer; a metal portion, disposed in the first dielectric layer and the doped dielectric layer; and a doped metal portion, disposed on the metal portion, wherein the doped dielectric layer applies compressive stress to the doped metal portion, a top surface of the doped metal portion is aligned with a top surface of the doped dielectric layer, a bottom surface of the doped metal portion is higher than a bottom surface of the doped dielectric layer, the first dielectric layer comprises a first dielectric material, and at least a portion of the doped dielectric layer comprises a second dielectric material different from the first dielectric material.

[0113] Example 9. The connection structure of Example 8, wherein the doped metal portion and the metal portion comprise the same metal material.

[0114] Example 10. The connection structure of Example 8, wherein the doped dielectric layer and the doped metal portion include the same dopant.

[0115] Example 11. The connection structure of Example 10, wherein the dopant comprises germanium, silicon, argon, xenon, arsenic, or a combination thereof.

[0116] Example 12. The connection structure of Example 8, wherein the doped dielectric layer is in contact with the first dielectric layer.

[0117] Example 13. The connection structure according to Example 8 further includes: a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer includes the second dielectric material.

[0118] Example 14. The connection structure of Example 13, wherein the second dielectric layer is disposed between the doped dielectric layer and the first dielectric layer.

[0119] Example 15. A connection structure according to Example 8, wherein the doped dielectric layer includes: a first portion including the first dielectric material; and a second portion including the second dielectric material.

[0120] Example 16. A method for forming a semiconductor device, the method comprising: forming a dielectric structure above a conductive feature, wherein the dielectric structure includes an opening exposing a portion of the conductive feature; filling the opening with a metal layer; forming a doped metal portion in the metal layer, and forming a doped dielectric layer in the dielectric structure, wherein the doped dielectric layer includes a compressive stress layer for the doped metal portion, a top surface of the doped metal portion is separated from a top surface of the metal layer, wherein a top surface of the doped dielectric layer is separated from a top surface of the dielectric structure; and removing at least a portion of the metal layer and at least a portion of the dielectric structure to form a connecting structure.

[0121] Example 17. The method of Example 16, wherein the doped metal portion and the doped dielectric layer include the same dopant, wherein the dopant includes germanium, silicon, argon, xenon, arsenic, or a combination thereof.

[0122] Example 18. The method of Example 16, wherein removing at least a portion of the metal layer and at least a portion of the dielectric structure is performed after forming the doped metal portion and the doped dielectric layer.

[0123] Example 19. The method of Example 18, wherein during the removing of the portion of the metal layer and the portion of the dielectric structure, the doped metal portion is completely removed.

[0124] Example 20. The method of Example 16, wherein removing at least a portion of the metal layer and at least a portion of the dielectric structure is performed before forming the doped metal portion and the doped dielectric layer.

Claims

1. A connection structure, comprising: a first dielectric layer disposed over the conductive features; A second dielectric layer, disposed on the first dielectric layer; a doped dielectric layer, disposed on the first dielectric layer; as well as A metal feature is disposed in the first dielectric layer and the doped dielectric layer, wherein the doped dielectric layer applies a compressive stress to the metal feature, wherein the metal feature contacts the conductive feature, the doped dielectric layer and the first dielectric layer, wherein a top surface of the metal feature and a top surface of the doped dielectric layer are aligned, wherein the first dielectric layer includes a first dielectric material and at least a portion of the doped dielectric layer includes a second dielectric material different from the first dielectric material, the second dielectric layer includes the second dielectric material, and the second dielectric layer is free of a dopant of the doped dielectric layer.

2. The connection structure according to claim 1, wherein: The metallic feature comprises a precious metal material.

3. The connection structure according to claim 1, wherein: The doped dielectric layer includes a dopant, wherein the dopant includes germanium Ge, silicon Si, argon Ar, xenon Xe or nitrogen N.

4. The connection structure according to claim 1, wherein: A bottom surface of the doped dielectric layer contacts the first dielectric layer.

5. The connection structure according to claim 1, wherein: The second dielectric layer is disposed between the doped dielectric layer and the first dielectric layer.

6. The connection structure according to claim 1, wherein: The doped dielectric layer comprises: A first portion comprising the first dielectric material; and The second part includes the second dielectric material.

7. A connection structure comprising: a first dielectric layer disposed over the conductive features; A second dielectric layer, disposed on the first dielectric layer; a doped dielectric layer, disposed on the first dielectric layer; a metal portion, disposed in the first dielectric layer and the doped dielectric layer; as well as A doped metal portion is disposed above the metal portion, wherein the doped dielectric layer applies compressive stress to the doped metal portion, a top surface of the doped metal portion is aligned with a top surface of the doped dielectric layer, a bottom surface of the doped metal portion is higher than a bottom surface of the doped dielectric layer, the first dielectric layer includes a first dielectric material, and at least a portion of the doped dielectric layer includes a second dielectric material different from the first dielectric material, and the second dielectric layer includes the second dielectric material.

8. The connection structure according to claim 7, wherein: The doped metal portion and the metal portion include a same metal material.

9. The connection structure according to claim 7, wherein: The doped dielectric layer and the doped metal portion include the same dopant.

10. The connection structure according to claim 9, wherein: The dopant includes germanium, silicon, argon, xenon, arsenic, or a combination thereof.

11. The connection structure according to claim 7, wherein: The doped dielectric layer contacts the first dielectric layer.

12. The connection structure according to claim 7, wherein: The second dielectric layer is disposed between the doped dielectric layer and the first dielectric layer.

13. The connection structure according to claim 7, wherein: The doped dielectric layer comprises: A first portion comprising the first dielectric material; and The second part includes the second dielectric material.

14. A method for forming a semiconductor device, the method comprising: forming a dielectric structure over the conductive feature, wherein the dielectric structure includes an opening exposing a portion of the conductive feature, and the dielectric structure includes a first dielectric layer and a second dielectric layer disposed over the first dielectric layer; filling the opening with a metal layer; forming a doped metal portion in the metal layer, and forming a doped dielectric layer in the dielectric structure, wherein the doped dielectric layer comprises a compressive stress layer for the doped metal portion, a top surface of the doped metal portion is separated from a top surface of the metal layer, wherein a top surface of the doped dielectric layer is separated from a top surface of the dielectric structure, the first dielectric layer comprises a first dielectric material, at least a portion of the doped dielectric layer comprises a second dielectric material different from the first dielectric material, and the second dielectric layer comprises the second dielectric material; and At least a portion of the metal layer and at least a portion of the dielectric structure are removed to form a connection structure.

15. The method according to claim 14, wherein: The doped metal portion and the doped dielectric layer include a same dopant, wherein the dopant includes germanium, silicon, argon, xenon, arsenic, or a combination thereof.

16. The method according to claim 14, wherein: Removing at least a portion of the metal layer and at least a portion of the dielectric structure is performed after forming the doped metal portion and the doped dielectric layer.

17. The method according to claim 16, wherein: During the removal of the portion of the metal layer and the portion of the dielectric structure, the doped metal portion is completely removed.

18. The method according to claim 14, wherein: Removing at least a portion of the metal layer and at least a portion of the dielectric structure is performed prior to forming the doped metal portion and the doped dielectric layer.

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