Three-dimensional semiconductor memory device

Abstract

Disclosed is a three-dimensional semiconductor memory device including: a substrate including a cell region and a connection region; a plurality of electrode interlayer dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein end portions of the plurality of electrode layers form a step shape on the connection region; a planarized dielectric layer on the connection region and covering the end portions of the plurality of electrode layers; and a first abnormal pseudo-vertical pattern on the connection region and passing through the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is disposed between the first abnormal pseudo-vertical pattern and the substrate and is insulated from the first abnormal pseudo-vertical pattern.

Description

[0001] Cross-reference of related technologies

[0002] This U.S. non-provisional application claims priority to Korean Patent Application No. 10-2020-0006638, filed on January 17, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a three-dimensional semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device with enhanced reliability. Background Technology

[0004] Semiconductor devices are highly integrated to meet consumer demands for higher performance and / or lower manufacturing costs. Because the integration of semiconductor devices is a factor determining product price, the requirement for high integration is increasing. The integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a single memory cell, making it susceptible to the level of technology used to form fine patterns. However, the expensive processing equipment required to increase pattern fineness sets practical limitations on increasing the integration of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional semiconductor device integration system has been proposed.

[0005] A three-dimensional semiconductor memory device with memory cells arranged in a three-dimensional manner. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide a three-dimensional semiconductor memory device with enhanced reliability.

[0007] The advantages of the present invention are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description other advantages not mentioned above.

[0008] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: a substrate including cell regions and connection regions; a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, the ends of the plurality of electrode layers forming a stepped shape on the connection regions; a planarized dielectric layer on the connection regions, the planarized dielectric layer covering the ends of the plurality of electrode layers; and a first anomalous pseudo-vertical pattern on the connection regions, the first anomalous pseudo-vertical pattern penetrating the planarized dielectric layer in a first direction perpendicular to the top surface of the substrate. At least one of the plurality of electrode layers may be disposed between the first anomalous pseudo-vertical pattern and the substrate, and may be insulated from the first anomalous pseudo-vertical pattern.

[0009] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: a substrate including cell regions and connection regions; a first stacked structure including a plurality of first inter-electrode dielectric layers and a plurality of first electrode layers alternately stacked on the substrate; a second stacked structure including a plurality of second inter-electrode dielectric layers and a plurality of second electrode layers alternately stacked on the first stacked structure; a cell vertical pattern on the cell regions, the cell vertical pattern passing through the first stacked structure and the second stacked structure in a first direction perpendicular to the top surface of the substrate; and an anomalous pseudo-vertical pattern on the connection regions, the anomalous pseudo-vertical pattern passing through one or more of the plurality of second electrode layers. The sidewalls of the cell vertical pattern may have inflection points adjacent to the boundary between the first stacked structure and the second stacked structure. At least one of the plurality of first electrode layers may be located between the anomalous pseudo-vertical pattern and the substrate in the first direction.

[0010] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: a peripheral circuit structure including transistors and peripheral wiring; and a cell array structure on the peripheral circuit structure. The cell array structure may include: a first substrate including cell regions and connection regions; a first stack structure including a plurality of first inter-electrode dielectric layers and a plurality of first electrode layers alternately stacked on the first substrate; a second stack structure including a plurality of second inter-electrode dielectric layers and a plurality of second electrode layers alternately stacked on the first stack structure; an anomalous pseudo-vertical pattern located on the connection regions, the anomalous pseudo-vertical pattern passing through one or more of the plurality of second electrode layers in a first direction perpendicular to the top surface of the substrate; and a sacrificial buried pattern located in the first stack structure on the connection regions, the sacrificial buried pattern being spaced apart from the anomalous pseudo-vertical pattern. Attached Figure Description

[0011] Figure 1A A block diagram illustrating a three-dimensional semiconductor memory device showing some example embodiments of the concept according to the present invention is shown;

[0012] Figure 1B Circuit diagrams illustrating some exemplary embodiments of a semiconductor memory device according to a concept of the present invention are shown;

[0013] Figure 2 A plan view of a three-dimensional semiconductor memory device showing some example embodiments of the concept according to the present invention is shown;

[0014] Figure 3A It shows along Figure 2 A sectional view taken by line A-A';

[0015] Figure 3B It shows along Figure 2 A sectional view taken by line B-B';

[0016] Figure 4A The display shows Figure 3A A magnified view of part P1;

[0017] Figure 4B The display shows Figure 3A A magnified view of part P2;

[0018] Figures 5A to 9A The illustration shows some example embodiments of manufacturing processes based on the concept of the present invention. Figure 3A A cross-sectional view of a method for creating a three-dimensional semiconductor memory device;

[0019] Figures 5B to 9B The illustration shows some example embodiments of manufacturing processes based on the concept of the present invention. Figure 3B A cross-sectional view of a method for creating a three-dimensional semiconductor memory device;

[0020] Figure 10 It shows along Figure 2 A sectional view taken by line A-A';

[0021] Figure 11 It shows along Figure 2 A sectional view taken by line A-A';

[0022] Figures 12 to 14 Display manufacturing is shown Figure 11 A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device;

[0023] Figure 15 It shows along Figure 2 A sectional view taken by line A-A';

[0024] Figure 16 It shows along Figure 2 A sectional view taken by line A-A';

[0025] Figure 17 The display shows Figure 16 Enlarged view of part of P8;

[0026] Figure 18 It shows along Figure 2 A sectional view taken by line A-A';

[0027] Figure 19 A cross-sectional view of a three-dimensional semiconductor memory device showing some example embodiments of the concept according to the present invention is shown. Detailed Implementation

[0028] Some exemplary embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings to help to clearly explain the inventive concept.

[0029] Figure 1A A block diagram illustrating a three-dimensional semiconductor memory device showing some example embodiments of the concept according to the present invention is shown.

[0030] Reference Figure 1A A three-dimensional semiconductor memory device according to some exemplary embodiments of the present invention may include a cell array structure CS disposed on a substrate. The cell array structure CS may include a plurality of memory blocks BLK0 to BLKn, each of which is a data erasure cell. Each of the memory blocks BLK0 to BLKn may include a memory cell array having a three-dimensional structure (or a vertical structure).

[0031] Figure 1B A circuit diagram illustrating a three-dimensional semiconductor memory device showing some example embodiments of the concept according to the present invention is shown.

[0032] Reference Figure 1B Each of the memory blocks BLK0 to BLKn can be configured such that the cell strings CSTR are arranged two-dimensionally along a first direction D1 and a second direction D2, and extended along a third direction D3. Multiple cell strings CSTR can be connected in parallel with each of the bit lines BL0 to BL2. Multiple cell strings CSTR can be connected together to the common source line CSL.

[0033] Bit lines BL0 to BL2 can be arranged in a two-dimensional configuration, and multiple cell strings (CSTRs) can be connected in parallel with each of the bit lines BL0 to BL2. Multiple cell strings (CSTRs) can be connected together to a common source line (CSL). For example, multiple cell strings (CSTRs) can be positioned between multiple bit lines BL0 to BL2 and a common source line (CSL). The common source line (CSL) can be configured as multiple lines arranged in a two-dimensional configuration. The common source lines (CSLs) can be supplied with the same voltage or can be electrically controlled independently of each other.

[0034] In some example embodiments, one of the cell strings (CSTRs) may include series-connected string select transistors SST21 and / or SST11, series-connected memory cell transistors (MCTs) and / or ground select transistors (GSTs). Each of the memory cell transistors (MCTs) may include a data storage element. One of the cell strings (CSTRs) may also include a pseudo-cell (DMC) between the string select transistor SST11 and the memory cell transistors (MCTs) and between the ground select transistor (GST) and the memory cell transistors (MCTs). Other cell strings (CSTRs) may have the same or similar structures as discussed above.

[0035] The string select transistor SST21 can be coupled to the first bit line BL1, and the ground select transistor GST can be coupled to the common source line CSL. The memory cell transistor MCT connected to a cell string CSTR can be connected in series, for example, between the string select transistor SST11 and the ground select transistor GST.

[0036] Alternatively, in each of the cell strings CSTRs, the ground selection transistor GST may include multiple MOS transistors connected in series, similar to the string selection transistors SST21 and SST11. The difference is that each of the cell strings CSTRs may include one string selection transistor.

[0037] In some example embodiments, the string select transistor SST11 can be controlled by the string select line SSL11, and the string select transistor SST21 can be controlled by the string select line SSL21. The memory cell transistor MCT can be controlled by multiple word lines WL0 to WLn, and the pseudo-cell DMC can be controlled by the pseudo-word line DWL. The ground select transistor GST can be controlled by ground select lines GSL0-GSL2. The common source line CSL can be connected to the source of the ground select transistor GST.

[0038] A cell string (CSTR) may include multiple memory cell transistors (MCTs) located at different distances from the common-source line (CSL). Multiple word lines (WL0 to WLn) and DWL may be positioned between the common-source line (CSL) and bit lines (BL0 to BL2).

[0039] A memory cell transistor (MCT) may include a gate electrode located at the same or substantially the same distance from the common source line (CSL), and the gate electrode may be commonly connected to one of the word lines WL0 to WLn and DWL, thereby being in an equipotential state. Alternatively, although the gate electrode of the memory cell transistor (MCT) is set at the same or substantially the same distance from the common source line (CSL), gate electrodes located in different rows or columns can be controlled independently of each other.

[0040] Figure 2 A plan view of a three-dimensional semiconductor memory device showing some example embodiments of the concept according to the present invention is shown. Figure 3A It shows along Figure 2 A sectional view taken by line A-A'. Figure 3B It shows along Figure 2 The sectional view taken by line B-B'. Figure 4A The display shows Figure 3A A magnified view of part P1. Figure 4B The display shows Figure 3A A magnified view of part P2.

[0041] Reference Figure 2 , Figure 3A , Figure 3B , Figure 4A and Figure 4B The cell array structure CS can be disposed on the substrate 10. The cell array structure CS may include multiple memory blocks BLK0 to BLKn, and Figure 2 A plan view of a memory block BLK selected from a plurality of memory blocks BLK0 to BLKn is shown. Substrate 10 may be formed of one of a semiconductor material (e.g., silicon wafer), a dielectric material (e.g., glass), and a conductor or semiconductor covered by the dielectric material. Substrate 10 may be doped with impurities, for example, having a first conductivity type. Substrate 10 may include cell regions CAR, dummy cell regions DCR, and / or connection regions CNR arranged in a first direction D1. Buffer dielectric layer 11 may be disposed on substrate 10. Buffer dielectric layer 11 may have a single-layer or multi-layer structure, comprising, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0042] The buffer dielectric layer 11 may have alternately stacked electrode layers EL1, EL, ELm, and ELn, as well as an inter-electrode dielectric layer 12 disposed thereon. The electrode layers EL1, EL, ELm, and ELn may include a first electrode layer EL1 closest to the substrate 10, an nth electrode layer ELn furthest from the substrate 10, an mth electrode layer ELm adjacent to the nth electrode layer ELn, and a plurality of intermediate electrode layers EL between the first electrode layer EL1 and the mth electrode layer ELm. The nth electrode layer ELn may be covered by a capping dielectric layer 14.

[0043] The capping dielectric layer 14 may comprise the same material as the inter-electrode dielectric layer 12. For example, the inter-electrode dielectric layer 12 may comprise a silicon oxide layer. The electrode layers EL1, EL, ELm, and ELn may comprise a metal, such as tungsten. The buffer dielectric layer 11, the inter-electrode dielectric layer 12, the electrode layers EL1, EL, ELm, and ELn, and / or the capping dielectric layer 14 may form a stacked structure ST.

[0044] Electrode layers EL1, EL, ELm, and ELn may have ends (or pad portions) forming stepped structures on the connection region CNR. For example, electrode layers EL1, EL, ELm, and ELn may have a length that decreases with increasing distance from the substrate 10 in the first direction D1, and the stacked structure ST may have a height that decreases with increasing distance from the cell region CAR. On the connection region CNR, electrode layers EL1, EL, ELm, and ELn may have sidewalls that are equidistant from each other along the first direction D1. Each of electrode layers EL1, EL, ELm, and ELn may have a pad portion on the connection region CNR, and the pad portions of electrode layers EL1, EL, ELm, and ELn may be positioned horizontally and vertically at different locations. The nth electrode layer ELn and the mth electrode layer Elm among electrode layers EL1, EL, ELm, and ELn may each have a linear shape extending in the first direction D1 and may be spaced apart from each other across the discrete dielectric pattern 9.

[0045] In some example embodiments, a NAND flash memory device can be used as the three-dimensional semiconductor memory device according to the present invention. For example, the first electrode layer EL1 can correspond to Figure 1B The ground selection lines are GSL0 to GSL2. The m-th electrode layer ELm can correspond to Figure 1B The string selection lines are SSL11, SSL12, and SSL13. The nth electrode layer ELn can correspond to... Figure 1B The serial selection lines SSL21, SSL22, and SSL23 are used. The intermediate electrode layer EL can correspond to... Figure 1B The word lines WL0 to WLn and the pseudo-word line DWL. On the connection region CNR, the stacked structure ST may have ends covered by a planarized dielectric layer 20. The planarized dielectric layer 20 may comprise the same dielectric material as the inter-electrode dielectric layer 12. The top surface of the planarized dielectric layer 20 may be coplanar with the top surface of the capping dielectric layer 14.

[0046] On the cell region CAR, the stacked structure ST may include a plurality of vertical vias CH that expose the substrate 10 and are spaced apart from each other. On the pseudo-cell region DCR, the stacked structure ST may include a plurality of first pseudo-vertical vias DCH1 that expose the substrate 10 and are spaced apart from each other. On the connection region CNR, the stacked structure ST may include a plurality of second pseudo-vertical vias DCH2 that expose the substrate 10 and are spaced apart from each other. On the connection region CNR, the second pseudo-vertical vias DCH2 may extend into the planarized dielectric layer 20. The vertical vias CH, the first pseudo-vertical vias DCH1 and the second pseudo-vertical vias DCH2 may have corresponding semiconductor patterns EP that contact the substrate 10. For example, the semiconductor pattern EP may be a single-crystal silicon pattern. The semiconductor pattern EP may be doped with impurities having a first conductivity type.

[0047] The ground gate dielectric layer 22 may be located between the first electrode layer EL1 and the semiconductor pattern EP. For example, the ground gate dielectric layer 22 may include a silicon oxide layer. The ground gate dielectric layer 22 may not extend onto the intermediate electrode layer EL.

[0048] A vertical hole CH may have a corresponding unit vertical pattern VS in contact with the semiconductor pattern EP. A first pseudo-vertical hole DCH1 may have a corresponding first pseudo-vertical pattern DVS1 in contact with the semiconductor pattern EP. A second pseudo-vertical hole DCH2 may have a corresponding second pseudo-vertical pattern DVS2 in contact with the semiconductor pattern EP. For example, the unit vertical pattern VS, the first pseudo-vertical pattern DVS1, and / or the second pseudo-vertical pattern DVS2 may comprise a polycrystalline silicon layer or a monocrystalline silicon layer, either doped or undoped. The unit vertical pattern VS, the first pseudo-vertical pattern DVS1, and / or the second pseudo-vertical pattern DVS2 may each have a hollow cup shape. When viewed in a plan view, the first pseudo-vertical pattern DVS1 and / or the unit vertical pattern VS may each have a circular shape. The first pseudo-vertical pattern DVS1 and the unit vertical pattern VS may have the same diameter (or maximum width). When viewed in a plan view, the second pseudo-vertical pattern DVS2 may each have an elliptical or circular shape. Figure 3A As shown in the cross-sectional view, the width of each of the second pseudo-vertical patterns DVS2 parallel to the first direction D1 can be equal to or greater than the width of each of the unit vertical patterns VS parallel to the first direction D1.

[0049] like Figure 2 As shown, the cell region CAR may include multiple cell vertical patterns VS and / or multiple center pseudo-vertical patterns CDVS. The center pseudo-vertical patterns CDVS may be linearly arranged along a first direction D1 on the central portion of a portion of the memory block BLK. Separating dielectric patterns 9 may be disposed between the upper portions of the center pseudo-vertical patterns CDVS. For example, the separating dielectric patterns 9 may include a silicon oxide layer.

[0050] Reference Figure 2When viewed in a planar view, the second pseudo-vertical pattern DVS2 can pass through the ends (or pad portions) of electrode layers EL1, EL, ELm, and ELn. The number of electrode layers EL1, EL, ELm, and ELm traversed by the second pseudo-vertical pattern DVS2 can gradually decrease as the second pseudo-vertical pattern DVS2 moves further away from the cell region CAR. When viewed in a planar view, a cell contact plug CPLG can be surrounded by four second pseudo-vertical patterns DVS2 that are adjacent to each other and configured to pass through the corresponding pad portions. For another example, when viewed in a planar view, one or more of the second pseudo-vertical patterns DVS2 can pass through the boundaries between adjacent electrode layers EL1, EL, ELm, and ELn. In some example embodiments, the arrangement of the second pseudo-vertical patterns DVS2 can be varied. The cell contact plug CPLG can pass through the planarized dielectric layer 20 and / or the first interlayer dielectric layer 16 and the second interlayer dielectric layer 18, which will be discussed below, thereby coupling to the corresponding pad portions of electrode layers EL1, EL, ELm, and ELn.

[0051] Bit line conductive pads 34 may be formed on the top of the unit vertical pattern VS, the top of the central pseudo-vertical pattern CDVS, and the top of the first pseudo-vertical pattern DVS1 and the second pseudo-vertical pattern DVS2. The bit line conductive pads 34 may be doped regions or formed of a conductive material. The bit line conductive pads 34 on the unit vertical pattern VS may be connected to the bit line BL. Conversely, the bit line conductive pads 34 on the central pseudo-vertical pattern CDVS and the first pseudo-vertical pattern DVS1 and the second pseudo-vertical pattern DVS2 may not be connected to the bit line BL. The unit vertical pattern VS, the central pseudo-vertical pattern CDVS, the first pseudo-vertical pattern DVS1, and / or the second pseudo-vertical pattern DVS2 may each include a channel spacer layer 25 and / or a channel connection layer 27, such as... Figure 4A As shown. The channel spacer layer 25 and / or the channel connection layer 27 can be formed of a polycrystalline silicon layer or a monocrystalline silicon layer doped with impurities.

[0052] The first gate dielectric layer GI can be correspondingly located between the inner wall of the cell vertical pattern VS and the vertical hole CH, between the inner wall of the first pseudo-vertical pattern DVS1 and the first pseudo-vertical hole DCH1, and between the inner wall of the second pseudo-vertical pattern DVS2 and the second pseudo-vertical hole DCH2. The first gate dielectric layer GI can each include a tunnel dielectric layer TL, a charge storage layer SN, and / or a barrier dielectric layer BCL, such as... Figure 4AAs shown. The charge storage layer SN can be a trapping dielectric layer, a floating gate electrode, or a dielectric layer comprising conductive nanodots. For example, the charge storage layer SN may include one or more of silicon nitride, silicon oxynitride, silicon-rich nitride, nanocrystalline silicon, and stacked trapping layers. The tunneling dielectric layer TL may include one of the materials with a band gap larger than that of the charge storage layer SN, and the blocking dielectric layer BCL may include a high-k dielectric layer such as an alumina layer or a hafnium oxide layer.

[0053] The first gate dielectric layer GI can partially cover the corresponding top surface of the semiconductor pattern EP. The cell vertical pattern VS, the first pseudo-vertical pattern DVS1, and / or the second pseudo-vertical pattern DVS2 can each pass through the first gate dielectric layer GI and contact the semiconductor pattern EP. For example, as... Figure 4A As shown, the channel connection layer 27 of each of the cell vertical pattern VS, the first pseudo-vertical pattern DVS1, and / or the second pseudo-vertical pattern DVS2 can penetrate the first gate dielectric layer GI and contact the semiconductor pattern EP. The channel connection layer 27 can have a hollow cup shape, and the buried dielectric pattern 29 can fill the empty spaces within the channel connection layer 27. For example, the buried dielectric pattern 29 may include a silicon oxide layer.

[0054] The high-k dielectric layer HL can be located between the first gate dielectric layer GI and the electrode layers EL1, EL, ELm and ELn, and between the electrode layers EL1, EL, ELm and ELn and the inter-electrode dielectric layer 12. The high-k dielectric layer HL can be a layer with a dielectric constant greater than that of the silicon oxide layer (such as an aluminum oxide layer or a hafnium oxide layer).

[0055] The stacked structure ST can be sequentially covered by a first interlayer dielectric layer 16 and / or a second interlayer dielectric layer 18. Each of the first interlayer dielectric layer 16 and the second interlayer dielectric layer 18 can have a single-layer or multi-layer structure, including one or more of silicon oxide layers, silicon nitride layers, and silicon oxynitride layers. The bit line conductive pad 34 on the cell vertical pattern VS can be connected to the bit line BL via a bit line contact plug BPLG passing through the first interlayer dielectric layer 16 and the second interlayer dielectric layer 18. The bit line BL can extend in a second direction D2 intersecting the first direction D1 and can be parallel to each other. The bit line contact plug BPLG and the bit line BL can include metals such as tungsten, aluminum, and copper. The bit line contact plug BPLG and the bit line BL may not be provided on the bit line conductive pad 34 on the pseudo cell region DCR and the connection region CNR. In some example embodiments, the pseudo cell region DCR may include a pseudo bit line contact plug (not shown) and a pseudo bit line (not shown) on the bit line conductive pad 34. In some example embodiments, the pseudo bit line can be electrically floating without a voltage supply. Similar to the bit line BL, the pseudo bit line can also extend in the second direction D2.

[0056] The cell array structure CS may include a stacked structure ST, a first interlayer dielectric layer 16, a second interlayer dielectric layer 18, and / or bit lines BL. First source contact plugs CSPLG1 may be disposed between adjacent memory blocks BLK included in the cell array structure CS. Additionally, second source contact plugs CSPLG2 may each be disposed on the central portion of a memory block BLK, and may divide the memory block BLK into two parts in the second direction D2. Figure 2 As shown in the plan view, the first source contact plug CSPLG1 may have a linear shape that extends continuously in the first direction D1. On the other hand, the second source contact plug CSPLG2 may have discontinuous portions (or cut-off regions) in the connection region CNR.

[0057] like Figure 3B As shown in the cross-sectional view, the first source contact plug CSPLG1 and the second source contact plug CSPLG2 may be spaced apart from each other and adjacent to the substrate 10, while passing through the first interlayer dielectric layer 16 and the stacked structure ST. A dielectric spacer SP may be located between the stacked structure ST and the first source contact plug CSPLG1, and between the stacked structure ST and the second source contact plug CSPLG2. The substrate 10 may have a common source region CSR therein, correspondingly contacting the first source contact plug CSPLG1 and the second source contact plug CSPLG2. The common source region CSR may be doped with impurities having a second conductivity type opposite to the first conductivity type of the impurities doped in the substrate 10. For example, the first source contact plug CSPLG1 and the second source contact plug CSPLG2 may include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum).

[0058] Reference Figure 3A and Figure 4B Abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 can be disposed on the connection area CNR. Abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 can correspond to some portions of the second pseudo-vertical pattern DVS2. Abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 can include first abnormal pseudo-vertical patterns DVS2_1 to fourth abnormal pseudo-vertical patterns DVS2_4. First abnormal pseudo-vertical patterns DVS2_1 to fourth abnormal pseudo-vertical patterns DVS2_4 can be respectively disposed in first abnormal vertical holes FCH1 to fourth abnormal vertical holes FCH4. Abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 may not be connected to the bit line BL. Voltage may not be applied to abnormal pseudo-vertical patterns DVS2_1 to DVS2_4. Abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 may each have a hollow cup shape.

[0059] The abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 may each include a channel spacer layer 25 and / or a channel connection layer 27, such as Figure 4B As shown. The channel spacer layer 25 and / or the channel connection layer 27 can be formed of a polycrystalline silicon layer or a monocrystalline silicon layer doped with impurities. The second gate dielectric layer GIF can be located between the inner walls of the abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 and the abnormal vertical holes FCH1 to FCH4. The second gate dielectric layer GIF can each include a tunnel dielectric layer TL, a charge storage layer SN, and / or a barrier dielectric layer BCL, such as Figure 4B As shown. The second gate dielectric layer GIF can cover the corresponding bottom surfaces of the abnormal vertical holes FCH1 to FCH4. The abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 can not penetrate the second gate dielectric layer GIF and can be spaced apart from the bottom surfaces of the abnormal vertical holes FCH1 to FCH4. One or more of the electrode layers EL1, EL, ELm, and ELn can be located between the substrate 10 and the abnormal pseudo-vertical patterns DVS2_1 to DVS2_4. The second gate dielectric layer GIF can insulate the abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 from the electrode layers EL1, EL, ELm, and ELn.

[0060] For example, a first anomalous pseudo-vertical pattern DVS2_1 can be set in a first anomalous vertical hole FCH1. The first anomalous vertical hole FCH1 can have a pointed lower portion. The lowermost end of the first anomalous vertical hole FCH1 can be adjacent to half the height of the stacked structure ST. For example... Figure 3A As shown, approximately seven electrode layers EL1 and EL can be located between the substrate 10 and the lowermost end of the first abnormal vertical via FCH1. A first abnormal pseudo-vertical pattern DVS2_1 can vertically overlap with the approximately seven electrode layers EL1 and EL. The second gate dielectric layer GIF and / or the first abnormal pseudo-vertical pattern DVS2_1 disposed in the first abnormal vertical via FCH1 can have a pointed lower portion. For example, the first abnormal pseudo-vertical pattern DVS2_1 can have an upper width and a lower width parallel to the first direction D1, and the lower width can preferably be about 85% or less of the upper width, more preferably about 35% to about 85%.

[0061] The first anomalous pseudo-vertical pattern DVS2_1 can pass through the planarized dielectric layer 20, one or more inter-electrode dielectric layers 12, and one or more intermediate electrode layers EL.

[0062] The second anomalous pseudo-vertical pattern DVS2_2 can be set in the second anomalous vertical aperture FCH2. The second anomalous vertical aperture FCH2 can have a flat bottom surface. The lowermost end of the second anomalous vertical aperture FCH2 can be closer to the substrate 10 than the first anomalous vertical aperture FCH1. Figure 3A As shown, the two electrode layers EL1 and EL can be located between the substrate 10 and the lowermost end of the second abnormal vertical hole FCH2 (or between the substrate 10 and the second abnormal pseudo-vertical pattern DVS2_2). The second abnormal pseudo-vertical pattern DVS2_2 can vertically overlap with the two electrode layers EL1 and EL. The second gate dielectric layer GIF and the second abnormal pseudo-vertical pattern DVS2_2 disposed in the second abnormal vertical hole FCH2 can also have flat bottom surfaces. The second abnormal pseudo-vertical pattern DVS2_2 can pass through the planarized dielectric layer 20, one or more inter-electrode dielectric layers 12 and / or one or more intermediate electrode layers EL.

[0063] A third anomalous pseudo-vertical pattern DVS2_3 can be disposed in a third anomalous vertical via FCH3. The third anomalous vertical via FCH3 can have a flat bottom surface and / or sloping sidewalls. The lowermost end of the third anomalous vertical via FCH3 can be closer to the substrate 10 than the first anomalous vertical via FCH1, but farther from the substrate 10 than the second anomalous vertical via FCH2. The third anomalous vertical via FCH3 can have a bottom surface on one of the intermediate electrode layers EL. For example... Figure 3A As shown, approximately four electrode layers EL1 and EL can be located between the substrate 10 and the lowermost end of the third anomalous vertical via FCH3 (or between the substrate 10 and the third anomalous pseudo-vertical pattern DVS2_3). The third anomalous pseudo-vertical pattern DVS2_3 can vertically overlap with the approximately four electrode layers EL1 and EL. The second gate dielectric layer GIF and / or the third anomalous pseudo-vertical pattern DVS2_3 disposed in the third anomalous vertical via FCH3 can have a flat bottom surface and / or sloping sidewalls. The third anomalous pseudo-vertical pattern DVS2_3 can pass through the planarized dielectric layer 20, one or more inter-electrode dielectric layers 12, and / or one or more intermediate electrode layers EL.

[0064] A fourth anomalous pseudo-vertical pattern DVS2_4 can be disposed in a fourth anomalous vertical via FCH4. The fourth anomalous vertical via FCH4 can have a flat bottom surface. The lowermost end of the fourth anomalous vertical via FCH4 can be closer to the substrate 10 than the first anomalous vertical via FCH1, but farther from the substrate 10 than the third anomalous vertical via FCH3. The fourth anomalous vertical via FCH4 can be formed in a planarized dielectric layer 20 and / or can be spaced apart from the inter-electrode dielectric layer 12 and the electrode layers EL1, EL, ELm, and ELn. Figure 3AAs shown, the three electrode layers EL1 and EL can be located between the substrate 10 and the lowermost end of the fourth abnormal vertical hole FCH4 (or between the substrate 10 and the fourth abnormal pseudo-vertical pattern DVS2_4). The fourth abnormal pseudo-vertical pattern DVS2_4 can vertically overlap with the three electrode layers EL1 and EL. The second gate dielectric layer GIF and / or the fourth abnormal pseudo-vertical pattern DVS2_4 disposed in the fourth abnormal vertical hole FCH4 can have a flat bottom surface. The fourth abnormal pseudo-vertical pattern DVS2_4 can penetrate a portion of the planarized dielectric layer 20.

[0065] The first abnormal pseudo-vertical pattern DVS2_1 to the fourth abnormal pseudo-vertical pattern DVS2_4 can have side and bottom surfaces surrounded by a second gate dielectric layer GIF and electrically insulated from electrode layers EL1, EL, ELm, and ELn. Therefore, programming errors and / or current leakage can be reduced or prevented in a three-dimensional semiconductor memory device, thus increasing reliability. Figure 3A Four abnormal vertical holes and four abnormal pseudo-vertical patterns are shown, but there is no limit to the number of abnormal vertical holes or abnormal pseudo-vertical patterns. For example, the number of abnormal vertical holes or abnormal pseudo-vertical patterns can be less than or greater than four.

[0066] Figures 5A to 9A The manufacture of some example embodiments of the invention is shown. Figure 3A A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device. Figures 5B to 9B The manufacture of some example embodiments of the invention is shown. Figure 3B A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device.

[0067] Reference Figure 5A and Figure 5BA substrate 10 comprising a cell region (CAR), a pseudo-cell region (DCR), and / or a connection region (CNR) can be fabricated. A buffer dielectric layer 11 can be formed on the substrate 10. For example, the buffer dielectric layer 11 may comprise a silicon oxide layer. An inter-electrode dielectric layer 12 and / or a sacrificial layer 13 can be alternately formed on the buffer dielectric layer 11. A capping dielectric layer 14 can be formed on the uppermost of the sacrificial layers 13. In this way, an initial stacked structure PST can be formed. The sacrificial layer 13 can be formed of a material having etch selectivity relative to the buffer dielectric layer 11, the inter-electrode dielectric layer 12, and / or the capping dielectric layer 14. For example, the sacrificial layer 13 can be formed of a silicon nitride layer. For example, the buffer dielectric layer 11, the inter-electrode dielectric layer 12, and / or the capping dielectric layer 14 can be formed of a silicon oxide layer. Trimming and etching processes can be performed alternately and repeatedly to give the initial stacked structure PST a stepped end on the connection region CNR. A planarized dielectric layer 20 can be formed on the entire surface of the substrate 10, and then a chemical mechanical polishing (CMP) process can be performed to remove the planarized dielectric layer 20 covering the ends of the initial stacked structure PST.

[0068] An etching process can be performed to etch the initial stacked structure PST and the planarized dielectric layer 20 to form cell vertical vias CH and a central pseudo-vertical via CDCH spaced apart from each other on the cell region CAR, and also to form a first pseudo-vertical via DCH1 and a second pseudo-vertical via DCH2 on the pseudo-cell region DCR and the connection region CNR, respectively. The substrate 10 can be exposed to the cell vertical vias CH, the central pseudo-vertical via CDCH, the first pseudo-vertical via DCH1 and the second pseudo-vertical via DCH2. The first pseudo-vertical via DCH1 can be formed to reduce or prevent defects in the cell vertical vias CH due to the loading effect caused by differences in pattern density.

[0069] The unit vertical via CH, the central pseudo vertical via CDCH, and the first pseudo vertical via DCH1 can have the same size and the same spacing between them. The size and spacing of the second pseudo vertical via DCH2 can be larger than that of the unit vertical via CH. When performing an etching process, the unit vertical via CH, the central pseudo vertical via CDCH, and the first pseudo vertical via DCH1 can be formed with almost no defects to expose the substrate 10 on the unit region CAR and the pseudo unit region DCR (each of which has a uniform via density). Conversely, because the second pseudo vertical via DCH2 has a relatively low density, blockage failures can occur due to loading effects when performing an etching process. For example, during the formation of the second pseudo vertical via DCH2, etching byproducts such as polymers can accumulate on the bottom and / or side surfaces of one or more of the second pseudo vertical via DCH2, so one or more of the second pseudo vertical via DCH2 will not be further etched, which will result in the generation of unopened defects in which the substrate 10 is not exposed. Due to the step difference between the connection region CNR and the cell region CAR, blockage failures may occur. Therefore, during the etching process, first abnormal vertical holes FCH1 to fourth abnormal vertical holes FCH4 can be formed on the connection region CNR. The first abnormal vertical holes FCH1 to fourth abnormal vertical holes FCH4 can differ in depth, location, and shape.

[0070] Reference Figure 6A and Figure 6B Selective epitaxial growth (SEG) can be performed to form semiconductor patterns EP in holes CH, CDCH, DCH1, and DCH2. When forming the semiconductor pattern EP, impurities of a first conductivity type can be doped in situ. At this stage, since the abnormal vertical holes FCH1 to FCH4 do not expose the substrate 10, semiconductor patterns EP may not be formed in the abnormal vertical holes FCH1 to FCH4. The gate dielectric layer GIO can be conformally formed across the entire surface of the substrate 10. The gate dielectric layer GIO can be formed by sequentially forming a tunnel dielectric layer TL, a charge storage layer SN, and / or a barrier dielectric layer BCL, as follows: Figure 4AAs shown. A channel spacer layer 25 can be formed conformally on the gate dielectric layer GIO. The channel spacer layer 25 can be formed of a polysilicon layer. The gate dielectric layer GIO and / or the channel spacer layer 25 can also be formed conformally on the inner walls and / or bottom surfaces of the vias CH, CDCH, DCH1, DCH2, and FCH1 to FCH4. A mask pattern MK can be formed on the channel spacer layer 25 on the connection region CNR. The mask pattern MK can be formed to expose the cell region CAR and / or the dummy cell region DCR. For example, the mask pattern MK can be formed of a layer with poor step coverage, so it can not enter the vias CH, CDCH, DCH1, DCH2, and FCH1 to FCH4. For example, the mask pattern MK can be formed of an amorphous carbon layer (ACL). Therefore, in subsequent processing, it may be possible to reduce or prevent defects caused by the mask pattern MK remaining in the vias CH, CDCH, DCH1, DCH2, and FCH1 to FCH4.

[0071] Reference Figure 7A and Figure 7B The mask pattern MK can be used as an etching mask to etch the channel spacer layer 25 and / or gate dielectric layer GIO exposed on the cell region CAR and / or dummy cell region DCR, thereby forming multiple channel spacer layers 25 and / or multiple first gate dielectric layers GI to expose the top surface of the semiconductor pattern EP and cover the sidewalls of the vertical hole CH, the sidewalls of the central dummy vertical hole CDCH and the sidewalls of the first dummy vertical hole DCH1.

[0072] Reference Figure 4A , Figure 4B , Figure 7A , Figure 7B , Figure 8A and Figure 8BThe mask pattern MK can be removed to expose the connection region CNR. A channel connection layer 27 can be conformally formed across the entire surface of the substrate 10, thereby contacting the sidewalls of the channel spacer layer 25 and the top surface of the semiconductor pattern EP. A buried dielectric layer can be formed to fill vias CH, CDCH, DCH1, DCH2, and FCH1 to FCH4. A chemical mechanical polishing (CMP) process can be performed to remove the gate dielectric layer GIO, the channel connection layer 27, and the buried dielectric layer to form vertical patterns VS, CDVS, DVS1, DVS2, and DVS2_1 to DVS2_4, a first gate dielectric layer GI, a second gate dielectric layer GIF, and a buried dielectric pattern 29 in vias CH, CDCH, DCH1, DCH2, and FCH1 to FCH4. Vertical patterns VS, CDVS, DVS1, DCH2 and FCH1 to FCH4, the first gate dielectric layer GI and the second gate dielectric layer GIF, and the buried dielectric pattern 29 can be partially removed from the upper part of the holes CH, CDCH, DCH1, DCH2 and FCH1 to FCH4. Then, a conductive layer can be formed to form bit line conductive pads 34 in the area where the patterns and layers have been partially removed.

[0073] Reference Figure 2 , Figure 9A and Figure 9B The initial stacked structure PST can be etched to form a groove GR extending in the first direction D1 and exposing the substrate 10. The sacrificial layer 13 can be completely removed through the groove GR to form an empty space R1 exposing the top and bottom surfaces of the inter-electrode dielectric layer 12, the sidewalls of the gate dielectric layers GI and GIF, and the sidewalls of the semiconductor pattern EP. At this stage, the second pseudo-vertical pattern DVS2 can reduce or prevent the collapse of the initial stacked structure PST.

[0074] Reference Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 9A and Figure 9BThermal oxidation can be performed to form a ground gate dielectric layer 22 on the exposed sidewalls of the semiconductor pattern EP. A high-k dielectric layer HL can be conformally formed across the entire surface of the substrate 10, and / or a conductive layer can be formed to fill empty spaces R1. The conductive layer in the trench GR can be removed to expose the substrate 10. An ion implantation process can be performed to form a common source region CSR in the substrate 10. The dielectric layer can be conformally formed and then anisotropically etched to form a dielectric spacer SP covering the inner wall of the trench GR. A conductive layer can be formed to fill the trench GR, and then etched to form a first source contact plug CSPLG1 and a second source contact plug CSPLG2 in the trench GR. Next, a process can be performed to form a first interlayer dielectric layer 16 and a second interlayer dielectric layer 18, a bit line contact plug BPLG, and a bit line BL.

[0075] According to some exemplary embodiments of the present invention, a method of manufacturing a three-dimensional semiconductor memory device may include: etching a gate dielectric layer GIO to expose the top surface of a semiconductor pattern EP while the mask pattern MK covers a connection region CNR where a non-opening fault is highly likely. As a result, the gate dielectric layer GIO may not be etched in the connection regions CNR within the abnormal vertical holes FCH1 to FCH4. The bottom surfaces of the abnormal vertical holes FCH1 to FCH4 can therefore be covered by a second gate dielectric layer GIF. Thus, the contact between the channel connection layers 27 of the abnormal pseudo-vertical patterns DVS2_1 to DVS2_4 and the electrode layers EL and EL1 below the abnormal vertical holes FCH1 to FCH4 can be reduced or prevented. Consequently, the reliability of the three-dimensional semiconductor memory device can be improved.

[0076] Figure 10 It shows along Figure 2 A sectional view taken by line A-A'.

[0077] Reference Figure 10According to this example embodiment, a three-dimensional semiconductor memory device can be configured to include a fifth abnormal pseudo-vertical pattern DVS 1_1 on the pseudo-cell region DCR. The fifth abnormal pseudo-vertical pattern DVS1_1 can be disposed in a fifth abnormal vertical via FCH5. The fifth abnormal vertical via FCH5 can be formed in a portion of the stacked structure ST. The fifth abnormal pseudo-vertical pattern DVS1_1 can correspond to one of the first pseudo-vertical patterns DVS1. The fifth abnormal vertical via FCH5 can have a flat bottom surface. The fifth abnormal pseudo-vertical pattern DVS1_1 can also have a flat bottom surface. A second gate dielectric layer GIF can be interposed between the fifth abnormal pseudo-vertical pattern DVS1_1 and the inner surface of the fifth abnormal vertical via FCH5. The fifth abnormal pseudo-vertical pattern DVS1_1 may not penetrate the second gate dielectric layer GIF and may be spaced apart from the bottom surface of the fifth abnormal vertical via FCH5. Other configurations may be referenced. Figures 2 to 4B The same or similar aspects discussed can be fabricated by forming a mask pattern MK to cover the pseudo-cell region DCR (without covering the CNR region, or in addition to covering the CNR region) and then performing subsequent processing. Figure 10 A three-dimensional semiconductor memory device.

[0078] Figure 11 It shows along Figure 2 A sectional view taken by line A-A'.

[0079] Reference Figure 11The cell array structure CS may include a first sub-stack structure ST1 and / or a second sub-stack structure ST2. The first sub-stack structure ST1 may include a buffer dielectric layer 11 on the substrate 10, and further include an inter-electrode dielectric layer 12 and alternatingly stacked first electrode layers to the i-th electrode layers EL1, EL, and ELi on the buffer dielectric layer 11. The second sub-stack structure ST2 may include the inter-electrode dielectric layer 12 and alternatingly stacked j-th to n-th electrode layers ELj, EL, Elm, and ELn. Here, i, j, m, and n are integers greater than 2, where i < j < m < n. The vertical hole CH, the central pseudo-vertical hole CDCH, the first pseudo-vertical hole DCH1, and the second pseudo-vertical hole DCH2 may each include a lower hole BH and an upper hole UH that are vertically overlapping each other and spatially connected to each other. The vertical hole CH, the central pseudo-vertical hole CDCH, the first pseudo-vertical hole DCH1, and / or the second pseudo-vertical hole DCH2 may have inner walls such that each of these inner walls has an inflection point between the first sub-stacking structure ST1 and the second sub-stacking structure ST2. The vertical patterns VS, CDVS, DVS1, and DVS2 may have sidewalls such that each of these sidewalls has an inflection point adjacent to the location between the first sub-stacking structure ST1 and the second sub-stacking structure ST2 (or between the i-th electrode layer Eli and the j-th electrode layer ELj). The end of the first sub-stacking structure ST1 may be covered by a lower planarized dielectric layer 201. The top surface of the lower planarized dielectric layer 201 may be coplanar with the top surface of the first sub-stacking structure ST1. The ends of the lower planarized dielectric layer 201 and the second sub-stacking structure ST2 may be covered by an upper planarized dielectric layer 203. The top surface of the upper planarized dielectric layer 203 may be coplanar with the top surface of the second sub-stacking structure ST2.

[0080] A first abnormal vertical via FCH1 can be disposed in the third portion P3 of the connection region CNR. The first abnormal vertical via FCH1 may include an upper via UH and a first abnormal lower via FBH1 spatially connected to the upper via UH. The first abnormal lower via FBH1 may not expose the substrate 10. The first abnormal vertical via FCH1 can be formed in the planarized dielectric layer 203 and the first sub-stack structure ST1 and the second sub-stack structure ST2, and the three electrode layers EL1 and EL can be disposed below the bottom surface of the first abnormal lower via FBH1. A first abnormal pseudo-vertical pattern DVS2_1 can be disposed in the first abnormal vertical via FCH1. The sidewall of the first abnormal pseudo-vertical pattern DVS2_1 may have an inflection point IFP adjacent to the position between the first sub-stack structure ST1 and the second sub-stack structure ST2.

[0081] The first abnormal upper via FUH1 can be disposed in the fourth portion P4 of the connection region CNR. The first abnormal upper via FUH1 may not expose the first sub-stack structure ST1. The first abnormal upper via FUH1 can be formed in the second sub-stack structure ST2, and the three electrode layers ELj and EL of the second sub-stack structure ST2 can be disposed below the bottom surface of the first abnormal upper via FUH1. The first abnormal upper via FUH1 can vertically overlap with the lower via BH formed in the first sub-stack structure ST1, and can be spaced apart from the lower via BH formed in the first sub-stack structure ST1. The lower via BH can extend partially into the substrate 10. A semiconductor pattern EP and / or a sacrificial buried pattern 31 can be disposed in the lower via BH. The sacrificial buried pattern 31 can contact the top surface of the semiconductor pattern EP. The sacrificial buried pattern 31 can have a single-layer structure or a multilayer structure including one or more of a polysilicon layer, an amorphous carbon layer (ACL), a spin-on hard mask (SOH) layer, a spin-on carbon (SOC) layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The second abnormal pseudo-vertical pattern DVS2_2 can be set in the first abnormal upper hole FUH1.

[0082] The second abnormal upper aperture FUH2 can be located in the fifth part P5 of the connection region CNR. The second abnormal upper aperture FUH2 can expose the first sub-stack structure ST1. The second abnormal upper aperture FUH2 can not vertically overlap with its adjacent lower aperture BH, but can be misaligned with its adjacent lower aperture BH. The electrode layers EL1, EL, and Eli of the first sub-stack structure ST1 can be located below the second abnormal upper aperture FUH2. The third abnormal pseudo-vertical pattern DVS2_3 can be located in the second abnormal upper aperture FUH3. The sacrificial burial pattern 31 can be located in the lower aperture BH.

[0083] The third anomalous upper aperture FUH3 can be located in the sixth part P6 of the connection region CNR. The third anomalous upper aperture FUH3 can expose the first sub-stack structure ST1. The third anomalous upper aperture FUH3 can not vertically overlap with the adjacent second anomalous lower aperture FBH2, but can be misaligned with the adjacent second anomalous lower aperture FBH2. The second anomalous lower aperture FBH2 can have a pointed lower portion. The electrode layers EL1 and EL of the first sub-stack structure ST1 can be located below the third anomalous upper aperture FUH3. The fourth anomalous pseudo-vertical pattern DVS2_4 can be located in the third anomalous upper aperture FUH3. The sacrificial burial pattern 31 can be located in the second anomalous lower aperture FBH2.

[0084] The fourth anomalous upper aperture FUH4 can be located in the seventh part P7 of the connection area CNR. The fourth anomalous upper aperture FUH4 may not expose the first sub-stack structure ST1. The fourth anomalous upper aperture FUH4 may have a pointed lower portion. The fourth anomalous upper aperture FUH4 may be spaced apart from the lower aperture BH below it. The sacrificial burial pattern 31 can be located in the lower aperture BH. The fifth anomalous pseudo-vertical pattern DVS2_5 can be located in the fourth anomalous upper aperture FUH4. Other configurations can be referenced. Figures 2 to 4B The ones discussed are the same or similar.

[0085] The manufacturing process will be described below. Figure 11 A method for constructing a three-dimensional semiconductor memory device.

[0086] Figures 12 to 14 Display manufacturing is shown Figure 11 A cross-sectional view of a method for constructing a three-dimensional semiconductor memory device.

[0087] Reference Figure 12 A buffer dielectric layer 11 can be formed on a substrate 10 including cell regions (CAR), dummy cell regions (DCR), and / or connection regions (CNR). A sacrificial layer 13 and an inter-electrode dielectric layer 12 can be alternately formed on the buffer dielectric layer 11 to form a first initial sub-stacking structure PST1. Trimming and etching processes can be repeatedly performed to give the first initial sub-stacking structure PST1 a stepped end. A planarized dielectric layer 201 can be formed, followed by chemical mechanical polishing (CMP) to allow the planarized dielectric layer 201 to cover the ends of the first initial sub-stacking structure PST1. The first initial sub-stacking structure PST1 can be etched to form a lower via BH exposing the substrate 10. During this stage, a blockage fault can occur on the connection region CNR to form abnormal lower vias FBH1 and FBH2. Selective epitaxial growth (SEG) can be performed to form a semiconductor pattern EP in the lower via BH. A sacrificial burial layer can be formed to fill the lower borehole BH and the abnormal lower boreholes FBH1 and FBH2, and then a blanket etch-back process can be performed to form the lower sacrificial burial pattern 31.

[0088] Reference Figure 13An inter-electrode dielectric layer 12 and a sacrificial layer 13 can be alternately formed on the first initial sub-stacking structure PST1. Then, a capping dielectric layer 14 can be formed on the uppermost of the sacrificial layers 13, resulting in the formation of a second initial sub-stacking structure PST2. Trimming and etching processes can be repeatedly performed to give the second initial sub-stacking structure PST2 a stepped end. An upper planarized dielectric layer 203 can be formed, followed by chemical mechanical polishing (CMP) to allow the upper planarized dielectric layer 203 to cover the end of the second initial sub-stacking structure PST2. The second initial sub-stacking structure PST2 can be etched to form upper vias UH that expose the lower sacrificial buried pattern 31. During this stage, blockage faults can occur in the connection region CNR to form aberrations FUH1 to FUH4.

[0089] Reference Figure 14 The substrate 10 can be exposed by removing the lower sacrificial buried pattern 31 exposed to the upper via UH. Alternatively, the lower sacrificial buried pattern 31 below or adjacent to the aberrant upper via FUH1 to FUH4 can be retained instead of being removed. Selective epitaxial growth (SEG) can be performed to form a semiconductor pattern EP. The semiconductor pattern EP can be formed outside of the aberrant lower vias FBH1 and FBH2 or outside of the lower vias BH below or adjacent to the aberrant upper vias FUH1 and FUH2. A reference process can then be performed. Figures 6A to 9B and Figures 2 to 4B The handling of the discussion.

[0090] Figure 15 It shows along Figure 2 A sectional view taken by line A-A'.

[0091] Reference Figure 15The cell array structure CS may include a first sub-stack structure ST1, a second sub-stack structure ST2, and / or a third sub-stack structure ST3 stacked in sequence. The first sub-stack structure ST1 may include a buffer dielectric layer 11 on the substrate 10, and further include an inter-electrode dielectric layer 12 and alternately stacked first to f electrode layers EL1, EL, and ELf. The second sub-stack structure ST2 may include an inter-electrode dielectric layer 12 and alternately stacked g to i electrode layers ELg, EL, and ELi. The third sub-stack structure ST3 may include an inter-electrode dielectric layer 12 and alternately stacked j to n electrode layers ELj, EL, Elm, and ELn, and further include a capping dielectric layer 14. Here, f, g, i, j, m, and n are each integers greater than 2, where f < g < i < j < m < n. The vertical hole CH, the central pseudo-vertical hole CDCH, the first pseudo-vertical hole DCH1, and the second pseudo-vertical hole DCH2 may each include a lower hole BH, a middle hole MH, and an upper hole UH that are vertically overlapping each other and spatially connected to each other. The vertical hole CH, the central pseudo-vertical hole CDCH, the first pseudo-vertical hole DCH1, and / or the second pseudo-vertical hole DCH2 may have inner walls such that each of these inner walls has an inflection point between the first sub-stacking structure ST1 and the second sub-stacking structure ST2 (or between the f-th electrode layer Elf and the g-th electrode layer Elg) and between the second sub-stacking structure ST2 and the third sub-stacking structure ST3 (or between the i-th electrode layer ELi and the j-th electrode layer ELj). The vertical patterns VS, CDVS, DVS1, and DVS2 may have sidewalls such that each of these sidewalls has an inflection point adjacent to a position between the first sub-stacking structure ST1 and the second sub-stacking structure ST2 and between the second sub-stacking structure ST2 and the third sub-stacking structure ST3.

[0092] The ends of the first sub-stack structure ST1 can be covered by the lower planarized dielectric layer 201. The top surface of the lower planarized dielectric layer 201 can be coplanar with the top surface of the first sub-stack structure ST1. The middle planarized dielectric layer 202 can cover the ends of the lower planarized dielectric layer 201 and the second sub-stack structure ST2. The top surface of the middle planarized dielectric layer 202 can be coplanar with the top surface of the second sub-stack structure ST2. The upper planarized dielectric layer 203 can cover the ends of the middle planarized dielectric layer 202 and the third sub-stack structure ST3. The top surface of the upper planarized dielectric layer 203 can be coplanar with the top surface of the third sub-stack structure ST3.

[0093] A first abnormal vertical via FCH1 may be disposed in the third portion P3 of the connection region CNR. The first abnormal vertical via FCH1 may include an upper via UH, a middle via MH, and / or a first abnormal lower via FBH1 spatially connected to the middle via MH and the upper via UH. The first abnormal lower via FBH1 may not expose the substrate 10. The first abnormal vertical via FCH1 may be formed in the planarized dielectric layer 203 and the first sub-stack structures ST1 to ST3, and the three electrode layers EL1 and EL may be disposed below the bottom surface of the first abnormal lower via FBH1. A first abnormal pseudo-vertical pattern DVS2_1 may be disposed in the first abnormal vertical via FCH1. The sidewalls of the first abnormal pseudo-vertical pattern DVS2_1 may have inflection points adjacent to the positions between the first sub-stack structure ST1 and the second sub-stack structure ST2 and between the second sub-stack structure ST2 and the third sub-stack structure ST3.

[0094] The first abnormal upper via FUH1 can be disposed in the fourth portion P4 of the connection region CNR. The first abnormal upper via FUH1 may not expose the second sub-stack structure ST2. The first abnormal upper via FUH1 can be formed in the third sub-stack structure ST3. The first abnormal upper via FUH1 can vertically overlap with its lower intermediate via MH and lower via BH. The first abnormal upper via FUH1 can be spaced apart from its lower intermediate via MH. The semiconductor pattern EP and the sacrificial buried pattern 31 can be disposed in the lower via BH. The intermediate sacrificial buried pattern 33 can be disposed in the intermediate via MH. The lower sacrificial buried pattern 31 and the intermediate sacrificial buried pattern 33 can be in contact with each other. The intermediate sacrificial buried pattern 33 may include the same material as the lower sacrificial buried pattern 31. The second abnormal pseudo-vertical pattern DVS2_2 can be disposed in the first abnormal upper via FUH1.

[0095] The second abnormal vertical hole FCH2 can be located in the fifth part P5 of the connection area CNR. The second abnormal vertical hole FCH2 may include an upper hole UH and an abnormal intermediate hole FMH1 spatially connected to the upper hole UH. The abnormal intermediate hole FMH1 may not expose the lower hole BH below it and may be spaced apart from the lower hole BH below it. The third abnormal pseudo-vertical pattern DVS2_3 can be located in the second abnormal vertical hole FCH2.

[0096] The second abnormal upper hole FUH2 can be located in the sixth part P6 of the connecting area CNR. The second abnormal upper hole FUH2 can be spaced apart from the second abnormal middle hole FMH2 below it. The second abnormal middle hole FMH2 can be spaced apart from the second abnormal lower hole FBH2 below it. The lower sacrificial burial pattern 31 can be located in the second abnormal lower hole FBH2, and the intermediate sacrificial burial pattern 33 can be located in the second abnormal middle hole FMH2.

[0097] The third anomaly upper hole FUH3 can be located in the seventh part P7 of the connection area CNR. The third anomaly upper hole FUH3 can be spaced apart from the third anomaly intermediate hole FMH3 below it. The third anomaly intermediate hole FMH3 can be spaced apart from the lower hole BH below it. The lower sacrificial burial pattern 31 can be located in the lower hole BH, and the intermediate sacrificial burial pattern 33 can be located in the third anomaly intermediate hole FMH3. Other configurations can be referenced. Figure 11 The discussions revolve around those that are the same or similar. Manufacturing. Figure 15 The method for constructing a three-dimensional semiconductor memory device can be compared with a reference. Figures 12 to 14 The ones discussed are the same or similar.

[0098] Figure 16 It shows along Figure 2 A sectional view taken by line A-A'. Figure 17 The display shows Figure 16 A magnified view of part P8.

[0099] Reference Figure 16 and Figure 17 The cell array structure CS can be stacked on the peripheral circuit structure PS. The peripheral circuit structure PS may include a peripheral circuit transistor PTR disposed on the peripheral circuit substrate 100, a peripheral interlayer dielectric layer 102 covering the peripheral circuit transistor PTR, and peripheral wiring 104 disposed in the peripheral interlayer dielectric layer 102.

[0100] The cell array structure CS can be with Figure 11 The configuration is similar, but with the difference that the first source pattern SC1 and the second source pattern SC2 are located between the first electrode layer EL1 and the substrate 10. The substrate 10 can be referred to as a semiconductor layer. The inter-electrode dielectric layer 12 can be located between the first source pattern SC1 and the first electrode layer EL1. For example, the first source pattern SC1 and the second source pattern SC2 can each include a polycrystalline silicon pattern or a monocrystalline silicon pattern doped with impurities having a first conductivity type. The second source pattern SC2 can pass through the first gate dielectric layer GI and can be coupled to the cell vertical pattern VS, the first pseudo-vertical pattern DVS2, and the second pseudo-vertical pattern DVS2. The residual tunnel dielectric layer TLr, the residual charge storage layer SNr, and the residual barrier dielectric layer BCLr can be located between the substrate 10 and the cell vertical pattern VS, between the substrate 10 and the first pseudo-vertical pattern DVS1, and between the substrate 10 and the second pseudo-vertical pattern DVS2. In this example embodiment, the vertical patterns VS, CDVS, DVS1, DVS2 and DVS2_1 to DVS2_5 can be formed by a single semiconductor layer or multiple semiconductor layers.

[0101] The abnormal pseudo-vertical patterns DVS2_1 to DVS2_5 can be spaced apart from the first source pattern SC1 and the second source pattern SC2. The lower sacrificial buried pattern 31 set in the lower hole BH can contact the first source pattern SC1 and the second source pattern SC2.

[0102] The second interlayer dielectric layer 18 may have interconnects 128 spaced apart from the bit line BL. The interconnects 128 may be electrically connected to the peripheral wiring 104 via a through-electrode TVS passing through a portion of the upper planarized dielectric layer 203, the lower planarized dielectric layer 201, the substrate 10, and the peripheral interlayer dielectric layer 102. The through-electrode TVS may have sidewalls surrounded by the through-dielectric layer TI. Other configurations may be referenced. Figure 11 The ones discussed are the same or similar.

[0103] Figure 18 It shows along Figure 2 A sectional view taken by line A-A'.

[0104] Reference Figure 18 The three-dimensional semiconductor memory device according to this example embodiment can be configured to... Figure 11 The pseudo-cell region DCR shown includes a sixth anomalous pseudo-vertical pattern DVS1_2. The sixth anomalous pseudo-vertical pattern DVS1_2 can be disposed within a fifth anomalous vertical aperture FCH5. The fifth anomalous vertical aperture FCH5 can be formed within a portion of the second stacked structure ST2. The first stacked structure ST1 may include a sacrificial burial pattern 31 that vertically overlaps with and is spaced apart from the fifth anomalous vertical aperture FCH5. Additionally, as shown in reference... Figure 10 The sixth anomalous pseudo-vertical pattern DVS1_2 on the pseudo-unit region DCR, as discussed, can avoid contacting the bottom surface of the fifth anomalous vertical hole FCH5. Other configurations can be referenced. Figure 10 and Figure 11 The ones discussed are the same or similar.

[0105] Figure 19 A cross-sectional view of a three-dimensional semiconductor memory device showing some example embodiments of the concept according to the present invention is shown.

[0106] Reference Figure 19 According to this example embodiment, the three-dimensional semiconductor memory device can be configured such that the centers of the lower holes BH, FBH1, and / or FBH2 formed in the first sub-stacking structure ST1 are spaced apart from the centers of the upper holes UH, FUH1, FUH2, and FUH3 formed in the second sub-stacking structure ST2 by a specific distance in the first direction D1. The vertical hole CH can then have the same... Figure 18 The sidewall profiles shown are different from the sidewall profiles. Therefore, vertical holes CH, DCH1, DCH2, and FCH1 can have sidewall profiles different from those shown. Figure 18 The sidewall profiles shown are different from the sidewall profiles. Additionally, the vertical patterns VS, CDVS, DVS1, DVS2, DVS2_1, and the gate dielectric layers GI and GIF can have the same sidewall profiles as those shown. Figure 18 The sidewall profiles shown are different. For example, the upper via UH can partially expose the top surface of the inter-electrode dielectric layer 12 located on top of the first sub-stack structure ST1. Therefore, in the vertical vias CH, DCH1, DCH2, and FCH1, the gate dielectric layers GI and GIF can contact the top surface of the inter-electrode dielectric layer 12 located on top of the first sub-stack structure ST1. Other configurations can be compared with the reference. Figure 18 Those that are the same or similar.

[0107] The three-dimensional semiconductor memory device conceived according to the present invention can be configured such that, on the connection region, an abnormal pseudo-vertical pattern is electrically insulated from the adjacent or underlying electrode layer by a gate dielectric layer surrounding the bottom and side surfaces of the abnormal pseudo-vertical pattern. Therefore, programming failures and / or current leakage can be reduced or prevented in the three-dimensional semiconductor memory device, thereby improving reliability.

[0108] Although the inventive concept has been described with reference to some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept.

Claims

1. A three-dimensional semiconductor memory device, comprising: The substrate includes cell regions and connection regions; Multiple inter-electrode dielectric layers and multiple electrode layers are alternately stacked on the substrate, and the ends of the multiple electrode layers are formed in a stepped shape on the connection region; A planarized dielectric layer is located on the connection region, and the planarized dielectric layer covers the ends of the plurality of electrode layers; as well as A first anomalous pseudo-vertical pattern is located on the connection region, and the first anomalous pseudo-vertical pattern penetrates the planarized dielectric layer in a first direction perpendicular to the top surface of the substrate. Wherein, at least one of the plurality of electrode layers is disposed between the first abnormal pseudo-vertical pattern and the substrate, and the first abnormal pseudo-vertical pattern is insulated from the at least one electrode layer by a gate dielectric layer surrounding its bottom surface and side surface.

2. The three-dimensional semiconductor memory device of claim 1, further comprising a second anomalous pseudo-vertical pattern located on the connection region and spaced apart from the first anomalous pseudo-vertical pattern, the second anomalous pseudo-vertical pattern passing through the planarized dielectric layer, one or more of the plurality of inter-electrode dielectric layers, and one or more of the plurality of electrode layers. in, At least one of the plurality of electrode layers is disposed in the first direction between the second anomalous pseudo-vertical pattern and the substrate, and is insulated from the second anomalous pseudo-vertical pattern. The first interval between the first abnormal pseudo-vertical pattern and the substrate is different from the second interval between the second abnormal pseudo-vertical pattern and the substrate.

3. The three-dimensional semiconductor memory device according to claim 2, wherein, The first abnormal pseudo-vertical pattern has a flat bottom surface, and The second anomalous pseudo-vertical pattern has an upper width and a lower width parallel to a second direction parallel to the top surface of the substrate, and the lower width is 85% or less of the upper width.

4. The three-dimensional semiconductor memory device of claim 1, further comprising a cell vertical pattern that extends through the plurality of inter-electrode dielectric layers and the plurality of electrode layers, adjacent to the substrate on the cell region. in, The first abnormal pseudo-vertical pattern and the unit vertical pattern have a first width and a second width respectively at the same horizontal height in a second direction parallel to the top surface of the substrate, wherein the first width is equal to or greater than the second width.

5. The three-dimensional semiconductor memory device according to claim 4, further comprising: A gate dielectric layer is located between the vertical pattern of the cell and the plurality of electrode layers; as well as A semiconductor pattern is located between the substrate and the vertical pattern of the cell. The gate dielectric layer extends to cover at least a portion of the top surface of the semiconductor pattern, and The vertical pattern of the cell passes through the gate dielectric layer and contacts the semiconductor pattern.

6. The three-dimensional semiconductor memory device according to claim 1, wherein, The substrate also includes a pseudo-cell region between the cell region and the connection region. The three-dimensional semiconductor memory device further includes a first pseudo-vertical pattern that passes through the plurality of inter-electrode dielectric layers and the plurality of electrode layers to be adjacent to the substrate. The first pseudo-vertical pattern is located on the pseudo-cell region. The bottom surface of the first pseudo-vertical pattern is closer to the substrate than the bottom surface of the first abnormal pseudo-vertical pattern.

7. The three-dimensional semiconductor memory device according to claim 6, further comprising: The unit has a vertical pattern that extends through the plurality of inter-electrode dielectric layers and the plurality of electrode layers to be adjacent to the substrate on the unit region; as well as Bit lines, which are electrically connected to the vertical pattern of the unit. The bit line is electrically insulated from the first pseudo-vertical pattern.

8. The three-dimensional semiconductor memory device of claim 6, further comprising a second anomalous pseudo-vertical pattern located on the pseudo-cell region and spaced apart from the first pseudo-vertical pattern, the second anomalous pseudo-vertical pattern passing through one or more of the plurality of inter-electrode dielectric layers and one or more of the plurality of electrode layers. in, At least one of the plurality of electrode layers is disposed between the second anomalous pseudo-vertical pattern and the substrate, and is insulated from the second anomalous pseudo-vertical pattern.

9. The three-dimensional semiconductor memory device according to claim 1, wherein, The first anomalous pseudo-vertical pattern has an upper width and a lower width parallel to a second direction, the second direction being parallel to the top surface of the substrate, and the lower width being 35% to 85% of the upper width.

10. The three-dimensional semiconductor memory device according to claim 1, in, The plurality of inter-electrode dielectric layers include: A plurality of first electrode inter-dielectric layers adjacent to the substrate; and A plurality of second electrode inter-dielectric layers, which are located on the uppermost of the plurality of first electrode inter-dielectric layers. Each of the plurality of electrode layers includes: A plurality of first electrode layers, each located between a plurality of inter-electrode dielectric layers; and Multiple second electrode layers are respectively located between the multiple second electrode dielectric layers. The plurality of inter-electrode dielectric layers and the plurality of first electrode layers constitute a first stacked structure. The plurality of inter-electrode dielectric layers and the plurality of second electrode layers constitute a second stacked structure, and The sidewall of the first abnormal pseudo-vertical pattern has an inflection point between the first stacked structure and the second stacked structure.

11. The three-dimensional semiconductor memory device according to claim 10, further comprising: A second anomalous pseudo-vertical pattern is located on the connection area and spaced apart from the first stack structure and the first anomalous pseudo-vertical pattern. The second anomalous pseudo-vertical pattern passes through the planarized dielectric layer, one or more of the plurality of second electrode inter-dielectric layers, and one or more of the plurality of second electrode layers. as well as A sacrificial burial pattern is located in the first stacked structure, and the sacrificial burial pattern is spaced apart from the second anomalous pseudo-vertical pattern in the first direction.

12. The three-dimensional semiconductor memory device according to claim 11, further comprising: A semiconductor pattern is present in the first stacked structure and between the sacrificial buried pattern and the substrate, wherein the semiconductor pattern is in contact with both the sacrificial buried pattern and the substrate.

13. The three-dimensional semiconductor memory device according to claim 11, wherein, At least one of the plurality of first electrode layers is located between the sacrificial buried pattern and the substrate.

14. The three-dimensional semiconductor memory device according to claim 1, further comprising: The unit has a vertical pattern that extends through the inter-electrode dielectric layer and the electrode layer, adjacent to the substrate on the unit region; as well as A source pattern is located between the substrate and the lowest one of the plurality of electrode dielectric layers. The source pattern is in contact with the vertical pattern of the cell and is spaced apart from the first abnormal pseudo-vertical pattern.

15. The three-dimensional semiconductor memory device according to claim 1, further comprising: The unit has a vertical pattern that extends through the plurality of inter-electrode dielectric layers and the plurality of electrode layers to be adjacent to the substrate on the unit region; as well as The peripheral circuit structure is located below the first abnormal pseudo-vertical pattern, and the peripheral circuit structure includes transistors and peripheral wiring.

16. A three-dimensional semiconductor memory device, comprising: The substrate includes cell regions and connection regions; A first stacked structure includes a plurality of inter-electrode dielectric layers and a plurality of first electrode layers alternately stacked on the substrate; The second stacked structure includes a plurality of inter-electrode dielectric layers and a plurality of second electrode layers alternately stacked on the first stacked structure; A vertical cell pattern is located on the cell region, and the vertical cell pattern passes through the first stacked structure and the second stacked structure in a first direction perpendicular to the top surface of the substrate; as well as An abnormal pseudo-vertical pattern is located on the connection region, and the abnormal pseudo-vertical pattern passes through one or more of the plurality of second electrode layers. The sidewalls of the vertical pattern of the unit have inflection points adjacent to the boundary between the first stacked structure and the second stacked structure, and Wherein, at least one of the plurality of first electrode layers is located between the anomalous pseudo-vertical pattern and the substrate in the first direction, and the anomalous pseudo-vertical pattern is insulated from the at least one first electrode layer by a gate dielectric layer surrounding its bottom surface and side surface.

17. The three-dimensional semiconductor memory device according to claim 16, wherein, The abnormal pseudo-vertical pattern extends into the first stacked structure, and The sidewalls of the anomalous pseudo-vertical pattern have inflection points adjacent to the boundary between the first stacked structure and the second stacked structure.

18. The three-dimensional semiconductor memory device according to claim 16, wherein, The abnormal pseudo-vertical pattern is spaced apart from the first stacked structure. The three-dimensional semiconductor memory device further includes a sacrificial buried pattern located in the first stacked structure and adjacent to the anomalous pseudo-vertical pattern in the first direction.

19. The three-dimensional semiconductor memory device of claim 16, further comprising a source pattern located between the substrate and the lowermost of the plurality of first electrode dielectric layers. in, The source pattern is in contact with the cell vertical pattern and is spaced apart from the abnormal pseudo-vertical pattern.

20. A three-dimensional semiconductor memory device, comprising: The peripheral circuit structure includes transistors and peripheral wiring; as well as The unit array structure is located on the peripheral circuit structure. The unit array structure includes: The first substrate includes a cell region and a connection region; A first stacked structure includes a plurality of inter-electrode dielectric layers and a plurality of first electrode layers alternately stacked on the first substrate; The second stacked structure includes a plurality of inter-electrode dielectric layers and a plurality of second electrode layers alternately stacked on the first stacked structure; An anomalous pseudo-vertical pattern, located on the connection region, penetrates one or more of the plurality of second electrode layers in a first direction perpendicular to the top surface of the substrate, and is insulated from the plurality of second electrode layers by a gate dielectric layer surrounding its bottom and side surfaces; and The sacrificial burial pattern is located in the first stacked structure on the connecting area. The sacrificial burial pattern is spaced apart from the abnormal pseudo-vertical pattern.

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