Switching Converter with Adaptive Compensation

Abstract

A switching converter, a transconductance circuit, a system, and a method are provided. The switching converter includes a voltage conversion circuit that provides an output voltage from an input voltage and a PWM voltage generated in response to first and second oscillating voltages. An input stage of the transconductance circuit provides an input reference current based on a difference between a reference voltage and a voltage depending on the output voltage and according to transconductance, and an output stage is configured to provide an output reference current based on the input reference current. A phase shifter shifts an oscillating reference voltage based on the output reference current to obtain the first and second oscillating voltages. The transconductance is controlled in response to the input voltage, resulting in a change in the input reference current. Compensation for such a change is provided by subtracting a variable compensation current generated in response to the input voltage from the input reference current.

Description

[0001] Priority Claim

[0002] This application claims priority to Italian Patent Application No. 102020000000844, filed on January 17, 2020, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] The present invention generally relates to the field of switched converters, and more particularly to a DC-DC switched converter for converting a DC input voltage into a DC output voltage different from the input voltage. More specifically, the present invention relates to a time-based DC-DC switched converter capable of operating with sufficient gain and stability over a wide range of input voltage values. Background Art

[0004] DC-DC switched converters can be used in any electronic system, including power sources (such as batteries) and one or more electronic / electromechanical components, each operating at its respective voltage: in such an electronic system, the DC-DC switched converter can be configured to generate multiple controlled output voltages based on a (single) input voltage provided by the power source.

[0005] This allows for space savings as it avoids using multiple power sources within the electronic system to power its different components.

[0006] Recently, time-based DC-DC switched converters have been developed, in which time-based control elements are used in place of broadband error amplifiers, analog or digital pulse width modulators, and high-resolution analog-to-digital converters (ADCs).

[0007] The time-based DC-DC switched converter is disclosed in "High Frequency Buck Converter Design Using Time-Based Control Techniques" by S.J. Kim et al. in Volume 50, Issue 4 of the IEEE Journal of Solid-State Circuits in April 2015 (incorporated by reference).

[0008] Such a time-based DC-DC switched converter includes a PID ("Proportional Integral Derivative") controller (i.e., a control loop mechanism configured to continuously calculate an error value as the difference between a desired setpoint and a measured process variable and apply corrections based on proportional, integral, and derivative terms), where the integral action is implemented by a current-controlled ring oscillator circuit, and the proportional and derivative actions are implemented by a differential transconductor circuit loaded with a controlled phase shift circuit.

[0009] Known time-based DC-DC switching converters are unsatisfactory for modern technological requirements, especially for applications that require a wide range of values for the desired input voltage. In fact, in the case of a wide range of values of the input voltage, a PID controller must be designed to ensure stability in the worst-case scenario (i.e., when the input voltage takes a high value). However, such a design criterion determines a low bandwidth at low values of the input voltage.

[0010] In other words, in known time-based DC-DC switching converters, a limited bandwidth at low values of the input voltage is traded for sufficient phase margin at high values of the input voltage.

[0011] In the art, there is a need to solve the above problems and provide a switching converter that achieves adaptive compensation and can ensure sufficient gain and phase margin / stability under both high and low input voltage conditions. Summary of the Invention

[0012] One aspect of the present invention relates to a switching converter for converting a DC input voltage into a DC output voltage. The switching converter includes: a signal generator circuit for providing a pulse width modulation voltage based on a phase shift between a first oscillation voltage and a second oscillation voltage; a voltage conversion circuit for providing an output voltage based on the input voltage and the pulse width modulation voltage; a transconductance circuit including an input stage and an output stage, the input stage for providing an input reference current based on the difference between a reference voltage and a working voltage depending on the output voltage and based on a transconductance value associated with the transconductance circuit, the output stage for providing an output reference current based on the input reference current; and a phase shift circuit for applying a phase shift to an oscillation reference voltage based on the output reference current to obtain the first oscillation voltage and the second oscillation voltage.

[0013] The switching converter further includes: an adjustment circuit for adjusting the transconductance value according to the input voltage, the adjustment of the transconductance value resulting in a change in the input reference current; and a compensation circuit for compensating for the change in the output reference current caused by the change in the input reference current.

[0014] According to one embodiment, in addition to or as an alternative to any of the foregoing embodiments, the adjustment circuit includes a biasing circuit for biasing the input stage with a bias current depending on the input voltage. The input reference current includes the bias current. The compensation circuit includes: a mirroring circuit for mirroring the input reference current to the output stage; and an additional biasing circuit for biasing the output stage with an additional bias current depending on the input voltage, the additional bias current compensating for the bias current.

[0015] According to one embodiment, additional to or alternative to any of the foregoing embodiments, the bias current is inversely proportional to the input voltage.

[0016] According to one embodiment, additional to or alternative to any of the foregoing embodiments, the input reference current includes a first input reference current and a second input reference current each including a respective portion of the bias current described above. The additional bias current includes a first additional bias current and a second additional bias current respectively corresponding to the portions of the bias current included in the first input reference current and the second input reference current.

[0017] According to one embodiment, additional to or alternative to any of the foregoing embodiments, the input stage includes a transistor-based differential input stage. The first input reference current and the second input reference current each include half of the bias current described above.

[0018] According to one embodiment, additional to or alternative to any of the foregoing embodiments, the mirror circuit includes: a first transistor-based current mirror for mirroring the first input reference current and a second transistor-based current mirror for mirroring the second input reference current. The first transistor-based current mirror and the second transistor-based current mirror are coupled to the input stage.

[0019] According to one embodiment, additional to or alternative to any of the foregoing embodiments, the switching converter further includes an additional transconductance circuit configured to provide an additional output reference current based on the difference between the reference voltage and the operating voltage and based on a transconductance value associated with the additional transconductance circuit. The switching converter further includes a reference voltage generation circuit for generating the oscillation reference voltage based on the additional output reference current. The switching converter is a time-based switching converter. The transconductance circuit, the voltage generation circuit, and the phase shift circuit determine the proportional-integral-derivative controller of the time-based switching converter.

[0020] According to one embodiment, additional to or alternative to any of the foregoing embodiments, the switching converter is a buck converter.

[0021] Another aspect of the present invention relates to an electronic system including such a switching converter.

[0022] Another aspect of the present invention relates to a method for converting a DC input voltage into a DC output voltage. The method includes: providing a pulse width modulation voltage according to a phase shift between a first oscillation voltage and a second oscillation voltage; providing an output voltage according to the input voltage and the pulse width modulation voltage; providing an input reference current at an input stage of a transconductance circuit according to a difference between a reference voltage and an operating voltage depending on the output voltage and according to a transconductance value associated with the transconductance circuit; providing an output reference current at an output stage of the transconductance circuit based on the input reference current; and phase-shifting an oscillation reference voltage according to the output reference current to obtain the first oscillation voltage and the second oscillation voltage.

[0023] The method further includes: adjusting the transconductance value according to the input voltage, the adjustment of the transconductance value causing a change in the input reference current; and compensating for a change in the output reference current caused by the change in the input reference current. Description of the Drawings

[0024] These and other features and advantages of the present invention will become apparent from the following description of some exemplary and non-limiting embodiments. For a better understanding, the following description should be read with reference to the drawings, in which:

[0025] Figure 1 A block diagram of a time-based switching converter to which embodiments can be applied is shown;

[0026] Figure 2 Shows Figure 1 A known circuit implementation of a part of the switching converter; and

[0027] Figure 3 Shows according to one embodiment Figure 1 A circuit implementation of a part of the switching converter. Detailed Description

[0028] Referring to the drawings, Figure 1 A block diagram of a time-based switching converter (or switching regulator) 100 to which embodiments can be applied is shown.

[0029] According to one embodiment, the switching converter 100 is a DC-DC switching converter, i.e., configured to convert a direct current (DC) input voltage V IN into a direct current (DC) output voltage V OUT (the output voltage V OUT is different from the input voltage V IN ) switching converter.

[0030] According to one embodiment, the output voltage V OUT is lower than the input voltage V IN, that is, the switching converter 100 is a buck converter (or step-down converter). However, these principles equally apply to other switching converters, such as a boost converter (or step-up converter) where the output voltage V OUT is higher than the input voltage V IN , or a combination of a buck converter and a boost converter (or buck-boost converter).

[0031] Without loss of generality, the switching converter 100 can be used in any electronic system including a power source (such as a battery) and one or more electronic / electromechanical components each operating at its respective voltage: in such an electronic system, the switching converter 100 (or multiple switching converters 100) can be configured to generate multiple controlled output voltages based on a single input voltage provided by the power source (thereby saving space as it avoids using multiple power sources within the electronic system to power its different components). Examples of such electronic systems include desktop computers, servers, laptop computers, media players (such as MP3 players), appliances, sub-notebooks / netbooks, tablet computers, smartphones, cellular phones, network devices, personal digital assistants (PDAs), toys, controllers, digital signal processors, gaming consoles, device controllers, portable computing devices, and / or portable electronic devices.

[0032] According to one embodiment, the switching converter 100 is a time-based switching converter, that is, a switching converter that uses time-based control techniques instead of a broadband error amplifier, an analog or digital pulse width modulator, or a high-resolution analog-to-digital converter (ADC).

[0033] According to one embodiment, the switching converter 100 includes an input terminal T IN for receiving the input voltage V IN and an output terminal T OUT for providing the output voltage V OUT .

[0034] According to one embodiment, the switching converter 100 includes a phase detector circuit 105 for detecting the phase shift between a first oscillating voltage V1 and a second oscillating voltage V2 and for providing a pulse width modulation voltage V PMW based on the phase shift between the first oscillating voltage V1 and the second oscillating voltage V2.

[0035] According to one embodiment, the phase detector circuit 105 can be based on a logic circuit including one or more RS latches (or flip-flops).

[0036] According to one embodiment, the switching converter 100 includes for receiving the input voltage V IN and for, based on the input voltage V IN and the pulse width modulation voltage VPMW Provide an output voltage V OUT of the switching circuit 110.

[0037] According to one embodiment, the switching circuit 110 includes a power stage circuit, such as a CMOS power stage circuit.

[0038] According to one embodiment, the power stage circuit includes a high-side switching element (e.g., a PMOS transistor) 110 H and a low-side switching element (e.g., an NMOS transistor) 110 L .

[0039] In the exemplary embodiment under consideration, the high-side PMOS transistor 110 H includes a source terminal electrically coupled (e.g., directly connected) to the input terminal T IN for receiving the input voltage V IN , a gate terminal for receiving the PWM voltage V PWM (or its regenerated version, as described below), and a drain terminal electrically coupled (e.g., directly connected) to the output terminal T of the switching converter 100 OUT .

[0040] In the exemplary embodiment under consideration, the low-side NMOS transistor 110 L includes a source terminal electrically connected (e.g., directly connected) to the ground terminal T GND for providing a ground voltage (e.g., 0V), a gate terminal for receiving the PWM voltage V PWM (or its regenerated version, as described below), and a drain terminal electrically coupled (e.g., directly connected) to the drain terminal of the high-side PMOS transistor 110 H .

[0041] According to one embodiment, the switching circuit 110 includes a drive stage circuit for driving the power stage circuit.

[0042] In the exemplary embodiment under consideration, the drive stage circuit includes a high-side drive circuit 110 DH (e.g., a tapered buffer arrangement) and a low-side drive circuit 110 DL (e.g., a tapered buffer arrangement), the high-side drive circuit 110 DH for receiving the PWM voltage V PWM and for providing its regenerated version to the high-side PMOS transistor 110 H (specifically provided to the gate terminal of the high-side PMOS transistor 110 H ), the low-side drive circuit 110 DL for receiving the PWM voltage V PWMand for providing its regenerated version to the low-side NMOS transistor 110 L (specifically to the low-side NMOS transistor 110 L to the gate terminal thereof).

[0043] According to one embodiment, the switching circuit 110 includes a filter circuit electrically coupled to the drain terminal of the high-side PMOS transistor 110 H (and thus coupled to the drain terminal of the low-side NMOS transistor 110 L to the drain terminal thereof).

[0044] According to one embodiment, the filter circuit includes an LC filter circuit.

[0045] According to one embodiment, the filter circuit includes: an inductor element 110 IND (or a plurality of inductor elements 110 IND ), the first terminal of the inductor element 110 IND is electrically coupled (e.g., directly connected) to the drain terminal of the high-side PMOS transistor 110 H (and thus electrically coupled to the drain terminal of the low-side NMOS transistor 110 L to the drain terminal thereof), and the second terminal of the inductor element 110 IND is electrically coupled (e.g., directly connected) to the output terminal T of the switching converter 100 OUT ; and a capacitor 110 CAP (or a plurality of capacitors 110 CAP ), the first terminal of the capacitor 110 CAP is electrically coupled (e.g., directly connected) to the first terminal of the inductor element 110 IND (and thus electrically coupled to the output terminal T of the switching converter 100 OUT ) and the second terminal of the capacitor 110 CAP is electrically coupled (e.g., directly connected) to the ground terminal T GND .

[0046] Thus, in the embodiment under consideration, the drain terminal of the high-side PMOS transistor 110 H (and equivalently, the drain terminal of the low-side NMOS transistor 110 L ) is electrically coupled to the output terminal T of the switching converter 100 through the filter stages 110 IND , 110 CAP . OUT .

[0047] According to one embodiment, the switching converter 100 includes one or more (three in the example under discussion) transconductance circuits 1151, 1152, 1153.

[0048] According to one embodiment, each transconductor circuit 1151, 1152, 1153 is associated with a respective transconductance value.

[0049] According to one embodiment, each transconductor circuit 1151, 1152, 1153 has a non-inverting input terminal (represented in the figure by "IN REF ") for receiving a reference voltage (e.g., a DC reference voltage) V + , an inverting input terminal (represented in the figure by "IN OUT ") electrically coupled to the output terminal T OUT for receiving a respective operating voltage depending on the output voltage V - ", a non-inverting output terminal (represented in the figure by "OUT REF ") for providing a respective first reference current according to the difference between the reference voltage V + and the respective operating voltage and according to the transconductance value associated with the transconductor circuit, and an inverting output terminal (represented in the figure by "OUT - ") for providing a second reference current opposite in value to the first reference current (as further described below, the first oscillating voltage V1 and the second oscillating voltage V2 depend on the first reference current and the second reference current).

[0050] As will be further discussed below when discussing known implementations of transconductor circuits and implementations of transconductor circuits according to one embodiment, each transconductor circuit is a differential transconductor circuit configured to convert the voltage difference between the reference voltage V REF and the respective operating voltage into a corresponding differential current (depending on the transconductance value associated with the transconductor circuit), and the first reference current and the second reference current provided by the non-inverting and inverting output terminals of each transconductor circuit respectively correspond to such differential currents in opposite directions relative to each other, and the differential current includes a common-mode current component.

[0051] Hereinafter, the first reference current and the second reference current will be represented by the same reference numeral (indicating that the first reference current and the second reference current in the module are equal), except for the negative sign ("-") associated with the second reference current (referring to the (same) direction shown in the figure for the first reference current and the second reference current, indicating that the actual directions of the first reference current and the second reference current are opposite to each other).

[0052] According to one embodiment, the transconductor circuit 1151 is configured to receive the operating voltage V OP1 and provide a first reference current I REF1 and a second reference current -I REF1 , and each of the transconductor circuits 1152, 1153 is configured to receive the operating voltage VOP23 and respectively provide a first reference current I REF2 , I REF3 and a second reference current -I REF2 , -I REF3 .

[0053] According to one embodiment, the in-phase output terminal of the transconductor circuit 1151 is electrically coupled (e.g., directly connected) to the in-phase output terminal of the transconductor circuit 1152.

[0054] According to one embodiment, the anti-phase output terminal of the transconductor circuit 1151 is electrically coupled (e.g., directly connected) to the anti-phase output terminal of the transconductor circuit 1152.

[0055] According to one embodiment, the operating voltage V OP1 is a filtered version of the output voltage V OUT .

[0056] According to one embodiment, the switching converter 100 includes a high-pass filter circuit 120 for filtering the output voltage V OUT into the operating voltage V OP1 .

[0057] According to one embodiment, the high-pass filter circuit 120 includes: a capacitor 120 CAP (or a plurality of capacitors 120 CAP ), a first terminal of the capacitor 120 CAP is electrically coupled (e.g., directly connected) to the output terminal T OUT of the switching converter 100 and a second terminal of the capacitor 120 CAP is electrically coupled (e.g., directly connected) to the anti-phase input terminal of the transconductor circuit 1151; and a resistor 120 R , a first terminal of the resistor 120 R is electrically coupled (e.g., directly connected) to the anti-phase input terminal of the transconductor circuit 1151 and a second terminal of the resistor 120 R is used to electrically receive the reference voltage V REF .

[0058] Thus, in the considered embodiment, the operating voltage V OP1 is a voltage indicating a voltage change affecting the output voltage V OUT . According to one embodiment, depending on the sizing of the high-pass filter, the voltage change "detected" by the high-pass filter 120 is a fast or relatively fast voltage change.

[0059] According to one embodiment, the operating voltage V OP23 is the output voltage V OUTA scaled version.

[0060] According to one embodiment, the switching converter 100 includes a voltage divider circuit 125 for scaling the output voltage V OUT to the operating voltage V OP23 .

[0061] According to one embodiment, the voltage divider circuit 125 includes: a resistor 125 R1 , the first terminal of which is electrically coupled (e.g., electrically connected) to the output terminal T of the switching converter 100 R1 , and the second terminal of which is electrically coupled (e.g., directly connected) to the inverting input terminals of the transconductance circuits 1152, 1153; and a resistor 125 OUT , the first terminal of which is electrically coupled (e.g., directly connected) to the inverting input terminals of the transconductance circuits 1152, 1153, and the second terminal of which is electrically coupled (e.g., directly connected) to the ground terminal T R1 . R2 , the first terminal of which is electrically coupled (e.g., directly connected) to the inverting input terminals of the transconductance circuits 1152, 1153, and the second terminal of which is electrically coupled (e.g., directly connected) to the ground terminal T R2 . R2 GND GND .

[0062] According to one embodiment, the switching converter 100 includes a plurality of current-controlled ring oscillator circuits configured to provide respective oscillating reference signals based on one or more reference currents.

[0063] According to one embodiment, the switching converter 100 includes two current-controlled ring oscillator circuits, namely, a first current-controlled ring oscillator circuit 1301 and a second current-controlled ring oscillator circuit 1302. The first current-controlled ring oscillator circuit 1301 is electrically coupled (e.g., directly connected) to the inverting output terminal of the transconductance circuit 1153 for receiving a second reference current -I REF3 and providing a first oscillating reference voltage V OSC1 , and the second current-controlled ring oscillator circuit 1302 is electrically coupled (e.g., directly connected) to the non-inverting output terminal of the transconductance circuit 1153 for receiving a first reference current I REF3 and providing a second oscillating reference voltage V OSC2 (as further discussed below, the first oscillating voltage V1 and the second oscillating voltage V2 depend on the first oscillating reference voltage V OSC1 and the second oscillating reference voltage V OSC2 respectively).

[0064] According to an embodiment not shown, the first oscillating reference voltage V OSC1 and the second oscillating reference voltage V OSC2 ​​is generated outside the switching converter 100, in which case, the transconductance circuit 1153 and / or the first current-controlled ring oscillator circuit 1301 and the second current-controlled ring oscillator circuit 1302 may be omitted.

[0065] According to one embodiment, the switching converter 100 includes a current-controlled phase-shift circuit for obtaining a first oscillation voltage V1 and a second oscillation voltage V2 by performing a phase shift on a first oscillation reference voltage V CTRL1 and a second oscillation reference voltage V CTRL2 in accordance with a first control current I OSC1 and a second control current I OSC2 .

[0066] According to one embodiment, the first control current I CTRL1 is equal to the sum of a second reference current -I REF1 provided by the transconductance circuit 1151 and a second reference current -I REF2 provided by the transconductance circuit 1152 (i.e., I CTRL1 = -I REF1 - I REF2 = -(I REF1 + I REF2 ))), and the second control current I CTRL2 is equal to the sum of a first reference current I REF1 provided by the transconductance circuit 1151 and a first reference current I REF2 provided by the transconductance circuit 1152 (i.e., I CTRL2 = I REF2 + I REF1 ), and thus, the second control current I CTRL2 and the first control current I CTRL1 are opposite to each other.

[0067] According to one embodiment, the switching converter 100 includes a first current-controlled phase-shift circuit 1351 and a second current-controlled phase-shift circuit 1352. The first current-controlled phase-shift circuit 1351 is electrically coupled (e.g., directly connected) to the inverting output terminal of the transconductance circuit 1151 (and thus electrically coupled to the inverting output terminal of the transconductance circuit 1152) for receiving the first control current I CTRL1 , is electrically coupled (e.g., directly connected) to the first current-controlled ring oscillator circuit 1301 for receiving the first oscillation reference voltage V OSC1 and is electrically coupled (e.g., directly connected) to the phase detector circuit 105 to, in accordance with the first oscillation reference voltage V OSC1 and the first control current I CTRL1A first oscillating voltage V1 is provided, and the second current-controlled phase-shift circuit 1352 is electrically coupled (e.g., directly connected) to the in-phase output terminal of the transconductance circuit 1151 (and thus electrically coupled to the in-phase output terminal of the transconductance circuit 1152) for receiving a second control current I CTRL2 and is electrically coupled (e.g., directly connected) to the second current-controlled ring oscillator circuit 1302 for receiving a second oscillating reference voltage V OSC2 and is electrically coupled (e.g., directly connected) to the phase detector circuit 105 to provide a second oscillating voltage V2 in accordance with the second oscillating reference voltage V OSC2 and the second control current I CTRL2

[0068] According to one embodiment, each current-controlled phase-shift circuit 1351, 1352 includes an n-stage CMOS inverter cascade (the size of n is determined according to a specific design option), which should not be construed as a limitation, however.

[0069] As disclosed in the above-cited article "High Frequency Buck Converter Design Using Time-Based Control Techniques", the transconductance circuits 1151, 1152, 1153, the high-pass filter 120, the current-controlled ring oscillator circuits 1301, 1302, and the current-controlled phase-shift circuits 1351, 1352 together determine a PID ("Proportional Integral Derivative") controller, i.e., a control loop mechanism configured to continuously calculate an error value as the difference between a desired setpoint and a measured process variable and apply corrections based on proportional, integral, and derivative terms.

[0070] Now referring to Figure 2 Figure 2 FIG. shows a known circuit implementation of a portion of the switching converter 100. In particular Figure 2 FIG. shows a known circuit implementation of the transconductance circuits 1151, 1152.

[0071] As can be seen in the figure, each transconductance circuit 1151, 1152 includes a conventional input differential stage.

[0072] In particular, the input differential stage of the transconductance circuit 1151 includes a first input transistor (e.g., a PMOS transistor) 2051 and a second input transistor (e.g., a PMOS transistor) 2101 coupled to each other in a conventional differential configuration.

[0073] More specifically, the first input transistor 2051 has a receiving operating voltage V OP1 ​​The gate terminal (the gate terminal of the first input transistor 2051 thus represents the inverting input terminal of the transconductor circuit 1151), providing a first reference current I REF1 The drain terminal (the drain terminal of the first input transistor 2051 thus represents the non-inverting output terminal of the transconductor circuit 1151), and the source terminal. The second input transistor 2101 has a gate terminal receiving a reference voltage V REF The gate terminal (the gate terminal of the second input transistor 2101 thus represents the non-inverting input terminal of the transconductor circuit 1151), providing a second reference current -I REF1 The drain terminal (the drain terminal of the second input transistor 2101 thus represents the inverting output terminal of the transconductor circuit 1151), and the source terminal electrically coupled to the source terminal of the first input transistor 2051.

[0074] According to an exemplary non-limiting embodiment contemplated herein, the input differential stage of the transconductor circuit 1151 further includes: a first input resistor 2151, a first terminal of the first input resistor 2151 being electrically coupled (e.g., directly connected) to the source terminal of the first input transistor 2051; and a second input resistor 2201, a first terminal of the second input resistor 2201 being electrically coupled (e.g., directly connected) to the source terminal of the second input transistor 2101 and a second terminal of the second input resistor 2201 being electrically coupled (e.g., directly connected) to a second terminal of the first input resistor 2151.

[0075] The input differential stage of the transconductor circuit 1152 includes a first input transistor (e.g., a PMOS transistor) 2052 and a second input transistor (e.g., a PMOS transistor) 2102 coupled to each other in a conventional differential configuration.

[0076] More specifically, the first input transistor 2052 has a gate terminal receiving an operating voltage V OP23 The gate terminal (the gate terminal of the first input transistor 2052 thus represents the non-inverting input terminal of the transconductor circuit 1152), providing a first reference current I REF2 The drain terminal (the drain terminal of the first input transistor 2052 thus represents the non-inverting output terminal of the transconductor circuit 1152), and the source terminal. The second input transistor 2102 has a gate terminal receiving a reference voltage V REF The gate terminal (the gate terminal of the second input transistor 2102 thus represents the non-inverting input terminal of the transconductor circuit 1152), providing a second reference current -I REF2 The drain terminal (the drain terminal of the second input transistor 2102 thus represents the inverting output terminal of the transconductor circuit 1152), and the source terminal electrically coupled to the source terminal of the first input transistor 2052.

[0077] According to the exemplary and non-limiting embodiments contemplated herein, the input differential stage of the transconductor circuit 1152 further includes: a first input resistor 2152, a first terminal of the first input resistor 2152 being electrically coupled (e.g., directly connected) to the source terminal of the first input transistor 2052; and a second input resistor 2202, a first terminal of the second input resistor 2202 being electrically coupled (e.g., directly connected) to the source terminal of the second input transistor 2102 and a second terminal of the second input resistor 2202 being electrically coupled (e.g., directly connected) to the second terminal of the first input resistor 2152.

[0078] As can be seen in the figure, the drain terminal of the first input transistor 2051 of the transconductor circuit 1151 is electrically coupled (e.g., directly connected) to the drain terminal of the first input transistor 2052 of the transconductor circuit 1152, whereby a first reference current I provided by the transconductor circuit 1151 REF1 and a first reference current I provided by the transconductor circuit 1152 REF2 are added to each other and generate a second control current I CTRL2 ; the drain terminal of the second input transistor 2101 of the transconductor circuit 1151 is electrically coupled (e.g., directly connected) to the drain terminal of the second input transistor 2102 of the transconductor circuit 1152, whereby a second reference current -I provided by the transconductor circuit 1151 REF1 and a second reference current -I provided by the transconductor circuit 1152 REF2 are added to each other and generate a first control current I CTRL1 .

[0079] As can be seen in the figure, each of the transconductor circuits 1151, 1152 further includes known tail bias current sources 2251, 2252, typically represented by a conventional electrical symbol for an ideal current generator.

[0080] Each of the tail bias current sources 2251, 2252 is electrically coupled (e.g., directly connected) between a power supply terminal providing a power supply DC voltage V DD and the source terminals of the first input transistors 2051, 2052 and the second input transistors 2101, 2102, respectively, thereby respectively using a first bias current I BIAS1 and a second bias current I BIAS2Input differential stages of the offset transconductance circuits 1151, 1152. In the example being discussed where the input differential stage of transconductance circuit 1151 includes a first input resistor 2151 and a second input resistor 2201 and the input differential stage of transconductance circuit 1152 includes a first input resistor 2152 and a second input resistor 2202, each tail bias current source 2251, 2252 is electrically coupled (e.g., directly connected) between the power supply terminal and the second terminal of the first input resistors 2151, 2152 (and thus the first terminal of the second input resistors 2201, 2202).

[0081] Thus, according to well-known principles, each of the first reference currents I REF1 , I REF2 and the second reference currents -I REF1 , -I REF2 includes a differential reference current (i.e., a current generated due to the difference / imbalance between the reference voltage V REF and the operating voltages V OP1 , V OP23 ) and (i.e., superimposed therewith) half of the corresponding bias current (i.e., I BIAS1 / 2, I BIAS2 / 2).

[0082] It can be easily verified that the transfer function H PID (s) of the PID controller can conceptually be represented as:

[0083]

[0084] Where:

[0085] -K CCDL is the gain of the first current-controlled phase-shift circuit 1351 and the second current-controlled phase-shift circuit 1352;

[0086] -K CCO is the gain of the first current-controlled ring oscillator circuit 1301 and the second current-controlled ring oscillator circuit 1302;

[0087] _Gm1 is the gain of the transconductance circuit 1151 and, for example, corresponds to the transconductance value associated with the transconductance circuit 1151;

[0088] _Gm2 is the gain of the transconductance circuit 1152 and, for example, corresponds to the transconductance value associated with the transconductance circuit 1152;

[0089] -Gm3 is the gain of the transconductance circuit 1153 and, for example, corresponds to the transconductance value associated with the transconductance circuit 1153;

[0090] -CD is the capacitance value associated with capacitor 120 CAP ; and

[0091] _R D is the resistance value associated with resistor 120 R ;

[0092] It should be noted that, in the case of a wide range of values of the input voltage V IN , the PID controller must be designed to ensure stability in the worst-case scenario (i.e., when the input voltage V IN takes a high value). However, such a design criterion determines a low bandwidth under low values of the input voltage V IN . In other words, it should be understood that in the known circuit implementation of the switching converter 100, a limited bandwidth under low values of the input voltage V IN is traded for sufficient phase margin under high values of the input voltage V IN .

[0093] Now referring to Figure 3 , Figure 3 shows a circuit implementation of a part of the switching converter 100 according to an embodiment. In particular, Figure 3 shows a circuit implementation of the transconductor circuits 1151, 1152 according to an embodiment.

[0094] According to an embodiment, the transconductor circuits 1151, 1152 have the same circuit implementation.

[0095] According to an embodiment, each of the transconductor circuits 1151, 1152 includes: an input stage for providing a respective input reference current according to the difference between the reference voltage V REF and the operating voltage V OP1 , V OP23 ; and an output stage for providing an output reference current based on the input reference current (i.e., reference currents I REF1 , -I REF1 and reference currents I REF2 , -I REF2 ).

[0096] According to an embodiment, the input stage of the transconductor circuits 1151, 1152 includes a differential stage.

[0097] According to an embodiment, the input stage of the transconductor circuits 1151, 1152 includes: a first input transistor (e.g., an NMOS transistor) 3051, 3052 and a second input transistor (e.g., an NMOS transistor) 3101, 3102 coupled to each other in a differential configuration.

[0098] According to one embodiment, the first input transistors 3051, 3052 have gate terminals that receive operating voltages V OP1 , V OP23 (the gate terminals of the first input transistors 3051, 3052 thus represent the inverting input terminals of the transconductor circuits 1151, 1152), drain terminals that provide second input reference currents -I REF1,in , -I REF2,in (as will be discussed better below, the second reference currents -I REF1 , -I REF2 are obtained based on the second input reference currents -I REF1,in , -I REF2,in ), and source terminals; the second input transistors 3101, 3102 have gate terminals that receive a reference voltage V REF (the gate terminals of the second input transistors 3101, 3102 thus represent the non-inverting input terminals of the transconductor circuits 1151, 1152), drain terminals that provide first input reference currents I REF1,in , I REF2,in (as will be discussed better below, the first reference currents I REF1 , I REF2 are obtained based on the second input reference currents I REF1,in , I REF2,in ), and source terminals that are electrically coupled (e.g., directly connected) to the source terminals of the first input transistors 3051, 3052.

[0099] According to one embodiment, the switching converter 100 includes an adjustment circuit for adjusting the transconductance value associated with the transconductor circuits 1151, 1152 according to the input voltage V IN .

[0100] According to one embodiment, the adjustment circuit includes bias circuits (e.g., tail bias current sources) 3151, 3152 for biasing the input stages of the transconductor circuits 1151, 1152 with respective bias currents I IN (V BIAS1 ), I IN (V BIAS2 ) (hereinafter referred to as variable bias currents) that depend on the input voltage V IN , whereby the transconductance value associated with the input stage can vary according to the input voltage V IN .

[0101] According to one embodiment, the variable bias current I BIAS1 (V IN ) is equal to the variable bias current I BIAS2 (V IN ).

[0102] According to one embodiment, the variable bias current I BIAS1 (V IN ) is different from the variable bias current I BIAS2 (V IN ).

[0103] In an example where the tail bias current sources 3151, 3152 are electrically coupled (e.g., directly connected) between the source terminals of the first input transistors 3051, 3101 and the second input transistors 3052, 3102 and the ground terminal T GND , when the switching converter 100 is in a steady state and the loop is closed, each input of the differential stage is "balanced" (i.e., V REF = V OP1 in the transconductance circuit 1151, and V REF = V OP23 in the transconductance circuit 1152), so the variable bias currents I BIAS1 (V IN ), I BIAS2 (V IN ) are split evenly between the first branch of the input stage (e.g., the branch including the first input transistors 3051, 3052) and the second branch of the input stage (e.g., the branch including the second input transistors 3101, 3102).

[0104] Thus, in this embodiment, the first input reference current I REF1,in and the second input reference current -I REF1,in each include a differential reference current (i.e., a current generated due to the difference / imbalance between the reference voltage V REF and the operating voltage V OP1 ) and (i.e., superimposed therewith) half of the variable bias current I BIAS1 (V IN ), and the first input reference current I REF2,in and the second input reference current -I REF2,in each include a differential reference current (i.e., a current generated due to the difference / imbalance between the reference voltage V REF and the operating voltage V OP23 ) and (i.e., superimposed therewith) half of the variable bias current I BIAS2 (V IN ). In any case, similar considerations apply to the case where, due to a particular design option, the first input reference currents I REF1,in , I REF2,in and the second input reference currents -I REF1,in , -I REF2,in each include the corresponding variable bias current I BIAS1 (V IN ), IBIAS2 (V IN ) corresponding part.

[0105] According to one embodiment, the tail bias current sources 3151, 3152 include a slave or controlled current source (in this case controlled by V IN ). In the figure, the conventional symbol for a controlled current source is used, which means that the tail bias current sources 3151, 3152 are not limited to any specific implementation of a controlled current source.

[0106] As conceptually shown in the figure, the tail bias current sources 3151, 3152 are electrically coupled (e.g., directly connected) to the input terminals T of the switched converter 100 IN for receiving the input voltage V IN and correspondingly generating a variable bias current I BIAS1 (V IN ), I BIAS2 (V IN ).

[0107] According to one embodiment, the variable bias currents I BIAS1 (V IN ), I BIAS2 (V IN ) are inversely proportional to the input voltage V IN (such that the transconductance values associated with the transconductor circuits 1151, 1152 decrease as the input voltage V IN increases, and increase as the input voltage V IN decreases).

[0108] According to one embodiment, the switched converter 100 includes a compensation circuit for compensating for the change in the common-mode current component of the output reference current caused by the change in the input reference current due to the adjustment of the transconductance value.

[0109] According to one embodiment, the compensation circuit includes a mirror circuit for mirroring the input reference currents I REF1,in , -I REF1,in , I REF2,in , -I REF2,in of the transconductor circuits 1151, 1152 to the corresponding output stages.

[0110] According to one embodiment, the input stage of the transconductor circuit 1151 includes a mirror circuit for mirroring the input reference currents I REF1,in , -I REF1,in to the corresponding first and second output stages of the transconductor circuit 1151, and the input stage of the transconductor circuit 1152 includes a mirror circuit for mirroring the input reference currents I REF2,in , -I REF2,inA mirror circuit that mirrors to the corresponding first output stage and second output stage of the transconductance circuit 1152.

[0111] According to one embodiment, the transconductance circuits 1151, 1152 include a first current mirror for mirroring (e.g., copying) a first input reference current I REF1,in , I REF2,in and a second current mirror for mirroring (e.g., copying) a second input reference current -I REF2,in , -I REF2,in .

[0112] According to one embodiment, the first current mirror and the second current mirror are conventional current mirrors.

[0113] According to one embodiment, the first current mirror of the transconductance circuits 1151, 1152 includes a first transistor 320 1A , 320 2A (e.g., PMOS transistor) and a second transistor 320 1B , 320 2B (e.g., PMOS transistor), that is, the source terminals of the first transistors 320 1A , 320 2A receive the power supply voltage V DD , the drain terminals of the first transistors 320 1A , 320 2A are electrically coupled (e.g., directly connected) to the drain terminals of the input transistors 3051, 3052, the gate terminals of the first transistors 320 1A , 320 2A are electrically connected to the drain terminals, the source terminals of the second transistors 320 1B , 320 2B receive the power supply voltage V DD , the gate terminals of the second transistors 320 1B , 320 2B are electrically coupled (e.g., directly connected) to the gate terminals of the first transistors 320 1A , 320 2A , and the drain terminals of the second transistors 320 1B , 320 2B provide a copy of the second input reference current -I REF1,in , -I REF2,in .

[0114] According to one embodiment, the second current mirror includes a first transistor 325 1A , 325 2A (e.g., PMOS transistor) and a second transistor 325 1B , 325 2B(e.g., PMOS transistor), i.e., the first transistor 325 1A 325 2A The source terminals of 1A and 325 receive the power supply voltage V DD The drain terminals of the first transistor 325 1A 325 2A are electrically coupled (e.g., directly connected) to the drain terminals of the input transistors 3101 and 3102. The gate terminals of the first transistor 325 1A 325 2A are electrically connected to the drain terminals. The source terminals of the second transistor 325 1B 325 2B receive the power supply voltage V DD The gate terminals of the second transistor 325 1B 325 2B are electrically coupled (e.g., directly connected) to the gate terminals of the first transistor 325 1A 325 2A The drain terminals of the second transistor 325 1B 325 2B provide a first input reference current I REF1,in I REF2,in copy.

[0115] According to one embodiment, the transconductor circuits 1151 and 1152 include first bias current sources 3301 and 3302 and second bias current sources 3351 and 3352, and each bias current source is typically represented by a conventional electrical symbol for an ideal current generator.

[0116] According to one embodiment, the first bias current sources 3301 and 3302 are electrically coupled (e.g., directly connected) between the source terminals and the drain terminals of the second transistor 320 1B 320 2B respectively, and the second bias current sources 3351 and 3352 are electrically coupled (e.g., directly connected) between the source terminals and the drain terminals of the second transistor 325 1B 325 2B respectively.

[0117] According to one embodiment, the first bias current source 3301 and the second bias current source 3351 of the transconductor circuit 1151 are designed to bias the first output stage and the second output stage of the transconductor circuit 1151 with a bias current corresponding to the first bias current I BIAS1 and the first bias current source 3302 and the second bias current source 3352 of the transconductor circuit 1152 are designed to bias the first output stage and the second output stage of the transconductor circuit 1152 with a bias current corresponding to the second bias current I BIAS2 respectively.

[0118] According to one embodiment, the first bias current sources 3301 and the second bias current sources 3351 of the transconductor circuits 1151 are designed to each provide half of a first bias current I BIAS1 (i.e., I BIAS1 / 2), and the first bias current sources 3302 and the second bias current sources 3352 of the transconductor circuits 1152 are designed to each provide half of a second bias current I BIAS2 (i.e., I BIAS2 / 2). As can be better understood from the discussion below, this design option allows the transconductor circuits 1151, 1152 to provide, through their respective output stages, the same reference currents I Figure 2 as those of the known implementation discussed in connection with REF1 -I REF1 I REF2 -I REF2 .

[0119] According to one embodiment, the compensation circuit includes additional bias circuits for biasing the output stages of each of the transconductor circuits 1151, 1152 with additional bias currents that are dependent on an input voltage V IN .

[0120] According to one embodiment, the additional bias currents are designed to compensate for the variable bias currents I BIAS1 (V IN ), I BIAS2 (V IN ), where the additional bias circuits and the additional bias currents will be referred to as compensation bias circuits and compensation bias currents, respectively.

[0121] According to one embodiment, the compensation bias circuit includes: first compensation bias current sources 3401, 3402 for biasing the first output stages of the transconductor circuits 1151, 1152 with respective compensation variable bias currents equal to half of the variable bias currents I BIAS1 (V IN ), I BIAS2 (V IN ) (i.e., I BIAS1 (V IN ) / 2, I BIAS2 (V IN ) / 2), and second compensation bias current sources 3451, 3452 for biasing the second output stages of the transconductor circuits 1151, 1152 with respective compensation variable bias currents equal to half of the variable bias currents I BIAS1 (V IN ), I BIAS2 (V IN ) (i.e., I BIAS1 (V IN ) / 2, I BIAS2 (VIN ) / 2) to bias the second output stages of the transconductor circuits 1151 and 1152.

[0122] According to this embodiment, the first input reference current I flowing through the first output stage and the second output stage of the transconductor circuit 1151 REF1,in and the second input reference current -I REF1,in Each variable bias current I included in BIAS1 (V IN ) / 2 is compensated (deleted; subtracted) by the compensation variable bias current I provided by each of the first compensation bias current source 3401 and the second compensation bias current source 3451 BIAS1 (V IN ) / 2, so that the output reference current provided by the first output stage and the second output stage of the transconductor circuit 1151 includes a first reference current I that is not affected by the input voltage change (in other words, the input voltage change affects the transconductance value Gm1 associated with the transconductor circuit 1151, but does not affect the first reference current I REF1 and the second reference current -I REF1 , so the first reference current I REF1 and the second reference current -I REF1 The common-mode voltage component of is fixed (constant) and independent of the change of the input voltage), the first reference current I REF1 and the second reference current -I REF1 (accurately implemented as Figure 2 known).

[0123] Similarly, according to this embodiment, the first input reference current I flowing through the first output stage and the second output stage of the transconductor circuit 1152 REF2,in and the second input reference current -I REF2,in Each variable bias current I included in BIAS2 (V IN ) / 2 is compensated (deleted) by the compensation variable bias current I provided by each of the first compensation bias current source 3402 and the second compensation bias current source 3452 BIAS2 (V IN ) / 2, so that the output reference current provided by the first output stage and the second output stage of the transconductor circuit 1152 includes a first reference current I that is not affected by the input voltage change (in other words, the input voltage change affects the transconductance value Gm2 associated with the transconductor circuit 1152, but does not affect the first reference current I REF2 and the second reference current -I REF2 , so the first reference current I REF2 and the second reference current -I REF2 The common-mode voltage component of is fixed (constant) and independent of the change of the input voltage), the first reference current IREF2 and a second reference current -I REF2 (exactly by a known implementation such as Figure 2 ).

[0124] In any case, in an embodiment where the first input reference current I REF1,in 、I REF2,in and the second input reference current -I REF1,in 、-I REF2,in (and thus the corresponding output reference currents) each include a corresponding variable bias current I BIAS1 (V IN )、I BIAS2 (V IN ) (except for half), each compensation variable bias current is equal to (or substantially equal to) the part of the variable bias current I BIAS1 (V IN )、I BIAS2 (V IN ) included in the corresponding input reference current.

[0125] According to one embodiment, the first compensation bias current sources 3401, 3402 are electrically coupled (e.g., directly connected) between the ground terminal T GND and the drain terminals of the second transistors 320 1B 、320 2B of the first current mirror of the transconductor circuits 1151, 1152, and such drain terminals thus represent the inverting output terminals of the transconductor circuits 1151, 1152.

[0126] According to one embodiment, the second compensation bias current sources 3451, 3452 are electrically coupled (e.g., directly connected) between the ground terminal T GND and the drain terminals of the second transistors 325 1B 、325 2B of the second current mirror of the transconductor circuits 1151, 1152, and such drain terminals thus represent the non - inverting output terminals of the transconductor circuits 1151, 1152.

[0127] As can be seen in the figure, the inverting output terminal of the transconductor circuit 1151 is electrically coupled (e.g., directly connected) to the inverting output terminal of the transconductor circuit 1152 (so that the second reference current -I REF1 provided by the transconductor circuit 1151 and the second reference current -I REF2 provided by the transconductor circuit 1152 are added to each other and generate the first control current I CTRL1 ), and the non - inverting output terminal of the transconductor circuit 1151 is electrically coupled (e.g., directly connected) to the non - inverting output terminal of the transconductor circuit 1152 (so that the first reference current IREF1 and a first reference current I provided by the transconductance circuit 1152 REF2 are added to each other and generate a second control current I CTRL2 ).

[0128] According to one embodiment, the compensating variable bias current sources 3401, 3402, 3451, 3452 include dependent or controlled current sources. In the figure, the conventional symbol of a controlled current source is used, which means that the compensating variable bias current sources 3401, 3402, 3451, 3452 are not limited to any specific implementation of a controlled current source.

[0129] As conceptually shown in the figure, each of the compensating variable bias current sources 3401, 3402, 3451, 3452 is electrically coupled (e.g., directly connected) to the input terminal T of the switched converter 100 IN for receiving an input voltage V IN and correspondingly generating a compensating variable bias current I BIAS1 (V IN ) / 2, I BIAS2 (V IN ).

[0130] The switched converter 100 (in particular, the transconductance circuits 1151, 1152) has high performance regardless of the value of the input voltage V IN .

[0131] In particular, due to the proposed arrangement of the transconductance circuits 1151, 1152, no fine-tuning action is required, and an automatic adjustment of the transconductance value associated with the transconductance circuits 1151, 1152 according to the input voltage change is achieved (which ensures sufficient gain and phase margin / stability under conditions of both high and low input voltage V IN values), while ensuring that the reference currents provided by the transconductance circuits 1151, 1152 are not affected by the input voltage change (which allows the phase shift circuits 1351, 1352 controlled by the control current).

[0132] In addition, the proposed arrangement of the transconductance circuits 1151, 1152 has a negligible impact on the power consumption, complexity, and area occupation of the switched converter 100.

[0133] Naturally, to meet local and specific requirements, those skilled in the art can apply many logical and / or physical modifications and changes to the above invention. More specifically, although the present invention has been described to a certain degree of specificity with reference to the preferred embodiments of the present invention, it should be understood that various omissions, substitutions, and changes in form and detail, as well as in other embodiments, are possible. In particular, different embodiments of the present invention can even be practiced without the specific details set forth in the foregoing description in order to provide a more comprehensive understanding of the present invention; conversely, well-known features may have been omitted or simplified so as not to encumber the description with unnecessary details. Moreover, it is expressly intended that the specific elements and / or method steps described in connection with any disclosed embodiment of the present invention can be incorporated in any other embodiment.

[0134] In particular, similar considerations apply when the switching converter has a different structure or includes equivalent components. In any case, any of its components can be divided into several elements, or two or more components can be combined into a single element; in addition, each component can be replicated to support the parallel execution of corresponding operations. It should also be noted (unless otherwise stated) that any interaction between different components generally does not need to be continuous and can be direct or indirect through one or more intermediaries.

[0135] One or more aspects of the present invention are set forth in the independent claims, and the advantageous features of the present invention are pointed out in the dependent claims, the wording of which is hereby incorporated by reference in its entirety (the advantageous features provided with reference to a specific aspect of the present invention apply, mutatis mutandis, to any other aspect in detail).

Claims

1. A switching converter for converting a DC input voltage into a DC output voltage, wherein the switching converter comprises: A signal generator circuit for providing a pulse width modulation voltage in accordance with a phase shift between a first oscillation voltage and a second oscillation voltage; A voltage conversion circuit for providing the output voltage in response to the input voltage and the pulse width modulation voltage; A transconductance circuit, comprising: An input stage for providing an input reference current based on a difference between a reference voltage and an operating voltage depending on the output voltage, and based on a transconductance value associated with the transconductance circuit, and An output stage for providing a differential output reference current based on the input reference current, the differential output reference current comprising a positive output reference current and a negative output reference current; and A phase shift circuit comprising a first phase shifter and a second phase shifter, the first phase shifter applying a first phase shift controlled by the positive output reference current to generate the first oscillation voltage, and the second phase shifter applying a second phase shift controlled by the negative output reference current to generate the second oscillation voltage; Wherein the transconductance circuit further comprises: An adjustment circuit for adjusting the transconductance value according to the input voltage, wherein the adjustment of the transconductance value results in a change in the input reference current; and A compensation circuit configured to subtract a compensation current from the input reference current to generate the positive output reference current and the negative output reference current, wherein the compensation current is generated in response to the input voltage.

2. The switching converter according to claim 1, wherein the adjustment circuit comprises a bias circuit for biasing the input stage with a bias current depending on the input voltage, the input reference current comprising the bias current, and wherein the compensation circuit comprises: A mirror circuit for mirroring the input reference current to the output stage, and An additional bias circuit for biasing the output stage with the compensation current generated depending on the input voltage.

3. The switching converter according to claim 2, wherein the bias current is inversely proportional to the input voltage.

4. The switching converter according to claim 2, wherein the input reference current comprises a first input reference current and a second input reference current, each of the first input reference current and the second input reference current comprising a respective portion of the bias current, and wherein the compensation current comprises a first compensation current and a second compensation current, the first compensation current and the second compensation current corresponding respectively to the portions of the bias current comprised in the first input reference current and the second input reference current.

5. The switching converter according to claim 4, wherein the input stage comprises a transistor-based differential input stage, each of the first input reference current and the second input reference current comprising half of the bias current.

6. The switching converter according to claim 4, wherein the mirror circuit includes: A first transistor-based current mirror for mirroring the first input reference current and a second transistor-based current mirror for mirroring the second input reference current, the first transistor-based current mirror and the second transistor-based current mirror being coupled to the input stage.

7. The switching converter according to claim 1, further comprising a high-pass filter circuit configured to generate the operating voltage depending on the output voltage.

8. The switching converter according to claim 1, further comprising a voltage divider circuit configured to generate the operating voltage depending on the output voltage.

9. The switching converter according to claim 1, further comprising: A second transconductance circuit, comprising: A second input stage for providing a second input reference current based on the difference between the reference voltage and a second operating voltage depending on the output voltage, and according to a transconductance value associated with the second transconductance circuit, and A second output stage for providing a second differential output reference current based on the second input reference current, the second differential output reference current comprising a second positive output reference current and a second negative output reference current; wherein the first phase shift of the first phase shifter is further controlled by the second positive output reference current; and wherein the second phase shift of the second phase shifter is further controlled by the second negative output reference current.

10. The switching converter according to claim 9, wherein the second transconductance circuit further comprises: A second regulation circuit for regulating the transconductance value according to the input voltage, wherein the regulation of the transconductance value results in a change in the second input reference current; and A second compensation circuit configured to subtract a compensation current from the second input reference current to generate the second positive output reference current signal and the second negative output reference current signal, wherein the compensation current is generated in response to the input voltage.

11. The switching converter according to claim 10, wherein the compensation current ensures that the differential output reference current has a constant common-mode current regardless of the regulation of the transconductance value.

12. The switching converter according to claim 1, further comprising: A first current-controlled oscillator configured to generate a first oscillator signal applied to the input of the first phase shifter; and A second current-controlled oscillator configured to generate a first oscillator signal applied to the input of the first phase shifter.

13. The switching converter according to claim 12, further comprising: A third transconductance circuit that generates a third differential output reference current in response to the difference between the reference voltage and an operating voltage depending on the output voltage; the third differential output reference current comprising a third positive output reference current signal and a third negative output reference current signal; wherein the first current-controlled oscillator is biased by the third positive output reference current signal, and wherein the second current-controlled oscillator is biased by the third negative output reference current signal.

14. The switching converter according to claim 12, wherein the switching converter is a time-based switching converter, and the transconductor circuit, the first current-controlled oscillator circuit and the second current-controlled oscillator circuit, and the first phase shifter and the second phase shifter of the phase shift circuit identify the proportional-integral-derivative controller of the time-based switching converter.

15. The switching converter according to claim 1, wherein the compensating current ensures that the differential output reference current has a constant common-mode current, regardless of the adjustment of the transconductance value.

16. The switching converter according to claim 1, wherein the switching converter is a buck converter.

17. An electronic system, comprising at least one switching converter according to claim 1.

18. A transconductor circuit, comprising: An input stage, including a first variable current source that generates a variable bias current in response to a control signal, the variable bias current being configured to bias a differential input transistor circuit, the differential input transistor circuit being configured to provide a positive input reference current and a negative input reference current in response to a difference between a first voltage and a second voltage; And An output stage, configured to provide a differential output reference current based on the positive input reference current and the negative input reference current, the differential output reference current including a positive output reference current and a negative output reference current; Wherein the output stage includes a compensation circuit, and the compensation circuit includes: A second variable current source that generates a first variable compensation current in response to the control signal, wherein the first variable compensation current is subtracted from the positive input reference current to generate the positive output reference current; And A third variable current source that generates a second variable compensation current in response to the control signal, wherein the second variable compensation current is subtracted from the negative input reference current to generate the negative output reference current.

19. The circuit according to claim 18, wherein the output stage includes: A first current mirror circuit, configured to mirror the positive input reference current to generate the positive output reference current; And A second current mirror circuit, configured to mirror the negative input reference current to generate the negative output reference current.

20. The circuit according to claim 18, wherein the output stage includes: A first fixed current source, configured to generate a first fixed bias current that is added to the positive output reference current; And A second fixed current source, configured to generate a second fixed bias current that is added to the negative output reference current.

21. The circuit according to claim 18, wherein the first variable current source provides a variable common-mode bias current component of the differential input reference current formed by the positive input reference current and the negative input reference current, and wherein the first variable compensation current and the second variable compensation current generated by the compensation circuit ensure that: the common-mode component of the differential output reference current formed by the positive output reference current and the negative output reference current is fixed, regardless of the change of the control signal.

22. A method for converting a DC input voltage into a DC output voltage, the method comprising: providing a pulse width modulation voltage based on a phase shift between a first oscillation voltage and a second oscillation voltage; providing the output voltage based on the input voltage and the pulse width modulation voltage; providing an input reference current at an input stage of the transconductance circuit based on a difference between a reference voltage and an operating voltage depending on the output voltage, and based on a transconductance value associated with the transconductance circuit, and providing an output reference current at an output stage of the transconductance circuit based on the input reference current; phase-shifting an oscillation reference voltage according to the output reference current to obtain the first oscillation voltage and the second oscillation voltage; adjusting the transconductance value according to the input voltage, the adjustment of the transconductance value causing a change in the input reference current; and subtracting a variable compensation current from the input reference current to generate the output reference current, wherein the variable compensation current is generated in response to the input voltage.

23. The method according to claim 22, wherein the variable compensation current controls the output reference current to have a common-mode component that is fixed and independent of changes in the input voltage.

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