Display device

Abstract

A display device is provided. The display device comprises: a first conductive layer, comprising a horizontal scan line and an island-type electrode spaced apart from the horizontal scan line; a first insulating layer, disposed on the first conductive layer; a second conductive layer, disposed on the first insulating layer, the second conductive layer comprising a data line and a plurality of vertical scan lines; a second insulating layer, disposed on the second conductive layer; and a third conductive layer, disposed on the second insulating layer and comprising a first shielding electrode and a second shielding electrode, the first shielding electrode covering a first edge of the vertical scan line, the second shielding electrode spaced apart from the first shielding electrode and covering a second edge of the vertical scan line, wherein the vertical scan line is electrically connected to the island-type electrode via a contact hole extending through the first insulating layer.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2020-0001865, filed on January 7, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] With the development of multimedia, display devices have become increasingly important, and various types of display devices such as organic light emitting diode (OLED) displays and liquid crystal displays (LCD) have been used. Applications of display devices have been diversified, ranging from various mobile electronic devices such as portable electronic devices such as smart phones, smart watches, and tablet personal computers (PCs).

[0004] There is a region on the outside of the glass substrate of the display device in which a driving integrated circuit (IC) or other printed circuits are mounted, and this region is a non-display region in which an image is not displayed and may be referred to as a bezel. Summary of the invention

[0005] An embodiment of the present disclosure provides a display device having a source driver and a gate driver attached to one side of a display panel of the display device, thereby providing a small non-display area.

[0006] However, the embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] An embodiment of the display device includes a first conductive layer, the first conductive layer includes a horizontal scan line extending in a first direction and an island-type electrode extending in a second direction intersecting the first direction and spaced apart from the horizontal scan line. A first insulating layer is disposed on the first conductive layer. A second conductive layer is disposed on the first insulating layer. The second conductive layer includes a data line extending in a second direction and a vertical scan line extending in the second direction. The second insulating layer is disposed on the second conductive layer. A third conductive layer is disposed on the second insulating layer and includes a first shielding electrode and a second shielding electrode, the first shielding electrode extending in the second direction and covering a first edge of the vertical scan line, the second shielding electrode extending in the second direction, spaced apart from the first shielding electrode and covering a second edge of the vertical scan line. The vertical scan line is electrically connected to the island-type electrode via a contact hole extending through the first insulating layer.

[0008] An embodiment of the display device includes a first horizontal scan line and a second horizontal scan line extending in a first direction. A first vertical scan line extends in a second direction intersecting the first direction. A first data line, a second data line, a third data line, and a fourth data line extend in the second direction and are sequentially arranged along the first direction. A first switching element is connected to the first horizontal scan line and the first data line. A second switching element is connected to the first horizontal scan line and the third data line. A third switching element is connected to the second horizontal scan line and the second data line. A fourth switching element is connected to the second horizontal scan line and the fourth data line. A first pixel electrode is connected to the first switching element. A second pixel electrode is connected to the second switching element. A third pixel electrode is connected to the third switching element. A fourth pixel electrode is connected to the fourth switching element. An island-type electrode extends in the second direction, is disposed in the same layer as the first horizontal scan line and the second horizontal scan line, and overlaps with the first vertical scan line in the thickness direction. A first shielding electrode extends in the second direction and covers a first edge of the first vertical scan line. The second shielding electrode is spaced apart from the first shielding electrode and covers a second edge of the first vertical scan line. The first vertical scan line electrically connects the first horizontal scan line and the second horizontal scan line.

[0009] According to the foregoing and other embodiments of the present disclosure, the source driver and the gate driver are attached to one side of the display panel. Therefore, a display device having a small non-display area is provided.

[0010] Other features and embodiments may be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other embodiments and features of the present disclosure will become more apparent by describing the embodiments in detail with reference to the attached drawings.

[0012] Figure 1 is a plan view of a display device according to an embodiment of the present disclosure.

[0013] Figure 2 yes Figure 1 Equivalent circuit diagram of some pixels.

[0014] Figure 3 It is shown Figure 1 An enlarged plan view of area Q.

[0015] Figure 4 is an enlarged layout diagram showing a first pixel, a second pixel, and a third pixel.

[0016] Figure 5 It is shown Figure 4 Layout diagram of the gate conductive layer.

[0017] Figure 6 It is shown Figure 4 Layout diagram of the data conductive layer.

[0018] Figure 7 yes Figure 4 Layout diagram of the pixel electrode layer.

[0019] Figure 8 It is along Figure 4 A cross-sectional view taken along line VIII-VIII'.

[0020] Fig. 9 It is along Figure 4 A cross-sectional view taken along line IX-IX'.

[0021] Fig.10 It is along Figure 4 A cross-sectional view taken along line XX'.

[0022] Fig.11 It is shown Figure 1 A cross-sectional view of the construction of a shielding electrode in a display device.

[0023] Fig.12 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0024] Fig.13 It is shown Fig.12 A cross-sectional view of the construction of a shielding electrode in a display device.

[0025] Fig.14 is a plan view of a display device according to an embodiment of the present disclosure.

[0026] Fig.15 yes Fig.14 Equivalent circuit diagram of some pixels.

[0027] Fig.16 It is shown Fig.14 A plan view of region R.

[0028] Fig.17 is an enlarged layout diagram showing a first pixel and a second pixel.

[0029] Fig.18 It is shown Fig.17 Layout diagram of the gate conductive layer.

[0030] Fig.19 It is shown Fig.17 Layout diagram of the data conductive layer.

[0031] Fig. 20 yes Fig.17 Layout diagram of the pixel electrode layer.

[0032] Fig.21 It is along Fig.17A sectional view taken along line XIX-XIX'.

[0033] Fig. 22 is a cross-sectional view of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which embodiments are shown. However, the inventive concept may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the specification, the same reference numerals represent the same components. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity.

[0035] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0036] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the inventive concept, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0037] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0038] Figure 1 is a plan view of a display device 1 according to an embodiment of the present disclosure. Figure 2 yes Figure 1 Equivalent circuit diagram of some pixels PX. Figure 3 It is shown Figure 1 An enlarged plan view of area Q.

[0039] The display device 1 will be described hereinafter as, for example, a liquid crystal display (LCD) including a liquid crystal layer.

[0040] The display device 1 can be applied to large electronic devices (e.g., televisions (TVs) or external billboards) and small and medium-sized electronic devices (e.g., personal computers, notebook computers, car navigation units, or cameras). The display device 1 can also be applied to tablet personal computers (tablet PCs), smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, watch-type electronic devices, and / or some other forms of electronic devices. All of these electronic devices are provided as examples, and the display device 1 can also be applied to other electronic devices without departing from the spirit and scope of the inventive concept of the present disclosure.

[0041] Reference Figures 1 to 3 , the display device 1 may have a display area DA and a non-display area NDA defined on the display device 1, and the non-display area NDA may be disposed around the display area DA. The display area DA may be positioned in the middle of the display device 1, and the non-display area NDA may be positioned at an edge of the display device 1 and may surround the display area DA. The display area DA may be an area in which an image is displayed, and the non-display area NDA may be an area in which an image is not displayed.

[0042] The pixels PX may be disposed in the display area DA. The pixels PX may be arranged in a matrix in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The first direction DR1 and the second direction DR2 may be perpendicular to each other. The display device 1 may have a rectangular shape in a plan view, but the plan shape of the display device 1 is not specifically limited. That is, the display device 1 may have a square shape, another polygonal shape, a circular shape, or an elliptical shape in a plan view. In the case where the display device 1 has a rectangular shape in a plan view, the first direction DR1 may be the direction of the long side of the display device 1, and the second direction DR2 may be the direction of the short side of the display device 1.

[0043] In some embodiments, the display device 1 may be applied to a public information display (PID) or a spliced ​​display (TD). In particular, a plurality of display devices 1 may be arranged in a spliced ​​display in such a way that the long side or the short side of each of the plurality of display devices 1 may be connected. Some of the plurality of display devices 1 may form one side of the spliced ​​display, some of the plurality of display devices 1 may be positioned at the corners of the spliced ​​display to form adjacent two sides of the spliced ​​display, and some of the plurality of display devices 1 may be disposed inside the spliced ​​display to be surrounded by other display devices 1. The plurality of display devices 1 may have different frame shapes depending on their positioning in the spliced ​​display, or may have the same frame shape.

[0044] The plurality of display devices 1 may be arranged in a grid shape. The plurality of display devices 1 may be connected to each other in a first direction DR1, may be connected in a second direction DR2, or may be connected to form a specific shape. The plurality of display devices 1 may have the same size. Alternatively, the plurality of display devices 1 may have different sizes.

[0045] The spliced ​​display may be a flat panel display. Optionally, the spliced ​​display may have a three-dimensional (3D) shape to provide a 3D effect. In the case where the spliced ​​display has a 3D shape, each of the multiple display devices 1 in the spliced ​​display may have a curved shape. Optionally, the multiple display devices 1 may have a flat shape and may be connected to each other at a predetermined angle to form a 3D spliced ​​display. The multiple display devices 1 may be connected so that their frames may abut each other, or may be connected via a connecting member.

[0046] An embodiment of the display device 1 which can be used alone as a single display will be described below.

[0047] The display device 1 may include a display panel DP, a driving controller SPCB disposed at one side of the display panel DP, and an integrated driver DIC connected to the driving controller SPCB.

[0048] The display panel DP may display an image using a scan signal Sn (where n is an integer of 1 or more) and a data signal Dm (where m is an integer of 1 or more).

[0049] The scan lines SL may include horizontal scan lines HSL and vertical scan lines VSL. The horizontal scan lines HSL extending in the first direction DR1, the data lines DL extending in the second direction DR2, and the vertical scan lines VSL also extending in the second direction DR2 may be disposed on the display panel DP. The vertical scan lines VSL may be disposed to be spaced apart from and parallel to the data lines DL. Some of the vertical scan lines VSL (specifically, Figure 3 The gate channel GC) can be connected to the horizontal scan line HSL. Here, the expression "connection" as used herein not only means physical connection, but also includes electrical connection. The vertical scan line VSL and the horizontal scan line HSL can be placed in contact and the vertical scan line VSL and the horizontal scan line HSL can be connected. That is, the vertical scan line VSL and the horizontal scan line HSL can be electrically connected in a manner other than that described herein. The pixel PX can be arranged at the intersection between the horizontal scan line HSL and the data line DL. The data line DL and the vertical scan line VSL can be simultaneously formed by a single mask process, but the horizontal scan line HSL can be formed by a mask process different from the mask process of the data line DL and the vertical scan line VSL.

[0050] The pixel column PXC may be disposed between a pair of adjacent vertical scan lines VSL, for example, between the first vertical scan line VSL1 and the second vertical scan line VSL2. For example, three pixel columns extending in the second direction DR2 (i.e., the first pixel column PXC1, the second pixel column PXC2, and the third pixel column PXC3) may be disposed between the first vertical scan line VSL1 and the second vertical scan line VSL2, and six data lines DL (i.e., the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6) may be disposed between the first vertical scan line VSL1 and the second vertical scan line VSL2.

[0051] Each of the gate channels GC of the vertical scan lines VSL connected to the horizontal scan lines HSL can electrically connect the two horizontal scan lines HSL. For example, the first vertical scan line VSL1 can connect the first horizontal scan line HSL1 and the second horizontal scan line HSL2, and the second vertical scan line VSL2 can connect the third horizontal scan line HSL3 and the fourth horizontal scan line HSL4. Therefore, the same scan signal can be applied to the pairs of horizontal scan lines HSL electrically connected through the vertical scan lines VSL. For example, the first scan signal S1 can be applied from the first vertical scan line VSL1 to both the first horizontal scan line HSL1 and the second horizontal scan line HSL2 at the same time, and the second scan signal S2 can be applied from the second vertical scan line VSL2 to both the third horizontal scan line HSL3 and the fourth horizontal scan line HSL4 at the same time. Therefore, each of the vertical scan lines VSL can electrically connect the two horizontal scan lines HSL in the display area DA.

[0052] The horizontal scan line HSL may be connected to the pixel rows PXR adjacent to the horizontal scan line HSL in the second direction DR2. The horizontal scan line HSL may be disposed between the pixel rows PXR. In addition, the pixel rows PXR may be disposed between the horizontal scan lines HSL. The number of the horizontal scan lines HSL may be substantially the same as the number of the pixel rows PXR.

[0053] The first horizontal scan line HSL1, the second horizontal scan line HSL2, the third horizontal scan line HSL3, and the fourth horizontal scan line HSL4 may be sequentially arranged along the second direction DR2. The first horizontal scan line HSL1 may be connected to the first pixel row PXR1. The second horizontal scan line HSL2 may be connected to the second pixel row PXR2. The third horizontal scan line HSL3 may be connected to the third pixel row PXR3. The fourth horizontal scan line HSL4 may be connected to the fourth pixel row PXR4.

[0054] The data line DL may be arranged to overlap the pixel column PXC at the first side and the second side (e.g., the right side and the left side) of each of the pixel columns PXC in the first direction DR1. For example, the first data line DL1 may be arranged at the second side of the first pixel column PXC1 in the first direction DR1, and the second data line DL2 may be arranged at the first side of the first pixel column PXC1 in the first direction DR1. For example, the third data line DL3 may be arranged at the second side of the second pixel column PXC2 in the first direction DR1, and the fourth data line DL4 may be arranged at the first side of the second pixel column PXC2 in the first direction DR1. For example, the fifth data line DL5 may be arranged at the second side of the third pixel column PXC3 in the first direction DR1, and the sixth data line DL6 may be arranged at the first side of the third pixel column PXC3 in the first direction DR1. Two data lines DL may be arranged at both sides of each of the pixel columns PXC in the first direction DR1. That is, the number of data lines DL may be twice the number of pixel columns PXC.

[0055] The seventh data line DL7 may be disposed at a first side of the sixth data line DL6 in the first direction DR1 with the second vertical scan line VSL2 interposed therebetween. The seventh data line DL7 may provide a data signal Dm to a pixel column PXC disposed at a first side of the second vertical scan line VSL2 in the first direction DR1.

[0056] In the pixels PX forming the pixel rows PXR and the pixel columns PXC, switching elements TR1 to TR12 connected to the horizontal scan lines HSL and the data lines DL may be provided. The switching elements TR1 to TR12 may be formed as thin film transistors (TFTs). Each of the TFTs may include a gate electrode GE (see Figure 5 ), source electrode SE (see Figure 6 ) and the drain electrode DE (see Figure 6 ). The switching elements TR1 to TR12 may be connected to the horizontal scan line HSL and the data line DL. In particular, the gate electrodes GE of the switching elements TR1 to TR12 may be connected to the horizontal scan line HSL, and the source electrodes SE of the switching elements TR1 to TR12 may be connected to the data line DL.

[0057] For example, the first horizontal scan line HSL1 and the first data line DL1 may be connected to the first switching element TR1. The first horizontal scan line HSL1 and the third data line DL3 may be connected to the second switching element TR2. The first horizontal scan line HSL1 and the fifth data line DL5 may be connected to the third switching element TR3. The second horizontal scan line HSL2 and the second data line DL2 may be connected to the fourth switching element TR4. The second horizontal scan line HSL2 and the fourth data line DL4 may be connected to the fifth switching element TR5. The second horizontal scan line HSL2 and the sixth data line DL6 may be connected to the sixth switching element TR6. The third horizontal scan line HSL3 and the first data line DL1 may be connected to the seventh switching element TR7. The third horizontal scan line HSL3 and the third data line DL3 may be connected to the eighth switching element TR8. The third horizontal scan line HSL3 and the fifth data line DL5 may be connected to the ninth switching element TR9. The fourth horizontal scan line HSL4 and the second data line DL2 may be connected to the tenth switching element TR10. The fourth horizontal scan line HSL4 and the fourth data line DL4 may be connected to the eleventh switching element TR11. The fourth horizontal scan line HSL4 and the sixth data line DL6 may be connected to the twelfth switching element TR12.

[0058] A storage capacitor Cst and a liquid crystal capacitor Clc may be connected to each of the switching elements TR1 to TR12 .

[0059] The driving controller SPCB and the integrated driver DIC may form a power supply for displaying an image on the display panel DP and a driving unit for providing a plurality of signals.

[0060] The integrated driver DIC may generate a scan signal Sn using a scan control signal, and may generate a data signal Dm using a data control signal and image data. The scan signal Sn generated by the integrated driver DIC may be sequentially provided to the horizontal scan line HSL via the vertical scan line VSL of the display panel DP. The data signal Dm generated by the integrated driver DIC may be provided to the data line DL of the display panel DP.

[0061] Each of the integrated driver DICs may be implemented as a chip on film (COF) including a flexible printed circuit board (FPCB) SFPC and a first integrated circuit GDIC and a second integrated circuit SDIC, the flexible printed circuit board (FPCB) SFPC including a plurality of wirings and connected to one of the drive controller SPCBs and the display panel DP, the first integrated circuit GDIC and the second integrated circuit SDIC being mounted on the flexible printed circuit board SFPC and being connectable to one side of the display panel DP.

[0062] The first integrated circuit GDIC may include a shift register and may generate a scan signal Sn. The second integrated circuit SDIC may include a digital-to-analog converter (DAC) and may generate a data signal Dm.

[0063] One first integrated circuit GDIC and two second integrated circuits SDIC may be disposed on the flexible printed circuit board SFPC. The first integrated circuit GDIC may be disposed on a first side of the second integrated circuit SDIC in the second direction DR2, and the second integrated circuit SDIC may be disposed on a second side of the first integrated circuit GDIC in the second direction DR2. The second integrated circuit SDIC may be symmetrical with respect to a line that divides the flexible printed circuit board SFPC into two halves and is parallel to the second direction DR2.

[0064] A plurality of connection lines extending toward the display panel DP may be provided on each of the integrated drivers DIC. The connection lines may include a first connection line extending from the first integrated circuit GDIC of each of the integrated drivers DIC and connected to the gate channel GC of the vertical scan line VSL, and a second connection line extending from the second integrated circuit SDIC of each of the integrated driver DIC and connected to the data line DL. The number of first connection lines provided on each of the integrated drivers DIC to extend from a single first integrated circuit GDIC may be 270, and the number of second connection lines provided on each of the integrated drivers DIC to extend from each second integrated circuit SDIC may be 960. Therefore, the total number of second connection lines provided on each of the integrated drivers DIC may be 1920, i.e., 960×2.

[0065] In a region covered by each integrated driver DIC on the display panel DP, the vertical scan lines VSL and the data lines DL may be disposed to extend in the second direction DR2.

[0066] In the area covered by each integrated driver DIC, the vertical scan line VSL may include an array of gate channels GC disposed in the middle and dummy lines DM disposed at first and second sides of the array of gate channels GC in the first direction DR1 .

[0067] The gate channel GC may be a vertical scan line VSL connected to the horizontal scan line HSL and to which a scan signal Sn is applied. The gate channel GC may be in direct contact with the horizontal scan line HSL and connected to the horizontal scan line HSL. The dummy line DM may be a wiring to which a gate-off voltage (Voff) or a common voltage (Vcom) is applied instead of the scan signal Sn. The dummy line DM may not be connected to the horizontal scan line HSL. The gate channel GC and the dummy line DM may include the same material.

[0068] As described above, the gate channels GC may be connected to the first integrated circuit GDIC of the integrated driver DIC. Therefore, the number of the gate channels GC may be the same as the number of the first connection lines. The dummy lines DM may not be connected to the first integrated circuit GDIC.

[0069] In the area covered by each integrated driver DIC, the number of vertical scan lines VSL may be the same as the sum of the number of gate channels GC and the number of dummy lines DM. For example, if there are 270 first connection lines on each integrated driver DIC, 270 gate channels GC, 50 dummy lines DM, and 320 vertical scan lines VSL may be provided in the area covered by the corresponding integrated driver DIC.

[0070] In this case, half of the dummy lines DM may be disposed on a first side of the array of gate channels GC in the first direction DR1, and the other half may be disposed on a second side of the array of gate channels GC in the first direction DR1. That is, 25 dummy lines DM may be disposed on a first side of the array of gate channels GC in the first direction DR1, and 25 dummy lines DM may be disposed on a second side of the array of gate channels GC in the first direction DR1.

[0071] The data lines DL may be connected to the second integrated circuit SDIC of each integrated driver DIC via the second connection lines. Therefore, in the area covered by each integrated driver DIC, the number of data lines DL may be the same as the number of second connection lines provided on the corresponding integrated driver DIC. For example, if two second integrated circuits SDIC are provided in each integrated driver DIC and 960 second connection lines extend from each of the two second integrated circuits SDIC, the number of data lines DL provided in the area covered by the corresponding integrated driver DIC may be 1920.

[0072] The vertical scan lines VSL may be arranged to be spaced apart from each other. The distance between the vertical scan lines VSL may be uniform, but may vary from one region to another. The pixels PX and the data lines DL may be arranged between each pair of adjacent vertical scan lines VSL. Two data lines DL may be arranged, one data line DL being arranged on each side of each pixel column PXC. Therefore, the number of data lines DL may be twice the number of pixel columns PXC. In the display device 1, three pixel columns PXC and six data lines DL may be arranged between each pair of adjacent vertical scan lines VSL. The number of data lines DL may be six times the number of vertical scan lines VSL.

[0073] The driving controller SPCB may generate a gate control signal, a data control signal, and image data using an image signal and a plurality of timing signals received from an external system, and may provide the gate control signal, the data control signal, and the image data to the integrated driver DIC.

[0074] For example, the drive controller SPCB may include a timing controller, the plurality of timing signals may include a data enable (DE) signal, a horizontal synchronization (HSY) signal, a vertical synchronization (VSY) signal and a clock (CLK), the scan control signal may include a gate start pulse (GSP), a gate shift clock (GSC) and a gate output enable (GOE) signal, and the data control signal may include a source start pulse (SSP), a source sampling clock (SSC) and a source output enable (SOE) signal.

[0075] Since the scan signal Sn is transmitted to the horizontal scan line HSL via the vertical scan line VSL, the transmission path of the scan signal Sn may be undesirably lengthened, and as a result, the scan signal Sn may be attenuated and / or delayed. In order to prevent the attenuation and / or delay of the scan signal Sn, the display panel DP may be divided into a plurality of parts along the first direction DR1, and different drive controllers SPCB may be used to drive different parts. For example, the display panel DP may be divided into three different parts along the first direction DR1, and different drive controllers SPCB may be provided in the three different parts.

[0076] The driving controller SPCB may be a printed circuit board (PCB) connected to the integrated driver DIC. Hereinafter, the driving controller SPCB will be described by taking three driving controllers including three PCBs (ie, a first driving controller SPCB1, a second driving controller SPCB2, and a third driving controller SPCB3) as an example.

[0077] The three PCBs may be connected to correspond to the three parts of the display panel DP. For example, the first drive controller SPCB1, the second drive controller SPCB2, and the third drive controller SPCB3 may be connected to the three parts of the display panel DP. Eight integrated drivers DIC may be connected to each of the first drive controller SPCB1, the second drive controller SPCB2, and the third drive controller SPCB3.

[0078] The display panel DP may include a display area DA for displaying an image and a non-display area NDA not for displaying an image.

[0079] Since the integrated driver DIC is connected to one side of the display panel DP, and the scan signal Sn generated by the integrated driver DIC is transmitted to the horizontal scan line HSL via the vertical scan line VSL, a pad (also called a "pad" or "pad") for connecting to the gate driver or a plurality of wirings for providing a gate control signal and a scan signal Sn may not be provided in the non-display area NDA. Therefore, the size of the non-display area NDA of the display panel DP may be minimized, and as a result, a display device 1 with a narrow frame may be provided.

[0080] Figure 4 is an enlarged layout diagram showing a first pixel PX1 , a second pixel PX2 , and a third pixel PX3 . Figure 5 It is shown Figure 4 Layout diagram of the gate conductive layer 120. Figure 6 It is shown Figure 4 FIG. 1 is a layout diagram of the data conductive layer 170 . Figure 7 yes Figure 4 Layout diagram of the pixel electrode layer 190. Figure 8 It is along Figure 4 A cross-sectional view taken along line VIII-VIII'. Fig. 9 It is along Figure 4 A cross-sectional view taken along line IX-IX'. Fig.10 It is along Figure 4 A cross-sectional view taken along line XX'. Fig.11 It is shown Figure 1 FIG. 1 is a cross-sectional view showing a structure of a shield electrode SH in the display device 1 .

[0081] Reference Figures 4 to 11 , the display device 1 may include a first substrate 100, a second substrate 200, and a liquid crystal layer 300. The second substrate 200 may face the first substrate 100, and the liquid crystal layer 300 may be disposed between the first substrate 100 and the second substrate 200.

[0082] The first substrate 100 may be a TFT array substrate having a switching element disposed on the first substrate 100. The second substrate 200 may be a corresponding substrate opposite to the first substrate 100.

[0083] The first substrate 100 may include a first base substrate 110, a gate conductive layer 120, a gate insulating layer 130, a passivation layer 140, a semiconductor layer 150, a data conductive layer 170, a planarization layer 160, and a pixel electrode layer 190. The first substrate 100 may further include a color filter CF.

[0084] The first base substrate 110 may be formed of an insulating material such as glass, quartz or a polymer resin. The polymer resin may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) or a combination thereof. The first base substrate 110 may also include a metal material.

[0085] The pixel area PA and the switching element area TA may be defined on the first base substrate 110. The pixel area PA may be defined as an area in which the pixel electrode PE is disposed, and the switching element area TA may be defined as an area in which the switching element TR is disposed. The switching element area TA may be disposed between the pixel areas PA in the second direction DR2.

[0086] The gate conductive layer 120 is disposed on the first base substrate 110. The gate conductive layer 120 may include a first horizontal scan line HSL1 and a gate electrode GE. Here, the expression "conductive layer including a specific structure" as used herein means that the specific structure is disposed in the same layer and is formed of the same material. The specific structure formed by a single conductive layer can be simultaneously formed by patterning through a single mask process.

[0087] The first horizontal scan line HSL1 may extend in the first direction DR1. The first horizontal scan line HSL1 may be disposed between the pixel rows PXR. The gate electrode GE may be connected to the first horizontal scan line HSL1. For example, the gate electrodes GE may be disposed in the pixels PX and may be connected to each other through the first horizontal scan line HSL1. Each of the pixels PX may include one gate electrode GE.

[0088] The first horizontal scan line HSL1 may include a first sub-horizontal scan line HSL1a and a second sub-horizontal scan line HSL1b. The first sub-horizontal scan line HSL1a and the second sub-horizontal scan line HSL1b may extend in the first direction DR1. The first sub-horizontal scan line HSL1a may be disposed at a first side (i.e., an upper side) in a gap between a pixel row PXR including the first pixel PX1, the second pixel PX2, and the third pixel PX3 and a pixel row PXR directly above the pixel row PXR including the first pixel PX1, the second pixel PX2, and the third pixel PX3 in the second direction DR2. The second sub-horizontal scan line HSL1b may be disposed at a second side (i.e., a lower side) in a gap between a pixel row PXR including the first pixel PX1, the second pixel PX2, and the third pixel PX3 and a pixel row PXR directly above the pixel row PXR including the first pixel PX1, the second pixel PX2, and the third pixel PX3 in the second direction DR2. The first sub-horizontal scan line HSL1a may be connected to a first end of the gate electrode GE in the second direction DR2, and the second sub-horizontal scan line HSL1b may be connected to a second end of the gate electrode GE in the second direction DR2. A hole may be disposed between the first sub-horizontal scan line HSL1a and the second sub-horizontal scan line HSL1b. A boundary of each of the holes may be defined by the first sub-horizontal scan line HSL1a, the second sub-horizontal scan line HSL1b, and the gate electrode GE.

[0089] The gate conductive layer 120 may further include a holding line 127. A holding voltage may be applied to the holding line 127. The holding voltage may be substantially the same as a common voltage (Vcom) applied to the common electrode CE, and may be a direct current (DC) voltage.

[0090] The holding line 127 may include a central line portion 1278 extending in the first direction DR1 , extension portions 1274 , 1275 , 1276 , and 1277 disposed at both sides of each of the pixels PX in the first direction DR1 , and protrusion portions 1271 , 1272 , and 1273 protruding from the central line portion 1278 to the pixel electrode PE.

[0091] The extending portions 1274, 1275, 1276 and 1277 of the holding line 127 may include outer extending portions 1274 and 1277 and inner extending portions 1275 and 1276, the outer extending portions 1274 and 1277 being respectively arranged on the second side of the first pixel PX1 in the first direction DR1 and the first side of the third pixel PX3 in the first direction DR1, and the inner extending portions 1275 and 1276 being respectively arranged between the first pixel PX1 and the second pixel PX2 and between the second pixel PX2 and the third pixel PX3.

[0092] The first ends of the extended portions 1274, 1275, 1276 and 1277 of the holding line 127 in the second direction DR2 may be connected to the center line portion 1278 of the holding line 127, but the second ends of the extended portions 1274, 1275, 1276 and 1277 of the holding line 127 in the second direction DR2 may not be connected to other elements.

[0093] The outer extensions 1274 and 1277 of the holding wire 127 may have a substantially uniform width, but the inner extensions 1275 and 1276 of the holding wire 127 may have different widths from one region to another. For example, the inner extensions 1275 and 1276 may have a relatively small width at the first and second ends of the inner extensions 1275 and 1276, and may have a relatively large width between the first and second ends of the inner extensions 1275 and 1276. The widths of the inner extensions 1275 and 1276 at the first and second ends of the inner extensions 1275 and 1276 may be substantially the same as the widths of the outer extensions 1274 and 1277. The outer extensions 1274 and 1277 may have a relatively smaller width than that of the inner extensions 1275 and 1276 to improve transmittance. The extension portions 1274 , 1275 , 1276 , and 1277 of the holding line 127 may function as light shielding patterns for blocking transmission of light at first and second sides of the pixel electrode PE in the first direction DR1 .

[0094] The outer extension portions 1274 and 1277 of the holding line 127 may not overlap the pixel electrode PE in the thickness direction. For example, the outer extension portions 1274 and 1277 of the holding line 127 may not overlap the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 in the thickness direction. The outer extension portions 1274 and 1277 of the holding line 127 may be disposed to be spaced apart from the first sub-horizontal scan line HSL1a and the second sub-horizontal scan line HSL1b, and may not overlap the first vertical scan line VSL1 and the second vertical scan line VSL2.

[0095] The first protrusion 1271, the second protrusion 1272, and the third protrusion 1273 of the holding line 127 may overlap the first pixel PX1, the second pixel PX2, and the third pixel PX3 in the thickness direction, respectively. The first protrusion 1271 may overlap the first drain electrode DE1 in the thickness direction to form a holding capacitor. The second protrusion 1272 may overlap the second drain electrode DE2 in the thickness direction to form a holding capacitor. The third protrusion 1273 may overlap the third drain electrode DE3 in the thickness direction to form a holding capacitor. The first protrusion 1271, the second protrusion 1272, and the third protrusion 1273 of the holding line 127 may substantially have the same area as the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3.

[0096] The gate conductive layer 120 may further include an island electrode IG, and the island electrode IG may include a first island electrode IG1 and a second island electrode IG2. The island electrode IG may have a rectangular shape in a plan view, but the shape of the island electrode IG is not specifically limited. The island electrode IG may be arranged to overlap with the vertical scan line VSL in the thickness direction. The width of the vertical scan line VSL may be greater than the width of the island electrode IG. In the region where the island electrode IG and the vertical scan line VSL overlap, the vertical scan line VSL may protrude outwardly beyond the island electrode IG.

[0097] The island-type electrode IG may be connected to the vertical scan line VSL in a region where the island-type electrode IG overlaps with the vertical scan line VSL in the thickness direction. Here, the expression "connection" as used herein not only means physical connection, but also includes electrical connection. The island-type electrode IG may be in direct contact with the vertical scan line VSL and connected to the vertical scan line VSL. For example, the island-type electrode IG may be electrically connected to the vertical scan line VSL overlapping with the island-type electrode IG via a contact hole. In this example, the island-type electrode IG and the vertical scan line VSL may form a double wiring structure in a region where the island-type electrode IG and the vertical scan line VSL overlap and are connected in the thickness direction. Due to the double wiring structure, the attenuation and / or delay of the scan signal Sn applied to the vertical scan line VSL can be minimized.

[0098] The island type electrode IG may be disposed to be spaced apart from the first sub-horizontal scan line HSL1 a , the second sub-horizontal scan line HSL1 b , and the holding line 127 .

[0099] The gate conductive layer 120 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate conductive layer 120 may be a single-layer structure or a multi-layer structure consisting of a plurality of films of different materials.

[0100] The gate insulating layer 130 may be disposed on the gate conductive layer 120. The gate insulating layer 130 may cover the gate conductive layer 120. The gate insulating layer 130 may be disposed on the entire surface of the first base substrate 110. The gate insulating layer 130 may include an opening exposing at least a portion of the first horizontal scan line HSL1. The first horizontal scan line HSL1 may be connected to the vertical scan line VSL via the opening included in the gate insulating layer 130.

[0101] The gate insulating layer 130 may include an inorganic insulating material such as a silicon compound or a metal oxide. For example, the gate insulating layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. The gate insulating layer 130 may be a single-layer film or a multilayer film composed of a plurality of films of different materials.

[0102] The semiconductor layer 150 may be disposed on the gate insulating layer 130. The semiconductor layer 150 may include semiconductor patterns 151, 152, and 153 formed as islands. In particular, the semiconductor layer 150 may include a first semiconductor pattern 151, a second semiconductor pattern 152, and a third semiconductor pattern 153. The first semiconductor pattern 151 may form a channel of a TFT that provides a first data signal D1 to the first pixel electrode PE1. The second semiconductor pattern 152 may form a channel of a TFT that provides a second data signal D2 to the second pixel electrode PE2. The third semiconductor pattern 153 may form a channel of a TFT that provides a third data signal D3 to the third pixel electrode PE3.

[0103] The second semiconductor pattern 152 may be disposed to be spaced apart from the first semiconductor pattern 151 in the first direction DR1, and the third semiconductor pattern 153 may be disposed to be spaced apart from the second semiconductor pattern 152 in the first direction DR1. A distance between the first and second semiconductor patterns 151 and 152 may be substantially the same as a distance between the second and third semiconductor patterns 152 and 153.

[0104] The first semiconductor pattern 151, the second semiconductor pattern 152, and the third semiconductor pattern 153 may overlap the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 in the thickness direction, respectively. The first semiconductor pattern 151, the second semiconductor pattern 152, and the third semiconductor pattern 153 may be regions (sometimes referred to as channel regions) in which the conductivity between the source electrode SE and the drain electrode DE is reversed in response to an electric field applied by the gate electrode GE, thereby forming a channel. For example, if an electric field is applied to the first semiconductor pattern 151 through the first gate electrode GE1, the conductivity between the first source electrode SE1 and the first drain electrode DE1 may be reversed, thereby forming a channel. If an electric field is applied to the second semiconductor pattern 152 through the second gate electrode GE2, the conductivity between the second source electrode SE2 and the second drain electrode DE2 may be reversed, thereby forming a channel. If an electric field is applied to the third semiconductor pattern 153 through the third gate electrode GE3, the conductivity between the third source electrode SE3 and the third drain electrode DE3 may be reversed, thereby forming a channel.

[0105] The semiconductor layer 150 may further include a supporting semiconductor pattern 154. The supporting semiconductor pattern 154 may be disposed between the gate insulating layer 130 and the data conductive layer 170. The supporting semiconductor pattern 154 may support the first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6 and the first, second, and third source electrodes SE1, SE2, and SE3.

[0106] The supporting semiconductor pattern 154 may be disposed in a region where the first sub-horizontal scan line HSL1a overlaps the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6, in a region where the second sub-horizontal scan line HSL1b overlaps the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6, and in a region where a central line portion 1278 of the holding line 127 overlaps the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6. The supporting semiconductor pattern 154 may also be disposed in a region where the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 overlap the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3. The supporting semiconductor pattern 154 may also be disposed in a region where the central line portion 1278 of the holding line 127 and the vertical scan line VSL overlap. However, the supporting semiconductor pattern 154 may also be disposed between the gate insulating layer 130 and the data conductive layer 170 in other regions than those set forth herein.

[0107] The supporting semiconductor pattern 154 may completely cover the above-mentioned overlapping area. Therefore, even if the alignment between the semiconductor layer 150 and the data conductive layer 170 is changed, the supporting semiconductor pattern 154 may properly support the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 and the vertical scan line VSL.

[0108] As the size of the display device 1 increases, the length of the data line DL, the vertical scan line VSL, and / or the first horizontal scan line HSL1 also increases. Therefore, the resistance of the data line DL increases, and as a result, attenuation and / or delay of the data signal Dm may occur. In order to reduce the resistance of the data line DL, the data line DL may be formed to be sufficiently thick. In this case, since the supporting semiconductor pattern 154 supports the data line DL, defects such as interference and short circuit that may occur as the thickness of the data line DL increases may be mitigated or prevented.

[0109] The semiconductor layer 150 may include a silicon-based semiconductor material (such as amorphous silicon, polycrystalline silicon, or single crystal silicon). Alternatively, the semiconductor layer 150 may include single crystal silicon, low temperature polycrystalline silicon, or amorphous silicon. Also alternatively, the semiconductor layer 150 may include an oxide semiconductor. For example, the semiconductor layer 150 may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), or magnesium (Mg).x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z The semiconductor layer 150 may also include indium tin zinc oxide (ITZO) or indium gallium zinc oxide (IGZO).

[0110] The data conductive layer 170 may be disposed on the gate insulating layer 130 and the semiconductor layer 150. The data conductive layer 170 may be formed using a mask different from that of the semiconductor layer 150. Therefore, a portion of the data conductive layer 170 may be in contact with a side surface (e.g., a side surface of the first semiconductor pattern 151) of at least one of the elements of the semiconductor layer 150. In each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, an area occupied by the data conductive layer 170 may be greater than an area occupied by the semiconductor layer 150.

[0111] The data conductive layer 170 may include first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6, first, second, and third source electrodes SE1, SE2, and SE3, first, second, and third drain electrodes DE1, DE2, and DE3, and a vertical scan line VSL.

[0112] The first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 may extend substantially in the second direction DR2. The first data line DL1 and the second data line DL2 may partially overlap the first pixel electrode PE1. The third data line DL3 and the fourth data line DL4 may partially overlap the second pixel electrode PE2. The fifth data line DL5 and the sixth data line DL6 may partially overlap the third pixel electrode PE3.

[0113] The source electrode SE may include a first source electrode SE1 connected to the first data line DL1, a second source electrode SE2 connected to the third data line DL3, and a third source electrode SE3 connected to the fifth data line DL5. The first source electrode SE1 may be disposed on the first semiconductor pattern 151. The second source electrode SE2 may be disposed on the second semiconductor pattern 152. The third source electrode SE3 may be disposed on the third semiconductor pattern 153. Each of the source electrodes SE may include a horizontal extension portion extending from one of the data lines DL in the first direction DR1 and a pair of vertical extension portions extending from a first end of the horizontal extension portion in the first direction DR1 and from the middle of the horizontal extension portion in the second direction DR2. The horizontal extension portion and the vertical extension portion of each of the source electrodes SE may have the same width. In particular, the regions where the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 overlap the first semiconductor pattern 151, the second semiconductor pattern 152, and the third semiconductor pattern 153, respectively, may be portions of the paired vertical extension portions of the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3.

[0114] The drain electrode DE may include a first drain electrode DE1 connected to the first pixel electrode PE1 , a second drain electrode DE2 connected to the second pixel electrode PE2 , and a third drain electrode DE3 connected to the third pixel electrode PE3 .

[0115] The drain electrode DE may be disposed to be spaced apart from and face the source electrode SE over the semiconductor patterns 151, 152, and 153. For example, the first drain electrode DE1 may be disposed to be spaced apart from and face the first source electrode SE1 over the first semiconductor pattern 151. The second drain electrode DE2 may be disposed to be spaced apart from and face the second source electrode SE2 over the second semiconductor pattern 152. The third drain electrode DE3 may be disposed to be spaced apart from and face the third source electrode SE3 over the third semiconductor pattern 153.

[0116] The first drain electrode DE1 may include a first rod-shaped portion DE1a partially overlapping the first gate electrode GE1 in the first direction DR1 and extending along the second direction DR2, a first extension portion DE1b partially overlapping the first pixel electrode PE1, and a first connection portion DE1c disposed between the first rod-shaped portion DE1a and the first extension portion DE1b. The second drain electrode DE2 may include a second rod-shaped portion DE2a partially overlapping the second gate electrode GE2 in the first direction DR1 and extending along the second direction DR2, a second extension portion DE2b partially overlapping the second pixel electrode PE2, and a second connection portion DE2c disposed between the second rod-shaped portion DE2a and the second extension portion DE2b. The third drain electrode DE3 may include a third rod-shaped portion DE3a partially overlapping the third gate electrode GE3 in the first direction DR1 and extending along the second direction DR2, a third extension portion DE3b partially overlapping the third pixel electrode PE3, and a third connection portion DE3c disposed between the third rod-shaped portion DE3a and the third extension portion DE3b. Portions of the first rod-shaped portion DE1a, the second rod-shaped portion DE2a, and the third rod-shaped portion DE3a may be respectively disposed on the first semiconductor pattern 151, the second semiconductor pattern 152, and the third semiconductor pattern 153. The first connection portion DE1c, the second connection portion DE2c, and the third connection portion DE3c may have a greater width than the first rod-shaped portion DE1a, the second rod-shaped portion DE2a, and the third rod-shaped portion DE3a.

[0117] The first extension portion DE1b, the second extension portion DE2b, and the third extension portion DE3b may have a rectangular shape in a plan view. The first extension portion DE1b, the second extension portion DE2b, and the third extension portion DE3b may have an area substantially the same as that of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. The first extension portion DE1b, the second extension portion DE2b, and the third extension portion DE3b may be shorter than the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 in the first direction DR1, but may be longer than the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 in the second direction DR2. The first extension portion DE1b, the second extension portion DE2b, and the third extension portion DE3b may not overlap with the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. Although not specifically shown, an ohmic contact layer may be further disposed between the semiconductor patterns 151, 152, and 153 and the source electrode SE / drain electrode DE.

[0118] The data conductive layer 170 may include a vertical scan line VSL. The vertical scan line VSL may extend in the second direction DR2 and may be parallel to the pixel column PXC. For example, one vertical scan line VSL may be provided for every three pixel columns PXC. That is, three pixel columns PXC may be provided between each pair of adjacent vertical scan lines VSL. For example, the vertical scan line VSL may include a first vertical scan line VSL1 provided on the second side of the first pixel column PXC1 in the first direction DR1 and a second vertical scan line VSL2 provided on the first side of the third pixel column PXC3 in the first direction DR1.

[0119] As mentioned above Figure 3 As described, the vertical scan line VSL may extend from the first integrated circuit GDIC of the integrated driver DIC in the second direction DR2, and may include a gate channel GC disposed in the middle of the array of gate channels GC and a dummy line DM disposed on both the first side and the second side of the array of gate channels GC in the first direction DR1. A scan signal Sn may be applied to the gate channel GC, and a gate-off voltage (Voff) or a common voltage (Vcom) may be applied to the dummy line DM instead of the scan signal Sn.

[0120] The data conductive layer 170 may include at least one metal selected from Al, Pt, Pd, Ag, Mg, Mo, Au, Ni, Nd, Ir, Cr, Ti, Ta, W, and Cu. The data conductive layer 170 may be a single-layer film or a multi-layer film. For example, the data conductive layer 170 may be formed to have a stack structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0121] The passivation layer 140 may be disposed on the data conductive layer 170. The passivation layer 140 may be disposed on the entire surface of the first base substrate 110. The passivation layer 140 may include an opening exposing at least a portion of the drain electrode DE. The passivation layer 140 may be formed of, for example, an inorganic insulating material such as silicon nitride or silicon oxide. The passivation layer 140 may prevent the pigment from penetrating from the color filter CF into the semiconductor layer 150.

[0122] The color filter CF may be disposed on the passivation layer 140. The color filter CF may include a first color filter CF1 overlapped with the first pixel PX1, a second color filter CF2 overlapped with the second pixel PX2, and a third color filter CF3 overlapped with the third pixel PX3. The color of each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be one of red, green, and blue. The color filters CF may partially overlap each other at the boundaries between the color filters CF. The color filter CF may overlap with the pixel electrode PE. The color filter CF may also be disposed in a region in which the switching element TR is disposed, and thus may overlap with the switching element TR.

[0123] The planarization layer 160 may be disposed on the color filter CF. The planarization layer 160 may have excellent planarization characteristics and may include an organic material having photosensitivity. The planarization layer 160 may fill any height difference generated by the underlying structure (e.g., the color filter CF) and may planarize the surface on which the pixel electrode PE is to be disposed. However, the planarization layer 160 or the color filter CF may not be provided.

[0124] Contact holes CH1, CH2, and CH3 exposing a portion of the drain electrode DE may be disposed in the passivation layer 140, the color filter CF, and the planarization layer 160. The contact holes CH1, CH2, and CH3 may include a first contact hole CH1 disposed in the first pixel PX1, a second contact hole CH2 disposed in the second pixel PX2, and a third contact hole CH3 disposed in the third pixel PX3.

[0125] The first extension portion DE1b of the first drain electrode DE1 may be exposed through the first contact hole CH1, the second extension portion DE2b of the second drain electrode DE2 may be exposed through the second contact hole CH2, and the third extension portion DE3b of the third drain electrode DE3 may be exposed through the third contact hole CH3.

[0126] The pixel electrode layer 190 may be disposed on the planarization layer 160. The pixel electrode layer 190 may include a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3.

[0127] The first pixel electrode PE1 may be electrically connected to the first drain electrode DE1 through the first contact hole CH1 and in contact with the first drain electrode DE1. The second pixel electrode PE2 may be electrically connected to the second drain electrode DE2 through the second contact hole CH2 and in contact with the second drain electrode DE2. The third pixel electrode PE3 may be electrically connected to the third drain electrode DE3 through the third contact hole CH3 and in contact with the third drain electrode DE3.

[0128] The first pixel electrode PE1 may include a trunk portion 191a, branch portions 191b extending outward from the trunk portion 191a and spaced apart from each other by slits 191c, and a pixel extension portion 191d extending to the switching element region TA1. The second pixel electrode PE2 may include a trunk portion 192a, branch portions 192b extending outward from the trunk portion 192a and spaced apart from each other by slits 192c, and a pixel extension portion 192d extending to the switching element region TA2. The third pixel electrode PE3 may include a trunk portion 193a, branch portions 193b extending outward from the trunk portion 193a and spaced apart from each other by slits 193c, and a pixel extension portion 193d extending to the switching element region TA3. The pixel electrode layer 190 may further include a pixel contour portion 194 disposed on a first side and a second side of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 in the second direction DR2.

[0129] The trunk portion 191a, 192a or 193a may include a horizontal trunk extending generally in the first direction DR1 and a vertical trunk extending generally in the second direction DR2, and may divide the first pixel electrode PE1, the second pixel electrode PE2 or the third pixel electrode PE3 into sub-regions (sometimes referred to as domains). The trunk portion 191a, 192a or 193a may be set in a cross shape. In this case, the first pixel electrode PE1, the second pixel electrode PE2 or the third pixel electrode PE3 may be divided into four sub-regions (sometimes referred to as four domains) by the trunk portion 191a, 192a or 193a. The direction along which the branch portion 191b, 192b or 193b extends may change from one sub-region (sometimes referred to as a domain) of the first pixel electrode PE1, the second pixel electrode PE2 or the third pixel electrode PE3 to another sub-region (sometimes referred to as a domain). For example, referring to Figure 7 , the branch portion 191b, 192b or 193b may extend diagonally from the trunk portion 191a, 192a or 193a in the upper right direction in the upper right sub-region of the first pixel electrode PE1, the second pixel electrode PE2 or the third pixel electrode PE3, in the lower right direction in the lower right sub-region of the first pixel electrode PE1, the second pixel electrode PE2 or the third pixel electrode PE3, in the upper left direction in the upper left sub-region of the first pixel electrode PE1, the second pixel electrode PE2 or the third pixel electrode PE3, and in the lower left direction in the lower left sub-region of the first pixel electrode PE1, the second pixel electrode PE2 or the third pixel electrode PE3.

[0130] The pixel extension portion 191d, 192d or 193d can extend from the trunk portion 191a, 192a or 193a or from the branch portion 191b, 192b or 193b to the switching element area TA1, TA2 or TA3, and thus can be connected to the first drain electrode DE1, the second drain electrode DE2 or the third drain electrode DE3 via the first contact hole CH1, the second contact hole CH2 or the third contact hole CH3.

[0131] The first pixel electrode PE1 may overlap the first data line DL1 and the second data line DL2. Portions of the first data line DL1 and the second data line DL2 disposed on the first pixel PX1 may completely overlap the first pixel electrode PE1. The second pixel electrode PE2 may overlap the third data line DL3 and the fourth data line DL4. Portions of the third data line DL3 and the fourth data line DL4 disposed on the second pixel PX2 may completely overlap the second pixel electrode PE2. The third pixel electrode PE3 may overlap the fifth data line DL5 and the sixth data line DL6. Portions of the fifth data line DL5 and the sixth data line DL6 disposed on the third pixel PX3 may completely overlap the third pixel electrode PE3.

[0132] In the display device 1, a parasitic capacitance (Cgs) may be generated between the pixel electrode PE and the vertical scan line VSL. The parasitic capacitance (Cgs) may change the retrace voltage (Vkb) of the pixel PX. The relationship between the parasitic capacitance (Cgs) and the retrace voltage (Vkb) may be expressed by equation (1):

[0133]

[0134] Wherein, Von is the gate-on voltage. The kickback voltage (Vkb) of the pixel PX may generate a brightness difference between the pixels PX. Therefore, the distribution of the kickback voltage (Vkb) of the pixel PX may cause an afterimage in the displayed image or degrade visibility.

[0135] The pixel electrode layer 190 may further include a shielding electrode SH. The shielding electrode SH may be disposed to be spaced apart from the pixel electrode PE. The shielding electrode SH may not be electrically connected to the pixel electrode PE. A shielding voltage may be applied to the shielding electrode SH. The shielding voltage may be substantially the same as the common voltage (Vcom) applied to the common electrode CE, or may be a DC voltage.

[0136] The shielding electrode SH may include a first shielding electrode SH1 partially overlapping the first vertical scan line VSL1 and a second shielding electrode SH2 partially overlapping the second vertical scan line VSL2. Each of the shielding electrodes SH1 and SH2 may include two sub-shielding electrodes spaced apart from each other in the first direction DR1. For example, one sub-shielding electrode of the first shielding electrode SH1 may cover a first edge of the first vertical scan line VSL1 in the first direction DR1, and the other sub-shielding electrode of the first shielding electrode SH1 may cover a second edge of the first vertical scan line VSL1 in the first direction DR1. In a plan view, one sub-shielding electrode of the first shielding electrode SH1 may be positioned between the first vertical scan line VSL1 and a pixel electrode PE in a pixel PX disposed on a first side of the first vertical scan line VSL1 in the first direction DR1, and in a plan view, the other sub-shielding electrode of the first shielding electrode SH1 may be positioned between the first vertical scan line VSL1 and a pixel electrode PE in a pixel PX disposed on a second side of the first vertical scan line VSL1 in the first direction DR1. One sub-shielding electrode of the second shielding electrode SH2 may cover a first edge of the second vertical scan line VSL2 in the first direction DR1 , and another sub-shielding electrode of the second shielding electrode SH2 may cover a second edge of the second vertical scan line VSL2 in the first direction DR1 .

[0137] The first shielding electrode SH1 may be disposed at a second side of the first pixel PX1 in the first direction DR1 and may extend in the second direction DR2. The second shielding electrode SH2 may be disposed at a first side of the third pixel PX3 in the first direction DR1 and may extend in the second direction DR2. Each of the shielding electrodes SH1 and SH2 may include two sub-shielding electrodes extending in the second direction DR2 and spaced apart from each other. A hole may be placed between the two sub-shielding electrodes of each of the shielding electrodes SH1 and SH2.

[0138] In the following we will refer to Fig.11 The construction of the shield electrode SH is described. Fig.11, the shielding electrode SH may be disposed on the planarization layer 160, and may partially overlap with the island electrode IG, the vertical scan line VSL, and the holding line 127 in the thickness direction. In particular, the shielding electrode SH may partially overlap with the island electrode IG and the vertical scan line VSL on their first side in the first direction DR1, and may partially overlap with the holding line 127 or align with one edge of the holding line 127 on their second side in the first direction DR1. Alternatively, the shielding electrode SH may partially overlap with the island electrode IG and the vertical scan line VSL on their second side in the first direction DR1, and may partially overlap with the holding line 127 or align with one edge of the holding line 127 on their first side in the first direction DR1. The shielding electrode SH may partially overlap with the vertical scan line VSL, thereby providing a light leakage prevention function. A shielding capacitor (Csh) may be generated between the shielding electrode SH and the holding line 127. Due to the shielding capacitor (Csh), the parasitic capacitor (Cgs) generated between the vertical scan line VSL and the pixel electrode PE may be minimized. Since the DC voltage is applied to both the shield electrode SH and the holding line 127 , the shield capacitance (Csh) may be uniform.

[0139] The shielding electrode SH may overlap the common electrode CE and overlap a portion of the black matrix BM. The shielding electrode SH may not overlap the data line DL in a thickness direction.

[0140] The pixel electrode layer 190 may be formed of a transparent conductive material, for example, the pixel electrode layer 190 may include a transparent conductive oxide film of indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZO).

[0141] The second substrate 200 is disposed to face the first substrate 100. Although not particularly shown, the second substrate 200 may include a second base substrate similar to the first base substrate 110, and may further include a black matrix BM, an overcoat layer OC, and a common electrode CE.

[0142] The liquid crystal layer 300 may be disposed between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 may include liquid crystal molecules having dielectric anisotropy. In the case where an electric field is applied between the first substrate 100 and the second substrate 200, the liquid crystal molecules may rotate in a specific direction between the first substrate 100 and the second substrate 200, and thus the phase delay of the light transmitted through the liquid crystal layer 300 may be adjusted. The amount of polarized light (i.e., light transmitted through the lower polarization member) passing through the upper polarization member (e.g., disposed on the light exit side of the display device 1 and attached to, for example, the outer surface of the second substrate 200) varies according to the degree to which the phase delay of the light is changed due to the rotation of the liquid crystal molecules, and as a result, the transmittance of the display device 1 may be controlled.

[0143] Since shielding electrodes SH1 and SH2 to which a DC voltage substantially the same as the common voltage (Vcom) is applied are provided in the pixel electrode layer 190, shielding capacitance (Csh) can be generated between the shielding electrodes SH1 and SH2 and the outer extensions 1274 and 1277 of the holding line 127, and as a result, parasitic capacitance (Cgs) between the pixel electrode PE and the vertical scanning line VSL can be minimized. Therefore, the kickback voltage (Vkb) can be minimized. Therefore, a display device 1 having a first integrated circuit GDIC and a second integrated circuit SDIC attached to one side of a display panel DP and thus having a small non-display area NDA can be provided.

[0144] Fig.12 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Fig.13 It is shown Fig.12 sectional view of the structure of the shielding electrode SH in the display device.

[0145] Reference Fig.12 and Fig.13 , display device and Figures 4 to 10 The difference of its corresponding display device 1 is that the shielding electrodes SH1b and SH2b are not included in the pixel electrode layer 190, but are disposed on the color filter CF. Specifically, the shielding electrodes SH1b and SH2b may be disposed on the color filter CF, and the planarization layer 160 may be disposed on the shielding electrodes SH1b and SH2b. The shielding electrodes SH1b and SH2b may be disposed on the flat portion of the color filter CF. In particular, the shielding electrodes SH1b and SH2b may be disposed on portions of the color filter CF that do not overlap each other.

[0146] The shielding electrodes SH1b and SH2b may be formed of a transparent conductive material like the pixel electrode layer 190. For example, the shielding electrodes SH1b and SH2b may include a transparent conductive oxide film of ITO, IZO, or ZO.

[0147] The shielding electrodes SH1b and SH2b may be configured in the first direction DR1 and the second direction DR2 in the same manner as Figures 4 to 11 The constructions of the shield electrodes SH1b and SH2b are the same, and therefore, a detailed description of the constructions of the shield electrodes SH1b and SH2b will be omitted.

[0148] Since the shielding electrodes SH1b and SH2b to which a DC voltage substantially the same as the common voltage (Vcom) is applied are provided on the color filter CF, a shielding capacitance (Csh) can be generated between the shielding electrodes SH1b and SH2b and the outer extension portions 1274 and 1277 of the holding line 127, and as a result, a parasitic capacitance (Cgs) generated between the pixel electrode PE and the vertical scanning line VSL can be minimized. Therefore, a kickback voltage (Vkb) can be minimized. Therefore, a display device having a first integrated circuit GDIC and a second integrated circuit SDIC attached to one side of a display panel DP and thus having a small non-display area can be provided.

[0149] Fig.14 is a plan view of a display device 1_1 according to an embodiment of the present disclosure. Fig.15 yes Fig.14 Equivalent circuit diagram of some pixels PX_1. Fig.16 It is shown Fig.14 A plan view of region R. Fig.17 is an enlarged layout diagram showing a first pixel and a second pixel. Fig.18 It is shown Fig.17 Layout diagram of the gate conductive layer 120_1. Fig.19 It is shown Fig.17 Layout diagram of the data conductive layer. Fig. 20 yes Fig.17 Layout diagram of the pixel electrode layer 190_1. Fig.21 It is along Fig.17 A sectional view taken along line XIX-XIX'.

[0150] Reference Figures 14 to 21 , the display device 1_1 and Figures 1 to 11 The display device 1 is different from its counterpart in that, in order to reduce the delay and / or attenuation of the scan signal Sn_1, the display panel DP_1 is divided into four parts in the first direction DR1, four driving controllers SPCB_1 are arranged in the four parts, and eight integrated drivers DIC_1 are connected to each of the four driving controllers SPCB_1. Unless otherwise discussed below, Figure 14-Figure 21 in Figure 1-Figure 11 Similar elements in FIG. 1 are marked with similar reference numerals with an additional “_1”.

[0151] Display device 1_1 and Figures 1 to 11The difference of its corresponding display device 1 is that two pixel columns PXC_1 are arranged between each pair of adjacent vertical scan lines VSL_1, and four data lines DL_1 are arranged between each pair of vertical scan lines VSL_1. The data line DL_1 may be arranged on the first side and the second side (e.g., the right side and the left side) of each of the pixel columns PXC_1 in the first direction DR1. For example, the first data line DL1_1 may be arranged on the second side of the first pixel column PXC1_1 in the first direction DR1, and the second data line DL2_1 may be arranged on the first side of the first pixel column PXC1_1 in the first direction DR1. The third data line DL3_1 may be arranged on the second side of the second pixel column PXC2_1 in the first direction DR1, and the fourth data line DL4_1 may be arranged on the first side of the second pixel column PXC2_1 in the first direction DR1. Two data lines DL_1 may be arranged on both sides of each of the pixel columns PXC_1 in the first direction DR1. That is, the number of data lines DL_1 may be twice the number of pixel columns PXC_1. The pixel PX_1 included in the first pixel column PXC1_1 may receive the first data signal D1_1 from the first data line DL1_1 , and the pixel PX_1 included in the second pixel column PXC2_1 may receive the third data signal D3_1 from the third data line DL3_1 .

[0152] In the area covered by each integrated driver DIC_1, the number of vertical scan lines VSL_1 may be the same as the sum of the number of gate channels GC_1 and the number of dummy lines DM_1. For example, if there are 270 first connection lines on each integrated driver DIC_1, 270 gate channels GC_1, 90 dummy lines DM_1, and 360 vertical scan lines VSL_1 may be provided in the area covered by each integrated driver DIC_1.

[0153] In this case, half of the dummy lines DM_1 may be disposed on a first side of the array of gate channels GC_1 in the first direction DR1, and the other half may be disposed on a second side of the array of gate channels GC_1 in the first direction DR1. That is, 45 dummy lines DM_1 may be disposed on a first side of the array of gate channels GC_1 in the first direction DR1, and 45 dummy lines DM_1 may be disposed on a second side of the array of gate channels GC_1 in the first direction DR1.

[0154] The data line DL_1 may be connected to the second integrated circuit SDIC_1 of each integrated driver DIC_1. Therefore, in the area covered by each integrated driver DIC_1, the number of data lines DL_1 may be the same as the number of second connection lines provided on the corresponding integrated driver DIC_1. For example, if two second integrated circuits SDIC_1 are provided in each integrated driver DIC_1, and 720 second connection lines extend from each of the two second integrated circuits SDIC_1, the number of data lines DL_1 provided in the area covered by the corresponding integrated driver DIC_1 may be 1440. That is, the number of pixel columns PXC_1 is twice the number of vertical scan lines VSL_1, and the number of data lines DL_1 may be four times the number of vertical scan lines VSL_1.

[0155] A color of each of the first and second color filters CF1_1 and CF2_1 of the first and second pixel columns PXC1_1 and PXC2_1 disposed between the first and second vertical scan lines VSL1_1 and VSL2_1 may be one of red, green, and blue.

[0156] Since shielding electrodes SH1_1 and SH2_1 to which a DC voltage substantially the same as the common voltage (Vcom) is applied are provided in the pixel electrode layer 190_1 of the display device 1_1, shielding capacitance (Csh) can be generated between the shielding electrodes SH1_1 and SH2_1 and the outer extension portions 1274_1 and 1277_1 of the holding line 127_1, and as a result, parasitic capacitance (Cgs) generated between the pixel electrode PE_1 and the vertical scanning line VSL_1 can be minimized. Therefore, the kickback voltage (Vkb) can be minimized. Therefore, a display device 1_1 having a first integrated circuit GDIC_1 and a second integrated circuit SDIC_1 attached to one side of the display panel DP_1 and thus having a small non-display area NDA_1 can be provided.

[0157] Fig. 22 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0158] Reference Fig. 22 , display device and Figures 14 to 21The difference of its corresponding display device 1_1 is that the shielding electrodes SH1a_1 and SH2a_1 are not included in the pixel electrode layer 190_1, but are arranged on the color filter CF_1. In particular, the shielding electrodes SH1a_1 and SH2a_1 can be arranged on the color filter CF_1, and the planarization layer 160_1 can be arranged on the shielding electrodes SH1a_1 and SH2a_1. Like the pixel electrode layer 190_1, the shielding electrodes SH1a_1 and SH2a_1 can be formed of a transparent conductive material. For example, the shielding electrodes SH1a_1 and SH2a_1 can include a transparent conductive oxide film of ITO, IZO or ZO.

[0159] The shield electrodes SH1a_1 and SH2a_1 can be constructed with Figures 14 to 21 The construction of the shield electrodes SH1_1 and SH2_1 is the same, and therefore, a detailed description of the construction of the shield electrodes SH1a_1 and SH2a_1 will be omitted.

[0160] Since shielding electrodes SH1a_1 and SH2a_1 to which a DC voltage substantially the same as the common voltage (Vcom) is applied are provided on the color filter CF_1 of the display device 1_1, shielding capacitance (Csh) can be generated between the shielding electrodes SH1a_1 and SH2a_1 and the outer extension portions 1274_1 and 1277_1 of the holding line 127_1, and as a result, parasitic capacitance (Cgs) generated between the pixel electrode PE_1 and the vertical scanning line VSL_1 can be minimized. Therefore, the retrace voltage (Vkb) can be minimized. Therefore, a display device 1_1 having a first integrated circuit GDIC_1 and a second integrated circuit SDIC_1 attached to one side of the display panel DP_1 and thus having a small non-display area NDA_1 can be provided.

[0161] Advantageous effects according to the embodiments are not limited to the above-mentioned advantageous effects, and various other advantageous effects are included herein.

[0162] The embodiments of the present disclosure have been described above with reference to the accompanying drawings, but it should be understood by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical concept or essential features of the present disclosure. Therefore, the embodiments described above should be understood to be illustrative in all aspects and not restrictive.

Claims

1. A display device, comprising: Display panel; An integrated driver connected to one side of the display panel, Wherein, the display panel comprises: A first conductive layer including a horizontal scanning line extending in a first direction and an island-type electrode extending in a second direction intersecting the first direction and spaced apart from the horizontal scanning line; A first insulating layer, disposed on the first conductive layer; a second conductive layer, disposed on the first insulating layer, the second conductive layer comprising data lines extending in the second direction and vertical scanning lines extending in the second direction; a second insulating layer, disposed on the second conductive layer; and a third conductive layer, disposed on the second insulating layer and comprising a first shielding electrode and a second shielding electrode, wherein the first shielding electrode extends in the second direction and covers a first edge of the vertical scanning line, and the second shielding electrode extends in the second direction, is spaced apart from the first shielding electrode, and covers a second edge of the vertical scanning line, wherein the vertical scan line is electrically connected to the island-type electrode via a contact hole extending through the first insulating layer, and Wherein, the scanning signal generated by the integrated driver is transmitted to the horizontal scanning line via the vertical scanning line.

2. The display device according to claim 1, wherein: The third conductive layer further includes a pixel electrode that is spaced apart from the first shielding electrode and the second shielding electrode and disposed in a pixel.

3. The display device according to claim 2, wherein: The first conductive layer further includes a holding line extending in the second direction and spaced apart from the horizontal scan line and the island-type electrode.

4. The display device according to claim 3, wherein: The holding line does not overlap the pixel electrode in a thickness direction.

5. The display device according to claim 4, wherein In a plan view, the first shielding electrode is positioned between the vertical scan line and a pixel electrode in a pixel disposed on a first side of the vertical scan line in the first direction, and In a plan view, the second shielding electrode is positioned between the vertical scan line and a pixel electrode in a pixel disposed on a second side of the vertical scan line in the first direction.

6. The display device according to claim 3, wherein: A first edge of the first shielding electrode overlaps with or is aligned with the holding line.

7. The display device according to claim 1, wherein: The island-type electrode overlaps the vertical scan line, and in a region where the island-type electrode overlaps the vertical scan line, the vertical scan line protrudes outward beyond the island-type electrode.

8. A display device, comprising: Display panel; An integrated driver connected to one side of the display panel, Wherein, the display panel comprises: A first horizontal scan line and a second horizontal scan line extending in a first direction; a first vertical scanning line extending in a second direction intersecting the first direction; A first data line, a second data line, a third data line and a fourth data line extending in the second direction and sequentially arranged along the first direction; a first switching element connected to the first horizontal scan line and the first data line; a second switching element connected to the first horizontal scan line and the third data line; a third switching element connected to the second horizontal scan line and the second data line; a fourth switching element connected to the second horizontal scan line and the fourth data line; A first pixel electrode connected to the first switching element; a second pixel electrode connected to the second switching element; a third pixel electrode connected to the third switching element; a fourth pixel electrode connected to the fourth switching element; an island-type electrode extending in the second direction, being disposed in the same layer as the first horizontal scanning line and the second horizontal scanning line, and overlapping the first vertical scanning line in a thickness direction; a first shielding electrode extending in the second direction and covering a first edge of the first vertical scanning line; and a second shielding electrode, spaced apart from the first shielding electrode and covering a second edge of the first vertical scanning line, The first vertical scan line electrically connects the first horizontal scan line and the second horizontal scan line, and The scanning signal generated by the integrated driver is transmitted to the first horizontal scanning line and the second horizontal scanning line via the first vertical scanning line.

9. The display device according to claim 8, further comprising: a third horizontal scan line and a fourth horizontal scan line; as well as a second vertical scan line electrically connected to the third horizontal scan line and the fourth horizontal scan line, Wherein, the first horizontal scan line, the second horizontal scan line, the third horizontal scan line and the fourth horizontal scan line are sequentially arranged along the second direction.

10. The display device according to claim 8, further comprising: A holding line extends in the second direction and is spaced apart from the first and second horizontal scan lines and the island type electrode.

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