A memory error correction method and device

Abstract

The present application provides a memory error correction method and device. When it is measured that the storage time of a memory block is greater than or equal to a first preset time, or when the bit error rate of data in the memory block is greater than or equal to a first preset threshold, the memory block is used as a target memory block, and the hot data storage page corresponding to the hot data is marked as invalid, so that the hot data storage page is no longer accessed. The hot data is data with a reading frequency greater than or equal to the first preset frequency, and the hot data storage page is a storage page that stores hot data. Since the read interference generated by the hot data with a high reading frequency increases the threshold voltage of the target memory block, the threshold voltage of the target memory block caused by the data retention error can be reduced, that is, the data retention error can be reduced; at the same time, since the hot data storage page is marked as invalid and not accessed, the read interference caused by the high hot data reading frequency causing the threshold voltage of the hot data storage page to increase can be reduced, that is, the data retention error and data read interference error of the memory can be reduced at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and their manufacturing, and in particular to a memory error correction method and device. Background Art

[0002] Semiconductor memory devices can be characterized as either volatile or nonvolatile. Although volatile semiconductor memory devices can perform read and write operations at high speed, the contents stored in volatile semiconductor memory devices are lost when power is off. In contrast, nonvolatile semiconductor memory devices retain their stored contents regardless of whether power is applied or not. Flash memory devices are a typical example of nonvolatile semiconductor memory devices and are widely used as data storage media.

[0003] In NAND Flash memory devices, different numbers of electrons can be injected into the floating gate or charge-trapping layer to obtain different threshold voltages, thereby representing different logic states. Taking multi-level cell (MLC) NAND Flash as an example, when reading data, three different read voltages are applied to the gate to distinguish the four logic states.

[0004] However, the threshold voltage of a memory cell generally varies with the characteristics of the memory device, the passage of time, and / or the ambient temperature. For example, Figure 1 As shown, electrons in the floating gate or charge trapping layer will gradually be lost over time, reducing the threshold voltage of the storage cell. When the threshold voltage of the storage cell decreases from a voltage higher than the corresponding read voltage to a voltage lower than the corresponding read voltage, the storage cell will generate a read error, called a data retention error. Data retention errors will gradually increase with the increase in storage time. Error Correcting Code (ECC) can correct errors in read data and is an important means to ensure the consistency of written and read data and improve the reliability of the storage system. However, ECC also has a limited error correction range. If the original error rate of the read data is high, it will exceed the error correction capability of the error control code and the written data cannot be correctly recovered.

[0005] refer to Figure 2The figure shows a current data storage diagram, where the horizontal axis represents the threshold voltage (threhold voltage) and the vertical axis represents the number of storage cells. The figure uses the E, P1, P2, and P3 states as examples for illustration. The solid line represents the initial threshold voltage distribution formed by the threshold voltage of the storage cell at time zero when data is written to the flash memory, and the dotted line represents the threshold voltage distribution of the flash memory after a period of storage time. As can be seen from the figure, after a period of storage time, due to the leakage of charge retained by the storage cell, the threshold voltage distribution of the flash memory shifts toward the side with a smaller threshold voltage, that is, the distribution shifts to the left. If the read voltages Vread1, Vread2, and Vread3 used at time zero for data writing are used to read the flash memory at this time, the read data will have a high bit error rate. It is very likely that the ECC check will not pass, and the correct stored data will not be obtained.

[0006] Data retention errors are the most important component of NAND Flash data errors and have the greatest impact on NAND Flash reliability. The longest storage time required for data to be correctly read after storage is called the data retention time. How to extend data retention time and reduce data retention errors is an important research direction in this field.

[0007] In addition, when reading data from a memory cell in NAND Flash, a turn-on voltage greater than the threshold voltage of all cells is applied to the gates of the other cells in the string containing this cell, turning the cell into the on state. Due to the high turn-on voltage, the threshold voltage of the memory cell increases, causing data reading errors, which is called read disturbance.

[0008] See also Figure 3 As shown in the figure, the shaded part is the storage unit affected by read interference, see Figure 4 As shown in Figure 1, a higher on-state voltage will inject electrons into these cells. The interference effect caused by a single read disturb is small and has little impact on the reliability of NAND Flash. However, each read disturb will accumulate. After tens of thousands of read operations, the read disturb effect will become significant. See Figure 5As shown in the figure, it is a schematic diagram of current data storage, where the horizontal axis is the threshold voltage (threhold voltage) and the vertical axis is the number of storage cells. The figure takes the E, P1, P2, and P3 states as examples for explanation. The solid line represents the initial threshold voltage distribution formed by the threshold voltage of the storage cell at time zero when data is written into the flash memory, and the dotted line represents the threshold voltage distribution of the flash memory after tens of thousands of read disturbances. It can be seen from the figure that each time the data in the storage cell is read, the higher conduction voltage will inject electrons into these storage cells, causing the threshold voltage distribution of the flash memory to shift to the side with a larger threshold voltage, that is, the distribution shifts to the right. If the read voltages Vread1, Vread2, and Vread3 used at time zero for data writing are used to read the flash memory at this time, data reading errors will occur.

[0009] Therefore, how to reduce data read disturb errors and data retention errors in the memory without reducing the performance and reliability of NAND Flash is a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0010] In view of this, the purpose of the present application is to provide a memory error correction method and device, which can simultaneously reduce data read disturbance and data retention errors in the memory without reducing the reliability and performance of the memory.

[0011] To achieve the above objectives, this application has the following technical solutions:

[0012] In a first aspect, the present application provides a memory error correction method, comprising:

[0013] When it is detected that the storage time of the storage block is greater than or equal to a first preset time, or when the bit error rate of the data in the storage block is greater than or equal to a first preset threshold, the storage block is used as a target storage block;

[0014] Marking a hot data storage page corresponding to hot data as invalid so that the hot data storage page is no longer accessed; the hot data is data whose reading frequency is greater than or equal to a first preset frequency; the hot data storage page is a storage page storing the hot data;

[0015] The hot data is copied and written into a blank storage page in the target storage block.

[0016] Optionally, writing the hot data to a blank storage page in the target storage block includes:

[0017] selecting corresponding target hot data from the hot data according to the bit error rate;

[0018] The target hot data is written into a blank storage page in the target storage block.

[0019] Optionally, the method further includes:

[0020] Increasing the original on-voltage of the target memory block to a first preset voltage;

[0021] When reading data in the target memory block, the first preset voltage is applied to the target memory block to put the target memory block into a conducting state.

[0022] Optionally, the target thermal data includes:

[0023] one or more target hot data pages;

[0024] The target hot data page is a data page corresponding to the target hot data; target hot data with different reading frequencies correspond to different target hot data pages.

[0025] Optionally, writing the target hot data into a blank storage page in the target storage block includes:

[0026] The blank storage page includes multiple pages;

[0027] At different data storage moments, one or more target hot data pages are written to the blank storage page; or, at the same data storage moment, one or more target hot data pages are written.

[0028] In a second aspect, the present application provides a memory error correction device, comprising:

[0029] a target storage block determining unit, configured to, when it is detected that the storage duration of a storage block is greater than or equal to a first preset duration, or when it is detected that the bit error rate of data in the storage block is greater than or equal to a first preset threshold, use the storage block as a target storage block;

[0030] a hot data storage page invalidation unit, configured to mark a hot data storage page corresponding to hot data as invalid, so that the hot data storage page is no longer accessed; the hot data is data whose reading frequency is greater than or equal to a first preset frequency; and the hot data storage page is a storage page storing the hot data;

[0031] The hot data writing unit is configured to copy the hot data and write the hot data into a blank storage page in the target storage block.

[0032] Optionally, the hot data writing unit includes:

[0033] a target hot data selection unit, configured to select corresponding target hot data from the hot data according to the bit error rate;

[0034] The target hot data writing unit is configured to write the target hot data into a blank storage page in the target storage block.

[0035] Optionally, the device further includes:

[0036] a voltage increasing unit, configured to increase an original on-voltage of the target memory block to a first preset voltage;

[0037] The voltage applying unit is configured to apply the first preset voltage to the target memory block when reading data in the target memory block, so as to put the target memory block into a conducting state.

[0038] Optionally, the target thermal data includes:

[0039] one or more target hot data pages;

[0040] The target hot data page is a data page corresponding to the target hot data; target hot data with different reading frequencies correspond to different target hot data pages.

[0041] Optionally, the target hot data writing unit includes:

[0042] The target hot data page writing unit is used to write one or more target hot data pages to the blank storage page at different data storage moments; or write one or more target hot data pages at the same data storage moment; the blank storage page includes multiple pages.

[0043] An embodiment of the present application provides a memory error correction method and device. When it is detected that the storage time of a memory block is greater than or equal to a first preset time, or when the bit error rate of the data in the memory block is greater than or equal to a first preset threshold, the memory block is used as a target memory block, and the hot data storage page corresponding to the hot data is marked as invalid so that the hot data storage page is no longer accessed. Hot data is data with a read frequency greater than or equal to the first preset frequency, and the hot data storage page is the memory page that stores hot data. Since the read interference generated by the hot data with a high read frequency increases the threshold voltage of the target memory block, the reduction in the threshold voltage of the target memory block caused by data retention errors can be reduced, that is, data retention errors can be reduced. At the same time, since the hot data storage page is marked as invalid and not accessed, the read interference caused by the high read frequency of the hot data, which increases the threshold voltage of the hot data storage page, can be reduced, and thus data retention errors and data read interference errors of the memory can be simultaneously reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 A schematic diagram of the direction of electron movement in a current memory device subject to data retention errors;

[0046] Figure 2 is a schematic diagram of a threshold voltage distribution of a current memory device that suffers from data retention errors;

[0047] Figure 3 A schematic diagram of a current memory cell subject to a data read disturb error;

[0048] Figure 4 A schematic diagram of the direction of electron movement in a current memory device subject to a data read disturb error;

[0049] Figure 5 A schematic diagram of a distribution state of a memory device currently subject to data read disturb errors;

[0050] Figure 6 A flowchart of a memory error correction method provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of the mapping relationship between the logical pages of an upper-layer operating system and the physical pages of an underlying NAND Flash provided in an embodiment of the present application;

[0052] Figure 8 A schematic diagram of a threshold voltage distribution state of a memory cell after experiencing a data retention error and a data read disturb error provided by an embodiment of the present application;

[0053] Figure 9 A schematic diagram of the mapping relationship between a logical table and a physical table of a memory error correction method provided in an embodiment of the present application;

[0054] Figure 10 A schematic diagram showing the correspondence between data storage time and bit error rate after multiple data retention error recovery provided by an embodiment of the present application;

[0055] Figure 11 A schematic diagram of a memory error correction device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] To facilitate understanding of the reading method provided in the embodiments of the present application, we first introduce the specific application scenarios of the embodiments of the present application. A non-volatile memory includes a plurality of storage cells arranged in an array for storing data. The storage cells are divided into a number of blocks, each of which is further divided into a number of pages. Operations such as reading, writing, verifying, and clearing the non-volatile memory can all be performed on a page-by-page basis.

[0058] A nonvolatile memory device includes a memory cell array, control logic, a page buffer (PB), a wordline voltage generator, and a wordline decoder. Each column of memory cells in the memory cell array is connected to the page buffer via a bitline (BL), and the gates of each row of memory cells are connected to the wordline decoder via a wordline (WL). The control logic controls the wordline voltage generator and the page buffer. During a read operation, the control logic controls the wordline voltage generator to apply a read voltage to the selected wordline and a read pass voltage to the unselected wordlines. The page buffer then senses the data stored in the memory cells on the corresponding bitlines according to different read operation methods, thereby reading the data stored in the nonvolatile memory device.

[0059] Non-volatile memory is mainly divided into several types, such as SLC (Single-Level Cell), MLC (Milti-Level Cell), TLC (Trinary-Level Cell), and QLC (Quad-Level Cell). SLC is 1 bit / cell, and each memory cell stores 1 bit of data. The memory cell has only two storage states: "0" and "1". MLC is 2 bits / cell, and each memory cell stores 2 bits of data. The memory cell has four storage states: "00", "01", "10", and "11". TLC is 3 bits / cell, and each memory cell stores 3 bits of data. The memory cell has eight storage states: "000", "001", "010", "011", "100", "101", "110", and "111". It can be understood that the memory cells of non-volatile memory can also store more than 3 bits of data. QLC, that is, 4 bits / cell, each memory cell stores 4 bits of data, and the memory cell has 16 storage states: "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111".

[0060] To determine the storage state of a memory cell and thus read the stored data, for SLC non-volatile memories, a read operation is performed on a selected word line, a read voltage is applied to the word line, and the data is sensed. This allows the data stored in the corresponding memory cell to be read. However, for non-volatile memories such as MLC and TLC, which store multiple bits of data per cell, since each memory cell can have more than two storage states, multiple consecutive read operations are required on the same memory cell, with multiple read voltages of varying magnitudes applied to the word line, followed by sensing of the stored data. This is necessary to determine the actual storage state of the memory cell and read the data stored in the non-volatile memory.

[0061] However, during the data storage process, after the data has been stored in the flash memory for a period of time, the charge stored in the storage cell will leak, and the threshold voltage distribution in the flash memory will shift toward the side with a smaller threshold voltage. If the read voltage used in the initial stage of data storage is used for the read operation, the error rate of the read data will be high, even exceeding the ECC error correction capability.

[0062] The maximum amount of time required for data to be correctly read after storage is called data retention. Extending this time is a key research topic in this field. Data recovery technology involves charging cells with electrons to shift their threshold distribution to the right, reducing bit errors to within the ECC correction range and enabling correct decoding. However, ECC has a limited error correction range. If the original error rate of the read data is high, it will exceed the error correction capability of the error control code, making it impossible to correctly recover the written data.

[0063] refer to Figure 2 The figure shows a current data storage diagram, where the horizontal axis represents the threshold voltage (threhold voltage) and the vertical axis represents the number of storage cells. The figure uses the E, P1, P2, and P3 states as examples for illustration. The solid line represents the initial threshold voltage distribution formed by the threshold voltage of the storage cell at time zero when data is written to the flash memory, and the dotted line represents the threshold voltage distribution of the flash memory after a period of storage time. As can be seen from the figure, after a period of storage time, due to the leakage of charge retained by the storage cell, the threshold voltage distribution of the flash memory shifts toward the side with a smaller threshold voltage, that is, the distribution shifts to the left. If the read voltages Vread1, Vread2, and Vread3 used at time zero for data writing are used to read the flash memory at this time, the read data will have a high bit error rate. It is very likely that the ECC check will not pass, and the correct stored data will not be obtained.

[0064] Data retention errors are the most important component of NAND Flash data errors and have the greatest impact on NAND Flash reliability. The longest storage time required for data to be correctly read after storage is called the data retention time. How to extend data retention time and reduce data retention errors is an important research direction in this field.

[0065] In addition, when reading data from a memory cell in NAND Flash, a turn-on voltage greater than the threshold voltage of all cells is applied to the gates of the other cells in the string containing this cell, turning the cell into the on state. Due to the high turn-on voltage, the threshold voltage of the memory cell increases, causing data reading errors, which is called read disturbance.

[0066] See also Figure 3 As shown in the figure, the shaded part is the storage unit affected by read interference, see Figure 4 As shown in Figure 1, a higher on-state voltage will inject electrons into these cells. The interference effect caused by a single read disturb is small and has little impact on the reliability of NAND Flash. However, each read disturb will accumulate. After tens of thousands of read operations, the read disturb effect will become significant. See Figure 5 As shown in the figure, it is a schematic diagram of current data storage, where the horizontal axis is the threshold voltage (threhold voltage) and the vertical axis is the number of storage cells. The figure takes the E, P1, P2, and P3 states as examples for explanation. The solid line represents the initial threshold voltage distribution formed by the threshold voltage of the storage cell at time zero when data is written into the flash memory, and the dotted line represents the threshold voltage distribution of the flash memory after tens of thousands of read disturbances. It can be seen from the figure that each time the data in the storage cell is read, the higher conduction voltage will inject electrons into these storage cells, causing the threshold voltage distribution of the flash memory to shift to the side with a larger threshold voltage, that is, the distribution shifts to the right. If the read voltages Vread1, Vread2, and Vread3 used at time zero for data writing are used to read the flash memory at this time, data reading errors will occur.

[0067] Therefore, how to reduce data read disturb errors and data retention errors in the memory without reducing the performance and reliability of NAND Flash is a technical problem that needs to be solved urgently in this field.

[0068] Based on the above technical problems, the present application provides a memory error correction method and device. When it is measured that the storage time of a memory block is greater than or equal to a first preset time, or when the bit error rate of the data in the memory block is greater than or equal to a first preset threshold, the memory block is used as a target memory block, and the hot data storage page corresponding to the hot data is marked as invalid so that the hot data storage page is no longer accessed. Hot data is data with a read frequency greater than or equal to the first preset frequency, and the hot data storage page is a memory page that stores hot data. Since the read interference generated by hot data with a high read frequency increases the threshold voltage of the target memory block, the threshold voltage of the target memory block caused by data retention errors can be reduced, that is, the data retention errors can be reduced. At the same time, since the hot data storage page is marked as invalid and not accessed, the read interference caused by the high read frequency of the hot data causing the threshold voltage of the hot data storage page to increase can be reduced, which can simultaneously reduce the data retention errors and data read interference errors of the memory.

[0069] Based on the above ideas, in order to make the above-mentioned purposes, features and advantages of this application more obvious and easy to understand, the specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0070] First, it should be noted that the non-volatile memory reading method, device and related equipment provided in the embodiments of the present application are not only applicable to NAND flash memory (2D, 3D, MLC, TLC, QLC), but also applicable to other non-volatile memories such as magnetoresistive random access memory (MRAM), phase change memory (PCRAM), phase change memory and switch (PCMS), resistive memory, ferroelectric RAM (FRAM), spin torque transfer memory (STT), thermally assisted switching memory (TAS), millipede memory, floating junction gate memory (FJG RAM), battery backup RAM, etc. Each storage cell in the non-volatile memory can store 3 bits or more of data.

[0071] Exemplary Methods

[0072] refer to Figure 6 FIG. 1 is a flowchart of a memory error correction method provided in an embodiment of the present application. The method may include:

[0073] S101 , when it is detected that the storage duration of a storage block is greater than or equal to a first preset duration, or when the bit error rate of data in the storage block is greater than or equal to a first preset threshold, the storage block is used as a target storage block.

[0074] In a memory, generally speaking, within a block, the gates of each layer of memory cells are connected to a wordline decoder via a wordline, forming a page. In the embodiments of the present application, the memory can be one of 2D, 3D, MLC, TLC, and QLC, and its memory cells have multiple threshold voltage distribution states.

[0075] Therefore, in an embodiment of the present application, when writing to a storage block, a layer of blank pages can be reserved without writing data. Generally speaking, an entire layer of blank pages at the top of a storage block can be reserved to facilitate subsequent writing of hot data into the blank pages, thereby reducing data retention errors in the storage block.

[0076] When it is detected that the storage duration of the storage block is greater than or equal to a first preset duration, or when the bit error rate of data in the storage block is greater than or equal to a first preset threshold, the storage block is used as a target storage block.

[0077] Specifically, in NAND Flash, some memory blocks are frequently erased and written, known as hot data blocks. Due to frequent read and write operations, the data in hot data blocks is subject to significant read disturb. Other memory blocks, known as cold data blocks, are not erased or written for a long time after data is stored. Data in cold data blocks is stored for a long time and is prone to data retention errors.

[0078] Therefore, when it is detected that the storage time of a storage block is long, the storage block is prone to data retention errors. The storage block can be used as a target storage block to execute a subsequent memory error correction method. It should be noted that the first preset time length can be set differently for different storage blocks. The embodiment of the present application does not make specific limitations here and can be set by those skilled in the art according to actual conditions.

[0079] When it is detected that the bit error rate of the data in the storage block is greater than or equal to the first preset threshold, it indicates that a data retention error has occurred in the storage block, and the storage block can be used as a target storage block to execute a subsequent memory error correction method. It should be noted that the first preset threshold can be set differently for different storage blocks. The embodiment of the present application does not make any specific limitations here, and can be set by those skilled in the art according to actual conditions.

[0080] S102: Marking a hot data storage page corresponding to hot data as invalid so that the hot data storage page is no longer accessed; the hot data is data whose reading frequency is greater than or equal to a first preset frequency; the hot data storage page is a storage page storing the hot data;

[0081] In an embodiment of the present application, in order to reduce data read interference errors in hot data storage pages, the hot data storage pages corresponding to the hot data can first be marked as invalid so that the hot data storage pages are no longer accessed, and thus the hot data pages can no longer be read, written, or erased, thereby reducing data read interference errors in the hot data storage pages and reducing data read interference errors in the memory.

[0082] Specifically, when reading data stored in NAND Flash, some data is read frequently, called hot data, and some data is read less frequently, called cold data. Hot data is data with a read frequency greater than or equal to a first preset frequency. Accordingly, the storage page storing hot data is the hot data storage page.

[0083] Optionally, the upper-layer operating system uses sectors as the minimum operation unit, while the underlying NAND Flash chip uses pages as the minimum operation unit. Therefore, a translation layer called FTL (Flash translation layer) is required between the upper-layer operating system and the underlying NAND Flash. The function of the translation layer includes implementing the mutual mapping between logical pages and physical pages.

[0084] Specifically, the page that the upper-layer operating system can access is called a logical page, and its address is LPN (logical page number). The page where data is actually stored in NAND Flash is called a physical page, and its address is PPN (physical page number). When the data corresponding to the LPN is updated, NAND Flash does not directly change the data corresponding to the PPN, but instead marks the PPN as invalid. The invalid PPN will not be accessed, and the updated data will be written to a new PPN. The updated LPN is then mapped to the corresponding new PPN, thus updating the mapping relationship between LPN and PPN. This process is called mutual mapping between logical pages and physical pages. See Figure 7 As shown, it is a schematic diagram of the mapping relationship between LPN and PPN.

[0085] Since operations such as reading, writing, verifying, and clearing the non-volatile memory can be performed in units of pages, the hot data storage page corresponding to the hot data is marked as invalid so that the hot data storage page is no longer accessed.

[0086] First, optionally, the LPNs corresponding to all eligible hot data pages can be put into a table, called the read hot page table, and sorted from large to small according to the number of times the LPNs are read, so that they can be used for subsequent data retention error recovery.

[0087] In an embodiment of the present application, the hot data storage page corresponding to the hot data is marked as invalid so that the hot data storage page is no longer accessed, and thus the hot data page can no longer be read, written, or erased, thereby reducing the data read interference error of the hot data storage page and the data read interference error of the memory.

[0088] S103: Copy the hot data and write the hot data into a blank storage page in the target storage block.

[0089] Currently, the primary approach for handling data with a high accumulation of read interference errors is to correct it with ECC before reading it out and writing it to the original location or another location. This approach results in additional read, write, and erase operations, reducing NAND Flash performance. Currently, data with a high accumulation of read disturb errors is typically corrected with ECC before writing it to the original location or another location. This approach also results in additional read, write, and erase operations, reducing NAND Flash performance.

[0090] In an embodiment of the present application, in order to reduce data retention errors in the target storage block, hot data can be copied and written to blank storage pages in the target storage block. Since the hot data can impose a large amount of read interference on the entire target storage block, data retention errors in the target storage block are reduced.

[0091] It should be noted that, see Figure 8 As shown, a data retention error manifests as a leftward shift in the threshold voltage of a memory cell, while a data read disturb error manifests as a rightward shift in the threshold voltage of a memory cell. Data read disturb errors can be used to partially shift back the threshold voltage that was leftward shifted by the data retention error, thereby partially recovering the data retention error. However, when using data read disturb errors to reduce data retention errors, the effect gradually weakens. After the number of data reads reaches a certain threshold, the data read disturb error essentially ceases to have any further effect in reducing data retention errors. Therefore, for target memories with severe data retention errors, data retention errors can only be mitigated, but not fully recovered.

[0092] Optionally, corresponding target hot data can be selected from the hot data according to the bit error rate in the target storage block, and the target hot data can be written to a blank storage page in the target storage block to utilize the read interference error of the target hot data to recover the data retention error in the target storage block.

[0093] Specifically, optionally, a corresponding target hot data page can be selected from the hot data page table according to the bit error rate, and the target hot data page can be written into a blank storage page in the target storage block. When a certain LPN is selected to recover the data retention error in the target storage block, this LPN is removed from the hot data page table, and the PPN corresponding to the LPN is marked as invalid, so that the PPN cannot be accessed, and the hot data in this PPN is written into the blank storage page, and the mapping relationship between the LPN and the PPN is updated to use the target hot data to recover the data retention error in the target storage block.

[0094] For example, see Figure 9 As shown, when LPN1 is selected based on the bit error rate to recover data retention errors in the target memory block, LPN1 is removed from the hot data page table. PPN1 corresponding to LPN1 is marked invalid, and the hot data in PPN1 is written to a blank memory page at the new address called PPN. LPN1 is then pointed to PPN. Thus, during read and write operations, the hot data can be used to recover data retention errors in the target memory block.

[0095] In addition, optionally, see Figure 9 As shown, after the data retention error of the target storage block is recovered, the PPN can be set to invalid and the LPN can be redirected to PPN1.

[0096] In one embodiment of the present application, the original on-state voltage of the target storage block may be increased to a first preset voltage. When reading data in the target storage block, the first preset voltage is applied to the target storage block to put the target storage block into an on-state.

[0097] Since increasing the on-voltage can increase data read disturb errors, appropriately increasing the on-voltage of the target memory block and enhancing the read disturb effect can speed up the recovery of data retention errors.

[0098] It should be noted that the embodiment of the present application does not specifically limit the first preset voltage, and it can be set by those skilled in the art according to actual conditions.

[0099] Optionally, the target hot data may include one or more hot data pages to accelerate recovery from data retention errors in the target storage block. The target hot data page is the data page corresponding to the target hot data page. Target hot data with different read frequencies corresponds to different target hot data pages. In other words, a blank storage page can store multiple hot data pages, thereby accelerating recovery from data retention errors.

[0100] For example, for triple-level cell NAND Flash (TLC NAND Flash), including the low, middle, and upper pages, all three pages are written with hot data and written into the blank storage pages of the target storage block, increasing the total number of hot data reads and data read interference, thereby speeding up the recovery of data retention errors.

[0101] Optionally, when writing to the target storage block, multiple layers of blank storage pages can be reserved for writing, so that one or more target hot data pages can be written to the blank storage pages at different data storage times, or one or more target hot data pages can be written at the same data storage time. After writing to the target hot data page, read and write operations on the target hot data are awaited to utilize the read disturb effect to mitigate data retention errors.

[0102] It should be noted that the number of hot data pages that can be written into a blank memory page varies depending on the memory. For example, a blank memory page in TLC can write up to three hot data pages.

[0103] For example, see Figure 10 As shown, one or more target storage pages can be written into a blank storage page at different data storage moments, thereby utilizing multiple data recovery to extend the data retention time and reduce the bit error rate to within the ECC correctable range, thereby achieving recovery from data retention errors.

[0104] Optionally, during the process of data retention error recovery, the number of times the hot data page is read can be counted. When the number exceeds a certain threshold, the bit error rate at this time is read to determine whether the bit error rate is reduced to the ECC correctable range. If it is reached, the data retention error recovery is stopped, the blank storage pages in the target storage block are set to invalid, and the hot data pages therein are copied to other non-cold data pages. If it is not reached, the number of times the hot data page is read can continue to be counted until the maximum threshold of the number of times the hot data page can be read is reached.

[0105] An embodiment of the present application provides a memory error correction method. When it is measured that the storage duration of a memory block is greater than or equal to a first preset duration, or when the bit error rate of the data in the memory block is greater than or equal to a first preset threshold, the memory block is used as a target memory block, and the hot data storage page corresponding to the hot data is marked as invalid, so that the hot data storage page is no longer accessed. Hot data is data with a read frequency greater than or equal to the first preset frequency, and the hot data storage page is a memory page that stores hot data. Since the read interference generated by the hot data with a high read frequency increases the threshold voltage of the target memory block, the reduction in the threshold voltage of the target memory block caused by data retention errors can be reduced, that is, data retention errors can be reduced. At the same time, since the hot data storage page is marked as invalid and not accessed, the read interference caused by the high read frequency of the hot data, which increases the threshold voltage of the hot data storage page, can be reduced, thereby reducing both data retention errors and data read interference errors in the memory.

[0106] Exemplary devices

[0107] See also Figure 11 FIG. 1 is a schematic diagram of a memory error correction device provided in an embodiment of the present application, comprising:

[0108] The target storage block determining unit 1101 is configured to, when it is detected that the storage duration of a storage block is greater than or equal to a first preset duration, or when it is detected that the bit error rate of data in the storage block is greater than or equal to a first preset threshold, select the storage block as a target storage block;

[0109] A hot data storage page invalidation unit 1102 is configured to mark a hot data storage page corresponding to hot data as invalid, so that the hot data storage page is no longer accessed; the hot data is data whose reading frequency is greater than or equal to a first preset frequency; and the hot data storage page is a storage page storing the hot data;

[0110] The hot data writing unit 1103 is configured to copy the hot data and write the hot data into a blank storage page in the target storage block.

[0111] Optionally, the hot data writing unit includes:

[0112] a target hot data selection unit, configured to select corresponding target hot data from the hot data according to the bit error rate;

[0113] The target hot data writing unit is configured to write the target hot data into a blank storage page in the target storage block.

[0114] Optionally, the device further includes:

[0115] a voltage increasing unit, configured to increase an original on-voltage of the target memory block to a first preset voltage;

[0116] The voltage applying unit is configured to apply the first preset voltage to the target memory block when reading data in the target memory block, so as to put the target memory block into a conducting state.

[0117] Optionally, the target thermal data includes:

[0118] one or more target hot data pages;

[0119] The target hot data page is a data page corresponding to the target hot data; target hot data with different reading frequencies correspond to different target hot data pages.

[0120] Optionally, the target hot data writing unit includes:

[0121] The target hot data page writing unit is used to write one or more target hot data pages to the blank storage page at different data storage moments; or write one or more target hot data pages at the same data storage moment; the blank storage page includes multiple pages.

[0122] An embodiment of the present application provides an error correction device for a memory. When it is measured that the storage duration of a memory block is greater than or equal to a first preset duration, or when the bit error rate of the data in the memory block is greater than or equal to a first preset threshold, the memory block is used as a target memory block, and the hot data storage page corresponding to the hot data is marked as invalid, so that the hot data storage page is no longer accessed. Hot data is data with a read frequency greater than or equal to the first preset frequency, and the hot data storage page is a memory page that stores hot data. Since the read interference generated by the hot data with a high read frequency increases the threshold voltage of the target memory block, the reduction in the threshold voltage of the target memory block caused by data retention errors can be reduced, that is, data retention errors can be reduced. At the same time, since the hot data storage page is marked as invalid and not accessed, the read interference caused by the high read frequency of the hot data, which increases the threshold voltage of the hot data storage page, can be reduced, thus reducing both data retention errors and data read interference errors in the memory.

[0123] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0124] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A memory error correction method, characterized in that: include: When it is detected that the storage time length of the storage block is greater than or equal to the first preset time length, or when the bit error rate of the data in the storage block is greater than or equal to the first preset threshold, the storage block is used as a target storage block with data retention error; Marking a hot data storage page corresponding to the hot data as invalid, so that the hot data storage page is no longer accessed, thereby reducing data read disturbance errors of the hot data storage page; The thermal data is data with a reading frequency greater than or equal to a first preset frequency; the thermal data storage page is a storage page storing the thermal data; Copying the hot data and writing the hot data into a blank storage page in the target storage block, wherein the hot data applies read interference to the target storage block, so as to utilize the read interference to mitigate data retention errors in the target storage block; Writing the hot data into a blank storage page in the target storage block includes: Selecting corresponding target hot data from the hot data according to the bit error rate; Writing the target hot data into a blank storage page in the target storage block; Also includes: Increasing the original on-voltage of the target storage block to a first preset voltage; When reading data in the target storage block, applying the first preset voltage to the target storage block to put the target storage block in a conducting state, thereby increasing data read disturbance errors; Also includes: During the process of data retention error recovery, the number of times the hot data stored in the blank storage pages in the target storage block are read is counted. When the number exceeds a certain threshold, the bit error rate at this time is read to determine whether the bit error rate is reduced to the correctable range of the error control code ECC. If it is reached, the data retention error recovery is stopped, the blank storage pages in the target storage block are set to invalid, and the hot data therein is copied to other non-cold data pages. If it is not reached, the number of times the hot data stored in the blank storage pages in the target storage block are read continues to be counted until the maximum threshold of the number of times the hot data stored in the blank storage pages in the target storage block can be read is reached.

2. The method according to claim 1, characterized in that The target thermal data includes: one or more target hot data pages; The target hot data page is a data page corresponding to the target hot data; target hot data with different reading frequencies correspond to different target hot data pages.

3. The method according to claim 2, characterized in that The step of writing the target hot data into a blank storage page in the target storage block comprises: The blank storage page includes a plurality of pages; At different data storage moments, one or more target hot data pages are written to the blank storage page; or, at the same data storage moment, one or more target hot data pages are written.

4. A memory error correction device, characterized in that: include: a target storage block determining unit, configured to, when it is detected that the storage time length of the storage block is greater than or equal to a first preset time length, or when the bit error rate of the data in the storage block is greater than or equal to a first preset threshold, use the storage block as a target storage block with data retention errors; A hot data storage page invalidation unit, used to mark the hot data storage page corresponding to the hot data as invalid, so that the hot data storage page is no longer accessed, thereby reducing data read interference errors of the hot data storage page; The thermal data is data with a reading frequency greater than or equal to a first preset frequency; the thermal data storage page is a storage page storing the thermal data; a hot data writing unit, configured to copy the hot data and write the hot data into a blank storage page in the target storage block, wherein the hot data applies a read disturbance to the target storage block, so as to utilize the read disturbance to mitigate a data retention error in the target storage block; The thermal data writing unit comprises: a target hot data selection unit, configured to select corresponding target hot data from the hot data according to the bit error rate; A target hot data writing unit, used for writing the target hot data into a blank storage page in the target storage block; Also includes: A voltage increasing unit, used for increasing an original on-voltage of the target storage block to a first preset voltage; a voltage applying unit, configured to apply the first preset voltage to the target storage block when reading data in the target storage block, so as to put the target storage block in a conducting state and increase data read disturbance errors; The hot data writing unit is also used for: During the process of data retention error recovery, the number of times the hot data stored in the blank storage pages in the target storage block are read is counted. When the number exceeds a certain threshold, the bit error rate at this time is read to determine whether the bit error rate is reduced to the correctable range of the error control code ECC. If it is reached, the data retention error recovery is stopped, the blank storage pages in the target storage block are set to invalid, and the hot data therein is copied to other non-cold data pages. If it is not reached, the number of times the hot data stored in the blank storage pages in the target storage block are read continues to be counted until the maximum threshold of the number of times the hot data stored in the blank storage pages in the target storage block can be read is reached.

5. The device according to claim 4, characterized in that The target thermal data includes: one or more target hot data pages; The target hot data page is a data page corresponding to the target hot data; target hot data with different reading frequencies correspond to different target hot data pages.

6. The device according to claim 5, characterized in that The target hot data writing unit comprises: The target hot data page writing unit is used to write one or more target hot data pages to the blank storage page at different data storage moments; or to write one or more target hot data pages at the same data storage moment; the blank storage page includes multiple pages.

Images