Three-dimensional semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device is disclosed, including a second substrate on a first substrate, and the second substrate includes a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer; an electrode structure on the upper semiconductor layer, and the electrode structure includes a plurality of stacked electrodes; a vertical channel structure that penetrates the electrode structure and is connected to the second substrate; an interlayer dielectric layer that covers the electrode structure; and a cut structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cut structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0008895, filed on January 22, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a three-dimensional semiconductor memory device with improved reliability and a method for manufacturing the same. Background Technology

[0004] Semiconductor devices have become highly integrated to meet customer demands for high performance and low manufacturing costs. Because the integration of semiconductor devices is a significant factor in determining product pricing, the demand for highly integrated semiconductor devices is increasing. The integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a single memory cell; therefore, integration is largely influenced by the technological level required to form intricate patterns. However, the extremely expensive processing equipment required to increase pattern refinement can impose practical limitations on increasing the integration of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a three-dimensional semiconductor memory device with improved reliability.

[0006] Some exemplary embodiments of the present invention provide a method for manufacturing a three-dimensional semiconductor memory device with improved reliability.

[0007] According to an exemplary embodiment of the present invention, a semiconductor memory device may include: a second substrate on a first substrate, the second substrate including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer; an electrode structure on the upper semiconductor layer, the electrode structure including a plurality of stacked electrodes; a vertical channel structure penetrating the electrode structure and connected to the second substrate; an interlayer dielectric layer covering the electrode structure; and a dicing structure penetrating the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer may have a first sidewall defined by the dicing structure. The lower semiconductor layer may have a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall may be horizontally offset from each other.

[0008] According to an exemplary embodiment of the present invention, a semiconductor memory device may include: a second substrate on a first substrate; a dicing structure that separates the second substrate into a first semiconductor layer and a second semiconductor layer; a first electrode structure and a second electrode structure respectively on the first and second semiconductor layers, each of the first and second semiconductor layers including a plurality of stacked electrodes; a molding structure between the first electrode structure and the second electrode structure, the molding structure including a plurality of stacked sacrificial layers; and a first vertical channel structure and a second vertical channel structure that penetrate the first electrode structure and the second electrode structure respectively. The stacked sacrificial layers may be located at the same height as the corresponding stacked electrodes. The dicing structure may penetrate the molding structure and the second substrate below the molding structure.

[0009] According to an exemplary embodiment of the present invention, a semiconductor memory device may include: a peripheral circuit structure on a substrate, the peripheral circuit structure including a peripheral transistor on the substrate, peripheral lines on the peripheral transistor, and peripheral contacts electrically connecting the peripheral transistor to the peripheral lines; a lower semiconductor layer on the peripheral circuit structure; an upper semiconductor layer on the lower semiconductor layer; a dicing structure penetrating the upper semiconductor layer, the vertical height of the bottom surface of the dicing structure being between the bottom surface of the upper semiconductor layer and the bottom surface of the lower semiconductor layer; a source semiconductor layer between the lower semiconductor layer and the upper semiconductor layer; an electrode structure on the upper semiconductor layer, the electrode structure including a plurality of stacked electrodes; a vertical channel structure penetrating the electrode structure and electrically connected to the source semiconductor layer; an interlayer dielectric layer covering the electrode structure; and through contacts penetrating the interlayer dielectric layer and electrically connected to the peripheral lines. The upper semiconductor layer may have a first sidewall defined by the dicing structure. The through contacts may be spaced apart from the first sidewall.

[0010] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor memory device may include: forming a first lower semiconductor layer and a second lower semiconductor layer spaced apart from each other on a first substrate; forming an upper semiconductor layer on the first lower semiconductor layer and the second lower semiconductor layer; forming a molding structure by alternately stacking a plurality of dielectric layers and a plurality of sacrificial layers on the upper semiconductor layer; forming an interlayer dielectric layer covering the molding structure; forming a vertical channel structure penetrating the molding structure; forming a first trench penetrating the molding structure and extending in one direction; allowing a plurality of electrodes to replace the sacrificial layers exposed to the first trench; and forming a dicing structure that penetrates the interlayer dielectric layer and the upper semiconductor layer and separates the upper semiconductor layer into a first upper semiconductor layer and a second upper semiconductor layer. The first upper semiconductor layer may have a first sidewall defined by the dicing structure. The first lower semiconductor layer may have a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall may be horizontally offset from each other. Attached Figure Description

[0011] Figure 1A plan view of a first substrate on which a three-dimensional semiconductor memory device is integrated, according to an exemplary embodiment of the present invention, is shown.

[0012] Figure 2 A simplified perspective view of a three-dimensional semiconductor memory device according to an example embodiment of the present invention is shown.

[0013] Figure 3 A simplified plan view of a three-dimensional semiconductor memory device according to an example embodiment of the present invention is shown.

[0014] Figure 4 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown.

[0015] Figure 5 It shows Figure 4 The enlarged plan view of part M in the figure shows a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0016] Figure 6A , Figure 6B and Figure 6C It shows the respective along Figure 5 The cross-sectional views taken from lines I-I', II-II', and III-III'.

[0017] Figure 7 A simplified perspective view of a three-dimensional semiconductor memory device according to an example embodiment of the present invention is shown.

[0018] Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A It shows along Figure 5 The cross-sectional view taken by line I-I' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0019] Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B It shows along Figure 5 The cross-sectional view taken by line II-II' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0020] Figure 13A and Figure 13B It shows the respective along Figure 5 The cross-sectional views taken along lines I-I' and III-III' illustrate a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0021] Figure 14A and Figure 15A It shows along Figure 5 The cross-sectional view taken by line I-I' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0022] Figure 14B and Figure 15B It shows along Figure 5 The cross-sectional view taken by line II-II' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0023] Figure 16 It shows along Figure 5 The cross-sectional view taken by line I-I' illustrates a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0024] Figure 17 It shows Figure 4 The enlarged plan view of part M in the figure shows a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0025] Figure 18A and Figure 18B It shows the respective along Figure 17 The cross-sectional views taken from lines I-I' and II-II'.

[0026] Figure 19 It shows the method for forming Figure 9A and Figure 9B A cross-sectional view of the process of creating the channel hole.

[0027] Figure 20 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown.

[0028] Figure 21A and Figure 21B It shows the respective along Figure 20 The cross-sectional views taken from lines I-I' and II-II'.

[0029] Figure 22A and Figure 22B It shows the respective along Figure 20 The cross-sectional views taken along lines I-I' and II-II' illustrate a three-dimensional semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0030] Figure 23 It shows along Figure 20 The cross-sectional view taken by line I-I' shows a three-dimensional semiconductor storage device according to an exemplary embodiment of the present invention.

[0031] Figure 24 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown.

[0032] Figure 25 It shows along Figure 24 The cross-sectional view taken from line I-I'.

[0033] Figure 26 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown.

[0034] Figure 27 It shows Figure 4 The enlarged plan view of part M in the figure shows a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0035] Figure 28 It shows along Figure 27 The cross-sectional view taken from line I-I'. Detailed Implementation

[0036] Figure 1 A plan view of a first substrate on which a three-dimensional semiconductor memory device is integrated, according to an exemplary embodiment of the present invention, is shown. In the drawings, the same reference numerals consistently denote the same elements.

[0037] refer to Figure 1 The first substrate SUB (e.g., a wafer) may include chip regions 10 on which semiconductor chips are formed and scribe lines 20 between the chip regions 10. The chip regions 10 may be arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect each other. The scribe lines 20 may surround each of the chip regions 10. For example, the scribe lines 20 may be disposed between chip regions 10 adjacent to each other along the first direction D1 and between chip regions 10 adjacent to each other along the second direction D2. The scribe lines 20 may serve as boundaries between adjacent chip regions 10. For example, the scribe lines 20 may be regions in which the semiconductor substrate SUB is cut, thereby allowing the chip regions 10 to be physically separated from each other (e.g., forming individual semiconductor chips).

[0038] According to some exemplary embodiments of the present invention, each of the chip regions 10 included in the first substrate SUB may be provided thereon with a three-dimensional semiconductor memory device including memory cells arranged in three dimensions.

[0039] Figure 2 A simplified perspective view of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown. In the exemplary embodiment, Figure 2The three-dimensional semiconductor device can be disposed on the chip region 10 of the semiconductor substrate SUB, as shown above. Figure 1 It has been made public.

[0040] refer to Figure 2 A three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention may include a peripheral circuit structure PS, a cell array structure CS on the peripheral circuit structure PS, and a through contact (not shown) that vertically penetrates the cell array structure CS and the peripheral circuit structure PS. When viewed in a plan view, the cell array structure CS and the through contact may overlap with the peripheral circuit structure PS.

[0041] In some exemplary embodiments of the present invention, the peripheral circuit structure PS may include row decoders and column decoders, page buffers, control circuitry, and peripheral logic circuitry. The peripheral logic circuitry of the peripheral circuit structure PS may be integrated into, for example,... Figure 1 On the semiconductor substrate of the first substrate SUB.

[0042] A cell array structure CS may include a cell array comprising a plurality of storage cells arranged in three dimensions. For example, the cell array structure CS may include a plurality of storage blocks BLK0 to BLKn. Each of the storage blocks BLK0 to BLKn may be a data erasure unit (e.g., the smallest storage cell that can be erased in a single erase operation). Each of the storage blocks BLK0 to BLKn may include storage cells arranged in three dimensions.

[0043] Figure 3 A simplified plan view of a three-dimensional semiconductor memory device according to an example embodiment of the present invention is shown.

[0044] refer to Figure 1 and Figure 3 Each of the chip regions 10 of the first substrate SUB can be provided with the above reference. Figure 2 The peripheral circuit structure PS and the cell array structure CS are discussed.

[0045] Each of the chip regions 10 may have a peripheral circuit structure consisting of a row decoder (ROW DEC), a column decoder (COLDEC), a page buffer (PBR), and a control circuit (CTRL) (see [link]). Figure 2 The peripheral circuit structure PS).

[0046] Chip region 10 may have a cell array structure disposed thereon (see Figure 2 The cell array structure (CS) comprises multiple pads MT. The multiple pads MT can be arranged along a first direction D1 and a second direction D2. Each pad MT may include the reference above. Figure 2 The storage blocks BLK0 to BLKn are discussed.

[0047] Multiple pads MT can be configured with the external circuit structure (see...) Figure 2 The peripheral circuit structure (PS) overlaps. According to some exemplary embodiments of the present invention, the peripheral circuit structure (see...) Figure 2 The peripheral logic circuit of the PS can be freely set below the pad MT.

[0048] Figure 4 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown.

[0049] refer to Figure 4 The first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 can be disposed on the first substrate SUB of the chip region 10. The first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 can be arranged in two dimensions in the first direction D1 and the second direction D2. The first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 can be spaced apart from each other.

[0050] For example, the second lower semiconductor layer LSL2 can be adjacent to the first lower semiconductor layer LSL1 in the first direction D1. The third lower semiconductor layer LSL3 can be adjacent to the first lower semiconductor layer LSL1 in the second direction D2. The fourth lower semiconductor layer LSL4 can be adjacent to the second lower semiconductor layer LSL2 in the second direction D2. The fourth lower semiconductor layer LSL4 can be adjacent to the third lower semiconductor layer LSL3 in the first direction D1.

[0051] The upper semiconductor layer USL can be disposed on the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4. The upper semiconductor layer USL can include the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 respectively disposed on the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4. The diced structure TCP can divide the upper semiconductor layer USL into the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4. The first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 can be insulated from each other.

[0052] For example, the cut structure TCP may include a fourth cut structure TCP4 defining the outer periphery of the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4. The cut structure TCP may also include a first cut structure TCP1 and a second cut structure TCP2 extending transversely through the interior of the fourth cut structure TCP4 in a first direction D1. The first cut structure TCP1 and the second cut structure TCP2 may extend parallel to each other between the first upper semiconductor layer USL1 and the third upper semiconductor layer USL3. The first cut structure TCP1 and the second cut structure TCP2 may extend parallel to each other between the second upper semiconductor layer USL2 and the fourth upper semiconductor layer USL4. The cut structure TCP may also include a third cut structure TCP3 extending transversely through the interior of the fourth cut structure TCP4 in a second direction D2. The third cut structure TCP3 may extend between the first upper semiconductor layer USL1 and the second upper semiconductor layer USL2 in a second direction D2. The third cut structure TCP3 may extend between the third upper semiconductor layer USL3 and the fourth upper semiconductor layer USL4 in a second direction D2.

[0053] The upper semiconductor layer USL may further include a first dummy semiconductor layer DSL1 and a second dummy semiconductor layer DSL2 defined by the cut structure TCP. The first dummy semiconductor layer DSL1 may be inserted between the first upper semiconductor layer USL1 and the third upper semiconductor layer USL3. For example, the first dummy semiconductor layer DSL1 may be adjacent to both the first upper semiconductor layer USL1 and the third upper semiconductor layer USL3. The second dummy semiconductor layer DSL2 may be inserted between the second upper semiconductor layer USL2 and the fourth upper semiconductor layer USL4. For example, the second dummy semiconductor layer DSL2 may be adjacent to both the second upper semiconductor layer USL2 and the fourth upper semiconductor layer USL4.

[0054] The first electrode structures ST1 to ST4 can be disposed on the upper semiconductor layer USL. The first electrode structures ST1 to ST4 can be respectively disposed on the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4. Each of the first electrode structures ST1 to ST4 can be a memory structure including three-dimensionally arranged memory cells. Each of the first electrode structures ST1 to ST4 can constitute the above-mentioned reference. Figure 3 The discussion focuses on a single pad MT. Figure 4 In the example, chip region 10 includes four pads MT, but the embodiment is not limited to this.

[0055] The first molded structure MO1 can be inserted between the first electrode structure ST1 and the second electrode structure ST2, which are adjacent to each other in the first direction D1. The second molded structure MO2 can be inserted between the third electrode structure ST3 and the fourth electrode structure ST4, which are adjacent to each other in the first direction D1.

[0056] A through-contact region TVR can be provided between the first electrode structure ST1 and the third electrode structure ST3, and between the second electrode structure ST2 and the fourth electrode structure ST4. The through-contact region TVR can be arranged along the first direction D1. The through-contact region TVR can be located between the first cutting structure TCP1 and the second cutting structure TCP2.

[0057] Figure 5 It shows Figure 4 The enlarged plan view of part M in the figure shows a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. Figure 6A , Figure 6B and Figure 6C It shows the respective along Figure 5 The cross-sectional views taken from lines I-I', II-II', and III-III'. Figure 7 A simplified perspective view of a three-dimensional semiconductor memory device according to an example embodiment of the present invention is shown.

[0058] refer to Figure 5 , Figure 6A , Figure 6B and Figure 6C The first substrate SUB may have a peripheral circuit structure PS including a peripheral transistor PTR disposed thereon. The peripheral circuit structure PS may have a cell array structure CS including a first electrode structure ST1 to a fourth electrode structure ST4 disposed thereon. The first substrate SUB may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The first substrate SUB may include an active region defined by a device isolation layer DIL.

[0059] The peripheral circuit structure PS may include a plurality of peripheral transistors PTR disposed on the active region of the first substrate SUB. The peripheral circuit structure PS may also include a first interlayer dielectric layer ILD1 covering the peripheral transistors PTR.

[0060] As described above, the peripheral transistor PTR can form row and column decoders, page buffers, control circuits, and peripheral logic circuits. The peripheral line PIL can be electrically connected to the peripheral transistor PTR through the peripheral contact PCNT.

[0061] The first interlayer dielectric layer ILD1 may cover the peripheral transistor PTR, the peripheral contact PCNT, and the peripheral line PIL. In some embodiments, the top surface of the uppermost peripheral line PIL may be coplanar with the top surface of the first interlayer dielectric layer ILD1. The first interlayer dielectric layer ILD1 may include multiple stacked dielectric layers. For example, the first interlayer dielectric layer ILD1 may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0062] The etch stop layer (ESL) can be placed on the first interlayer dielectric layer (ILD1) of the peripheral circuit structure PS. A second interlayer dielectric layer (ILD2) and a cell array structure (CS) can be placed on the ESL. The cell array structure (CS) will be described in detail below.

[0063] The first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 can be disposed on the etch stop layer ESL. The first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 can be disposed in the second interlayer dielectric layer ILD2. The second interlayer dielectric layer ILD2 can insulate the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 from each other. For example, the vertical height of the top surface of the second interlayer dielectric layer ILD2 can be higher than the vertical height of the top surface of the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4.

[0064] The first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 may comprise semiconductor materials, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof. Each of the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 may have at least one selected from single-crystal structures, amorphous structures, and polycrystalline structures. For example, the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 may comprise a polycrystalline silicon layer doped with n-type impurities. As another example, the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 may also comprise a conductive material such as a metal.

[0065] The upper semiconductor layer USL can be disposed on the first lower semiconductor layers LSL1 to the fourth lower semiconductor layers LSL4 and the second interlayer dielectric layer ILD2. The upper semiconductor layer USL may include the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 respectively disposed on the first lower semiconductor layers LSL1 to the fourth lower semiconductor layers LSL4. The upper semiconductor layer USL may also include the first dummy semiconductor layer DSL1 and the second dummy semiconductor layer DSL2.

[0066] The upper semiconductor layer USL may include a semiconductor material, and the description of the semiconductor material may be substantially the same as that of the first lower semiconductor layers LSL1 to the fourth lower semiconductor layers LSL4. For example, the upper semiconductor layer USL may include a polycrystalline silicon layer doped with n-type impurities. The impurity concentration of the upper semiconductor layer USL may differ from the impurity concentration of the first lower semiconductor layers LSL1 to the fourth lower semiconductor layers LSL4.

[0067] The first electrode structure ST1 to the fourth electrode structure ST4 can be respectively disposed on the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4. The first electrode structure ST1, which is selected as the representative of the first electrode structure ST1 to the fourth electrode structure ST4, will be described in detail below. The description of the first electrode structure ST1 can also be applied to the second electrode structure ST2, the third electrode structure ST3, and the fourth electrode structure ST4.

[0068] The first electrode structure ST1 may include electrodes EL stacked vertically (e.g., third direction D3) on the first upper semiconductor layer USL1. The first electrode structure ST1 may also include a first dielectric layer IL1 that separates the stacked electrodes EL from each other. The first electrode structure ST1 may be configured such that the first dielectric layer IL1 and the electrodes EL are stacked alternately on the third direction D3.

[0069] The first electrode structure ST1 can extend from the cell array region CAR of the first lower semiconductor layer LSL1 toward the connection region CNR of the first lower semiconductor layer LSL1. The first electrode structure ST1 can have a stepped structure STS on the connection region CNR. For example, the stepped structure STS of the first electrode structure ST1 can be adjacent to the stepped structure STS of the third electrode structure ST3 in the second direction D2. The stepped structure STS of the first electrode structure ST1 can face the stepped structure STS of the third electrode structure ST3.

[0070] The lowest electrode EL of the first electrode structure ST1 can be the lower select line. The highest electrode EL of the first electrode structure ST1 can be the upper select line. Word lines can be defined to indicate the other electrodes EL besides the lower and upper select lines.

[0071] Electrode EL may include a conductive material selected from the following: doped semiconductor (e.g., doped silicon), metal (e.g., tungsten, copper, or aluminum), conductive metal nitride (e.g., titanium nitride or tantalum nitride), and transition metal (e.g., titanium or tantalum). The first dielectric layer IL1 may include a silicon oxide layer.

[0072] The first electrode structure ST1 on the cell array region CAR may further include a second dielectric layer IL2. The second dielectric layer IL2 may be selectively disposed on the cell array region CAR, rather than on the connection region CNR. For example, the side surface of the second dielectric layer IL2 may be vertically aligned with the side surface of the uppermost electrode EL. The thickness of the second dielectric layer IL2 may be greater than the thickness of the first dielectric layer IL1. The second dielectric layer IL2 may include the same dielectric material as the first dielectric layer IL1. For example, the second dielectric layer IL2 may include a silicon oxide layer. Thickness may refer to the thickness or height measured in a direction perpendicular to the top surface of the substrate SUB.

[0073] On the cell array region CAR, multiple vertical channel structures VS can be arranged to penetrate the first electrode structure ST1. When viewed in a plan view, the vertical channel structures VS can be arranged in a straight or zigzag pattern. Each of the vertical channel structures VS may include a vertical dielectric pattern VP, a vertical semiconductor pattern SP, and a buried dielectric pattern VI.

[0074] A vertical dielectric pattern VP can be inserted between the first electrode structure ST1 and the vertical semiconductor pattern SP, and can extend toward the first lower semiconductor layer LSL1. The vertical dielectric pattern VP can have a tubular shape with an open top. The vertical semiconductor pattern SP can cover the inner wall of the vertical dielectric pattern VP, and can extend toward the first lower semiconductor layer LSL1 together with the vertical dielectric pattern VP. The vertical semiconductor pattern SP can also have a tubular shape with an open top. A buried dielectric pattern VI can fill the interior of the vertical semiconductor pattern SP.

[0075] The vertical dielectric pattern VP can be formed from a single thin layer or multiple thin layers. In some exemplary embodiments of the present invention, the vertical dielectric pattern VP may include a data storage layer. For example, the vertical dielectric pattern VP may include a tunnel dielectric layer, a charge storage layer, and a barrier dielectric layer, which constitute the data storage layer of a NAND flash memory device.

[0076] The charge storage layer can be, for example, a trap dielectric layer, a floating gate electrode, or a dielectric layer comprising conductive nanodots. The charge storage layer can include at least one selected from silicon nitride layers, silicon oxynitride layers, silicon-rich nitride layers, nanocrystalline silicon layers, and stacked trap layers. The tunnel dielectric layer can include a material with a band gap larger than that of the charge storage layer. The tunnel dielectric layer can include a silicon oxide layer or a high-k dielectric layer, such as an aluminum oxide layer and a hafnium oxide layer. The blocking dielectric layer can include a silicon oxide layer.

[0077] Vertical semiconductor patterns SP can include semiconductor materials such as silicon (Si), germanium (Ge), or mixtures thereof. Additionally or alternatively, vertical channel structures VS can be doped semiconductors or undoped intrinsic semiconductors. Vertical semiconductor patterns SP comprising semiconductor materials can be used as channels for transistors constituting NAND cell strings.

[0078] Conductive pads (PADs) can be disposed on the upper part of each vertical channel structure (VS). The conductive pads (PADs) can cover the top surface of the vertical semiconductor pattern (SP) and the top surface of the buried dielectric pattern (VI). The conductive pads (PADs) can include one or more of doped semiconductor materials and conductive materials. Bit line contact plugs (BPLGs) can be electrically connected to the vertical semiconductor pattern (SP) via the conductive pads (PADs).

[0079] A source semiconductor layer SSP can be inserted between a first lower semiconductor layer LSL1 and a first upper semiconductor layer USL1. The source semiconductor layer SSP can electrically connect the first lower semiconductor layer LSL1 to the first upper semiconductor layer USL1. The source semiconductor layer SSP can directly contact the lower sidewall of each vertical semiconductor pattern SP. The source semiconductor layer SSP can electrically connect multiple vertical semiconductor patterns SP to each other. In some embodiments, the top surface of the source semiconductor layer SSP can contact the bottom surface of the first upper semiconductor layer USL1, and the bottom surface of the source semiconductor layer SSP can contact the top surface of the first lower semiconductor layer LSL1. The top surface of the source semiconductor layer SSP can be coplanar with the top surface of the second interlayer dielectric layer ILD2. The side surface of the source semiconductor layer SSP can be vertically aligned with the side surface of the first lower semiconductor layer LSL1. As used herein, unless the context otherwise indicates, the term "contact" means direct connection (i.e., touching).

[0080] In summary, electrical connections can be established between the vertical semiconductor pattern SP, the source semiconductor layer SSP, the first lower semiconductor layer LSL1, and the first upper semiconductor layer USL1. The first lower semiconductor layer LSL1, the source semiconductor layer SSP, and the first upper semiconductor layer USL1 can be used as the source of the memory cell. The source semiconductor layer SSP may include a semiconductor layer doped with n-type impurities.

[0081] The second substrate may consist of lower semiconductor layers LSL1 to LSL4, a source semiconductor layer SSP, and an upper semiconductor layer USL. The first substrate SUB may support the peripheral circuit structure PS, and the second substrate may support the cell array structure CS. The second substrate may include one or more of semiconductor layers and conductive layers. For example, refer to the following discussion... Figure 16 The second substrate may also include a metal pattern MP under each of the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4.

[0082] refer to Figure 5 , Figure 6B and Figure 6C Multiple discrete semiconductor structure (SPS) layers can penetrate the first electrode structure ST1. The discrete SPS layers can extend longitudinally parallel to each other in a second direction D2. For example, the first electrode structure ST1 can be configured such that the discrete SPS layers horizontally separate a single electrode EL into multiple electrodes EL. The multiple electrodes EL separated by the discrete SPS layers can extend parallel to each other in the second direction D2. The bottom surface of the discrete SPS layers can contact the top surface of the source semiconductor layer SSP. The discrete SPS layers can include a dielectric material, such as silicon oxide.

[0083] According to some exemplary embodiments of the present invention, NAND flash memory devices can be used as three-dimensional semiconductor memory devices. Multiple NAND cell strings can be integrated into a first electrode structure ST1 on a first lower semiconductor layer LSL1. For example, the first electrode structure ST1 and the vertical channel structure VS penetrating it can constitute a memory cell arranged three-dimensionally on the first lower semiconductor layer LSL1. The electrode EL of the first electrode structure ST1 can be used as the gate electrode of a transistor.

[0084] refer to Figure 5 The first molding structure MO1 can be disposed between the first electrode structure ST1 and the second electrode structure ST2, and the second molding structure MO2 can be disposed between the third electrode structure ST3 and the fourth electrode structure ST4. When viewed in a plan view, the first molding structure MO1 can be disposed between the first lower semiconductor layer LSL1 and the second lower semiconductor layer LSL2, and the second molding structure MO2 can be disposed between the third lower semiconductor layer LSL3 and the fourth lower semiconductor layer LSL4. The first molding structure MO1, selected as a representative of the first molding structure MO1 and the second molding structure MO2, will be described in detail below.

[0085] refer to Figure 6C The first molding structure MO1 may include a sacrificial layer HL stacked on the second interlayer dielectric layer ILD2 along the third direction D3. The first molding structure MO1 may also include a first dielectric layer IL1 that separates the stacked sacrificial layers HL from each other. The first molding structure MO1 may be configured such that the first dielectric layer IL1 and the sacrificial layer HL are stacked alternately on the third direction D3.

[0086] The sacrificial layer HL can be disposed at the same height as the corresponding electrode EL of the first electrode structure ST1. The sacrificial layer HL can also be disposed at the same height as the corresponding electrode EL of the second electrode structure ST2. In this configuration, the sacrificial layer HL of the first molding structure MO1 can physically connect the electrode EL of the first electrode structure ST1 to the electrode EL of the second electrode structure ST2. The sacrificial layer HL may include a dielectric material, such as a silicon oxide layer or a silicon oxynitride layer. Because the sacrificial layer HL of the first molding structure MO1 includes a dielectric material, the first molding structure MO1 can insulate the first electrode structure ST1 and the second electrode structure ST2 from each other.

[0087] Return to Figure 6A The third interlayer dielectric layer ILD3 can be disposed on the upper semiconductor layer USL. The third interlayer dielectric layer ILD3 can cover the stepped structure STS of each of the first electrode structures ST1 to the fourth electrode structure ST4. The top surface of the third interlayer dielectric layer ILD3 can be coplanar with the top surface of the second dielectric layer IL2. The fourth interlayer dielectric layer ILD4 can be disposed on the second dielectric layer IL2 and the third interlayer dielectric layer ILD3.

[0088] Multiple bit line contact plugs (BPLGs) can penetrate the fourth interlayer dielectric layer (ILD4) and can be coupled to corresponding conductive pads (PADs) on the upper part of the vertical channel structure (VS). Multiple bit lines (BLs) can be disposed on the fourth interlayer dielectric layer (ILD4). The bit lines (BLs) can extend parallel to each other in the first direction (D1). Each of the bit lines (BLs) can be electrically connected to the vertical semiconductor pattern (SP) through the bit line contact plugs (BPLGs).

[0089] Multiple unit contact plugs PLG can penetrate the third interlayer dielectric layer ILD3 and the fourth interlayer dielectric layer ILD4, and can be coupled to the corresponding electrode EL constituting the stepped structure STS. Multiple connection lines CL can be disposed on the fourth interlayer dielectric layer ILD4. Each of the connection lines CL can be electrically connected to the electrode EL through the unit contact plug PLG.

[0090] refer to Figure 4 , Figure 5 and Figure 6AA cut structure TCP can be configured. For example, a cut structure TCP can be formed to fill the second trench TR2. The cut structure TCP can penetrate the upper semiconductor layer USL and the third interlayer dielectric layer ILD3 and the fourth interlayer dielectric layer ILD4 and extend vertically to the second interlayer dielectric layer ILD2. The cut structure TCP can separate the upper semiconductor layer USL into first upper semiconductor layers USL1 to fourth upper semiconductor layers USL4 and first dummy semiconductor layers DSL1 and second dummy semiconductor layers DSL2. The bottom surface of the cut structure TCP can be lower than the bottom surface of the upper semiconductor layer USL. For example, the vertical height of the bottom surface of the cut structure TCP can be lower than the vertical height of the top surface of the second interlayer dielectric layer ILD2. The cut structure TCP can include a dielectric material, such as a silicon oxide layer.

[0091] The cut structure TCP may include, for example, a first cut structure TCP1 extending in a first direction D1, a second cut structure TCP2 extending in the first direction D1, and a third cut structure TCP3 extending in a second direction D2. When viewed in a plan view, the first cut structure TCP1, the second cut structure TCP2, and the third cut structure TCP3 may each have a linear shape. Figure 4 As shown, the cut structure TCP may further include a fourth cut structure TCP4, which defines the periphery of the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4.

[0092] refer to Figure 5 and Figure 6A The first dicing structure TCP1 and the second dicing structure TCP2 can be disposed between the first electrode structure ST1 and the third electrode structure ST3. The first dicing structure TCP1 and the second dicing structure TCP2 can divide the upper semiconductor layer USL into a first upper semiconductor layer USL1 and a second upper semiconductor layer USL2. The first dicing structure TCP1 and the second dicing structure TCP2 can insulate the first upper semiconductor layer USL1 and the second upper semiconductor layer USL2 from each other. The upper semiconductor layer USL may have a portion retained between the first dicing structure TCP1 and the second dicing structure TCP2, and the retained portion of the upper semiconductor layer USL can be defined as a first dummy semiconductor layer DSL1.

[0093] refer to Figure 5 and Figure 6CThe third dicing structure TCP3 can penetrate the first molding structure MO1 and the second molding structure MO2. For example, the third dicing structure TCP3 can penetrate the sacrificial layer HL of the first molding structure MO1, and it can also penetrate the upper semiconductor layer USL below the first molding structure MO1. The third dicing structure TCP3 can divide the upper semiconductor layer USL below the first molding structure MO1 into a first upper semiconductor layer USL1 and a second upper semiconductor layer USL2.

[0094] refer to Figure 6A The first upper semiconductor layer USL1 may have a first sidewall SW1 defined by a first dicing structure TCP1. The first lower semiconductor layer LSL1 below the first upper semiconductor layer USL1 may have a second sidewall SW2 adjacent to the first sidewall SW1. When viewed in the second direction D2, the second sidewall SW2 of the first lower semiconductor layer LSL1 may face the third lower semiconductor layer LSL3. The first sidewall SW1 may not be aligned with the second sidewall SW2. The first sidewall SW1 may be offset from the second sidewall SW2 in the second direction D2. The first sidewall SW1 may protrude beyond the second sidewall SW2 in the second direction D2. The first sidewall SW1 may be at an angle relative to the top surface of the substrate SUB. The second sidewall SW2 may be perpendicular to the top surface of the substrate SUB.

[0095] The dielectric pattern IP can be disposed on the through contact region TVR of the upper semiconductor layer USL. The dielectric pattern IP can also be disposed in the first dummy semiconductor layer DSL1 of the upper semiconductor layer USL. For example, the dielectric pattern IP can be formed to fill the opening OP in the first dummy semiconductor layer DSL1. The dielectric pattern IP can penetrate the first dummy semiconductor layer DSL1. The dielectric pattern IP can have a top surface and a bottom surface that are coplanar with the corresponding top and bottom surfaces of the first dummy semiconductor layer DSL1. The dielectric pattern IP can have a bottom surface that contacts the top surface of the second interlayer dielectric layer ILD2. The dielectric pattern IP can have a top surface that contacts the bottom surface of the third interlayer dielectric layer ILD3.

[0096] At least one through-contact TVS can be provided, which penetrates the fourth interlayer dielectric layer ILD4, the third interlayer dielectric layer ILD3, the dielectric pattern IP, the second interlayer dielectric layer ILD2, and the etch stop layer ESL, and is electrically connected to the peripheral line PIL of the peripheral circuit structure PS. When viewed in a plan view, the through-contact TVS can be located in the through-contact region TVR. For example, the through-contact TVS can be provided between the first electrode structure ST1 and the third electrode structure ST3. The through-contact TVS can be surrounded by spacers SS comprising dielectric material.

[0097] At least one connecting line CL can extend to the through contact TVS. The connecting line CL can be electrically connected to the peripheral line PIL via the through contact TVS. For example, the electrode EL can be electrically connected to the peripheral line PIL of the peripheral circuit structure PS via the connecting line CL and the through contact TVS.

[0098] refer to Figure 7 According to an exemplary embodiment of the present invention, the cut structure TCP can separate the cell array structure CS into multiple components. For example, the cut structure TCP can divide the upper semiconductor layer USL into multiple portions, which is formed in a single-plate shape across the entire surface of the first substrate SUB. When viewed in a plan view, the upper semiconductor layer USL divided by the cut structure TCP can be shaped like a tile. (Refer to above) Figure 3 The single pad MT discussed may include multiple tiles.

[0099] Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A It shows along Figure 5 The cross-sectional view taken by line I-I' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B It shows along Figure 5 The cross-sectional view taken by line II-II' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0100] refer to Figure 5 , Figure 8A and Figure 8B The peripheral circuit structure PS can be formed on the first substrate SUB. The formation of the peripheral circuit structure PS may include: forming a peripheral transistor PTR on the first substrate SUB, forming a peripheral line PIL on the peripheral transistor PTR, forming a peripheral contact PCNT that connects the peripheral transistor PTR to the peripheral line PIL, and forming a first interlayer dielectric layer ILD1.

[0101] For example, the formation of a peripheral transistor (PTR) may include: forming a device isolation layer (DIL) defining an active region on a first substrate (SUB), forming a gate dielectric layer and a gate electrode on the active region, and implanting impurities into the active region to form a source / drain region.

[0102] An etch stop layer (ESL) can be formed on the first interlayer dielectric layer (ILD1). A second interlayer dielectric layer (ILD2) can be formed on the etch stop layer (ESL). First lower semiconductor layers (LSL1) to fourth lower semiconductor layers (LSL4) can be formed on the second interlayer dielectric layer (ILD2).

[0103] The formation of the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4 may include: forming the first semiconductor layer on the entire surface of the first substrate SUB, and performing a patterning process on the first semiconductor layer. The patterning process may divide the first semiconductor layer into four parts, and the four parts may be defined accordingly as the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4.

[0104] The third dielectric layer IL3, the lower sacrificial layer LHL, and the fourth dielectric layer IL4 may be formed on each of the first lower semiconductor layers LSL1 to LSL4. When viewed in a plan view, the lower sacrificial layer LHL may overlap with a corresponding one of the first lower semiconductor layers LSL1 to LSL4. For example, the third dielectric layer IL3 and the fourth dielectric layer IL4 may comprise silicon oxide layers, and the lower sacrificial layer LHL may comprise a silicon nitride layer or a silicon oxynitride layer.

[0105] The upper semiconductor layer USL can be formed on the entire surface of the first substrate SUB. The upper semiconductor layer USL can be formed in a plate-like shape on the entire surface of the first substrate SUB. For example, when viewed in a plan view, the upper semiconductor layer USL can cover multiple chip regions (see...). Figure 1 The chip region 10). The upper semiconductor layer USL may include at least one through contact region TVR.

[0106] For example, the upper semiconductor layer USL can be formed by depositing a polysilicon layer to cover the entire surface of the first substrate SUB. As one embodiment, impurities can be doped in situ simultaneously with the deposition of the upper semiconductor layer USL. As another embodiment, the upper semiconductor layer USL can be doped with impurities after deposition.

[0107] The through-contact region (TVR) of the upper semiconductor layer (USL) can be selectively etched to form an opening (OP). A dielectric pattern (IP) can be formed to fill the opening (OP). The dielectric pattern (IP) may include a dielectric material, such as a silicon oxide layer.

[0108] A first molding structure MO1 and a second molding structure MO2 can be formed on an upper semiconductor layer USL. For example, a first dielectric layer IL1 and a sacrificial layer HL can be alternately formed on the upper semiconductor layer USL in a vertical direction to form a molding structure. A second dielectric layer IL2 can be formed on top of the molding structure.

[0109] The first dielectric layer IL, the sacrificial layer HL, and the second dielectric layer IL2 can be deposited using thermochemical vapor deposition (CVD), plasma-enhanced CVD, physical CVD processes, or atomic layer deposition (ALD). The first dielectric layer IL1 may include a silicon oxide layer, and the sacrificial layer HL may include a silicon nitride layer or a silicon oxynitride layer.

[0110] The molding structure can be patterned to form a first molding structure MO1 and a second molding structure MO2 spaced apart from each other in the second direction D2. The first molding structure MO1 can be formed on a first lower semiconductor layer LSL1 and a second lower semiconductor layer LSL2. The second molding structure MO2 can be formed on a third lower semiconductor layer LSL3 and a fourth lower semiconductor layer LSL4.

[0111] Each of the first molding structure MO1 and the second molding structure MO2 can be formed having a stepped structure STS. The first molding structure MO1 will be discussed exemplarily below. The first lower semiconductor layer LSL1 may include a cell array region CAR and a connection region CNR. The first molding structure MO1 may undergo a cyclic process to form the stepped structure STS on the connection region CNR. For example, the formation of the stepped structure STS may include: forming a mask pattern (not shown) on the first molding structure MO1, and repeatedly performing a cyclic process using the mask pattern. The cyclic process may include: using the mask pattern as an etching mask to etch a portion of the first molding structure MO1, and performing a trimming process to reduce the size of the mask pattern.

[0112] The third interlayer dielectric layer ILD3 can be formed on the first molding structure MO1 and the second molding structure MO2. The formation of the third interlayer dielectric layer ILD3 may include: forming a thick dielectric layer to cover the first molding structure MO1 and the second molding structure MO2, and performing a planarization process on the dielectric layer until the second dielectric layer IL2 is exposed.

[0113] refer to Figure 5 , Figure 9A and Figure 9B Channel holes CH can be formed to penetrate each of the first molding structure MO1 and the second molding structure MO2. For example, multiple channel holes CH penetrating the first molding structure MO1 can be formed on the cell array region CAR of the first lower semiconductor layer LSL1. The bottom surface of each channel hole CH can be at the vertical height between the bottom and top surfaces of the first lower semiconductor layer LSL1.

[0114] refer to Figure 19The formation of channel holes CH on the entire surface of the first substrate SUB or on the entire surface of the wafer will be described in detail below. The formation of channel holes CH may include: forming a hard mask layer MAP with an opening on the molded structure MO, the opening defining the area where the channel holes CH will be formed, and using the hard mask layer MAP as an etching mask for an anisotropic etching process for anisotropically etching the molded structure MO.

[0115] The hard mask layer MAP may include: silicon-containing materials, such as silicon oxide, silicon nitride, silicon oxynitride, or polycrystalline silicon; carbon-containing materials, such as amorphous carbon layer (ACL) or spin-on hard mask (SOH) layer; metal-containing materials, such as tungsten; or organic materials. The hard mask layer MAP can be formed to cover the entire surface of the first substrate SUB. At the edges of the first substrate SUB, the hard mask layer MAP can directly contact the upper semiconductor layer USL and the top surface of the edge of the first substrate SUB.

[0116] When viewed in a planar view, the channel vias CH can be arranged in one direction or in a zigzag pattern. For example, the anisotropic etching process used to form the channel vias CH can be a plasma etching process, a reactive ion etching (RIE) process, a radio frequency inductively coupled plasma reactive ion etching (ICP-RIE) process, or an ion beam etching (IBE) process.

[0117] When anisotropic etching processes are performed using high-power plasma, ions and / or positive charges caused by free radicals included in the plasma can be charged or accumulated on the surface of the upper semiconductor layer USL exposed to the channel via CH.

[0118] In the fabrication process of a three-dimensional semiconductor memory device according to some exemplary embodiments of the present invention, a first substrate SUB can be placed on a support (not shown) of a semiconductor manufacturing apparatus. While performing an anisotropic etching process to form channel vias CH, a ground voltage can be supplied from the support to the first substrate SUB.

[0119] The upper semiconductor layer USL can be formed as a plate covering the entire surface of the first substrate SUB. Therefore, the upper semiconductor layer USL can directly contact the first substrate SUB at its edges. This allows a ground voltage to be provided to the upper semiconductor layer USL via the support and the first substrate SUB during anisotropic etching processes. Consequently, during anisotropic etching processes using plasma (e.g., during the formation of vias CH), the positive charge accumulated on the upper semiconductor layer USL can be released to the outside.

[0120] Additionally, when the hard mask layer (MAP) includes an amorphous carbon layer (ACL), negative charges can be introduced or accumulated on the amorphous carbon layer during anisotropic etching processes using plasma. For example... Figure 19 As shown, the hard mask layer MAP can also directly contact the first substrate SUB at the edge of the first substrate SUB, so that the negative charge accumulated on the hard mask layer MAP can be released through the first substrate SUB.

[0121] According to some exemplary embodiments of the present invention, the upper semiconductor layer USL can be divided into multiple tiles (e.g., Figure 4 The formation of the channel via CH is performed before the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4. Therefore, while the channel via CH is being formed, the upper semiconductor layers USL on the first substrate SUB can be electrically grounded across their entire surface. Thus, arcing can be prevented during the formation of the channel via CH.

[0122] Refer again Figure 5 , Figure 9A and Figure 9B A vertical channel structure VS can be formed in the corresponding channel hole CH. The formation of the vertical channel structure VS may include: sequentially forming a vertical dielectric layer, a vertical semiconductor layer, and a buried dielectric layer on the inner wall of the channel hole CH, and performing a planarization process until the top surface of the second dielectric layer IL2 is exposed. The vertical dielectric layer and the vertical semiconductor layer can be formed conformally.

[0123] For example, a vertical dielectric pattern VP can be formed to cover the inner wall of a channel via CH. The vertical dielectric pattern VP can have a tubular shape, with an open top and a closed bottom. The vertical dielectric pattern VP can include a data storage layer. A vertical semiconductor pattern SP can be formed to cover the inner wall of the vertical dielectric pattern VP. The vertical semiconductor pattern SP can have a tubular shape, with an open top and a closed bottom. A buried dielectric pattern VI can be formed to fill the interior of the vertical semiconductor pattern SP. The vertical dielectric pattern VP, the vertical semiconductor pattern SP, and the buried dielectric pattern VI can constitute a vertical channel structure VS. Conductive pads PAD can be formed on the top of each of the vertical channel structures VS.

[0124] refer to Figure 5 , Figure 10A and Figure 10B The fourth interlayer dielectric layer ILD4 can be formed on the first molding structure MO1, the second molding structure MO2, and the third interlayer dielectric layer ILD3. The first molding structure MO1 and the second molding structure MO2 can be patterned to form a first trench TR1 penetrating each of the first molding structure MO1 and the second molding structure MO2. The first trench TR1 can extend parallel to each other in a first direction D1.

[0125] The first trench TR1 can expose the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4. Each of the first trenches TR1 can expose the sidewalls of the sacrificial layer HL. Each of the first trenches TR1 can expose the sidewalls of the third dielectric layer IL3, the sidewalls of the lower sacrificial layer LHL, and the sidewalls of the fourth dielectric layer IL4.

[0126] Similar to the formation of the channel via CH, the formation of the first trench TR1 can be achieved using an anisotropic etching process employing high-energy plasma. Therefore, positive charges can accumulate on the surface of the upper semiconductor layer USL, thereby generating an electric arc. Conversely, as referenced above… Figure 19 As discussed, because a ground voltage is applied to the plate-shaped upper semiconductor layer USL, the generation of an electric arc can be suppressed during the formation of the first trench TR1.

[0127] refer to Figure 5 , Figure 11A and Figure 11B The source semiconductor layer SSP can replace the lower sacrificial layer LHL exposed to the first trench TR1. For example, the lower sacrificial layer LHL exposed to the first trench TR1 can be selectively removed. Removal of the lower sacrificial layer LHL can expose the lower part of the vertical dielectric pattern VP of each of the vertical channel structures VS.

[0128] The exposed lower portion of the vertical dielectric pattern VP can be selectively removed. Therefore, the lower portion of the vertical semiconductor pattern SP can be exposed. Simultaneously with removing the lower portion of the vertical dielectric pattern VP, the third dielectric layer IL3 and the fourth dielectric layer IL4 can also be removed.

[0129] The source semiconductor layer SSP can be formed in the space where the third dielectric layer IL3, the lower sacrificial layer LHL, and the fourth dielectric layer IL4 have been removed. The source semiconductor layer SSP can directly contact the exposed lower portion of the vertical semiconductor pattern SP. The source semiconductor layer SSP can directly contact one of the first to fourth lower semiconductor layers LSL1 to LSL4 below the source semiconductor layer SSP. The source semiconductor layer SSP can directly contact the upper semiconductor layer USL above the source semiconductor layer SSP.

[0130] refer to Figure 5 , Figure 12A and Figure 12B Electrode EL can replace the corresponding sacrificial layer HL exposed to the first trench TR1. For example, the sacrificial layer HL exposed to the first trench TR1 can be selectively removed. Electrode EL can be formed in each space where the sacrificial layer HL has been removed.

[0131] A second trench TR2 can be formed to penetrate the fourth interlayer dielectric layer ILD4, the third interlayer dielectric layer ILD3, and the upper semiconductor layer USL. When viewed in a plan view, the second trench TR2 may include a portion extending in the first direction D1 and a portion extending in the second direction D2.

[0132] The second trench TR2 can divide the upper semiconductor layer USL into multiple parts. For example, the upper semiconductor layer USL can be divided into first upper semiconductor layers USL1 to fourth upper semiconductor layers USL4, and a first dummy semiconductor layer DSL1 and a second dummy semiconductor layer DSL2. The second trench TR2 can separate and insulate the first upper semiconductor layers USL1 to fourth upper semiconductor layers USL4 from each other. The first upper semiconductor layers USL1 to fourth upper semiconductor layers USL4 can be respectively disposed on the first lower semiconductor layers LSL1 to fourth lower semiconductor layers LSL4.

[0133] A cut structure TCP can be formed to fill the second trench TR2. Forming the cut structure TCP may include: forming a dielectric layer to fill the second trench TR2, and performing a planarization process until the top surface of the fourth interlayer dielectric layer ILD4 is exposed. For example, the cut structure TCP may include a first cut structure TCP1 and a second cut structure TCP2 disposed between the first electrode structure ST1 and the third electrode structure ST3.

[0134] The dicing structure TCP can divide the upper semiconductor layer USL into a first upper semiconductor layer USL1 to a fourth upper semiconductor layer USL4. The first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 can be insulated from each other. Therefore, the first electrode structure ST1 to the fourth electrode structure ST4 on the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 respectively can operate independently of each other.

[0135] Return to Figure 5 , Figure 6A , Figure 6B and Figure 6C At least one through contact TVS can be formed, which penetrates the fourth interlayer dielectric layer ILD4, the third interlayer dielectric layer ILD3, the dielectric pattern IP, the second interlayer dielectric layer ILD2, and the etch stop layer ESL and is electrically connected to the peripheral line PIL of the peripheral circuit structure PS. The through contact TVS can be formed on the through contact region TVR.

[0136] The formation of a through contact TVS may include: forming a via extending from the fourth interlayer dielectric layer ILD4 to the peripheral line PIL of the peripheral circuit structure PS, and filling the via with a conductive material. Before filling the via with the conductive material, spacers SS may be formed on the inner wall of the via.

[0137] A bit line contact plug BPLG can be formed, which penetrates the fourth interlayer dielectric layer ILD4 and is coupled to the corresponding vertical channel structure VS. A cell contact plug PLG can be formed, which penetrates the third interlayer dielectric layer ILD3 and the fourth interlayer dielectric layer ILD4 and is coupled to the corresponding electrode EL. On the fourth interlayer dielectric layer ILD4, the bit line BL can be formed to be electrically connected to the bit line contact plug BPLG, and the connecting line CL can be formed to be electrically connected to the cell contact plug PLG.

[0138] Figure 13A and Figure 13B It shows the respective along Figure 5 The cross-sectional views taken along lines I-I' and III-III' illustrate three-dimensional semiconductor memory devices according to some exemplary embodiments of the concept of the present invention. In the following embodiments, references to the above-mentioned references will be omitted. Figure 5 , Figure 6A , Figure 6B and Figure 6C The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0139] refer to Figure 5 , Figure 13A and Figure 13B The cut structure TCP can include an extension portion at its lower part. For example, the first cut structure TCP1 can include an extension portion P1 at its lower part and an extension portion P2 on the extension portion P1. The extension portion P2 can penetrate the upper semiconductor layer USL. The extension portion P1 can be disposed in the second interlayer dielectric layer ILD2.

[0140] The extended portion P1 of the first cut structure TCP1 may have a first width W1 in the second direction D2. As the extended portion P1 approaches its lower portion from its upper portion, the first width W1 may gradually increase to a maximum value and then gradually decrease. For example, when viewed in cross-section, the extended portion P1 may have an elliptical shape.

[0141] The extension portion P2 of the first cutting structure TCP1 can have a second width W2 in the second direction D2. As the extension portion P2 approaches its lower part from its upper part, the second width W2 can gradually decrease.

[0142] The maximum value of the first width W1 of the extended portion P1 can be greater than the maximum value of the second width W2 of the extended portion P2. The first cut structure TCP1 can have a width that changes abruptly at the boundary between the extended portion P1 and the extended portion P2. The boundary between the extended portion P1 and the extended portion P2 can be located at the height between the bottom surface of the first lower semiconductor layer LSL1 and the bottom surface of the first upper semiconductor layer USL1.

[0143] Figure 14A and Figure 15A It shows along Figure 5 The cross-sectional view taken by line I-I' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. Figure 14B and Figure 15B It shows along Figure 5 The cross-sectional view taken along line II-II' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. In the following embodiments, references will be omitted. Figures 8A to 12B The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0144] refer to Figure 5 , Figure 14A and Figure 14B ,exist Figure 10A and Figure 10B In the resulting structure, a second trench TR2 can be formed to penetrate the third interlayer dielectric layer ILD3 and the upper semiconductor layer USL. As an example embodiment of the inventive concept, the second trench TR2 can be formed simultaneously with the first trench TR1. As another example embodiment of the inventive concept, the first trench TR1 can be formed, followed by the formation of the second trench TR2. The second trench TR2 can expose a portion of the second interlayer dielectric layer ILD2.

[0145] refer to Figure 5 , Figure 15A and Figure 15B The source semiconductor layer SSP can replace the lower sacrificial layer LHL exposed in the first trench TR1. During the replacement of the source semiconductor layer SSP, the second interlayer dielectric layer ILD2 can be etched at the portion exposed in the second trench TR2. For example, the replacement of the source semiconductor layer SSP may include a process of etching the lower portion of the vertical dielectric pattern VP, and the second interlayer dielectric layer ILD2 can be etched at the portion exposed by the etching process. Thus, an extended space can be formed in the lower portion of the second trench TR2. Subsequently, the second trench TR2 can be filled with a dielectric material to form a cut structure TCP.

[0146] Figure 16 It shows along Figure 5 The cross-sectional view taken along line I-I' illustrates a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. In the following embodiments, references to the above will be omitted. Figure 5 , Figure 6A , Figure 6B and Figure 6C The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0147] refer to Figure 5and Figure 16 A metal pattern MP can be disposed beneath each of the first to fourth lower semiconductor layers LSL1 to LSL4. The metal pattern MP can directly contact the bottom surface of each of the first to fourth lower semiconductor layers LSL1 to LSL4. The side surface of the metal pattern MP can be vertically aligned with the side surface of each of the first to fourth lower semiconductor layers LSL1 to LSL4. When viewed in a plan view, the metal pattern MP can overlap with one of the lower semiconductor layers LSL1 to LSL4 that is overlaid thereon.

[0148] The metal pattern MP may include at least one selected from metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum). According to some exemplary embodiments of the invention, when the three-dimensional semiconductor memory device is operated, a voltage generated from a voltage generator may be supplied to the metal pattern MP.

[0149] Figure 17 It shows Figure 4 The enlarged plan view of part M in the figure shows a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. Figure 18A and Figure 18B It shows the respective along Figure 17 The cross-sectional views taken from lines I-I' and II-II' are shown. In the following embodiments, references to the above will be omitted. Figure 5 , Figure 6A , Figure 6B and Figure 6C The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0150] refer to Figure 17 , Figure 18A and Figure 18B The TCP segmentation structure can include multiple dummy contacts (DVS). For example, each of the first TCP segmentation structure TCP1 and the second TCP segmentation structure TCP2 can include multiple dummy contacts (DVS) arranged along a first direction D1. The third TCP segmentation structure TCP3 can include multiple dummy contacts (DVS) arranged along a second direction D2. For example, dummy contacts (DVS) arranged along one direction can be connected to each other. Therefore, when viewed in a plan view, each dummy contact (DVS) arranged along one direction can be shaped like a wire extending in that direction.

[0151] Each of the dummy contacts (DVS) may include a horizontal portion P3 located at its lower part and a vertical portion P4 located above the horizontal portion P3. The horizontal portion P3 may be disposed in the upper semiconductor layer USL. For example, the horizontal portion P3 may penetrate the upper semiconductor layer USL. The diameter of the horizontal portion P3 may be larger than the diameter of the vertical portion P4.

[0152] As an example of the inventive concept, the horizontal portions P3 of the dummy contact DVS can be arranged along one direction and connected to each other. As another example embodiment of the inventive concept, the horizontal portions P3 of the dummy contact DVS can be arranged spaced apart from each other in one direction.

[0153] The cut structure TCP can also include spacers SS surrounding each of the dummy contacts DVS. For example, spacers SS can be inserted between the upper semiconductor layer USL and the horizontal portion P3 of the dummy contacts DVS. The spacers SS can surround the horizontal portion P3 arranged in one direction. Therefore, the upper semiconductor layer USL can be divided into multiple portions that are insulated from each other.

[0154] For example, the first upper semiconductor layer USL1 and the first dummy semiconductor layer DSL1 can be insulated from each other by a spacer SS of a first cleaved structure TCP1 inserted between the first upper semiconductor layer USL1 and the first dummy semiconductor layer DSL1. The third upper semiconductor layer USL3 and the first dummy semiconductor layer DSL1 can be insulated from each other by a spacer SS of a second cleaved structure TCP2 inserted between the third upper semiconductor layer USL3 and the first dummy semiconductor layer DSL1. The first upper semiconductor layer USL1 and the second upper semiconductor layer USL2 can be insulated from each other by a spacer SS of a third cleaved structure TCP3 inserted between the first upper semiconductor layer USL1 and the second upper semiconductor layer USL2.

[0155] Figure 20 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown. Figure 21A and Figure 21B It shows the respective along Figure 20 The cross-sectional views taken from lines I-I' and II-II' are shown. In the following embodiments, references to the above will be omitted. Figure 5 , Figure 6A , Figure 6B and Figure 6C The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0156] refer to Figure 20 , Figure 21A and Figure 21BThe system can be configured with first lower semiconductor layers LSL1 through fourth lower semiconductor layers LSL4. When viewed in a plan view, each of the first lower semiconductor layers LSL1 through fourth lower semiconductor layers LSL4 can have a quadrilateral tile shape. The first lower semiconductor layers LSL1 through fourth lower semiconductor layers LSL4 can be arranged in two dimensions.

[0157] The upper semiconductor layer USL can be disposed on the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4. The upper semiconductor layer USL may include the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 respectively disposed on the first lower semiconductor layer LSL1 to the fourth lower semiconductor layer LSL4.

[0158] The upper semiconductor layer USL may also include connection patterns CNL between adjacent upper semiconductor layers in the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4. For example, two connection patterns CNL may be inserted between the first upper semiconductor layer USL1 and the second upper semiconductor layer USL2, which are adjacent to each other.

[0159] The above reference Figure 5 , Figure 6A , Figure 6B and Figure 6C The upper semiconductor layer USL in question can be plate-shaped across the entire surface of the first substrate SUB. Conversely, according to this embodiment, the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 can each be formed like a tile, and the upper semiconductor layers USL can have a tile-like shape. A connection pattern CNL can be disposed between the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4.

[0160] At least one cut structure TCP can be provided on each connection pattern CNL of the upper semiconductor layer USL. For example, a pair of cut structures TCP can be provided on the connection pattern CNL between the first upper semiconductor layer USL1 and the second upper semiconductor layer USL2. The cut structure TCP according to this embodiment can have a stripe with a long axis in one direction.

[0161] The cut structure TCP can penetrate the connection pattern CNL. The cut structure separates the connection pattern CNL from the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4, thus electrically isolating the connection pattern CNL from the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4. Therefore, the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 cannot be connected to each other through the connection pattern CNL. The cut structure TCP can separate the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 from each other.

[0162] The first upper semiconductor layer USL1 may have a first sidewall SW1 defined by a cut structure TCP. The first lower semiconductor layer LSL1 may have a second sidewall SW2 extending in a first direction D1. The first upper semiconductor layer USL1 may have a third sidewall SW3 extending in the first direction D1. The third sidewall SW3 may be located between a pair of connection patterns CNL.

[0163] The second sidewall SW2 may be offset from the first sidewall SW1 and the third sidewall SW3 in the second direction D2. The second sidewall SW2 may protrude beyond the first sidewall SW1 and the third sidewall SW3 in the second direction D2.

[0164] A further protrusion of the second sidewall SW2 allows the first lower semiconductor layer LSL1 to have a cut structure TCP thereon that penetrates the connection pattern CNL. The cut structure TCP may not penetrate the first lower semiconductor layer LSL1. The bottom surface of the cut structure TCP may be higher than the bottom surface of the first lower semiconductor layer LSL1. In some embodiments, the bottom surface of the cut structure TCP may contact the top surface of the first lower semiconductor layer LSL1.

[0165] When the cut structure TCP is formed, the first lower semiconductor layer LSL1 can be used as an etch stop layer. When the first lower semiconductor layer LSL1 is not provided below the cut structure TCP, the cut structure TCP may extend into the peripheral circuit structure PS, potentially damaging the peripheral trace PIL on top of the peripheral circuit structure PS. According to some exemplary embodiments of the present invention, one or more of the lower semiconductor layers LSL1 to LSL4 can prevent the cut structure TCP from being over-etched, thus avoiding process defects and improving device reliability.

[0166] Figure 22A and Figure 22B It shows the respective along Figure 20 The cross-sectional views taken along lines I-I' and II-II' illustrate a three-dimensional semiconductor memory device according to an exemplary embodiment of the concept of the present invention.

[0167] refer to Figure 20 , Figure 22A and Figure 22B Multiple cut structures TCP can be set on the first lower semiconductor layer LSL1. For example, three cut structures TCP can be set on the first lower semiconductor layer LSL1. The three cut structures TCP on the first lower semiconductor layer LSL1 can penetrate the connection pattern CNL. The first upper semiconductor layer USL1 can have a third sidewall SW3 between two adjacent cut structures in the three cut structures TCP.

[0168] Figure 23 It shows along Figure 20The cross-sectional view taken by line I-I' illustrates a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention.

[0169] refer to Figure 20 and Figure 23 Multiple cut structures TCP can be set on the first lower semiconductor layer LSL1. The cut structure TCP may include a first cut pattern TCPa, a second cut pattern TCPb, and a third cut pattern TCPc.

[0170] The bottom surface of the first diced pattern TCPa can be between the upper semiconductor layer USL and the first lower semiconductor layer LSL1. (Refer to the above reference.) Figure 13A Similar to the extended part P1 discussed, the first cutting pattern TCPa can be extended horizontally at its lower part.

[0171] The bottom surface of the second diced pattern TCPb can contact the top surface of the first lower semiconductor layer LSL1. (Refer to the above reference.) Figure 13A Similar to the extended portion P1 discussed, the second cutting pattern TCPb can be extended horizontally below it.

[0172] The bottom surface of the third dicing pattern TCPc can be between the top and bottom surfaces of the first lower semiconductor layer LSL1. Unlike the first dicing pattern TCPa and the second dicing pattern TCPb, the third dicing pattern TCPc may not include the extended portion.

[0173] Figure 24 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown. Figure 25 It shows along Figure 24 A cross-sectional view taken from line I-I'. In the following embodiments, references to the above will be omitted. Figure 5 , Figure 6A , Figure 6B and Figure 6C The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0174] refer to Figure 24 and Figure 25 The first lower semiconductor layer LSL1 may have a second sidewall SW2 that protrudes beyond the first sidewall SW1 of the first upper semiconductor layer USL1 in the second direction D2. The first sidewall SW1 is defined by a first dicing structure TCP1. Therefore, the first dicing structure TCP1 may be located on the first lower semiconductor layer LSL1. The first dicing structure TCP1 may not penetrate the first lower semiconductor layer LSL1.

[0175] As described above, one or more of the lower semiconductor layers LSL1 to LSL4 can prevent the cut structure TCP from being over-etched, thus avoiding process defects and improving device reliability.

[0176] Figure 26 A simplified plan view of a cell array structure of a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention is shown. Along Figure 26 The cross-sectional view intercepted by line I-I' can be compared with Figure 21A The cross-sectional views are basically the same, and along Figure 26 The cross-sectional view taken from line II-II' can be compared with Figure 25 The cross-sectional views are basically the same.

[0177] refer to Figure 26 The first upper semiconductor layer USL1 and the third upper semiconductor layer USL3 can be disposed on the first lower semiconductor layer LSL1 and the third lower semiconductor layer LSL3, respectively. Each of the first upper semiconductor layer USL1 and the third upper semiconductor layer USL3 can have a quadrilateral tile shape. A connecting pattern CNL can be inserted between the first upper semiconductor layer USL1 and the third upper semiconductor layer USL3.

[0178] The second upper semiconductor layer USL2 and the fourth upper semiconductor layer USL4 can be disposed on the second lower semiconductor layer LSL2 and the fourth lower semiconductor layer LSL4, respectively. The second upper semiconductor layer USL2 and the fourth upper semiconductor layer USL4 can each be formed as a plate. The first dicing structure TCP1 and the second dicing structure TCP2 can separate the plate-shaped upper semiconductor layer USL, and thus define the second dummy semiconductor layer DSL2 between the second upper semiconductor layer USL2 and the fourth upper semiconductor layer USL4.

[0179] The connection pattern CNL can be inserted between the first upper semiconductor layer USL1 and the second upper semiconductor layer USL2, and between the third upper semiconductor layer USL3 and the fourth upper semiconductor layer USL4.

[0180] The cut structure TCP can separate the first upper semiconductor layer USL1 to the fourth upper semiconductor layer USL4 from each other. When viewed in a planar view, the cut structure TCP that penetrates the connection pattern CNL can be given a bar shape. When viewed in a planar view, each of the first cut structure TCP1, the second cut structure TCP2, and the fourth cut structure TCP4 can be given a linear shape.

[0181] Figure 27 It shows Figure 4 The enlarged plan view of part M in the figure shows a three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention. Figure 28 It shows along Figure 27A cross-sectional view taken from line I-I'. In the following embodiments, references to the above will be omitted. Figure 5 , Figure 6A , Figure 6B and Figure 6C The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0182] refer to Figure 27 and Figure 28 , and above Figure 5 and Figure 6A Unlike the embodiments discussed herein, the dielectric pattern IP can be omitted on the contact area TVR. For example, the through contact TVS can directly penetrate the upper semiconductor layer USL or the first dummy semiconductor layer DSL1.

[0183] The spacer SS can be inserted between the first dummy semiconductor layer DSL1 and the through contact TVS, and can separate the through contact TVS from the first dummy semiconductor layer DSL1. Since the first dummy semiconductor layer DSL does not have a circuit function, no process defects will occur even if the through contact TVS and the first dummy semiconductor layer DSL1 are in direct contact with each other.

[0184] According to some exemplary embodiments of the present invention, during the execution of a process using radio frequency power, the upper semiconductor layer formed on the entire surface of the first substrate can be electrically grounded through the first substrate. During the use of radio frequency power, arcing caused by the accumulation of positive charge on the upper semiconductor layer can be prevented. Therefore, three-dimensional semiconductor memory devices can be manufactured without process defects caused by arcing.

[0185] After the process of using radio frequency power, the dicing structure can divide the electrically grounded upper semiconductor layer into multiple sections (e.g., tiles). Therefore, the memory stack structure formed on these sections can be electrically and physically separated from each other. In summary, the memory stack structure can be executed independently when operating three-dimensional semiconductor memory devices such as NAND flash memory.

[0186] Although the inventive concept has been described in conjunction with some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made therein without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor memory device, comprising: A second substrate on a first substrate, the second substrate including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer; An electrode structure comprising a plurality of electrodes stacked on the upper semiconductor layer; A vertical channel structure penetrates the electrode structure and connects to the second substrate; An interlayer dielectric layer covers the electrode structure and contacts the upper semiconductor layer; as well as A dicing structure is formed, penetrating the interlayer dielectric layer and the upper semiconductor layer, and spaced horizontally from the electrode structure, such that a portion of the interlayer dielectric layer lies between the electrode structure and the dicing structure in the horizontal direction. The upper semiconductor layer has a first sidewall defined by the dicing structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall, and The first sidewall and the second sidewall are offset horizontally from each other.

2. The semiconductor memory device of claim 1, wherein the first sidewall protrudes beyond the second sidewall in one direction.

3. The semiconductor memory device according to claim 1, The second sidewall protrudes beyond the first sidewall in one direction. The dicing structure penetrates the upper semiconductor layer and is disposed on the lower semiconductor layer, and The vertical height of the bottom surface of the cut structure is higher than the vertical height of the bottom surface of the lower semiconductor layer.

4. The semiconductor memory device of claim 1, wherein the second substrate further comprises a source semiconductor layer between the lower semiconductor layer and the upper semiconductor layer. The vertical channel structure is connected to the source semiconductor layer.

5. The semiconductor memory device according to claim 1, in, When viewed in a plan view, the upper semiconductor layer has a tile shape defined by the dicing structure, and When viewed in a plan view, the shape of the tile corresponds to the electrode structure.

6. The semiconductor memory device according to claim 1, further comprising: The connection pattern is separated from the upper semiconductor layer by the cutting structure. The cutting structure penetrates the connecting pattern, and The vertical height of the bottom surface of the cut structure is lower than the vertical height of the bottom surface of the upper semiconductor layer.

7. The semiconductor memory device according to claim 1, further comprising: The peripheral circuit structure is located between the first substrate and the second substrate; as well as A through contact penetrates the interlayer dielectric layer and is electrically connected to the peripheral circuit structure. The through contact is spaced apart from the first sidewall.

8. The semiconductor memory device according to claim 1, The cutting structure includes an extension portion and an extension portion on the extension portion, the extension portion being located at the lower part of the cutting structure, and The maximum width of the extended portion is greater than the maximum width of the extended portion.

9. The semiconductor memory device according to claim 1, The cutting structure includes multiple dummy contacts and spacers surrounding the dummy contacts. The dummy contacts are arranged in one direction, and Each of the dummy contacts includes a horizontal portion and a vertical portion on the horizontal portion, the horizontal portion penetrating the upper semiconductor layer.

10. The semiconductor memory device of claim 1, wherein the second substrate further includes a metal pattern beneath the lower semiconductor layer.

11. A semiconductor memory device, comprising: A second substrate on a first substrate; The cutting structure separates the second substrate into a first semiconductor layer and a second semiconductor layer; The first electrode structure and the second electrode structure are respectively located on the first semiconductor layer and the second semiconductor layer, and each of the first electrode structure and the second electrode structure includes a plurality of stacked electrodes. A molded structure, between the first electrode structure and the second electrode structure, the molded structure comprising a plurality of stacked sacrificial layers; as well as The first vertical channel structure and the second vertical channel structure penetrate the first electrode structure and the second electrode structure, respectively. The stacked sacrificial layers are located at the same height as the stacked electrodes, and The cutting structure penetrates the molding structure and the second substrate below the molding structure.

12. The semiconductor memory device according to claim 11, The stacked electrodes of the first electrode structure and the first vertical channel structure penetrating the first electrode structure constitute a plurality of first memory cells arranged in three dimensions. The stacked electrodes of the second electrode structure and the second vertical channel structure penetrating the second electrode structure constitute a plurality of second memory cells arranged in three dimensions.

13. The semiconductor memory device according to claim 11, The molded structure further includes multiple dielectric layers. The plurality of dielectric layers and the stacked sacrificial layers are stacked alternately in the vertical direction, and The plurality of dielectric layers extend from the molded structure toward the first electrode structure and the second electrode structure, respectively.

14. The semiconductor memory device according to claim 11, The second substrate includes a connection pattern between the first semiconductor layer and the second semiconductor layer. The cutting structure separates the connection pattern from the first semiconductor layer and the second semiconductor layer, and The vertical height of the bottom surface of the cut structure is lower than the vertical height of the bottom surface of each of the first semiconductor layer and the second semiconductor layer.

15. The semiconductor memory device according to claim 11, The cutting structure includes an extension portion and an extension portion on the extension portion, the extension portion being located at the lower part of the cutting structure, and The maximum width of the extended portion is greater than the maximum width of the extended portion.

16. A semiconductor memory device, comprising: A peripheral circuit structure on a substrate, the peripheral circuit structure including a peripheral transistor on the substrate, a peripheral line on the peripheral transistor, and a peripheral contact that electrically connects the peripheral transistor to the peripheral line; The lower semiconductor layer on the peripheral circuit structure; An upper semiconductor layer on the lower semiconductor layer; A cutting structure penetrates the upper semiconductor layer, and the vertical height of the bottom surface of the cutting structure is between the bottom surface of the upper semiconductor layer and the bottom surface of the lower semiconductor layer; The source semiconductor layer between the lower semiconductor layer and the upper semiconductor layer; An electrode structure comprising a plurality of electrodes stacked on the upper semiconductor layer; A vertical channel structure penetrates the electrode structure and is electrically connected to the source semiconductor layer; An interlayer dielectric layer covers the electrode structure; as well as A through contact penetrates the interlayer dielectric layer and is electrically connected to the peripheral wire. The upper semiconductor layer has a first sidewall defined by the dicing structure, and The through contact is spaced apart from the first sidewall.

17. The semiconductor memory device according to claim 16, The lower semiconductor layer has a second sidewall adjacent to the first sidewall, and The first sidewall and the second sidewall are offset from each other in one direction.

18. The semiconductor memory device of claim 16, wherein the vertical channel structure comprises: Vertical semiconductor pattern with a tubular shape and an opening at the top; as well as A vertical dielectric pattern has a data storage layer between the vertical semiconductor pattern and the electrode structure.

19. The semiconductor memory device of claim 16, further comprising: A dummy semiconductor layer is disposed adjacent to the upper semiconductor layer. The dicing structure is located between the upper semiconductor layer and the dummy semiconductor layer. The through contact penetrates the through contact area of ​​the dummy semiconductor layer. The dummy semiconductor layer has two sidewalls that are opposite to each other, and One of the two sidewalls is in contact with the cutting structure, and the other of the two sidewalls is spaced apart from the through contact.

20. The semiconductor memory device of claim 16, wherein the dicing structure comprises a first dicing structure and a second dicing structure disposed parallel to each other in one direction.

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