Three-dimensional memory device

Abstract

A three-dimensional memory device is provided, comprising: a substrate including a cell region and an extension region; a cell stack including an insulating layer and a word line alternately stacked on the substrate; a channel structure vertically passing through the cell stack; a word line separation layer vertically passing through the cell stack and extending longitudinally in a first direction; a contact plug vertically connected to the word line on the extension region; and a bit line extending longitudinally in a second direction on the channel structure, wherein each of the word lines comprises an inner pattern including polysilicon and an outer pattern including metal, the outer pattern surrounding an outer surface of the inner pattern, the channel structure vertically passing through the inner pattern, and the contact plug on the outer pattern.

Description

[0001] Korean Patent Application No. 10-2020-0009184, filed on January 23, 2020 in the Korean Intellectual Property Office, and entitled “3D Memory Device Including Word Line Including Polysilicon and Metal” is hereby incorporated by reference in its entirety. Technical Field

[0002] Embodiments relate to a three-dimensional (3D) memory device including a word line including polysilicon and metal. Background Art

[0003] A 3D memory device may use word lines including polysilicon. Summary of the invention

[0004] Embodiments may be implemented by providing a three-dimensional (3D) memory device, the three-dimensional memory device comprising: a substrate including a cell region and an extension region; a cell stack including a plurality of insulating layers and a plurality of word lines alternately stacked on the substrate; a plurality of channel structures vertically passing through the cell stack; a word line separation layer vertically passing through the cell stack and longitudinally extending in a first direction parallel to a surface of the substrate; a contact plug vertically connected to the plurality of word lines on the extension region; and a bit line longitudinally extending in a second direction orthogonal to the first direction on the plurality of channel structures, wherein each of the plurality of word lines comprises: an inner pattern including polysilicon; and an outer pattern including metal, the outer pattern surrounding an outer surface of the inner pattern, the plurality of channel structures vertically passing through the inner pattern, and the contact plug being located on the outer pattern.

[0005] An embodiment may be implemented by providing a three-dimensional (3D) memory device, the three-dimensional memory device comprising: a substrate including a cell region and an extension region; a cell stack including a plurality of insulating layers and a plurality of word lines alternately stacked on the substrate and having a stepped structure on the extension region; a plurality of cell channel structures vertically passing through the cell stack on the cell region; and a plurality of dummy channel structures vertically passing through the cell stack on the extension region, wherein the plurality of word lines have a plurality of internal patterns and a plurality of external patterns surrounding outer surfaces of the plurality of internal patterns, the plurality of internal patterns on the cell region have an integral plate shape, and the plurality of internal patterns on the extension region have a disk shape surrounding the plurality of cell channel structures.

[0006] Embodiments may be implemented by providing a three-dimensional (3D) memory device, the 3D memory device comprising: a substrate including a cell region and an extension region; a cell stack including a plurality of insulating layers and a plurality of word lines alternately stacked on the substrate; a plurality of channel structures on the cell region to vertically penetrate the cell stack; a plurality of dummy channel structures on the extension region to vertically penetrate the cell stack; a word line separation layer vertically penetrates the cell stack and extends longitudinally in a first direction parallel to a surface of the substrate; a contact plug on the extension region to vertically connect to the plurality of word lines; and a bit line extending longitudinally in a second direction orthogonal to the first direction on the plurality of channel structures, wherein each of the plurality of word lines includes a pad portion arranged as a step structure on the extension region, the pad portion including: a plurality of dummy inner patterns each surrounding a portion of a sidewall of a corresponding dummy channel structure among the plurality of dummy channel structures; and an outer pattern surrounding the plurality of dummy inner patterns, the plurality of dummy inner patterns being separated from each other in the first direction and the second direction in a plan view, the outer pattern contacting the word line separation layer, and the contact plug contacting the outer pattern.

[0007] An embodiment can be implemented by providing a method for manufacturing a three-dimensional (3D) memory device, the method comprising the following steps: forming a mold stack on a substrate so that the mold stack includes a plurality of insulating layers and a plurality of sacrificial layers; forming a plurality of unit channel structures and a plurality of dummy channel structures vertically passing through the mold stack; forming a word line separation layer passing through the mold stack and extending longitudinally in a row direction; doping a portion of each of the plurality of sacrificial layers with impurities and removing another portion of each sacrificial layer to form a plurality of word lines between the plurality of insulating layers; forming contact plugs connected to the plurality of word lines; and forming bit lines on the plurality of unit channel structures, wherein forming the plurality of word lines comprises: forming a plurality of internal patterns surrounding the plurality of unit channel structures and the plurality of dummy channel structures; and forming a plurality of external patterns surrounding the plurality of internal patterns and contacting the word line separation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings.

[0009] Figure 1A is a schematic plan view of a 3D memory device 100 according to an embodiment of the present disclosure.

[0010] Figure 1B 2 is a cross-sectional view taken along line II′ of the 3D memory device 100 according to an embodiment of the present disclosure.

[0011] Figure 1Cis a cross-sectional view taken along line II-II′ of the 3D memory device 100 according to an embodiment of the present disclosure.

[0012] Figure 2 yes Figure 1B FIG. 1 is an enlarged view of region A of a 3D memory device 100 a shown in FIG.

[0013] Figure 3 yes Figure 1B FIG. 1 is an enlarged view of region B of the 3D memory device 100 a shown in FIG.

[0014] Figure 4 is a plan view of a word line WL of the 3D memory device 100 according to an embodiment of the present disclosure.

[0015] FIG. 5A to FIG. 10B is a cross-sectional view of a stage in a method of manufacturing a 3D memory device 100 according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Figure 1A is a schematic plan view of a 3D memory device 100 according to an embodiment of the present disclosure.

[0017] Reference Figure 1A The 3D memory device 100 according to an embodiment of the present disclosure may include a cell region CEL in which a plurality of memory cells are disposed and an extension region EXT for connecting the memory cells to wirings. Figure 1A As shown in FIG, only a portion of the cell region CEL is shown and the extension region EXT is only at one side of the cell region CEL. In an embodiment, the extension region EXT may be at both sides of the cell region CEL.

[0018] The 3D memory device 100 may include a plurality of channel structures CH and DCH, a plurality of word lines WL, a plurality of word line separation layers WC, a plurality of dummy word line separation layers DWC, a plurality of string selection line separation patterns SSC, a plurality of contact plugs CNT, and a plurality of bit lines BL. The channel structures CH and DCH may include a plurality of unit channel structures CH and a plurality of dummy channel structures DCH.

[0019] The cell channel structure CH may be in the cell region CEL. The cell channel structure CH may be arranged in a first direction (column direction) D1, a pad row may be defined, and a plurality of pad rows may be arranged in parallel in a second direction (row direction) D2 (eg, a direction orthogonal to the first direction D1). The cell channel structure CH may be arranged in a hexagonal close-packed lattice form or a zigzag form.

[0020] The dummy channel structure DCH may be in the extension region EXT. The dummy channel structure DCH may have, for example, a circular shape, an elliptical shape, an elbow shape, or a strip shape. The dummy channel structure DCH may be arranged in an orthorhombic lattice form. The dummy channel structure DCH may have a pattern density lower than that of each of the unit channel structures CH. The dummy channel structure DCH may surround the contact plug CNT. In an embodiment, each of the contact plugs CNT may be at the center between four dummy channel structures DCH adjacent thereto.

[0021] The word lines WL may extend (eg, extend longitudinally) from the cell region CEL to the extension region EXT in the second direction D2, and the lengths of the word lines WL in the second direction D2 may be different. The word lines WL may include a plurality of inner patterns 116 and a plurality of outer patterns 118. At least one of the word lines WL may be a string selection line SSL. Figure 4 The inner pattern 116 and the outer pattern 118 are described in detail.

[0022] The word line separation layer WC may extend (e.g., extend longitudinally) from the cell region CEL to the extension region EXT in the second direction D2. The dummy word line separation layer DWC may be spaced apart in parallel with the word line separation layer WC and may extend (e.g., extend longitudinally) in the second direction D2. The dummy word line separation layer DWC may be between a pair of word line separation layers WC. The dummy word line separation layer DWC may include a first dummy word line separation layer DWC1 extending from the cell region CEL to the extension region EXT and a second dummy word line separation layer DWC2 only in the extension region EXT. The first dummy word line separation layer DWC1 and the second dummy word line separation layer DWC2 may be alternately disposed between the pair of word line separation layers WC in the first direction D1. The word line separation layer WC may be spaced apart from the inner pattern 116 of the word line WL and may contact the outer surface of the outer pattern 118.

[0023] The string selection line separation pattern SSC may extend (eg, extend longitudinally) in the second direction D2 in the cell region CEL to vertically overlap the word line WL. The string selection line SSL may be physically and materially separated. The string selection line separation pattern SSC may be on the same line as the second dummy word line separation layer DWC2 in the second direction D2.

[0024] The contact plugs CNT may be arranged in a lattice form in the extension region EXT. Each of the contact plugs CNT may be at a center point of four dummy channel structures DCH adjacent thereto or between four dummy channel structures DCH adjacent thereto. The contact plugs CNT may be spaced apart from the inner pattern 116. The contact plugs CNT may be on the outer pattern 118.

[0025] The bit lines BL may extend in the first direction D1 (eg, extend longitudinally) in the cell region CEL. The bit lines BL may be on the cell channel structures CH. The bit lines BL may extend along pad rows of the cell channel structures CH and may be spaced apart from each other in parallel in the second direction D2.

[0026] Figure 1B 2 is a cross-sectional view taken along line II′ of the 3D memory device 100 according to an embodiment of the present disclosure. Figure 1C is a cross-sectional view taken along line II-II′ of the 3D memory device 100 according to an embodiment of the present disclosure.

[0027] Reference Figure 1B and Figure 1C The 3D memory devices 100a and 100b may include a substrate 10 (including a cell region CEL and an extension region EXT), a peripheral circuit layer PS, a common source layer 40, a conductive line 42, a support layer 43, a cell stack 210, an interlayer insulating layer 120, a cell channel structure CH, a dummy channel structure DCH, a plurality of word lines WL, a word line separation layer WC, a dummy word line separation layer DWC, a string selection line separation pattern SSC, a plurality of contact plugs CNT, a plurality of capping layers (e.g., a first capping layer and a second capping layer) 130 and 132, and a plurality of bit lines BL.

[0028] The substrate 10 may include a silicon wafer. In an embodiment, the substrate 10 may include an epitaxially grown material layer, such as a silicon layer, a silicon germanium layer, or a silicon carbide layer. In an embodiment, the substrate 10 may include a silicon-on-insulator (SOI).

[0029] The peripheral circuit layer PS may be on the substrate 10. The peripheral circuit layer PS may include a transistor 20, a peripheral circuit wiring 32, and a peripheral insulating layer 34. The transistor 20 may include a source / drain region and a channel region each formed in an active region defined by an isolation layer. The peripheral circuit wiring 32 may be electrically connected to the transistor 20. The peripheral insulating layer 34 may cover the transistor 20 and the peripheral circuit wiring 32. The peripheral insulating layer 34 may include a plurality of insulating layers stacked as a multilayer. In an embodiment, the peripheral insulating layer 34 may include, for example, a silicon oxide layer, a silicon nitride layer, or a combination thereof. In an embodiment, the peripheral circuit layer PS may be outside the extension region EXT. As used herein, the term "or" is not an exclusive term, for example, "A or B" will include A, B, or A and B.

[0030] The common source layer 40 may be on the peripheral circuit layer PS. The common source layer 40 may include a semiconductor material, for example, may include silicon, germanium, silicon germanium, gallium arsenic, indium gallium arsenic, aluminum gallium arsenic, or a combination thereof. The common source layer 40 may include a semiconductor doped with p-type impurities or an undoped intrinsic semiconductor. In a top view or a plan view, the common source layer 40 may have a plate shape or a line shape.

[0031] The sacrificial pattern 41 may be on the common source layer 40 on the extension region EXT. The sacrificial pattern 41 may include a plurality of insulating layers stacked in multiple layers.

[0032] The conductive line 42 may be on the common source layer 40 on the cell region CEL. The conductive line 42 may be at the same level as the sacrificial pattern 41 (e.g., the same distance from the substrate 10 in a vertical direction orthogonal to the first direction D1 and the second direction D2). An opening adjacent to or spaced apart from the sacrificial pattern 41 and exposing a portion of the top surface of the common source layer 40 may be in the conductive line 42.

[0033] The support layer 43 may be on the sacrificial pattern 41 and the conductive line 42. The support layer 43 may extend to an inner portion of an opening between the conductive line 42 and the sacrificial pattern 41, and may cover a top surface of the common source layer 40.

[0034] The cell stack 210 may be on the support layer 43. The cell stack 210 may include insulating layers 112 and word lines WL that are alternately and repeatedly stacked.

[0035] The cell stack 210 may have a staircase structure on the extension region EXT. The paired insulating layers 112 and word lines WL may extend different lengths in the second direction D2 to provide a plurality of pads PAD having steps (e.g., height differences in the vertical direction) therebetween. The pad PAD may have a staircase structure on the extension region EXT. The pad PAD may be connected to the contact plug CNT.

[0036] At least one of the word lines WL may be a ground selection line GSL, and at least one of the word lines WL may be a string selection line SSL. In an embodiment, the lowermost word line WL (e.g., the word line WL closest to the substrate 10 in the vertical direction among the word lines WL) may be the ground selection line GSL. The uppermost word line WL (e.g., the word line WL farthest from the substrate 10 in the vertical direction among the word lines WL) may be the string selection line SSL.

[0037] In an embodiment, the word line WL may include an inner pattern 116 and an outer pattern 118. The inner pattern 116 and the insulating layer 112 may be alternately and repeatedly stacked on the substrate 10. The outer pattern 118 and the insulating layer 112 may be alternately and repeatedly stacked on the substrate 10. The inner pattern 116 and the outer pattern 118 may be at the same level, and the side surface of the inner pattern 116 may contact (e.g., directly contact) the side surface of the outer pattern 118. The inner pattern 116 and the outer pattern 118, both at the same level, may have the same thickness. In an embodiment, the inner pattern 116 may include, for example, polysilicon doped with P-type impurities. The outer pattern 118 may include a metal material, for example, tungsten (W).

[0038] The internal pattern 116 may include a cell internal pattern 116C on the cell region CEL and a dummy internal pattern 116D on the extension region EXT.

[0039] The cell internal pattern 116C may be between the cell channel structures CH on the cell region CEL. The cell internal pattern 116C may contact a portion of the side surface of each of the cell channel structures CH. The cell internal pattern 116C may be spaced apart from the word line separation layer WC and the dummy word line separation layer DWC. In a cross-sectional view, an outer portion of the cell internal pattern 116C may be between the cell channel structure CH and the outer pattern 118.

[0040] The dummy inner patterns 116D may be adjacent to the dummy channel structures DCH on the extension region EXT. The dummy inner patterns 116D may be spaced apart from each other in the first direction D1 and / or the second direction D2 and in the vertical direction. The inner surface of each of the dummy inner patterns 116D may surround a portion of the sidewall of the corresponding dummy channel structure DCH in the dummy channel structure DCH. Each of the dummy inner patterns 116D may be surrounded by the outer pattern 118, and its outer surface may contact the side surface of the outer pattern 118.

[0041] The outer pattern 118 may extend from the cell region CEL to the extension region EXT in the second direction D2. A portion of the outer pattern 118 may be located between the word line separation layer WC and the inner pattern 116 on the cell region CEL. An outer surface of the outer pattern 118 may contact an outer surface of the inner pattern 116 and an inner surface of the outer pattern 118 may contact a portion of a sidewall of the word line separation layer WC. The outer pattern 118 may be located between the inner patterns 116 on the extension region EXT. An outer surface of the outer pattern 118 on the extension region EXT may contact the interlayer insulating layer 120.

[0042] The interlayer insulating layer 120 may cover the top surface of the unit stack 210. The interlayer insulating layer 120 may cover the stepped structure of the unit stack 210. In an implementation, the interlayer insulating layer 120 includes silicon oxide.

[0043] The cell channel structure CH may pass through the conductive line 42 , the support layer 43 , and the cell stack 210 , and may longitudinally extend in a vertical direction on the cell region CEL The cell channel structure CH may be electrically connected to the conductive line 42 .

[0044] The dummy channel structure DCH may pass through the sacrificial pattern 41 , the support layer 43 , the cell stack 210 , and the interlayer insulating layer 120 , and may longitudinally extend in a vertical direction on the extension region EXT.

[0045] The first capping layer 130 and the second capping layer 132 may be sequentially stacked on the interlayer insulating layer 120. The bit line plug 160 may pass through the first capping layer 130 and the second capping layer 132 and may be connected to the conductive pad 153 (see FIG. Figure 2 The bit line BL may be on the second capping layer 132 and may be electrically connected to the bit line plug 160 .

[0046] The word line separation layer WC and the dummy word line separation layer DWC may pass through the conductive line 42, the sacrificial pattern 41, the support layer 43, the unit stack 210, the interlayer insulating layer 120, and the first capping layer 130, and may extend longitudinally in the vertical direction. The outer sidewall of each of the word line separation layer WC and the dummy word line separation layer DWC may contact the outer pattern 118.

[0047] The string selection line separation pattern SSC may be located on the cell stack 210 on the cell region CEL. The string selection line separation pattern SSC may extend downward from the top surface of the cell stack 210 in a vertical direction to vertically pass through the insulating layer 112 and the word line WL. In an embodiment, the string selection line separation pattern SSC may separate the cell stack 210 from the string selection line SSL at the uppermost level.

[0048] The contact plug CNT may be on the extension region EXT. The contact plug CNT may vertically pass through the capping layers 130 and 132 and the interlayer insulating layer 120, and may be vertically connected to the word line WL. The contact plug CNT may pass through the insulating layer 112 contacting the interlayer insulating layer 120, and may be vertically connected to the outer pattern 118 of the word line WL. The contact plug CNT may be connected to the outer pattern 118 constituting the pad portion PAD among the word line WL.

[0049] The capping layers 130 and 132 may be on the interlayer insulating layer 120. The bit line BL may be on the interlayer insulating layer 120. The bit line plug 160 may pass through the capping layers 130 and 132 and may be connected to the bit line BL and the cell channel structure CH.

[0050] Figure 2 yes Figure 1B FIG. 1 is an enlarged view of region A of a 3D memory device 100 a shown in FIG. Figure 3 yes Figure 1B FIG. 1 is an enlarged view of region B of the 3D memory device 100 a shown in FIG.

[0051] Reference Figure 2 , the unit channel structure CH may include an information storage pattern 140, a channel pattern 151, a buried insulating pattern 152, and a conductive pad 153. The channel pattern 151 may be disposed inwardly relative to the information storage pattern 140, and the buried insulating pattern 152 may be disposed inwardly relative to the channel pattern 151. The information storage pattern 140 may construct the channel structure CH and DCH, and may contact the inner pattern 116 of the word line WL. The information storage pattern 140 may include a blocking layer 142, a charge storage layer 144, and a tunnel insulating layer 146. The blocking layer 142 may be disposed inwardly relative to the charge storage layer 144, and the charge storage layer 144 may be disposed inwardly relative to the tunnel insulating layer 146. In an embodiment, the channel pattern 151 may include polysilicon. The buried insulating pattern 152 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the blocking layer 142 and the tunnel insulating layer 146 may include silicon oxide, and the charge storage layer 144 may include silicon nitride. The dummy channel structure DCH may have a structure substantially the same as that of the cell channel structure CH In an implementation, the dummy channel structure DCH may include an information storing pattern 140 , a channel pattern 151 , and a buried insulating pattern 152 .

[0052] Reference Figure 3 , the conductive line 42 may pass through the information storing pattern 140 and may directly contact the side surface of the channel pattern 151. A portion of the conductive line 42 contacting the channel pattern 151 may extend in an upward direction and a downward direction.

[0053] Figure 4 is a plan view of a word line WL of the 3D memory device 100 according to an embodiment of the present disclosure.

[0054] Reference Figure 1A , Figure 1B , Figure 1C and Figure 4, the word line WL may include an inner pattern 116 and an outer pattern 118 surrounding an outer surface of the inner pattern 116. The inner pattern 116 may include a cell inner pattern 116C on the cell region CEL and a dummy inner pattern 116D on the extension region EXT.

[0055] The unit internal pattern 116C may surround the unit channel structure CH and may fully fill the area between the unit channel structures CH adjacent to each other. The unit internal pattern 116C may include a plurality of inner surfaces DIS having a circular or rounded shape, and the inner surfaces DIS may respectively surround the side surfaces of the unit channel structure CH. In an embodiment, the unit internal pattern 116C may have a plate pattern shape including corresponding holes disposed in each region in which the unit channel structure CH is formed. The unit internal pattern 116C may have a plate shape integral with a ring or disk shape. The unit internal pattern 116C may include an outer surface DOS having an uneven shape. In an embodiment, in a top view or a plan view, the outer surface DOS of the unit internal pattern 116C may have an embossed shape, a waveform shape, or a shape in which a plurality of arcs are connected to each other. In an embodiment, the outer surface DOS of the unit internal pattern 116C may include a plurality of depressions R1 and R2 that are depressed in the inward direction of the unit internal pattern 116C.

[0056] The dummy internal pattern 116D may be on the extension region EXT and may be arranged in a lattice form. Each of the dummy internal patterns 116D may have a circular or elliptical ring shape or a circular or elliptical disk shape. In an embodiment, each of the dummy internal patterns 116D may include a circular or elliptical hole at its center. The dummy channel structure DCH may be in the hole, and the dummy internal pattern 116D may surround the outer surface of the dummy channel structure DCH. Each of the dummy internal patterns 116D may have a substantially uniform thickness (e.g., a substantially uniform thickness in the vertical direction).

[0057] The outer pattern 118 may be outside the unit inner pattern 116C. The outer pattern 118 may surround the unit inner pattern 116C. The outer pattern 118 may contact the unit inner pattern 116C. The outer pattern 118 may include an inner surface UIS having an uneven shape along the outer surface DOS of the unit inner pattern 116C (e.g., an inner surface UIS complementary to the outer surface DOS of the unit inner pattern 116C). In an embodiment, in a top view or a plan view, the inner surface UIS of the outer pattern 118 may have an embossed shape, a wave shape, or a shape in which a plurality of arcs are connected to each other. In an embodiment, the outer pattern 118 may include a plurality of protrusions PU1 and PU2 protruding toward the unit inner pattern 116C (e.g., corresponding to or complementary to the recesses R1 and R2 of the unit inner pattern 116C).

[0058] FIG. 5A to FIG. 10B is a cross-sectional view of a stage in a method of manufacturing a 3D memory device 100 according to an embodiment of the present disclosure.

[0059] Reference Figure 5A and Figure 5B , a method for manufacturing a 3D memory device according to an embodiment of the present disclosure may include: forming a peripheral circuit layer PS on a substrate 10; forming a common source layer 40 on the peripheral circuit layer PS; forming a sacrificial pattern 41 on the common source layer 40; forming a supporting layer 43 on the sacrificial pattern 41; forming a molding stack 110 on the supporting layer 43; and forming an interlayer insulating layer 120 on the molding stack 110.

[0060] Forming the sacrificial pattern 41 on the common source layer 40 may include: forming a sacrificial film on the common source layer 40; forming a mask pattern on the sacrificial film; and exposing a portion of the top surface of the common source layer 40 by etching the sacrificial film using the mask pattern as an etching mask. The sacrificial pattern 41 may include, for example, silicon nitride, silicon oxynitride, silicon carbide, or silicon germanium. The sacrificial pattern 41 may be formed, and the mask pattern may be removed.

[0061] The support layer 43 may be formed to cover the sacrificial pattern 41 and the exposed top surface of the common source layer 40 and fill the opening. In an implementation, the support layer 43 may include polysilicon doped with impurities.

[0062] Forming the molding stack 110 may include: forming a molding structure by alternately stacking insulating layers 112 and sacrificial layers 114 on the substrate 10 and performing a trimming process on the molding structure. The insulating layers 112 and the sacrificial layers 114 may independently include materials that can be etched with different etching selectivities. In an embodiment, the insulating layers 112 may include silicon oxide, and the sacrificial layers 114 may include polysilicon.

[0063] The trimming process may include a process of repeatedly forming a mask pattern on the mold structure to etch a portion of the mold structure and reducing the horizontal area of ​​the mask pattern. Through the trimming process, the mold stack 110 may be formed to have a stepped structure in which the height gradually decreases in a direction from the cell region CEL to the extension region EXT.

[0064] An interlayer insulating layer 120 may be formed on the substrate 10 to cover the mold stack 110. The interlayer insulating layer 120 may include a material having an etching selectivity with respect to the sacrificial layer 114. In an implementation, the interlayer insulating layer 120 may include, for example, silicon oxide, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0065] Reference Fig. 6A and Figure 6B , the method may include: forming a channel hole H1 and a dummy channel hole H2 passing through the mold stack 110, the interlayer insulating layer 120, the support layer 43, and the sacrificial pattern 41. Forming the channel hole H1 and the dummy channel hole H2 may include: forming a mask pattern on the interlayer insulating layer 120 and anisotropically etching the mold stack 110, the interlayer insulating layer 120, the support layer 43, and the sacrificial pattern 41 by using the mask pattern as an etching mask. Through the anisotropic etching, a portion of the common source layer 40 may be etched, and thus, a recess may be formed in the substrate 10. The channel hole H1 may be formed in the cell region CEL, and the dummy channel hole H2 may be formed in the extension region EXT. The channel hole H1 and the dummy channel hole H2 may expose the inner sidewalls of the mold stack 110, the interlayer insulating layer 120, the support layer 43, and the sacrificial pattern 41 and may expose the common source layer 40.

[0066] Reference Fig. 7A and Figure 7B , the method may include forming a plurality of doping regions DR1 and DR2 by doping the mold stack 110 with impurities. In an embodiment, forming the doping regions DR1 and DR2 may include performing a gas phase doping (GPD) process using a source gas including impurities. The source gas for the GPD process may include P-type impurities. In an embodiment, the source gas may include impurities such as boron (B) and carbon (C). In an embodiment, forming the doping regions may include performing a plasma doping process.

[0067] Through the GPD process, a source gas including a P-type impurity may be provided to the inner portion of the channel hole H1 and the dummy channel hole H2. The source gas including a P-type impurity may be provided at a certain flow rate to the entire inner sidewall surface of the interlayer insulating layer 120, the mold stack 110, the support layer 43, and the sacrificial pattern 41, which are exposed through the channel hole H1 and the dummy channel hole H2, so that the source gas including the P-type impurity may diffuse from the surface of each of the interlayer insulating layer 120, the mold stack 110, the support layer 43, and the sacrificial pattern 41 to the inner portion. In addition, the P-type impurity may diffuse from the surface of the common source layer 40 to the inner portion. In an embodiment, the P-type impurity may diffuse to each of the interlayer insulating layer 120, the mold stack 110, the support layer 43, and the sacrificial pattern 41 with a uniform horizontal thickness (for example, it may diffuse to a uniform depth). The doping regions DR1 and DR2 may have a uniform thickness outside or around the channel hole H1 and the dummy channel hole H2. Through the GPD process, a region between the channel holes H1 adjacent to each other on the cell region CEL may be sufficiently doped with P type impurities.

[0068] Reference Fig. 8A and Figure 8BThe method may include forming a cell channel structure CH and a dummy channel structure DCH and forming a first capping layer 130. Forming the cell channel structure CH and the dummy channel structure DCH may include sequentially forming an information storage pattern 140, a channel pattern 151, a buried insulating pattern 152, and a conductive pad 153 in the channel hole H1 and the dummy channel hole H2.

[0069] The information storage pattern 140 and the channel pattern 151 may be formed to fill a portion of each of the channel hole H1 and the dummy channel hole H2. The buried insulating pattern 152 may fill the residual space remaining after forming the information storage pattern 140 and the buried insulating pattern 152 in the channel hole H1 and the dummy channel hole H2. A conductive pad 153 may be formed on the information storage pattern 140, the channel pattern 151, and the buried insulating pattern 152. After forming the cell channel structure CH and the dummy channel structure DCH, a first capping layer 130 may be formed on the conductive pad 153 and the interlayer insulating layer 120.

[0070] Reference Fig. 9A and Fig. 9B The method may include: forming a word line cutout WLC and a dummy word line cutout DWLC; forming a conductive line 42 by removing a portion of a sacrificial pattern 41 ; and forming an open region OP by removing a sacrificial layer 114 .

[0071] The word line cutouts WLC and the dummy word line cutouts DWLC may be formed through the first capping layer 130, the interlayer insulating layer 120, the support layer 43, the sacrificial pattern 41, and the common source layer 40. Forming the word line cutouts WLC and the dummy word line cutouts DWLC may include performing an anisotropic etching process.

[0072] Forming the conductive line 42 may include selectively removing the sacrificial pattern 41 exposed by the word line cutout WLC and the dummy word line cutout DWLC by using an isotropic etching process. Through the isotropic etching process, a portion of the sacrificial pattern 41 on the cell region CEL may be removed, and a portion of the top surface of the common source layer 40, the bottom surface of the support layer 43, and the side surface of the cell channel structure CH may be exposed or removed. Subsequently, the conductive line 42 may be formed in the space from which the sacrificial pattern 41 is removed. In an embodiment, the conductive line 42 may include, for example, metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0073] The sacrificial layer 114 may be removed therefrom (e.g., in an undoped region as other regions except for a doped region doped thereto with impurities), and thus, an opening region OP may be formed. In an embodiment, a portion of the sacrificial layer 114 not doped with a P-type impurity may be selectively removed. A portion of the sacrificial layer 114 doped with a P-type impurity may remain, and thus, an inner pattern 116 may be formed.

[0074] Reference Fig. 10A and Fig. 10B , the method may include: forming a word line WL; forming a word line separation layer WC and a dummy word line separation layer DWC; forming a second capping layer 132; forming a bit line plug 160; forming a string selection line separation pattern SSC; forming a contact plug CNT; and forming a bit line BL.

[0075] Forming the word line WL may include forming an outer pattern 118 in the open region OP. The outer pattern 118 may fill the open region OP and may be between the insulating layers 112 vertically adjacent to each other. The outer pattern 118 may be connected to a side surface of the inner pattern 116. In an embodiment, the outer pattern 118 may include, for example, tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0076] A word line separation layer WC may be formed in the word line cutout WLC, and a dummy word line separation layer DWC may be formed in the dummy word line cutout DWLC. The word line separation layer WC and the dummy word line separation layer DWC may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0077] The second capping layer 132 may be formed on the first capping layer 130. The bit line plug 160 may be formed on the conductive pad 153 to pass through the first capping layer 130 and the second capping layer 132. The string selection line separation pattern SSC may be formed to pass through the string selection line SSL and the insulating layer 112, the interlayer insulating layer 120, the first capping layer 130, and the second capping layer 132, all of which are disposed on the string selection line SSL. A contact hole may be formed vertically passing through the first capping layer 130, the second capping layer 132, and the interlayer insulating layer 120 and exposing the top surface or the inner surface of the outer pattern 118, and then, a contact plug CNT may be formed in the contact hole. A bit line BL may be formed on the second capping layer 132 in the cell region CEL, and the bit line BL may be connected to the bit line plug 160.

[0078] By way of summary and review, in a 3D memory device using a word line including polysilicon, a punching phenomenon (wherein the word line pad is drilled) may occur when forming a contact connected to the word line pad. In addition, the word line including polysilicon may have low carrier mobility, resulting in increased resistance.

[0079] One or more embodiments may provide a 3D memory device including polysilicon and metal.

[0080] One or more embodiments may provide a 3D memory device including a word line having low resistance.

[0081] One or more embodiments may provide a 3D memory device including a word line for reducing the possibility of occurrence of a punch-out phenomenon or preventing the punch-out phenomenon from occurring.

[0082] A word line of a 3D memory device according to an embodiment of the present disclosure may include both polysilicon and metal materials and thus may have low resistance.

[0083] The word line of the 3D memory device according to an embodiment of the present disclosure may include a metal material at a pad portion connected to a contact, thereby reducing or preventing the occurrence of a punch-out phenomenon.

[0084] Example embodiments have been disclosed herein, and although specific terms are employed, they should be used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to those of ordinary skill in the art, as of the time of filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A three-dimensional memory device, comprising: a substrate, including a cell region and an extension region; A cell stack including a plurality of insulating layers and a plurality of word lines alternately stacked on a substrate; A plurality of channel structures vertically passing through the unit stack; a word line separation layer vertically passing through the cell stack and extending longitudinally in a first direction parallel to a surface of the substrate; contact plugs vertically connected to the plurality of word lines on the extension regions; as well as a bit line extending longitudinally in a second direction orthogonal to the first direction over the plurality of channel structures, in: Each of the plurality of word lines includes: an inner pattern including polysilicon; and an outer pattern including metal, The outer pattern surrounds the outer surface of the inner pattern. The plurality of channel structures vertically penetrate the inner pattern, and The contact plug is on the outer pattern.

2. The three-dimensional memory device according to claim 1, wherein: An outer surface of the outer pattern contacts the word line separation layer.

3. The three-dimensional memory device according to claim 1, wherein: A portion of the outer pattern is between the inner pattern and the word line separation layer.

4. The three-dimensional memory device according to claim 1, wherein: The inner pattern surrounds the plurality of channel structures and fills areas between the plurality of channel structures.

5. The three-dimensional memory device of claim 1, wherein: The polysilicon of the inner pattern is doped with P-type impurities, and The outer pattern includes tungsten.

6. The three-dimensional memory device according to claim 1, wherein: The inner pattern is spaced apart from the word line separation layer.

7. The three-dimensional memory device according to claim 1, wherein: Internal patterns include: Internal cell patterns, over the cell area; and Multiple dummy internal patterns on the extended area.

8. The three-dimensional memory device according to claim 7, further comprising a plurality of dummy channel structures vertically passing through the cell stack on the extension region, in, The plurality of dummy inner patterns surround the plurality of dummy channel structures, respectively.

9. The three-dimensional memory device according to claim 7, wherein: The cell internal pattern includes an outer surface having an uneven shape.

10. The three-dimensional memory device according to claim 7, wherein: The outer pattern includes protrusions protruding toward the cell inner pattern.

11. The three-dimensional memory device of claim 1 , wherein: Each of the plurality of word lines includes a string selection line at an uppermost level of a cell stack, and The three-dimensional memory device further includes a string selection line separation pattern that physically separates a string selection line of each of the plurality of word lines.

12. The three-dimensional memory device of claim 1, wherein: Each of the plurality of channel structures comprises: buried insulation pattern; a channel pattern surrounding a side surface of the buried insulating pattern; an information storage pattern surrounding a side surface of the channel pattern; and a conductive pad on the buried insulating pattern, the channel pattern and the information storage pattern, and The information storage pattern contacts the internal pattern.

13. A three-dimensional memory device, the three-dimensional memory device comprising: a substrate, including a cell region and an extension region; A cell stack including a plurality of insulating layers and a plurality of word lines alternately stacked on a substrate and having a stepped structure on an extension region; A plurality of unit channel structures vertically passing through the unit stack on the unit region; as well as A plurality of dummy channel structures vertically penetrate the unit stack on the extension region, in: The plurality of word lines include a plurality of inner patterns and a plurality of outer patterns surrounding outer surfaces of the plurality of inner patterns, The plurality of internal patterns on the unit area have an integral plate shape, and The plurality of inner patterns on the extension region have a disk shape surrounding the plurality of dummy channel structures.

14. The three-dimensional memory device of claim 13, wherein: The plurality of inner patterns include polysilicon doped with P-type impurities, and The plurality of outer patterns include metal.

15. The three-dimensional memory device according to claim 13, further comprising: a word line separation layer vertically passing through the cell stack and extending longitudinally in a first direction parallel to a surface of the substrate; as well as A contact plug is vertically connected to the plurality of outer patterns on the extension region.

16. The three-dimensional memory device according to claim 15, wherein: The plurality of outer patterns contact the word line separation layer.

17. The three-dimensional memory device according to claim 15, wherein: The plurality of inner patterns are separated from the word line separation layer.

18. A three-dimensional memory device, the three-dimensional memory device comprising: a substrate, including a cell region and an extension region; A cell stack including a plurality of insulating layers and a plurality of word lines alternately stacked on a substrate; A plurality of channel structures are provided on the cell region to vertically penetrate the cell stack; a plurality of dummy channel structures on the extension region to vertically penetrate the unit stack; a word line separation layer vertically passing through the cell stack and extending longitudinally in a first direction parallel to a surface of the substrate; contact plugs vertically connected to the plurality of word lines on the extension regions; as well as a bit line extending longitudinally in a second direction orthogonal to the first direction over the plurality of channel structures, in: Each of the plurality of word lines includes a pad portion arranged in a step structure on an extension region, The pad portion includes: a plurality of dummy inner patterns, each surrounding a portion of a sidewall of a corresponding dummy channel structure among the plurality of dummy channel structures; and an outer pattern surrounding the plurality of dummy inner patterns. In a plan view, the plurality of dummy inner patterns are separated from each other in a first direction and a second direction, The outer pattern contacts the word line separation layer, and The contact plug contacts the external pattern.

19. The three-dimensional memory device of claim 18, wherein: The plurality of dummy internal patterns each include polysilicon doped with P-type impurities, and The exterior pattern includes metal.

20. The three-dimensional memory device according to claim 18, wherein: The plurality of dummy inner patterns are spaced apart from the word line separation layer.

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