Apparatus and Method for Multi-Bank and Multi-Pump Refresh Operations

Abstract

Embodiments of the present disclosure relate to apparatuses and methods for locally generating refresh addresses at memory banks. The memory banks may include or be associated with bank logic circuitry that latches an initial refresh address from a global row address bus of a first pump for a refresh operation. The bank logic circuitry then updates the received latched refresh address to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.

Description

BACKGROUND OF THE DISCLOSURE

[0001] The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor memory devices. Specifically, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Volatile memory requires periodic refreshing of data in the memory to preserve the data. The refresh operation may include multiple pumps, where one or more rows in a memory array are refreshed with each pump. As the memory operation speed increases, it may become more difficult to provide multiple pump refresh commands and associated refresh addresses for the memory refresh operation. SUMMARY OF THE DISCLOSURE

[0002] The methods and devices described herein may allow for local generation of at least one refresh address and / or row hammer refresh address at a bank logic circuit associated with a memory bank. The locally generated address may allow for providing a memory address for other memory access commands on a global row address bus before completion of a refresh operation. This may reduce the time required between memory access operations.

[0003] According to an example of the present disclosure, a device may include: a global row address bus configured to operably convey a refresh address associated with a refresh command; and a plurality of memory banks, each coupled to the global row address bus. Each memory bank of the plurality of memory banks may include bank logic circuitry configured to temporarily latch the refresh address upon activation to provide a latched refresh address, and update the latched refresh address to provide an updated refresh address. Each memory bank of the plurality of memory banks may include a memory array and a row address decoder coupled between the bank logic circuitry and the memory array.

[0004] According to an example of the present disclosure, a device may include a plurality of memory banks, where each memory bank of the plurality of memory banks includes bank logic circuitry configured to latch a refresh address from a global row address bus upon activation to provide a latched refresh address, and update the latched refresh address to provide an updated refresh address. Each memory bank may include a memory array and a row address decoder coupled between the bank logic circuitry and the memory array. The device may include a command decoder coupled to the plurality of memory banks, the command decoder configured to provide a first control signal to activate the bank logic circuitry, a second control signal to indicate a pump of a refresh operation, and a third control signal to indicate a mode of the refresh operation in response to a refresh command.

[0005] According to an example of the present disclosure, a device may include: a global row address bus configured to operably transfer a refresh address associated with a refresh command; a plurality of memory banks, wherein each memory bank of the plurality of memory banks includes bank logic circuitry, the bank logic circuitry including an address latch including a plurality of latch circuits; row address latch control logic circuitry that, when activated, is configured to: provide a first control signal to cause the address latch to temporarily latch the refresh address to provide a latched refresh address, and provide a second control signal to cause the address latch to change a state of at least one of the plurality of latch circuits to provide an updated refresh address; a memory array and a row address decoder coupled between the bank logic circuitry and the memory array, the row address decoder being configured to activate a first word line of the memory array specified by the latched refresh address and a second word line of the memory array specified by the updated refresh address. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2A is a schematic diagram of an operation sequence of a per-bank refresh command according to an embodiment of the present disclosure.

[0008] Figure 2B is another schematic diagram of an operation sequence of a per-bank refresh command according to an embodiment of the present disclosure.

[0009] Figure 3 is a timing diagram of a dual-pump memory refresh operation according to an embodiment of the present disclosure.

[0010] Figure 4 is a timing diagram of a dual-pump memory refresh and a row hammer refresh operation according to an embodiment of the present disclosure.

[0011] Figure 5 is a timing diagram of a dual-pump row hammer refresh operation according to an embodiment of the present disclosure.

[0012] Figure 6 is a schematic diagram of an operation sequence of a refresh command and an activation command according to an embodiment of the present disclosure.

[0013] Figure 7 is according to an embodiment of the present disclosure Figure 6 shown timing diagram of the refresh command and the activation command.

[0014] Figure 8A is a schematic diagram of an operation sequence of all-bank refresh commands according to an embodiment of the present disclosure.

[0015] Figure 8BAnother schematic diagram of the operation sequence of all bank refresh commands according to an embodiment of the present disclosure.

[0016] Figure 9 A timing diagram of all bank refresh commands according to an embodiment of the present disclosure. Detailed implementation

[0017] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the present disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form a part of the present system and method, and which illustrate specific embodiments in which the described system and method may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Additionally, for clarity, when the detailed description of certain features is obvious to those skilled in the art, it will not be discussed so as not to obscure the description of the embodiments of the present disclosure. Accordingly, the following detailed description should not be considered limiting in nature, and the scope of the present disclosure is defined only by the appended claims.

[0018] A memory device, such as a DRAM device, may include multiple memory banks, each memory bank including one or more memory arrays. During a memory operation (e.g., read, write, refresh), one or more memory addresses may be provided to a memory bank to indicate the row and / or column of the memory array to be activated. The memory addresses may be provided via an address bus. To avoid an increase in die size, the row address bus is typically shared by all memory banks in the memory device. This shared row address bus may be referred to as a global row address bus.

[0019] For a typical (e.g., conventional) memory refresh operation, when a refresh command is provided, a row address is sent via the global row address bus to one or more memory banks for per-bank refresh operations (REFpb), or a row address is sent via the global address bus to all banks for all-bank refresh operations (REFab). Once the refresh address has been provided, an address for a subsequent memory command (e.g., an activate command) may be provided on the global row address bus. However, for a multi-pump refresh operation, one or more row addresses are provided on the global row address bus for each pump of the refresh operation. Providing additional addresses on the global row address bus may require additional latency between memory commands to avoid conflicting row address data on the global row address bus. This additional latency between memory commands may degrade the performance of the memory device.

[0020] Figure 1FIG. 0 is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a command address input (CA) 102, a command decoder 104, a row address latch 106, a refresh counter 108, a first multiplexer (MUX1) 110, a temperature sensor 112, a global row address bus 113, and a plurality of memory banks (BANK0-7). Although the semiconductor device 100 includes eight memory banks, it should be understood that the semiconductor device 100 may include any number of memory banks (e.g., four, sixteen, thirty-two, etc.). For clarity, only BANK0 and BANK7 are shown in Figure 1 FIG. 1. Each memory bank BANK0-7 may include bank logic circuitry 114. As described herein, the bank logic circuitry 114 may allow one or more row addresses to be locally generated at the memory banks BANK0-7 during a refresh operation. The bank logic circuitry 114 may include a row hammer refresh address generator circuit (RHR Add_Gen) 116, a refresh progress logic (Ref) circuit 118, a row address latch control logic (RaLatCtrl) circuit 120, a second multiplexer (MUX2) 122, and an address latch 124. Each memory bank BANK0-7 may include a row address decoder 126 and a memory array 128. In some embodiments, each memory array 128 may include a plurality of memory cells (not shown) organized into rows (e.g., word lines) and columns (e.g., bit lines).

[0021] The CA 102 may receive commands and memory addresses associated with memory commands (e.g., a memory refresh command) provided by a device external to the device 100 (e.g., a memory controller). The memory address may include a row address, a column address, and / or a memory bank address. The CA 102 may provide (e.g., operably transfer) the commands and at least one memory bank address to the command decoder 104. The command decoder 104 may also receive a temperature signal (TEMP) from the temperature sensor 112. The temperature sensor 112 may sense the operating temperature of the semiconductor device 100 to generate the TEMP signal. The TEMP signal may assume a first logic state (e.g., high, “1”) associated with a high temperature and may assume a second logic state (e.g., low, “0”) associated with a low temperature. In some embodiments, the TEMP signal may assume three or more states to divide the operating temperature into three or more ranges. At least partially based on the memory command, the memory bank address, and the TEMP signal, the command decoder 104 may generate a plurality of internal control signals, including Sample0-7, Rfsh, RRASTD0-7, DRateRHR, and REF, as will be described in more detail below.

[0022] The row address latch 106 can receive a row address from the CA 102. The row address latch 106 can latch the row address associated with a memory command (e.g., an activate command, a read command, a write command), and provide the latched row address as an output signal RR.

[0023] The refresh counter 108 can generate a refresh address specifying the row address to be refreshed. Whenever a refresh operation is completed on a row address, the refresh counter can be updated to generate an updated row address to be used during the next refresh operation. The refresh address can be provided as an output signal CBRA.

[0024] The MUX1 110 can receive the RR from the row address latch 106 and the CBRA from the refresh counter 108. The MUX1 110 can output the RR or the CBRA in response to a REF signal from the command decoder 104. When the command decoder decodes a refresh command, the REF signal takes a first state (e.g., high, "1") to cause the MUX1 110 to select and output the CBRA. When the command decoder 104 decodes a non-refresh command (e.g., an activate command, a read command, a write command), the REF signal takes a second state (e.g., low "0") to cause the MUX1 110 to select and output the RR. The output of the MUX1 110 can be provided as a global row address GRA[16:0] to the global row address bus. As indicated by the [16:0] notation, in some embodiments of the present disclosure, the GRA can be a seventeen (17)-bit address. Each bank BANK0-7 can be coupled to the global row address bus 113. The bank logic circuit 114 can receive the GRA from the global row address bus 113.

[0025] The GRA can be provided to the RHR Add_Gen 116. The RHR Add_Gen 116 generates a row hammer refresh address RHRA[16:0] that specifies the word lines to be refreshed due to the "row hammer effect". The row hammer effect is caused by repeatedly activating the same word line in a consecutive manner (i.e., by accessing the same row address). The word line being repeatedly accessed can be referred to as the "attack word line". Word lines that are physically directly adjacent to the attack word line (e.g., the attack word line can be sandwiched between two adjacent word lines) can be affected by the repeated activation / access of the attack line. These adjacent word lines can be referred to as "sacrificial word lines". Repeatedly activating / accessing the attack word line in a consecutive manner can cause the data stored in the memory cells of the sacrificial word lines to degrade. The sacrificial word lines may require a refresh operation in addition to the regular refresh operations performed for normal memory operations to prevent data loss. These additional refresh operations outside of the normal refresh operation cycle can be referred to as row hammer refresh operations. The row hammer refresh address RHRA can specify the row addresses of one or more sacrificial word lines to be refreshed during a row hammer refresh operation. That is, the RHR Add_Gen 116 can generate multiple row addresses for outputting the RHRA during a row hammer refresh operation. For example, the RHR Add_Gen 116 can output different row addresses for each pump of the refresh operation.

[0026] The increased density of DRAMs has resulted in each memory cell being physically smaller, resulting in storing smaller charges, lower operating noise margins, an increased rate of electromagnetic interaction between memory cells, and a greater likelihood of data loss. The row hammer effect can further degrade the data stored in the memory cells that are coupled to two word lines that are directly adjacent to the sacrificial word lines. That is, the attack word line and the two sacrificial word lines can be sandwiched between two other word lines. These additional word lines can be referred to as "secondary sacrificial word lines", and the word lines that are directly adjacent to the attack word line can be referred to as "primary sacrificial word lines". In some embodiments, in addition to specifying the row addresses of at least one primary sacrificial word line, the RHRA can also include the row addresses of at least one secondary sacrificial word line.

[0027] Still referring to Figure 1, the command decoder 104 may provide control signals Sample0-7 to the corresponding RHR Add_Gen 116 of each memory bank BANK0-7. For example, the RHR Add_Gen 116 of BANK0 will receive Sample0, the RHR Add_Gen 116 of BANK1 will receive Sample1, and so on. The RHR Add_Gen 116 of each of BANK0-7 is coupled to the global row address bus 113. The RHR Add_Gen 116 of each bank BANK0-7 may sample the global row address bus 113 in response to the assertion of the active state of the corresponding one of the Sample0-7 signals provided by the command decoder 104. Each of the Sample0-7 signals may be asserted based on a non-refresh memory command (e.g., an activate command, a read command, a write command) for accessing the memory array 128 of the corresponding one of the memory banks BANK0-7. In other words, the non-refresh memory command may indicate a row hammer operation on the attacking word line and may require additional refresh operations on the primary and / or secondary sacrificial word lines. At least partially based on sampling the address from the global row address bus 113, the RHR Add_Gen 116 may provide RHRA as an output, which, as discussed above, may be an address associated with one or more sacrificial word lines.

[0028] The command decoder 104 can provide the control signal Rfsh to the Ref circuits 118 of each memory bank BANK0-7. The command decoder 104 can also provide the control signals RRASTD0-7 to the corresponding Ref circuits 118 of each memory bank BANK0-7. For example, the Ref circuit 118 of BANK0 will receive RRASTD0, the Ref circuit 118 of BANK1 will receive RRASTD1, and so on. In some embodiments, in response to the command decoder 104 decoding a refresh command, the Rfsh signal can be asserted (e.g., transition to an active state) in a single trigger pulse. That is, the Rfsh signal can transition to an active state within a finite time (e.g., one clock cycle, two clock cycles). In response to the active Rfsh signal, the Ref circuit 118 can check the status of the corresponding RRASTD signal (e.g., RRASTD0 for BANK0). If the RRASTD signal is in an active state (e.g., high, "1"), then the Ref circuit 118 will output the control signal RfshIP to transition to an active state (e.g., high, "1"). During a single refresh operation, the instruction decoder 104 can transition the RRASTD signal to an active state multiple times. The number of times the command decoder 104 transitions the RRASTD signal to an active state can be determined by the number of pumps included in the refresh operation. Any number of pumps (e.g., two, three, four, etc.) can be performed during the refresh operation. The number of pumps can be indicated by the refresh command or can be preset in the device 100.

[0029] The RaLatCtrl circuit 120 can be activated by the active RfshIP signal provided by the Ref circuit 118. When activated, the RaLatCtrl circuit 120 can provide the control signals SELA / SELB, R2ndPump, and RaLatch. The states of the various control signals can be at least partially based on the corresponding RRASTD signal provided by the command decoder 104 to the memory bank (e.g., RRASTD1 for BANK1). The states of the various control signals of the RaLatCtrl circuit 120 can be further at least partially based on the DRateRHR signal provided by the command decoder 104. The DRateRHR signal can be provided to all memory banks BANK0-7. The DRateRHR signal can be based on whether a conventional refresh operation (CBRR) or a row hammer refresh operation (RHR) is performed during each pump of the refresh operation. As will be referred to Figure 2A and 2BMore specifically explained, a single refresh operation that includes multiple pumps can refresh the word lines on each pump corresponding to a conventional refresh operation (CBRR) based on the refresh counter 108, refresh the word lines on each pump corresponding to a row hammer refresh operation (RHR) based on the RHR Add_Gen 116, or some pumps can be part of the conventional refresh operation while other pumps can be part of the row hammer refresh operation.

[0030] MUX2 122 can receive the refresh address GRA from the global row address bus 113 at input A and the row hammer refresh address RHRA from the RHR Add_Gen 116 at input B. MUX2 122 can receive the control signal SELA / SELB from the RaLatCtrl circuit 120. In some embodiments, MUX2 122 can output GRA when SELA / SELB is in the high state and output RHRA when SELA / SELB is in the low state. The state of SELA / SELB can be at least partially based on the state of the DRateRHR signal provided by the command decoder 104 to the RaLatCtrl circuit 120. When DRateRHR is in the first state (e.g., high), SELA / SELB can be set to the low state to select RHRA for the row hammer refresh operation. When DRateRHR is in the second state (e.g., low), SELA / SELB can be set to the high state to select GRA to perform a typical refresh operation.

[0031] The address latch 124 can receive the address (GRA or RHRA) from MUX2 122. The address latch 124 can temporarily latch the address in response to the active RaLatch control signal received from the RaLatCtrl circuit 120. The address latch 124 includes seventeen (17) latch circuits X0 - 16 (e.g., bits). The state of the fourteenth (14th) latch circuit (X13) (more significant bit) of the address latch 124 is determined by the control signal R2ndPump provided by the RaLatCtrl circuit 120.

[0032] When the refresh address GRA is latched, the address circuit X13 may have an initial state (e.g., X13 = 0). During the first pump of the refresh operation, the initial address latched by the address latch 124 is provided to the row address decoder 126, and the row associated with the initial address can be refreshed. After the first pump is completed, the RRASTD signal may transition to indicate the state of the second pump, as described above. In response to the indication of the second pump, the R2ndPump signal may be asserted (e.g., transition to an active state) by the RaLatCtrl circuit 120 on a single trigger pulse. That is, the R2ndPump signal may transition to an active state within a finite time (e.g., one clock cycle, two clock cycles). In response to the active R2ndPump signal, the address latch circuit X13 may transition to a second state (e.g., X13 = 1). The new address in the address latch 124 is provided to the row address decoder 126, and the row associated with the new address is refreshed during the second pump.

[0033] As described herein, changing the address latch circuit X13 via the R2ndPump signal to update the latched address may allow the library logic circuit 114 to locally generate a second row address for refreshing during subsequent pumps of the refresh operation. Thus, there is no need to provide a refresh address for additional pumps on the global row address bus 113. Although Figure 1 the example shown in

[0034] includes logic for locally generating one row address, the library logic circuit 114 may include logic for locally generating multiple row addresses, e.g., when performing more than two pumps during a refresh operation. For example, two or more address latch circuits of the address latch 124 may have states based on control signals (e.g., X13 and X14) from the RaLatCtrl.

[0035] The operation of the apparatus 100 will be further described with reference to the following figures. Although the sequences and timing diagrams shown in FIGS. 2 - 5 are for memory bank BANK0, in some embodiments, all memory banks of the apparatus 100 may function the same as BANK0.

[0036] Figure 2A and 2BSchematic diagrams of operation sequences 200A and 200B for per-bank refresh commands according to embodiments of the present disclosure. In the illustrated example, each refresh operation includes two pumps (e.g., refreshing word lines associated with two row addresses). However, a refresh operation can include any number of pumps (e.g., one, three, four). A single refresh operation that includes multiple pumps can refresh word lines on each pump corresponding to a conventional refresh operation (CBRR) based on the refresh counter 108, refresh word lines on each pump corresponding to a row hammer refresh operation (RHR) based on the RHR Add_Gen 116, or some pumps can be part of a conventional refresh operation while other pumps can be part of a row hammer refresh operation. Thus, a refresh operation with multiple pumps can include a combination of refresh operations. When a refresh operation includes two pumps, the refresh operation can include three combinations: the CBRR-CBRR 202 mode, the CBRR-RHR 204 mode, and the RHR-RHR 206 mode. In some embodiments, the operation sequence mode of the three modes can depend on the operating temperature.

[0037] For the CBRR-CBRR 202 mode, a conventional refresh operation is performed on each pump based on the address provided on the global row address bus 113 or the address addressed thereby. For the CBRR-RHR 204 mode, a conventional refresh operation based on the address provided on the global row address bus 113 is performed on the first pump, and a row hammer refresh operation based on the address provided by the RHR Add_Gen 116 can be performed on the second pump. For the RHR-RHR 206 mode, a row hammer refresh operation based on the address provided by the RHR Add_Gen 116 can be performed on each pump of the refresh operation.

[0038] For example, when the TEMP signal provided by the temperature sensor 112 takes a first state to indicate a high operating temperature, the refresh operation sequence mode can be as Figure 2A shown. In some applications, it may be advantageous to favor refreshing data at a higher temperature because data in memory cells may degrade at a faster rate at a higher temperature. In response to the TEMP signal having the first state, upon receiving the first per-bank refresh (REFpb) command #H1-H7, the refresh operations in the CBRR-CBRR mode, the CBRR-CBRR mode, the CBRR-CBRR mode, the CBRR-CBRR mode, the CBRR-CBRR mode, the CBRR-RHR mode, and the CBRR-CBRR mode can be respectively performed. As long as the TEMP signal is in the first state, the operation sequence 200A can be repeated for subsequent REFpb commands.

[0039] When the TEMP signal takes a second state to indicate a low operating temperature, the following can be performed as Figure 2BThe operation sequence pattern 200B shown. At lower temperatures, it may be advantageous to perform a refresh operation that counteracts the row hammer effect, as at lower temperatures, the row hammer effect may pose a greater risk to data integrity than typical DRAM data degradation at other temperatures. In response to the reception of the REFpb commands #L1-L7, the refresh operations in the CBRR-CBRR mode, RHR-RHR mode, CBRR-RHR mode, CBRR-RHR mode, and CBRR-CBRR mode can be performed respectively. As long as the TEMP signal is in the second state, this operation sequence pattern can be repeated for subsequent REFpb commands.

[0040] Sequences 200A and 200B are provided for illustrative purposes only. It should be noted that any other sequence pattern can be set as needed. For example, the sequence during high operating temperature (or another temperature) can be CBRR-CBRR, CBRR-RHR, CBRR-CBRR, CBRR-CBRR, CBRR-CBRR, CBRR-CBRR, CBRR-CBRR. Additionally, as previously mentioned, the TEMP signal can have more than two states indicating additional operating temperature ranges. Additional refresh operation sequences can be provided in response to the additional states of the TEMP signal.

[0041] Alternatively, instead of relying on temperature, the operation sequences 200A and 200B can be changed by fuse selection. In these embodiments, a fuse circuit can be provided instead of a temperature sensor. When the fuse circuit provides a control signal with a first state to the command decoder (e.g., command decoder 104), the sequence pattern shown as Figure 2A can be executed. When the control signal from the fuse circuit has a second state, the sequence pattern shown as Figure 2B can be executed. In some embodiments, more than two sequences can be programmed in the memory, and two or more fuses can be used to select the desired sequence.

[0042] Figure 3 is a timing diagram 300 of a dual-pump memory refresh operation according to an embodiment of the present disclosure. In some embodiments, the timing diagram 300 can reflect the operation of the device 100 during the CBRR-CBRR mode 202 refresh operation. For the CBRR-CBRR 202 mode, a regular refresh operation is performed on each pump based on the address provided on the global row address bus 113 or the address addressed thereby.

[0043] At or after T0, a per-bank refresh command (REFpb) indicating a refresh operation for Bank0 may be received at the command decoder 104. At or after T1, in response to receiving the REFpb command, the REF signal provided by the command decoder 104 may transition to an active (e.g., high) state. In response to the active REF signal, the refresh row address (CBRA-1(X13 = 0)) generated by the refresh counter 108 may be output by MUX1 110 and provided as GRA[16:0] to the global row address bus 113.

[0044] Further in response to the REFpb command, the command decoder 104 may transition the Rfsh signal and the RRASTD0 signal to an active (e.g., high) state at or after T2. For a normal refresh operation, the DRateRHR signal may remain in an inactive (e.g., low) state. In response to the active Rfsh and RRASTD0 signals, the Ref circuit 118 switches the RFSHIP0 signal to an active (e.g., high) state to activate the RaLatCtrl circuit 120 at or after T3. In response to the activation signal, the RaLatCtrl circuit 120 transitions the RaLatch0 signal to an active (e.g., high) state at or after T4. Meanwhile, the SELA / SELB signal remains high, causing MUX2 122 to output the row address CBRA-1(X13 = 0) from the global address bus. In response to the active RaLatch0 signal, the address latch 124 latches the row address CBRA-1(X13 = 0) and the row address (RA0[16:0]) transmitted from the address latch 124 to the row address decoder 126 to activate the word line specified by the address for refreshing in the memory array 128.

[0045] When the first pump refresh is completed on CBRA-1(X13 = 0), the command decoder 104 transitions the RRASTD0 signal to an active state again at or after T5 to indicate the second pump. In response to the second active RRASTD0 signal, the RaLatCtrl circuit 120 asserts the active R2ndPump0 signal at or after T6. The active R2ndPump0 signal is supplied to the preset terminal of the X13 latch circuit of the address latch to change its logical state from an initial state (e.g., low, "0") to a second state (e.g., high, "1") at or after T7. The output RA0 of the address latch 124 transitions from CBRA-1(X13 = 0) to CBRA-1'(X13 = 1). The new row address generated in response to the R2ndPump0 signal is provided to the row address decoder 126 to activate the word line of the memory array 128 specified by CBRA-1'X13 = 1 for refreshing during the second pump of the refresh operation.

[0046] Figure 4FIG. 400 is a timing diagram of a dual-pump memory refresh and row hammer refresh operation according to an embodiment of the present disclosure. That is, a normal refresh operation is performed during a first pump, and a row hammer refresh operation is performed during a second pump. In some embodiments, the timing diagram 400 may reflect the operation of the device 100 during the CBRR-RHR mode 204 refresh operation. For the CBRR-RHR 204 mode, a normal refresh operation based on the address provided on the global row address bus 113 is performed on the first pump, and a row hammer refresh operation based on the address provided by the RHR Add_Gen 116 may be performed on the second pump.

[0047] In the CBRR-RHR mode, starting from T0, the signals provided during the first pump of the refresh operation are the same as the signals provided during the first pump of the refresh operation, as shown in Figure 3 the timing diagram 300. However, the signals and operations of the device 100 are different for the second pump. After T1, the command decoder 104 transitions the DRateRHR signal to the active state to indicate a row hammer refresh when transitioning the RRASTD0 signal to the active state to indicate T2 or before the second pump after that. In response to the active DRateRHR signal, the SELA / SELB signal is transitioned to the low state by the RaLatCtrl circuit 120. The low SELA / SELB signal causes the MUX2 122 output to receive the row hammer refresh address RHRA-1 from the RHR Add_Gen 116. At or after T3, the active RaLatch0 signal is asserted again to cause the address latch 124 to latch RHRA-1 and output the row hammer refresh address as RA0 to the row decoder 126 to activate the corresponding word line of the memory array 128 to perform the row hammer refresh operation. In the CBRR-RHR mode refresh operation, the active R2ndPump0 signal is not asserted. Therefore, the first row address is provided by the global address bus 113 and the second row address is provided locally by the RHR Add_Gen 116.

[0048] Figure 5 FIG. 500 is a timing diagram of a dual-pump row hammer refresh operation according to an embodiment of the present disclosure. In some embodiments, the timing diagram 500 may reflect the operation of the device 100 during the RHR-RHR mode 206 refresh operation. For the RHR-RHR 206 mode, a row hammer refresh operation based on the address provided by the RHR Add_Gen 116 may be performed on each pump of the refresh operation.

[0049] In the RHR-RHR mode, in response to each per-bank refresh command (REFpb) received at or after T0, the command decoder 104 transitions the DRateRHR signal and the RRASTD0 signal to an active (e.g., high) state at or after T1 for the first pump of the refresh operation. In response to the active DRateRHR signal, the RaLatCtrl circuit 120 transitions the SELA / SELB signal to a low logic state during the first active RRASTD0 signal. As a result of the low SELA / SELB signal, although the refresh address (CBRA-3(X13 = 0)) is provided on the global row address bus 113 by the refresh address counter 108, no refresh operation based on CBRA-3(X13 = 0) is performed. Instead, in response to the low SELA / SELB signal, MUX2 122 provides the row hammer refresh address (RHRA-2) from the RHR Add_Gen 116 to the address latch 124 to be provided to the row decoder 126 for performing a refresh operation on the word line associated with RHRA-2.

[0050] Again, for the second pump, at or after T2, the command decoder 104 transitions the DRateRHR and RRASTD0 signals to an active state. In response to the active DRateRHR signal, SELA / SELB transitions to a low state, and MUX2 122 provides the row hammer refresh address (RHRA-2) from the RHR Add_Gen 116 to the address latch 124. The address latch 124 provides RHRA-3 to the row decoder 126 for performing a refresh operation on the word line associated with RHRA-3. In some embodiments, RHRA-2 may be the address corresponding to the first primary sacrificial word line, and RHRA-3 may be the address corresponding to the second primary sacrificial word line. In some embodiments, RHRA-2 may be the address corresponding to the first secondary sacrificial word line, and RHRA-3 may be the address corresponding to the second secondary sacrificial word line. In some embodiments, the row hammer refresh addresses RHRA-2 and RHRA-3 may be generated by the RHR Add_Gen 116 at least in part based on the row addresses sampled from the global row address bus 113 during non-refresh memory commands.

[0051] As previously discussed, although sharing the global row address bus among memory banks saves space on the die of the memory device, it may be necessary to increase the latency between memory commands to avoid having conflicting row addresses on the global row address bus. However, because the bank logic circuit 114 locally generates at least one refresh address and / or row hammer refresh address at the memory banks BANK0-7, the device 100 does not need to wait for the memory bank to complete the refresh operation before providing the row address associated with a subsequent memory command to the global row address bus 113.

[0052] Figure 6 is a schematic operation sequence 600 of a refresh command and an activation command according to an embodiment of the present disclosure. As shown in sequence 600, the apparatus 100 receives a per-bank refresh command (REFpb) indicating memory bank BANK0. In response to the refresh command, memory bank BANK0 performs a dual-pump refresh operation (CBRR-CBRR). Although a dual-pump refresh operation is shown in the Figure 6 example, a refresh operation with any number of pumps may be performed. Additionally, although a CBRR-CBRR mode refresh operation is shown, any mode refresh operation may be performed. After receiving the refresh command, but before completing the refresh operation of memory bank BANK0, the memory device receives an activation command (ACT) indicating memory bank BANK7. The row address associated with the activation command may be provided to memory bank BANK7 on the global row address bus 113 during the refresh operation of memory bank BANK0 because memory bank BANK0 does not need to receive additional refresh addresses from the global row address bus 113. In response to the activation command, memory bank BANK7 performs an activation operation while memory bank BANK0 continues to perform the refresh operation. Thus, the latency between memory commands can be reduced.

[0053] Figure 7 is according to an embodiment of the present disclosure Figure 6 shown timing diagram 700 of the refresh command and the activation command. At or after T0, the command decoder 104 receives a per-bank refresh command (REFpb) indicating memory bank BANK0. In response to the refresh command, the command decoder 104 transitions the REF signal to a high state at or after T1. In response to the high REF signal, MUX1 110 outputs the refresh address CBRA-4 (X13 = 0) from the refresh counter 108 to the global row address bus 113 (GRA). Further in response to receiving REFpb, the command decoder 104 may provide active Rfsh and RRAST0 signals to memory bank BANK0 at or after T2. Since this is a normal refresh operation, DRateRHR may remain low. In response to the active Rfsh and RRASTD0 signals, the Ref circuit 118 may activate the RaLatCtrl circuit 120 via active RfshIP0. Once activated, the RaLatCtrl circuit 120 of memory bank BANK0 may transition RaLatch0 to an active state. The RaLatCtrl circuit 120 may provide a low SELA / SELB0 signal to MUX2 122 such that the address latch 124 latches CBRA-4. The refresh address CBRA-4 may be provided from the address latch 124 to the row decoder 126, and the word lines associated with the address may be refreshed during the first pump of the refresh operation.

[0054] At or after T3, the command decoder 104 receives an activation command (ACT) indicating the activation of memory bank BANK7. In response to the ACT command, the command decoder 104 may transition the REF signal to an inactive state. In response to the inactive REF signal, MUX1110 may provide the row address RR provided by the row address latch 106 to the global row address bus 113 at or after T5. Although Figure 7 not shown in [reference], memory bank BANK7 may receive inactive Rfsh, RRASTD7, and DRateRHR signals from the command decoder 104. In response to the inactive control signals, the RaLatCtrl circuit 120 of memory bank BANK7 may provide an active RaLatch7 signal and a high SELA / SELB7 signal, such that the address latch 124 latches the ACT address from the global memory bus 113. Memory bank BANK7 may also receive an active Sample7 signal, such that the RHR Add_Gen 116 of memory bank BANK7 samples the ACT address from the global address line at or after T6. The ACT address may be provided by the address latch 124 to the row decoder 126, and an activation operation may be performed on the word line associated with the ACT address.

[0055] Returning to memory bank BANK0, the command decoder 104 again transitions RRASTD0 to an active state, indicating the second pump in the refresh operation at or after T4. For example, in some embodiments, this may occur after receiving an activation command. In response to the active RRASTD0 signal, the RaLatCtrl circuit 120 may provide an active R2ndPump0 signal to the address latch 124 at or after T5. The active R2ndPump0 signal changes the 14th latch circuit (X13) of the address latch 124 to generate an updated refresh address: CBRA-4'(X13 = 1). The updated refresh address is provided to the row decoder 126, and the word line associated with the address is refreshed during the second pump of the refresh operation at or after T6.

[0056] As shown in the timing diagram 700, the ACT address associated with the ACT command for memory bank BANK7 may be transferred onto the global row address bus 113, because CBRA-4'(X13 = 1) for the second CBRR pump of the refresh operation is generated by the bank logic circuit 114 without using any row address on the global row address bus 113. Thus, no conflict occurs between CBRA and the ACT address on the global row address bus 113. Although Figure 7 the example of [reference] shows a CBRR-CBRR mode dual-pump refresh operation, there may also be no conflict between memory commands and refresh commands for other refresh operation modes (e.g., CBRR-RHR mode or RHR-RHR mode).

[0057] Figure 8A And 8B are schematic diagrams of operation sequences 800A and 800B of all bank refresh commands according to embodiments of the present disclosure. Figure 8A Sequence 800A showing the refresh operation in response to a plurality of refresh commands for a high operating temperature is similar to Figure 2A the sequence shown. Figure 8B Sequence 800B showing the refresh operation in response to a plurality of refresh commands for a low operating temperature is similar to Figure 2B the sequence shown. Figure 8A And 8B the refresh commands of may be all bank refresh commands (REFab). The generation of the updated refresh address described here with reference to per-bank refresh commands can be applied to all bank refresh commands. Each memory bank BANK0-7 can operate in a similar manner as referenced Figures 1 to 5 described.

[0058] In some applications, refreshing all memory banks BANK0-7 in response to all bank refresh commands may cause device 100 to consume a large amount of current. This current consumption may be undesirable in some applications. To reduce current consumption, the refresh operations of memory banks BANK0-7 can be performed in a time-division manner. That is, the refresh operations of memory banks BANK0-7 can be staggered in time as shown in Figure 8A and 8B shown. In some embodiments, the bank logic circuits 114 of memory banks BANK0-7 can be activated in a time-division manner. In some embodiments, command decoder 104 can delay the transition of one or more control signals to an active state until one or more bank logic circuits 114 of memory banks BANK0-7.

[0059] Figure 9 is a timing diagram of all bank refresh commands according to embodiments of the present disclosure. All bank refresh commands (REFab) are received by command decoder 104 at or after T0. In response to REFab, command decoder 104 can provide an active REF signal to MUX1 110. In response, MUX1 110 can output a refresh address CBRA-5 (X13 = 0) from refresh counter 108 to global row address bus 113 after T1. Command decoder 104 can also provide an active Rfsh signal and RRASTD0 signal at or after T2. Although the active Rfsh signal is provided to all memory banks BANK0-7, the refresh operations of at least other memory banks BANK1-7 are delayed because command decoder 104 only provides the active RRASTD signal (RRASTD0) to memory bank BANK0 at or after T2. As shown in Figure 9As shown, in some embodiments, before or after T3, memory bank BANK7 may not receive the active RRASTD7 signal. Therefore, the refresh operations of memory banks BANK0 - 7 in response to all bank refresh commands can be performed in a time - division manner (e.g., interleaved) to reduce current consumption.

[0060] The methods and devices described herein may allow for locally generating at least one refresh address and / or row - hammer refresh address at the bank logic circuit associated with a memory bank. In some embodiments, the refresh address may be generated by updating an initial refresh address received from a global row - address bus. The locally generated address may allow for providing a memory address for other memory access commands on the global row - address bus before the completion of the refresh operation. This can reduce the time required between memory access operations.

[0061] Of course, it should be understood that, according to the present system, apparatus, and method, any one of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed between separate devices or device parts.

[0062] Finally, the above discussion is only intended to illustrate the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that those of ordinary skill in the art may design many modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Therefore, the specification and drawings are to be regarded as illustrative rather than limiting the scope of the appended claims.

Claims

1. An apparatus, which comprises: A global row address bus configured to operably transfer a refresh address associated with a refresh command; And A plurality of memory banks, each memory bank coupled to the global row address bus, wherein each memory bank of the plurality of memory banks comprises: Bank logic circuitry, when activated, configured to: Temporarily latch the refresh address to provide a latched refresh address; Output the latched refresh address; Update the latched refresh address to provide an updated refresh address; and Output the updated refresh address after outputting the latched refresh address; A memory array; and A row address decoder coupled between the bank logic circuitry and the memory array, wherein the row address decoder is configured to activate a first word line of the memory array specified by the latched refresh address and a second word line of the memory array specified by the updated refresh address.

2. The apparatus according to claim 1, Wherein the refresh command is a per-bank refresh command; and Wherein the bank logic circuitry of a first memory bank of the plurality of memory banks is activated, the first memory bank being specified by a bank address associated with the per-bank refresh command.

3. The apparatus according to claim 2, Wherein the global row address bus is further configured to operably transfer an ACT address associated with an activation ACT command for a second memory bank of the plurality of memory banks, the ACT command being issued before the row address decoder of the first memory bank completes activation of the first word line and the second word line; and Wherein the bank logic circuitry of the second memory bank is configured to temporarily latch the ACT address.

4. The apparatus according to claim 1, Wherein the refresh command is an all-banks refresh command; and Wherein the bank logic circuitry of all of the plurality of memory banks is activated at least in part in response to the all-banks refresh command.

5. The apparatus according to claim 4, wherein the bank logic circuitry of all of the plurality of memory banks is activated in a time-division manner.

6. The apparatus according to claim 1, wherein the bank logic circuitry comprises an address latch, and the bank logic circuitry updates the latched refresh address to provide the updated refresh address by changing a state of an address circuit of the address latch.

7. The apparatus according to claim 1, wherein the bank logic circuitry is further configured to: Sample the global row address bus during a non-refresh command; Temporarily latch a memory address from the global row address bus to provide a latched memory address; and Generate a row hammer refresh address based on the latched memory address.

8. An apparatus, which comprises: A plurality of memory banks, wherein each memory bank of the plurality of memory banks comprises: Bank logic circuitry, when activated, configured to: Latch a refresh address from a global row address bus to provide a latched refresh address; Output the latched refresh address; Update the latched refresh address to provide an updated refresh address; and Output the updated refresh address after outputting the latched refresh address; A memory array; and A row address decoder coupled between the bank logic circuit and the memory array, wherein the row address decoder is configured to activate a first word line of the memory array specified by the latched refresh address and a second word line of the memory array specified by the updated refresh address; and A command decoder coupled to the plurality of memory banks, the command decoder being configured in response to a refresh command to: Provide a first control signal to activate the bank logic circuit; Provide a second control signal to indicate the pump for the refresh operation; and Provide a third control signal to indicate the mode of the refresh operation.

9. The apparatus according to claim 8, further comprising a temperature sensor configured to provide a temperature signal indicative of an operating temperature to the command decoder, wherein the mode of the refresh operation is at least partially based on the temperature signal.

10. The apparatus according to claim 8, wherein the mode of the refresh operation comprises a normal refresh operation for a first pump and a second pump.

11. The apparatus according to claim 8, wherein the mode of the refresh operation comprises a normal refresh operation for a first pump and a row hammer refresh operation for a second pump.

12. The apparatus according to claim 8, wherein the mode of the refresh operation comprises a row hammer refresh operation for a first pump and a second pump.

13. The apparatus according to claim 8, wherein the command decoder is further configured to provide a fourth control signal in response to a non-refresh memory command to cause the bank logic circuit to sample an address from the global row address bus.

14. The apparatus according to claim 13, wherein the command decoder is further configured to provide a fifth control signal having a first state indicative of a row hammer refresh operation and a second state indicative of a normal refresh operation.

15. An apparatus, which comprises: A global row address bus configured to operably transfer a refresh address associated with a refresh command; A plurality of memory banks, wherein each memory bank of the plurality of memory banks comprises: A bank logic circuit, which comprises: An address latch comprising a plurality of latch circuits; A row address latch control logic circuit configured, when activated, to provide a first control signal to cause the address latch to temporarily latch the refresh address to provide a latched refresh address, and to provide a second control signal to cause the address latch to change a state of at least one of the plurality of latch circuits to provide an updated refresh address; A memory array; and A row address decoder coupled between the bank logic circuit and the memory array, the row address decoder being configured to activate a first word line of the memory array specified by the latched refresh address and a second word line of the memory array specified by the updated refresh address.

16. The apparatus according to claim 15, wherein the bank logic circuit further comprises: A row hammer refresh address generator circuit configured to generate a row hammer refresh address; and a multiplexer coupled to the global row address bus, the row hammer refresh address generator, and the address latch; wherein the row address latch control logic circuit is further configured to provide a third control signal to the multiplexer, the third control signal having a first state that causes the multiplexer to provide the refresh address to the address latch and a second state that causes the multiplexer to provide the row hammer refresh address to the address latch.

17. The apparatus of claim 15, further comprising a command decoder coupled to the plurality of memory banks, wherein the command decoder is configured to provide an active control signal to activate the row address latch control logic circuit in response to the refresh command.

18. The apparatus of claim 17, wherein the refresh command is an all-bank refresh command and activates the row address latch control logic circuits of the plurality of memory banks in a time-division manner, wherein the time-division manner is provided by the command decoder delaying the active control signal to one or more of the row address latch control logic circuits of the plurality of memory banks.

19. The apparatus of claim 17, wherein the bank logic circuit further includes a refresh progress logic circuit configured to receive the active control signal from the command decoder, and the refresh progress logic circuit is further configured to activate the row address latch control logic circuit in response to the active control signal.

20. The apparatus of claim 15, wherein the refresh command is a per-bank refresh command, wherein the row address latch control logic circuit of a first memory bank of the plurality of memory banks is activated by the per-bank refresh command; wherein the global row address bus is further configured to provide an ACT address associated with an ACT command for activating a second memory bank of the plurality of memory banks, the ACT command being issued before the row address decoder of the first memory bank completes activation of a first word line and a second word line; and wherein the address latch of the second memory bank is configured to latch the ACT address.

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