A metal interconnect structure formed by a subtractive process

Abstract

A metal interconnect structure of an integrated circuit can be fabricated by forming one or more vias after forming two adjacent metallization layers. The one or more vias are fully aligned with the first metallization layer and the second metallization layer. During the processing of the metal interconnect structure, a hard mask material or other insulating isolation material is left on top of the first metallization layer and the second metallization layer. Some of the hard mask material or other insulating isolation material is etched and then backfilled with a conductive material to form one or more vias, where the one or more vias are accommodated in a space that does not overlap with the surrounding dielectric material.

Description

[0001] Incorporation by reference

[0002] The PCT application form is filed simultaneously with this specification as part of this application. Each application for which this application claims the benefit or priority as identified in the PCT application form filed simultaneously is incorporated herein by reference in its entirety and for all purposes. BACKGROUND OF THE INVENTION

[0003] The interconnect structures incorporated in integrated circuits (ICs) include one or more layers of metal lines to connect the electronic devices of the IC to each other and to external connections. One or more dielectric material interlayers may be used to insulate these metal line layers from each other. The interconnect structure may be formed by additive patterning techniques or subtractive patterning techniques. Additive patterning techniques may include damascene or dual damascene processes, which may be used to fabricate interconnect structures having metals such as copper or cobalt. Trenches and / or holes are etched in the dielectric material, metal is deposited in the trenches and / or holes, and chemical mechanical planarization (CMP) is utilized to remove the excess portions. However, in subtractive patterning techniques, a metal capping layer is deposited and etched to form trenches and / or holes in the metal, and a dielectric material is deposited in the trenches and / or holes.

[0004] The background description provided herein is for the purpose of generally presenting the background of the disclosure. The work of the currently named inventors, to the extent it is described in this background art section and in aspects of the specification that could not be determined at the time of filing to constitute prior art, is neither expressly nor impliedly admitted to be prior art against the disclosure. SUMMARY OF THE INVENTION

[0005] A method of fabricating a metal interconnect structure is provided herein. The method includes: forming a first patterned metal line layer on a substrate by subtractive patterning; and forming a second patterned metal line layer over the first patterned metal line layer by subtractive patterning. The method further includes: after forming the second patterned metal line layer, forming one or more vias that provide electrical interconnection between the first patterned metal line layer and the second patterned metal line layer, thereby forming the metal interconnect structure.

[0006] In some embodiments, forming the one or more vias includes: forming one or more via openings through at least the second patterned metal line layer to the first patterned metal line layer; and filling the one or more via openings with a conductive material. In some embodiments, the method further includes: forming a plurality of first insulating features on the first patterned metal line layer; and after forming the plurality of first insulating features, forming a first dielectric material in the spaces between adjacent metal lines of the first layer. The method further includes: forming a plurality of second insulating features on the second patterned metal line layer; and after forming the plurality of second insulating features, forming a second dielectric material in the spaces between adjacent metal lines of the second layer. In some embodiments, forming the one or more vias includes: etching through one or more of the second insulating features; etching through the second patterned metal line layer; etching through one or more of the first insulating features to form one or more via openings, thereby exposing the first patterned metal line layer; and depositing a conductive material in the one or more via openings to form the one or more vias on the exposed first patterned metal line layer. In some embodiments, the method further includes: forming a via mask over the plurality of second insulating features and the second dielectric material; and patterning one or more holes in the via mask, wherein each of the one or more holes has a diameter or width greater than the critical dimension (CD) of the second patterned metal line layer and / or the first patterned metal line layer. Each of the one or more holes may have a diameter or width that is up to about 100% greater than the CD of the second patterned metal line layer and / or the first patterned metal line layer. In some embodiments, depositing the conductive material includes: filling with the conductive material the locations where the first insulating features and the second patterned metal line layer were previously etched away. In some embodiments, each of the first patterned metal line layer, the second patterned metal line layer, and the conductive material includes molybdenum (Mo), ruthenium (Ru), aluminum (Al), or tungsten (W). In some embodiments, the one or more vias are completely aligned with the first patterned metal line layer and the second patterned metal line layer. In some embodiments, forming the first patterned metal line layer includes: depositing a first metal over the substrate; depositing a first mask layer over the first metal; etching the first mask layer to form a plurality of first insulating features over the first metal; and etching the first metal to form the first patterned metal line layer defined by the plurality of first insulating features.In some embodiments, forming the second patterned metal line layer includes: depositing a second metal over the first patterned metal line layer; depositing a second mask layer over the second metal; etching the second mask layer to form a plurality of second insulating features over the second metal; and etching the second metal to form the second patterned metal line layer defined by the plurality of second insulating features.

[0007] On the other hand, there is provided a metal interconnect structure for an integrated circuit. The metal interconnect structure includes: a first patterned metal line layer; a plurality of first insulating features located on at least some of the first patterned metal line layer; a second patterned metal line layer located over the first patterned metal line layer; a plurality of second insulating features located on at least some of the second patterned metal line layer; and one or more vias providing electrical interconnection between the first patterned metal line layer and the second patterned metal line layer, wherein the one or more vias are fully aligned with the first patterned metal line layer and the second patterned metal line layer.

[0008] In some embodiments, the one or more vias extend through the first insulating features to contact the first patterned metal line layer with the second patterned metal line layer. In some embodiments, the metal interconnect structure further includes: a first dielectric material surrounding the first patterned metal line layer and the plurality of first insulating features; and a second dielectric material surrounding the second patterned metal line layer and the plurality of second insulating features. In some embodiments, the metal interconnect structure further includes a third dielectric material located over the recessed via metal fill of the one or more vias. In some embodiments, each of the first dielectric material and the second dielectric material includes a low-k dielectric material, and each of the plurality of first insulating features and the plurality of second insulating features has an etching selectivity different from that of the low-k dielectric material. In some embodiments, the one or more vias include a conductive material, wherein each of the first patterned metal line layer, the second patterned metal line layer, and the conductive material includes Mo, Ru, Al, or W.

[0009] These and other aspects are further described below with reference to the accompanying drawings. Description of the Drawings

[0010] Figure 1A-1O A schematic diagram showing an exemplary process for forming a metal interconnect structure by subtractive patterning.

[0011] Figure 2A Shows from Figure 1F A cross-sectional schematic diagram of an exemplary partially processed metal interconnect structure of line A-A.

[0012] Figure 2B-1 Exemplary cross-sectional views of a partially processed metal interconnect structure showing line B-B from Figure 1H , where the via opening is aligned with the underlying metal line.

[0013] Figure 2B-2 Exemplary cross-sectional views of a partially processed metal interconnect structure showing line C-C from Figure 1H , where the via opening is not aligned with the underlying metal line.

[0014] Figure 2C-1 Exemplary cross-sectional views of a partially processed metal interconnect structure showing line C-C from Figure 1J , where the via is aligned with the underlying metal line.

[0015] Figure 2C-2 Exemplary cross-sectional views of a partially processed metal interconnect structure showing line C-C from Figure 1J , where the via opening is not aligned with the underlying metal line.

[0016] Figure 2D-1 Exemplary cross-sectional views of an exemplary metal interconnect structure showing line D-D from Figure 1N , where the via is aligned with the overlying metal line.

[0017] Figure 2D-2 Exemplary cross-sectional views of an exemplary metal interconnect structure showing line D-D from Figure 1N , where the via is not aligned with the overlying metal line.

[0018] Figure 3 Flowchart showing an exemplary method of fabricating a metal interconnect structure in an integrated circuit, according to certain embodiments.

[0019] Figure 4A-4N Schematic illustration showing an exemplary process of forming a metal interconnect structure with fully aligned vias by subtractive patterning, according to certain embodiments.

[0020] Figure 5A Exemplary cross-sectional views of a partially processed metal interconnect structure showing line A-A from Figure 4J , according to certain embodiments.

[0021] Figure 5B Exemplary cross-sectional views of a partially processed metal interconnect structure showing line B-B from Figure 4J , according to certain embodiments.

[0022] Figure 5C Exemplary cross-sectional views of a partially processed metal interconnect structure showing line A-A fromFigure 4N Cross-sectional schematic view of an exemplary metal interconnect structure of line C-C.

[0023] Figure 5D According to certain embodiments, a cross-sectional schematic view of an exemplary metal interconnect structure of line D-D from Figure 4N is shown. DETAILED DESCRIPTION

[0024] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially processed integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially processed integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit processing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various objects, such as printed circuit boards and the like.

[0025] Advances in integrated circuit technology involve shrinking to smaller and smaller features in integrated circuits. Integrated circuits typically include conductive microelectronic structures or vias that connect conductive structures or film layers. Conductive structures can include line features (such as metal lines or metallization layers) that span a certain distance on a chip, and interconnect features (such as vias) that connect line features in different levels. The line features and interconnect features can be insulated by a dielectric material.

[0026] Damascene and dual damascene manufacturing techniques have been used to create vias and metal lines in metal interconnect structures. Damascene and dual damascene techniques are additive patterning techniques relied upon in the process of manufacturing metal interconnect structures, such as copper interconnect structures. However, as the feature sizes in integrated circuits continue to shrink, additive patterning techniques may be insufficient for certain technology nodes. In cases where additive patterning techniques are insufficient, subtractive patterning techniques may be suitable.

[0027] Generally speaking, in subtractive patterning technology, a metal overlay is deposited, a mask is coated on the metal overlay, and the metal overlay is etched to pattern metal lines or features defined by the mask. In contrast, in additive patterning technology, a dielectric material overlay is deposited, a mask is coated on the dielectric material overlay, openings or recesses defined by the mask are etched in the dielectric material overlay, and the openings or recesses are filled with metal. Typical metals used in additive patterning technology include copper (Cu) or cobalt (Co). Copper has a high electrical conductivity (second only to silver), which makes it very suitable for use as interconnect metal. However, metals such as copper and cobalt are difficult to etch, and thus are not suitable choices for subtractive patterning technology commonly used in integrated circuit manufacturing.

[0028] Typical subtractive patterning technology uses metals such as aluminum (Al) in the process of manufacturing metal lines and metal interconnect structures. The line widths fabricated by subtractive patterning technology are generally about several micrometers to hundreds of nanometers. Copper damascene technology was introduced many years ago for manufacturing copper lines and copper interconnect structures, where the line widths fabricated by damascene technology are generally about dozens and hundreds of nanometers. However, it is difficult to reliably obtain line widths equal to or less than 30 nm, or equal to or less than 20 nm using copper damascene technology. For example, copper interconnect structures usually require a diffusion barrier layer and / or a liner layer to limit copper diffusion into the surrounding dielectric material, and these film layers may occupy more space, thus making it more difficult to achieve smaller line widths. Metals other than copper can be used in subtractive patterning where thinner diffusion barrier layers and / or liner layers (or none) are allowable. This can achieve smaller sizes and / or technology nodes in integrated circuit manufacturing.

[0029] Subtractive patterning

[0030] Figure 1A-1O A schematic diagram showing an exemplary process of forming a metal interconnect structure by subtractive patterning is shown. In Figure 1A , a first metal layer 101 (Mx) is deposited over a substrate 100. Figure 1AThe first metal layer 101 therein is an unpatterned covering layer. A suitable deposition process (such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), or electrodeposition) can be used to deposit the first metal layer 101. Electrodeposition can include, for example, electroplating or electroless plating. In certain embodiments, the first metal layer 101 can include metals that can be etched, and these metals can include (but are not limited to) molybdenum (Mo), ruthenium (Ru), tungsten (W), or aluminum (Al). In certain embodiments, a liner layer can be disposed between the first metal layer 101 and the substrate 100. Examples of the liner layer include (but are not limited to) titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbonitride (WCN). The thickness of the liner layer can be equal to or less than about 5 nm, or equal to or less than about 3 nm. In certain embodiments, a dielectric layer 102 can be disposed between the liner layer and the substrate 100. The liner layer is used to separate the first metal layer 101 from the dielectric layer 102.

[0031] To pattern the first metal layer 101, a first hard mask layer 103 can be deposited over the first metal layer 101. Examples of suitable hard mask materials can include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (such as amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). A photoresist 104 and an underlayer resist 105 that are subjected to extreme ultraviolet light (EUV) lithography can be used to pattern the first hard mask layer 103. Additional layers can be formed between the photoresist and the first hard mask layer, and these additional layers will be useful in the lithography process. For example, amorphous carbon 106 (a-C) and an anti-reflection layer 107 (ARL) can be disposed between the photoresist 104 and the first hard mask layer 103. The anti-reflection layer 107 can be used to prevent radiation from reflecting from the underlying film layers and interfering with the exposure process during subsequent lithography processes.

[0032] In Figure 1B this, a plurality of first hard mask features 108 are formed by patterning the first hard mask layer 103. The photoresist 104 can be patterned by using lithography (such as EUV lithography) to define the plurality of first hard mask features 108. In addition, in some embodiments, the feature size of the first hard mask features can be reduced by self-aligned double patterning (SADP) processing. For example, narrower hard mask features can be formed by pitch doubling, and the pitch in the plurality of first hard mask features 108 can be reduced from 80 nm to 40 nm by using SADP processing.

[0033] InFigure 1C In [description], additional mask layers may be optionally deposited and patterned over the plurality of first hard mask features 108. These additional mask layers may be patterned to etch the underlying plurality of first hard mask features 108 into a desired configuration of the first hard mask features for patterning the first metal layer 101. Further, the first metal layer 101 may be patterned and "cut" according to the desired configuration of the first hard mask features 108. In some embodiments, the additional mask layers may include photoresist 109, a photoresist underlayer 110, and spin-on carbon 111 (SoC). However, it should be understood that instead of using additional mask layers to etch the underlying plurality of first hard mask features 108, the etching of the first hard mask features 108 may be performed after etching the first metal layer 101. In other words, the first metal layer 101 is "cut" through the additional mask layers, rather than subjecting the plurality of first hard mask features 108 to "cutting".

[0034] In Figure 1D [description], the plurality of first hard mask features 108 are patterned through the additional mask layers. Through a "cutting" etching process, the additional mask layers shape the plurality of first hard mask features 108 into a desired feature configuration. Subsequently, these additional mask layers are removed.

[0035] In Figure 1E [description], the first metal layer 101 is patterned to form a first patterned metal line layer 112. During the metal line etching process, the first patterned metal line layer 112 is defined by the plurality of first hard mask features 108. The metal line etching process may selectively etch through the metal to form the first patterned metal line layer 112 without etching the underlying dielectric layer 102. A suitable etchant may be used to etch the metal while substantially not etching the dielectric material of the underlying dielectric layer 102. As used herein, "substantially not etching" may refer to an etching process in which the etching rate of the bulk material (e.g., dielectric) is at least 4 / 5 lower than the etching rate of the target material to be etched (e.g., metal). For example, a reductive plasma etch may remove the metal overlay at a significantly higher etching rate than the underlying dielectric layer 102. After forming the first patterned metal line layer 112, the plurality of hard mask features 108 may be removed. In some embodiments, a diffusion barrier layer and / or a liner layer may be deposited on the first patterned metal line layer 112. The diffusion barrier layer and / or the liner layer separate the first patterned metal line layer 112 from the surrounding dielectric material.

[0036] In Figure 1FIn [the structure], a first dielectric material 113 is deposited over a first patterned metal line layer 112 and fills the spaces between adjacent first metal lines. The first dielectric material 113 can surround the first patterned metal line layer 112. After etching the metal capping layer to form the first patterned metal line layer 112, the first dielectric material 113 fills the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after depositing the first dielectric material 113, the first dielectric material 113 can be planarized by a planarization process (such as chemical mechanical polishing (CMP) and / or blanket etch back). In some embodiments, the first dielectric material 113 is a dielectric material with a low dielectric constant (low-k dielectric). The low-k dielectric can have a dielectric constant equal to or lower than about 5.0, which can be equal to or lower than the dielectric constant of silicon oxide (about 4.2). The low-k dielectric material can include fluorine-doped or carbon-doped silicon oxide or a low-k material containing organic substances, such as organosilicate glass (OSG). In some embodiments, air gaps can be formed in the first dielectric material 113 between adjacent patterned metal lines, and these air gaps can be used to further reduce the dielectric constant of the first dielectric material 113 between adjacent patterned metal lines. In [a structure] Figure 1F a cross-sectional schematic view of a processed metal interconnect structure taken along line A-A of Figure 2A [the structure] Figure 2A As shown in [the structure], the first dielectric material 113 fills the spaces between adjacent patterned metal lines. Air gaps 114 are formed in the first dielectric material 113 in the spaces between adjacent patterned metal lines, where the patterned metal lines are separated from the air gaps 114 by the remaining first dielectric material 113.

[0037] In [the structure] Figure 1G a via mask 115 can be formed over the first dielectric material 113. In some embodiments, the via mask 115 can include one or more mask layers, where the one or more mask layers include a photoresist 116, an underlayer photoresist 117, and spin-on carbon 118 (SoC). To form vias connected to the first patterned metal line layer 112, via openings defined by the via mask 115 are patterned and formed in the first dielectric material 113. A lithography process can be applied to the photoresist 116 to pattern the photoresist 116 of the via mask 115. One or more holes 119 can be formed in the via mask 115 to define via openings in the first dielectric material 113. The one or more holes 119 in the via mask 115 are intended to be aligned with the first patterned metal line layer 112.

[0038] In [the structure] Figure 1HIn [description], a via opening 120 is formed in the first dielectric material 113 by etching. The via opening 120 is defined by one or more holes 119 of a via mask 115. It is intended that the via opening 120 be aligned with one or more patterned metal lines of the first layer 112. However, as described below, alignment errors may occur during the lithography process, which may cause the via opening 120 not to be aligned with one or more patterned metal lines of the first layer 112. The via mask 115 can be removed after the via opening 120 is formed. In Figure 2B-1 a via opening 120 that is fully aligned with one or more patterned metal lines of the first layer 112 can be observed, while in Figure 2B-2 a via opening 120 that is not aligned with one or more patterned metal lines of the first layer 112 can be observed.

[0039] As feature sizes shrink, it may be difficult to scale conventional lithography processes to provide smaller feature sizes. This is at least partly due to alignment or overlay errors between features in the metal interconnect structure. Alignment or overlay errors always occur during the lithography process because the mask is not fully aligned with the underlying structure. For example, during the exposure phase of using a photomask in the lithography process, there may be a misalignment of several nanometers for the patterning mask for vias and trenches. Therefore, the vias intended to be connected to the patterned metal lines may be misaligned. Although the overlay error can be minimized by re-performing the lithography process, a certain degree of overlay error is unavoidable.

[0040] As Figure 2B-1 shown, when the via opening 120 patterned via one or more mask layers is fully aligned with the first patterned metal line layer 112, the via opening 120 does not deviate from the first patterned metal line layer 112. The via opening 120 is formed directly above the first patterned metal line layer 112, rather than in the space between adjacent patterned metal lines of the first layer 112. However, alignment or overlay errors may cause one or more mask layers to shift in the x-direction or y-direction, even by several nanometers. As Figure 2B-2 shown, the via opening 120 is patterned via one or more mask layers and is not aligned with the first patterned metal line layer 112. The misalignment causes a part of the via opening 120 to be formed in the space between adjacent patterned metal lines of the first layer 112. The misalignment results in a loss of the contact area between the patterned metal lines of the first layer 112 and the via, and the via partially overlaps with the dielectric material surrounding the first patterned metal line layer 112. In addition, the misalignment may pose a risk of a notch near the air gap 114, which may lead to a short circuit or leakage.

[0041] In Figure 1IIn [the structure], a second metal layer 121 (Mx+1) is deposited on the first dielectric material 113, where the second metal layer 121 fills the via openings 120 to form one or more vias. The second metal layer 121 provides a metal covering layer above the first dielectric material 113. In some embodiments, a liner layer is disposed between the second metal layer 121 and the first dielectric material 113. The liner layer may also be disposed between one or more patterned metal lines of the first layer 112 and the vias. The second metal layer 121 may provide a metal covering layer above the first dielectric material 113, or it may be deposited to the target thickness of the second metal layer 121. The deposition of the second metal layer 121 may cause surface topography problems or surface roughness, which may be attributed to the metal filling the via openings 120 and covering the first dielectric material 113. In some embodiments, a planarization process may be utilized to planarize the second metal layer 121, thereby producing a relatively smooth and flat thin metal layer. In some embodiments, the second metal layer 121 is deposited by a suitable deposition technique (such as PVD, CVD, PECVD, ALD, or electrodeposition). In some embodiments, the second metal layer 121 comprises Mo, Ru, Al, or W. In some embodiments, the via openings 120 may be filled by a metal deposition process different from the metal deposition process for depositing the metal on the first dielectric material 113. For example, a suitable deposition process may be utilized to fill the via openings 120 using one of the above-listed metals. A separate process may be performed thereafter to deposit a covering layer of one of the above metals on the first dielectric material 113 and connect to the vias. In some embodiments, the planarization process may be performed until the desired thickness of the second metal layer 121.

[0042] In Figure 1J [the structure], a second hard mask layer 122 is deposited above the second metal layer 121. Examples of suitable hard mask materials include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (such as amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). The photoresist 123 and the photoresist underlayer 124, which are subjected to extreme ultraviolet light (EUV) lithography, may be utilized to pattern the second hard mask layer 122. Additional layers may be formed between the photoresist 123 and the second hard mask layer 122, where these additional layers will be useful in the lithography process. For example, amorphous carbon 125 (a-C) and an anti-reflection layer 126 (ARL) may be disposed between the photoresist 123 and the second hard mask layer 122.

[0043] Figure 2C-1 and 2C-2 shows a cross-sectional schematic view of a partially processed metal interconnect structure taken along line C-C from Figure 1J [the structure]. As Figure 2C-1 and 2C-2As shown, the second metal layer 121 fills the via opening 120 to form a via 127, which provides an electrical connection to the first patterned metal line layer 112. In Figure 2C-1 , the via 127 is perfectly aligned with the first patterned metal line layer 112. However, due to alignment or overlay errors, as Figure 2C-2 shown, the via 127 is not aligned with the first patterned metal line layer 112. Due to alignment or overlay errors, the via 127 partially "lands" on the top surface of one or more patterned metal lines of the first layer 112, causing the via 127 to shift closer to the adjacent patterned metal lines of the first layer 112 and into the surrounding dielectric material. This reduces the distance between conductive features, meaning that the insulating space between the via 127 and the adjacent patterned metal lines of the first layer 112 is smaller. The reduced distance may result in insufficient short - circuit margin and reduced time - dependent dielectric breakdown (TDDB), or even a complete short - circuit. TDDB is a failure mode in which an insulating layer (such as the first dielectric material 113) breaks down over time and no longer acts as an effective electrical insulator in a typical electric field. TDDB depends on the electric field between the metal lines because regions exposed to higher electric fields are more vulnerable to TDDB failures. High voltage and / or reduced insulator thickness result in higher electric fields. TDDB also depends on the spacing between adjacent metal lines because the spacing may be reduced to the point where the insulating layer cannot withstand the electric field, resulting in an undesired conductance between adjacent metal lines. When the insulating layer cannot withstand the operating electric field, the end result is a short - circuit or reduced reliability. "Unlanded" vias can cause serious reliability problems due to TDDB degradation. In addition, "unlanded" vias can create gaps in the underlying air gaps 114, which are deposited with conductive material and may lead to a short - circuit,

[0044] In Figure 1K , a plurality of second hard mask features 128 are formed by patterning the second hard mask layer 122. The photoresist 123 can be patterned using lithography (such as EUV lithography) to define the plurality of second hard mask features 128. Additionally, in some embodiments, the feature size of the second hard mask features 128 can be reduced by self - aligned double patterning (SADP) processes. For example, narrower hard mask features can be formed by pitch doubling, where the pitch of the plurality of second hard mask features 128 can be reduced from 40 nm to 20 nm using SADP processes.

[0045] In Figure 1LIn [the process], an additional mask layer may optionally be deposited and patterned over the plurality of second hard mask features 128. The additional mask layer may be patterned to etch the underlying plurality of second hard mask features 128 into a desired configuration of the second hard mask features 128, thereby patterning the second metal layer 121. Further, the second metal layer 121 may be patterned and "cut" according to the desired configuration of the second hard mask features 128. In some embodiments, the additional mask layer may include photoresist 129, a photoresist underlayer 130, and spin-on carbon 131 (SoC). However, it should be understood that instead of using an additional mask layer to etch the underlying plurality of second hard mask features 128, the etching of the second hard mask features 128 may be performed after the etching of the second metal layer 121. In other words, the second metal layer 121 is "cut" through the additional mask layer, rather than subjecting the plurality of second hard mask features 128 to "cutting".

[0046] In Figure 1M [the process], the plurality of second hard mask features 128 are patterned through the additional mask layer. Through a "cutting" etch process, the additional mask layer forms the plurality of second hard mask features 128 into a desired feature configuration. Subsequently, the additional mask layers are removed.

[0047] In Figure 1N [the process], the second metal layer 121 is patterned to form a second patterned metal line layer 132. During the metal line etch process, the patterned metal lines are defined by the plurality of second hard mask features 128. The metal line etch process may selectively etch through the metal to form the second patterned metal line layer 132 without etching the first dielectric material 113. A suitable etchant may be used to remove the metal without etching or substantially etching the first dielectric material 113. For example, a reductive plasma etch may remove the metal overlay at an etch rate significantly higher than that of the underlying first dielectric material 113. After forming the second patterned metal line layer 132, the plurality of second hard mask features 128 may be removed. In some embodiments, a diffusion barrier layer and / or a liner layer may be deposited on the second patterned metal line layer 132. The diffusion barrier layer and / or the liner layer separates the second patterned metal line layer 132 from the surrounding dielectric material.

[0048] The via hole 127 provides an electrical interconnection between the second patterned metal line layer 132 and the first patterned metal line layer 112 to form a metal interconnection structure. As described above, when patterning one or more holes 119 in the via hole mask 115, there is a risk of misalignment with the first patterned metal line layer 112. Not only is there a risk of misalignment with the first patterned metal line layer 112 (Mx), but there is also a risk of misalignment with the second patterned metal line layer 132 (Mx + 1). When patterning the second patterned metal line layer 132, there is a risk of misalignment between the via hole 127 and the second patterned metal line layer 132. Figure 2D-1 Shows a cross-sectional schematic view of the metal interconnection structure taken along line D-D from Figure 1N wherein the via hole 127 is aligned with the second patterned metal line layer 132. In Figure 2D-1 there is no loss of contact area between the via hole 127 and the second patterned metal line layer 132. Figure 2D-2 Shows a cross-sectional schematic view of the metal interconnection structure taken along line D-D from Figure 1N wherein the via hole 127 is misaligned with the second patterned metal line layer 132. Due to the misalignment, in Figure 2D-2 there is a loss of contact area between the via hole 127 and the second patterned metal line layer 132. This results in a loss of via hole area. The resistance is proportional to the resistivity of the material and its length, and inversely proportional to the cross-sectional area of the material. The loss of via hole area causes a higher via hole resistance, which leads to a reduction in performance and reliability.

[0049] In Figure 1OIn a similar manner to Mx, the dielectric material 133 is deposited over the second patterned metal line layer 132 and fills the space between adjacent second metal lines. The dielectric material 133 (hereinafter referred to as the second dielectric material) may surround the second patterned metal line layer 132. After etching the metal capping layer to form the second patterned metal line layer 132, the second dielectric material 133 fills the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after depositing the second dielectric material 133, the second dielectric material 133 may be planarized by a planarization process (such as CMP and / or blanket etchback). In some embodiments, the second dielectric material 133 is a low-k dielectric material. In some embodiments, the second dielectric material 133 has the same composition as the first dielectric material 113. In some embodiments, air gaps may be formed in the second dielectric material between adjacent second metal lines, and these air gaps can be used to further reduce the dielectric constant of the second dielectric material 133 between adjacent second metal lines. After depositing the second dielectric material 133, a metal interconnect structure is formed. The metal interconnect structure formed by the subtractive patterning technique has a first patterned metal line layer 112 and a second patterned metal line layer 132 located above the first patterned metal line layer 112, where one or more vias 127 provide electrical interconnection between the first patterned metal line layer 112 and the second patterned metal line layer 132. It should be understood that additional metal lines (such as Mx+2, Mx+3, etc.) may be deposited and patterned to build on this metal interconnect structure. The additional metal lines may be formed in the same or similar manner as the second patterned metal line layer 132 and the first patterned metal line layer 112.

[0050] Self-aligned vias in subtractive patterning

[0051] The present invention relates to the fabrication of metal interconnect structures, where one or more vias are formed after forming two adjacent metallization layers. The one or more via openings are filled with a conductive material after patterning the first metal layer and after patterning the second metal layer to form the one or more vias. The metal interconnect structure is fabricated by a subtractive patterning technique. The one or more vias are aligned with each of the two adjacent metallization layers. The alignment between the one or more vias and the adjacent metallization layers is achieved by leaving some hard mask material or other insulating isolation material above the patterned metal lines after forming the two adjacent metallization layers. Some of the remaining insulating isolation material is removed when etching through one of the adjacent metallization layers to form the one or more via openings. Due to the etching selectivity differences between the surrounding dielectric material and the insulating isolation material, and between the surrounding dielectric material and the adjacent metallization layers, the formation of the one or more vias is restricted to a space that does not form the surrounding dielectric material. In some embodiments, the one or more vias are fully aligned with the two adjacent metallization layers to provide improved contact area, reduced resistivity, reduced TDDB failure risk, and reduced short circuit risk.

[0052] According to some embodiments, Figure 3 A flowchart showing an exemplary method of fabricating a metal interconnect structure in an integrated circuit. The operations in process 300 may be performed in a different order, and / or using different, fewer, or additional operations.

[0053] In block 310 of process 300, a first patterned metal line layer (Mx) is formed on a substrate by subtractive patterning. In some embodiments, the substrate is a semiconductor wafer, disposed on a semiconductor wafer, or a portion of a semiconductor wafer. The substrate may include a dielectric layer on which the first patterned metal line layer is formed. In some embodiments, a diffusion barrier layer and / or a liner layer may be deposited on the dielectric layer to separate the first patterned metal line layer from the dielectric layer. The first patterned metal line layer represents the first metallization layer in the metal interconnect structure. As used herein, a patterned metal line layer may also be referred to as a metallization layer, a metal layer, a metal line, a metal feature, or a line feature. The first patterned metal line layer or the first metallization layer may also be referred to as the bottom patterned metal line layer or the bottom metallization layer.

[0054] In block 310 of process 300, forming the first patterned metal line layer by subtractive patterning may involve one or more operations. In some embodiments, forming the first patterned metal line layer includes: depositing a first metal layer on a substrate; depositing a first insulating layer on the first metal layer; etching the first insulating layer to form first insulating features over the first metal layer; and etching the first metal layer to form the first patterned metal line layer defined by the plurality of first insulating features. In some embodiments, the first insulating layer may be a first hard mask layer, and the first insulating features may be first hard mask features. The first metal layer may include any suitable metal that can be etched and patterned using subtractive patterning techniques. For example, the first metal layer may include Mo, Ru, Al, or W. In some embodiments, any suitable deposition technique (such as PVD, CVD, PECVD, ALD, or electrodeposition) is used to deposit the first metal layer. Electrodeposition may include, for example, electroplating or electroless plating. In some embodiments, the critical dimension (CD) of the patterned metal lines of the first layer (Mx) is equal to or less than about 50 nm, equal to or less than about 20 nm, equal to or less than about 15 nm, or equal to or less than about 10 nm. In some embodiments, the pitch of the patterned metal lines of the first layer (Mx) is equal to or less than about 100 nm, equal to or less than about 40 nm, equal to or less than about 30 nm, or equal to or less than about 20 nm.

[0055] In some embodiments, process 300 further includes forming a plurality of first insulating features on the first metal layer. The plurality of first insulating features may define patterned metal lines in the first metal layer. Process 300 further includes forming a first dielectric material in the spaces between adjacent metal lines. The first dielectric material may surround the plurality of first insulating features and the first patterned metal line layer. After forming the first dielectric material, the plurality of first insulating features are retained to cover the top surface of the first patterned metal line layer. This can be used to limit subsequent etching processes when forming one or more vias.

[0056] Figure 4A-4D A schematic diagram showing an exemplary process of forming a first patterned metal line layer on a substrate by subtractive patterning is shown. Compared with Figure 4A-4D that shown, the formation of the first patterned metal line layer in block 310 of process 300 may involve different, fewer, or additional operations. In Figure 4A , a first metal layer 401 (Mx) is deposited over a substrate 400. Figure 4AThe first metal layer 401 therein is an unpatterned metal capping layer. In some embodiments, a capping layer may be disposed between the first metal layer 401 and the substrate 400. Examples of the capping layer include (but are not limited to) titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbonitride (WCN). The thickness of the capping layer may be equal to or less than about 5 nm, or equal to or less than about 3 nm. In some embodiments, a dielectric layer 402 may be disposed between the capping layer and the substrate 400. The capping layer is used to separate the first metal layer 401 from the dielectric layer 402.

[0057] To pattern the first metal layer 401, a first hard mask layer 403 may be deposited over the first metal layer 401. Examples of suitable hard mask materials may include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (such as amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). A photoresist 404 and a photoresist underlayer 405 may be utilized to pattern the first hard mask layer 403, as Figure 1A shown, and an amorphous carbon layer 406 and an anti-reflection layer 407 are optionally disposed between the photoresist 404 and the first hard mask layer 403, as Figure 1A shown.

[0058] In Figure 4B forming a plurality of first hard mask features 408 by patterning the first hard mask layer 403. The patterning of the first hard mask layer 403 may be achieved by patterning the photoresist 404 using lithography (such as EUV lithography). In some embodiments, smaller feature sizes may be formed by pitch doubling as Figure 1B shown. In some embodiments, additional masking operations may be performed to "cut" the first hard mask features 408 into a desired configuration of the first hard mask features 408, as Figure 1C and 1D shown. Further, after the additional masking and cutting operations, the first metal layer 401 is patterned as defined by the first hard mask features 408.

[0059] In Figure 4C the first metal layer 401 is patterned to form a first patterned metal line layer 409. During the metal line etching process, the first patterned metal line layer 409 is defined by the plurality of first hard mask features 408. The metal line etching process may selectively etch through the metal to form the first patterned metal line layer 409 without etching or substantially not etching the underlying dielectric layer 402. For example, a reductive plasma etch may remove the metal capping layer at an etching rate significantly higher than that of the underlying dielectric layer 402. The plurality of first hard mask features 408 are retained without being removed from Figure 4CThe first patterned metal line layer 409 in removes the plurality of first hard mask features 408. In some embodiments, a liner layer and / or a diffusion barrier layer may be deposited on the plurality of first hard mask features 408 and the first patterned metal line layer 409. The liner layer and / or the diffusion barrier layer separates the first patterned metal line layer 409 and the plurality of first hard mask features 408 from the surrounding dielectric material.

[0060] In Figure 4D a first dielectric material 410 is deposited around the first patterned metal line layer 409 and the plurality of first hard mask features 408 and fills the space between adjacent patterned metal lines. The first dielectric material 410 may surround the first patterned metal line layer 409 and the first hard mask features 408. In some embodiments, the first dielectric material 410 is deposited over the plurality of first hard mask features 408. After etching the metal capping layer to form the first patterned metal line layer 409, the first dielectric material 410 fills the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after depositing the first dielectric material 410, the first dielectric material 410 and the plurality of first hard mask features 408 may be planarized by a planarization process (such as CMP and / or blanket etch). The planarization process may expose the top surface of the first hard mask features 408 covering the first patterned metal line layer 409. The top surface of the first hard mask features 408 and the first dielectric material 410 are coplanar. In some embodiments, the first dielectric material 410 is a low-k dielectric material. The low-k dielectric material may include fluorine-doped or carbon-doped silicon oxide or an organic-containing low-k material, such as OSG. In some embodiments, air gaps are formed in the first dielectric material 410 between adjacent patterned metal lines, where these air gaps can be used to further reduce the dielectric constant of the first dielectric material 410 between adjacent patterned metal lines. The air gaps are formed in the first dielectric material 410 in the space between adjacent patterned metal lines, where the patterned metal lines are separated from the air gaps by the remaining first dielectric material 410.

[0061] Returning to Figure 3 , at block 320 of process 300, a second patterned metal line layer is formed over the first patterned metal line layer by subtractive patterning. In some embodiments, a diffusion barrier layer and / or a liner layer may be deposited on the exposed surfaces of the first dielectric material and the plurality of first insulating features. The second patterned metal line layer represents the second metallization layer in the metal interconnect structure.

[0062] In block 320 of process 300, forming the second patterned metal line layer by subtractive patterning may involve one or more operations. In some embodiments, forming the second patterned metal line layer includes: depositing a second metal layer over the first dielectric material and the first patterned metal line layer, depositing a second insulating layer over the second metal layer, etching the second insulating layer to form a plurality of second insulating features over the second metal layer, and etching the second metal layer to form the second patterned metal line layer defined by the plurality of second insulating features. In some embodiments, the second insulating layer may be a second hard mask layer, and the second insulating features may be second hard mask features. The second metal layer may include any suitable metal that can be etched and patterned using subtractive patterning techniques. For example, the second metal layer may include Mo, Ru, Al, or W. In some embodiments, the second metal layer is the same material as the first metal layer. In some embodiments, any suitable deposition technique (e.g., PVD, CVD, PECVD, ALD, or electrodeposition) is used to deposit the second metal layer. Electrodeposition may include, for example, electroplating or electroless plating. In some embodiments, the critical dimension of the patterned metal lines of the second layer (Mx+1) is equal to or less than about 50 nm, equal to or less than about 20 nm, equal to or less than about 15 nm, or equal to or less than about 10 nm. In some embodiments, the pitch of the patterned metal lines of the second layer (Mx+1) is equal to or less than about 100 nm, equal to or less than about 40 nm, equal to or less than about 30 nm, or equal to or less than about 20 nm.

[0063] In some embodiments, process 300 further includes forming a plurality of second insulating features over the second metal layer. The plurality of second insulating features may define the second patterned metal line layer in the second metal layer. Process 300 further includes forming a second dielectric material in the spaces between adjacent metal lines. The second dielectric material may surround the plurality of second insulating features and the second patterned metal line layer. After forming the second dielectric material, the plurality of second insulating features are retained to cover the top surface of the second patterned metal line layer. This can be used to limit subsequent etching processes when forming one or more vias.

[0064] Figure 4E-4H A schematic diagram showing an exemplary process of forming a second patterned metal line layer over a first patterned metal line layer by subtractive patterning is shown. Compared with Figure 4E-4H that shown, the formation of the second patterned metal line layer in block 320 of process 300 may involve different, fewer, or additional operations. In Figure 4E , a second metal layer 411 (Mx+1) is deposited over the first patterned metal line layer 409, over the first dielectric material 410, and over the plurality of first hard mask features 408. Figure 4EThe second metal layer 411 therein provides a metal overlay above the first dielectric material 410 and the plurality of first hard mask features 408. In some embodiments, a liner layer is disposed between the second metal layer 411 and the first dielectric material 410, and between the second metal layer 411 and the plurality of first hard mask features 408. During patterning of the second metal layer 411, a second hard mask layer 412 may be deposited over the second metal layer 411, wherein the second hard mask layer 412 may be patterned using a photoresist 413 and a photoresist underlayer 414, as Figure 1J shown, and an amorphous carbon layer 415 and an anti-reflection layer 416 are optionally disposed between the photoresist 413 and the second hard mask layer 412, as Figure 1J shown.

[0065] In Figure 4F , a plurality of second hard mask features 417 are formed by patterning the second hard mask layer 412. The second hard mask layer 412 may be patterned by patterning the photoresist 413 using lithography (e.g., EUV lithography). In some embodiments, smaller feature sizes may be formed by pitch doubling as Figure 1K shown. In some embodiments, additional masking operations may be performed to "cut" the second hard mask features 417 into a desired configuration of the second hard mask features 417, as Figure 1L and 1M shown. Subsequently, after the additional masking and cutting operations, the second metal layer 411 is patterned as defined by the second hard mask features 417.

[0066] In Figure 4G , the second metal layer 411 is patterned to form a second patterned metal line layer 418. During the metal line etching process, the second patterned metal line layer 418 is defined by the plurality of second hard mask features 417. The metal line etching process may selectively etch through the second metal layer 411 to form the second patterned metal line layer 418 without etching or substantially not etching the first dielectric material 410 and the plurality of first hard mask features 408. For example, a reductive plasma etch may remove the metal overlay at an etching rate significantly higher than that of the first dielectric material 410 and the plurality of first hard mask features 408. As used herein, "significantly higher etching rate" may mean that the etching rate of the target material to be etched is at least 5 times greater than that of other materials. The plurality of second hard mask features 417 are retained without removing from Figure 4GThe second patterned metal line layer 418 in removes the plurality of second hard mask features 417. In some embodiments, a liner layer and / or a diffusion barrier layer may be deposited on the plurality of second hard mask features 417 and the second patterned metal line layer 418. The liner layer and / or the diffusion barrier layer separates the second patterned metal line layer 418 and the plurality of second hard mask features 417 from the surrounding dielectric material.

[0067] In Figure 4H a second dielectric material 419 is deposited around the second patterned metal line layer 418 and the plurality of second hard mask features 417 and fills the space between adjacent patterned metal lines. The second dielectric material 419 may surround the second patterned metal line layer 418 and the second hard mask features 417. In some embodiments, the second dielectric material 419 is deposited over the plurality of second hard mask features 417. After etching the metal capping layer to form the second patterned metal line layer 418, the second dielectric material 419 fills the gaps, recesses, openings, or spaces previously filled by the metal capping layer. In some embodiments, after depositing the second dielectric material 419, the second dielectric material 419 and the plurality of second hard mask features 417 may be planarized by a planarization process (such as CMP and / or blanket etch). The planarization process may expose the top surface of the second hard mask features 417 covering the second patterned metal line layer 418. The top surface of the second hard mask features 417 and the second dielectric material 419 are coplanar. In some embodiments, the second dielectric material 419 is a low-k dielectric material. In some embodiments, air gaps may be formed in the second dielectric material 419 between adjacent patterned metal lines, where the patterned metal lines are separated from the air gaps by the remaining second dielectric material 419.

[0068] Returning to Figure 3 , at block 330 of process 300, one or more vias are formed to provide electrical interconnection between the first patterned metal line layer and the second patterned metal line layer to form a metal interconnect structure. The one or more vias are formed after forming the first patterned metal line layer and the second patterned metal line layer. In addition, the one or more vias are formed after the following steps: subtractive patterning of the first metal layer and filling the space around the first patterned metal line layer with the first dielectric material, and subtractive patterning of the second metal layer and filling the space around the second patterned metal line layer with the second dielectric material. In other words, the operation of patterning the one or more vias is performed after defining two metallization layers.

[0069] In block 330 of process 300, the formation of the one or more vias may involve one or more operations. The one or more vias may be formed by forming one or more via openings through at least a second patterned metal line layer and into a first patterned metal line layer, and filling the one or more via openings with a conductive material. Forming the one or more via openings includes: etching through one or more second insulating features, etching through the second patterned metal line layer, and etching through one or more first insulating features. Etching through three or more layers of material can present many challenges, such as etching without or substantially without etching the surrounding materials. In some embodiments, the operation of etching through one or more second insulating features occurs without or substantially without etching the second dielectric material. In some embodiments, the operation of etching through the second patterned metal line layer occurs without or substantially without etching the second dielectric material. In some embodiments, the operation of etching through one or more first insulating features occurs without or substantially without etching the first dielectric material. As used herein, "substantially without etching" may refer to an etching process where the etching rate of the bulk material (e.g., dielectric) is at least 4 / 5 lower than the etching rate of the target material to be etched (e.g., hard mask). In other words, the etch selectivity of the target material to be etched relative to other materials is equal to or greater than about 5:1. Etching through three or more layers of material may use: the same etching process with the same etchant, or may use different etching processes with different etchants. In some embodiments, filling the one or more via openings with a conductive material includes: backfilling the second patterned metal line layer and the areas where one or more first insulating features have been etched away. Such a backfilling operation forms the one or more vias to provide an electrical connection to the remaining second patterned metal line layer.

[0070] The operation of forming the one or more via openings extending into the first patterned metal line layer may be restricted by the first insulating feature and the second insulating feature such that the one or more via openings do not shift or misalign. Specifically, the first insulating feature and the second insulating feature are used to restrict the etching process such that via openings do not form in the surrounding dielectric material. In the case where the first insulating feature and the second insulating feature are not retained after forming the first patterned metal line layer and the second patterned metal line layer, alignment or coverage errors may occur, which may create an undesired electrical connection (e.g., an undesired short circuit) between the first patterned metal line layer and the second patterned metal line layer.

[0071] The material differences between the first and second insulating features and the surrounding dielectric material contribute to an etch contrast, thereby restricting the formation of vias such that one or more vias can be self-aligned with the first patterned metal line layer and the second patterned metal line layer. Conventional manufacturing processes for providing vias between metallization layers typically use the same dielectric material as a space compensation between the metallization layers, while the first and second insulating features of the present invention provide a material difference with the surrounding dielectric material, which has different etch selectivities.

[0072] The vertical wall portions of the surrounding dielectric material serve as etch boundaries that restrict via etching such that the formation of the vias is aligned with the first patterned metal line layer and the second patterned metal line layer. Via etching does not extend into the surrounding dielectric material or adjacent vias. By restricting via formation, this ensures the self-alignment of one or more vias with the first patterned metal line layer and the second patterned metal line layer. When one or more vias are aligned with at least the first patterned metal line layer, the one or more vias directly contact the top surface of the first patterned metal line layer without overlap. Thus, the one or more vias do not overlap with the first dielectric material, and solve the TDDB degradation and short circuit problems caused by misaligned vias. When one or more vias are aligned with at least the second patterned metal line layer, the one or more vias are filled with a conductive material where one or more patterned metal lines of the previous second layer have been etched, and do not overlap with the second dielectric material. This solves the problems of reduced contact area, higher via resistance, and reduced reliability caused by misaligned vias. Thus, the self-aligned via patterning scheme can provide one or more vias that are fully aligned with the second patterned metal line layer and the first patterned metal line layer.

[0073] In some embodiments, process 300 further includes depositing a via mask over the second plurality of insulating features and the second dielectric material, and patterning one or more holes in the via mask to define one or more via openings. Each of the one or more holes has a diameter or width greater than the critical dimension of the second patterned metal line layer and / or the first patterned metal line layer. In some embodiments, each of the one or more holes has a diameter or width that is up to about 100% greater than the critical dimension of the second patterned metal line layer and / or the first patterned metal line layer. The diameter or width of the one or more holes in the via mask is made overly large such that it is greater than the diameter or width of the one or more vias that are actually formed. In this way, any misalignment between the one or more holes and the underlying layer to be etched does not result in leaving target material to be etched. By having overly large holes, this also ensures that the underlying layer to be etched is etched regardless of any alignment errors. This is partly due to the selectivity of the second insulating feature relative to the second dielectric material during etching, the selectivity of the second patterned metal line layer relative to the second dielectric material during etching, and the selectivity of the first insulating feature relative to the first dielectric material during etching. However, it should be understood that the diameter or width of the one or more holes is not so large as to risk extending into adjacent metal lines. Thus, the diameter or width of the one or more holes in the via mask is slightly overly large to address the misalignment tolerance issue, but not so large as to etch into other metal lines.

[0074] Figure 4I-4L A schematic illustration of an exemplary process for forming one or more vias is shown, where the one or more vias are used to provide electrical interconnection between a first patterned metal line layer and a second patterned metal line layer. Compared with Figure 4I-4L that shown, the formation of the one or more vias of block 330 of process 300 may involve different, fewer, or additional operations. In Figure 4IIn [the structure], a via mask 420 may be formed over a plurality of second hard mask features 417 and a second dielectric material 419. The via mask 420 may have one or more holes 421 for patterning one or more via openings through at least the second patterned metal line layer 418. The via mask 420 may include one or more layers for patterning, where the one or more layers may include a photoresist 422, a photoresist underlayer 423, spin-on carbon 424 (SoC), and a mask layer 425 (such as a hard mask layer). A lithography process may be applied to the photoresist 422 to pattern the mask layer 425, where one or more holes may be formed in the mask layer 425. Portions of the mask layer 425 may be etched to form one or more holes for defining one or more via openings. The one or more holes in the mask layer 425 are intended to be aligned with the second hard mask features 417, the second patterned metal line layer 418, and the first hard mask features 408 in which the one or more vias are to be formed. In some embodiments, the diameter of the one or more holes is greater than the critical dimension of the second patterned metal line layer 418 and / or the first patterned metal line layer 409. In some embodiments, the critical dimension of the first patterned metal line layer 409 or the second patterned metal line layer 418 may be equal to or less than about 50 nm, equal to or less than about 20 nm, or equal to or less than about 10 nm. In some embodiments, the diameter is greater than the critical dimension of the second patterned metal line layer 418 and / or the first patterned metal line layer 409 by between about 1% and about 100%, between about 5% and about 100%, or between about 10% and about 50%. The diameter of the one or more holes is greater than the actual one or more via openings formed through the second patterned metal line layer 418, where the difference in size addresses certain misalignment tolerance issues without etching adjacent metal lines. In some embodiments, the mask layer 425 of the via mask 420 comprises a material different from the materials of the second hard mask features 417, the second patterned metal line layer 418, and the first hard mask features 408.

[0075] In Figure 4JIn [the figure], one or more via openings 426 are formed by etching through at least the second patterned metal line layer 418 until the first patterned metal line layer 409. The one or more via openings 426 are defined by one or more holes 421 in the via mask 420. It is intended that the one or more via openings 426 be aligned with one or more patterned metal lines of the second layer 418 and one or more patterned metal lines of the first layer 409. By leaving an electrically insulating material (such as the first and second hard mask features) on the top surface of the patterned metal lines having an etching selectivity different from that of the surrounding dielectric material, the misalignment tolerance problem can be solved. In this way, the electrically insulating material is used to limit the etching process so that the one or more via openings 426 are not formed in the surrounding dielectric material. The misalignment tolerance problem can also be solved by having slightly oversized holes in the via mask 420 and ensuring that the etching process is selective with respect to the surrounding dielectric material for the second hard mask feature 417, the second patterned metal line layer 418, and the first hard mask feature 408. In this way, the oversized holes in the via mask 420 reduce the risk that the etching process misses the target material to be etched, so that the operation of forming the one or more via openings 426 does not leave any target material unetched.

[0076] Forming the one or more via openings 426 includes: etching through one or more second hard mask features 417, etching through the second patterned metal line layer 418, and etching through one or more first hard mask features 408. The etching process stops on the first patterned metal line layer 409. The first patterned metal line layer 409 is exposed after the etching process. The operation of etching through one or more second hard mask features is selective with respect to the second dielectric material 419, the operation of etching through the second patterned metal line layer 418 is selective with respect to the second dielectric material 419, and the operation of etching through one or more first hard mask features 408 is selective with respect to the first dielectric material 410. Along the Figure 4J lines A-A and B-B respectively taken Figure 5A and 5B in [the figure], it can be observed that via openings 426 are formed through one or more second hard mask features 417, through the second patterned metal line layer 418, and through one or more first hard mask features 408.

[0077] In Figure 4KIn [the figure], a conductive material 427 is deposited in one or more via openings 426 to fill the one or more via openings 426. One or more vias 428 are formed by filling the one or more via openings 426 that previously filled one or more first hard mask features 408 and a second patterned metal line layer 418. In some embodiments, the conductive material 427 is the same material as the first patterned metal line layer 409 and the second patterned metal line layer 418. For example, the conductive material 427 includes Mo, Ru, Al, or W. In some embodiments, the conductive material 427 is a material different from the first patterned metal line layer 409 and the second patterned metal line layer 418. In some embodiments, the conductive material 427 is deposited by a suitable deposition technique (such as PVD, CVD, PECVD, ALD, or electroplating) to at least substantially fill the one or more via openings 426. In some embodiments, a diffusion barrier layer and / or a liner layer may be deposited in the one or more via openings 426 before filling the one or more via openings 426 with the conductive material 427. The diffusion barrier layer and / or the liner layer may separate the one or more vias 428 from the surrounding dielectric material.

[0078] One or more vias 428 are formed by backfilling the areas where the second patterned metal line layer 418 and one or more first hard mask features 408 are etched away with the conductive material 427. By backfilling, the conductive material 427 contacts the exposed first patterned metal line layer 409 and provides electrical interconnection with the second patterned metal line layer 418. In some embodiments, the conductive material 427 is deposited to fill the one or more via openings 426, fill one or more holes in the fill mask layer 425, and provide a conductive material 427 cover layer above the one or more via openings 426. This provides a conductive material 427 overburden above the one or more via openings 426.

[0079] In Figure 4LTherein, a portion of the conductive material 427 is removed such that the remaining portion of the conductive material 427 fills where one or more first hard mask features 408 and the second patterned metal line layer 418 previously filled one or more via openings 426. This operation of removing this portion of the conductive material 427 includes etching the conductive material 427 in the following regions: above one or more via openings 426, in one or more holes in the mask layer 425, and where one or more second hard mask features 417 previously filled one or more via openings 426. This removes the conductive material 427 covering and leaves the conductive material 427 to the bottom level of the second hard mask feature 417. Thus, one or more recesses can be formed through the one or more holes to the bottom level of the second hard mask feature 417, thereby providing at least the recessed metal fill 429 to the bottom level of the second hard mask feature 417. In Figure 4L , the metal interconnect structure is fabricated to have two adjacent metallization layers connected by one or more fully aligned vias 428.

[0080] Returning to Figure 3 , process 300 may further include covering the exposed portions of the conductive material with a third dielectric material. In some embodiments, the third dielectric material may be deposited over the recessed via metal fill and the second insulating feature. The third dielectric material may be etched or polished to be coplanar with the second insulating feature. In some embodiments, the third dielectric material may be the same material as the second insulating feature.

[0081] In some embodiments, process 300 may further include forming a third patterned metal line layer (Mx+2) on the second patterned metal line layer by subtractive patterning. The third patterned metal line layer may represent the third metallization layer in the metal interconnect structure. In some embodiments, one or more additional vias may be formed, which provide electrical interconnection between the second patterned metal line layer and the third patterned metal line layer. Additional metallization layers and vias may continue to be fabricated in the metal interconnect structure, where the additional metallization layers may be formed in the same or similar manner as the first and second metallization layers, and the additional vias may be formed in the same or similar manner as the one or more vias that provide electrical interconnection between the first patterned metal line layer and the second patterned metal line layer.

[0082] Figure 4M-4N A schematic diagram showing an exemplary process of covering the recessed via metal fill with a third dielectric material is shown. Compared with Figure 4M-4N that shown, the operation of covering the recessed via metal fill may involve different, fewer, or additional operations. In Figure 4MIn [the above process], a third dielectric material 430 is deposited over the plurality of second hard mask features 417 and the recessed via metal fill 429. The third dielectric material 430 can be deposited in one or more recesses formed after removing a portion of the conductive material 427 that fills one or more via openings 426. In some embodiments, the third dielectric material 430 is the same material as the second hard mask features 417. In some embodiments, the third dielectric material 430 is deposited over the mask layer 425. The third dielectric material 430 can be the same material or the same type of material as the mask layer 425. The third dielectric material 430 is deposited to cover the exposed portions of the conductive material 427.

[0083] In Figure 4N [the above process], a planarization process is performed to remove the third dielectric material 430 until the second hard mask features 417. The planarization process can include CMP and / or blanket etch such that the third dielectric material 430 is coplanar with the second hard mask features 417. Additionally, while removing some of the third dielectric material 430, the mask layer 425 over the plurality of second hard mask features 417 can be removed. The third dielectric material 430 and the second hard mask features 417 are used to cap or cover the second patterned metal line layer 418. Additional patterned metal line layers and additional vias can then be formed in the same or a similar manner as the first patterned metal line layer 409, the second patterned metal line layer 418, and the one or more vias 428. After capping the recessed via metal fill 429, in [the cross-sections] Figure 4N taken along the lines C-C and D-D respectively Figure 5C and 5D [the cross-sections], a metal interconnect structure can be observed. Figure 5C and 5D The metal interconnect structures in [the cross-sections] show perfectly aligned vias 428 that provide electrical interconnection between the first patterned metal line layer 409 and the second patterned metal line layer 418.

[0084] After forming one or more vias 428 that provide electrical interconnection between the first patterned metal line layer 409 and the second patterned metal line layer 418, a metal interconnect structure is formed. Exemplary metal interconnect structures of the integrated circuit are shown in Figure 5C and 5DAmong them. The metal interconnect structure may include a first patterned metal line layer 409, a plurality of first insulating features 431 on at least some of the patterned metal lines in the first layer 409, a second patterned metal line layer 418 above the first patterned metal line layer 409, and a plurality of second insulating features 432 on at least some of the patterned metal lines in the second layer 418. The metal interconnect structure further includes one or more vias 428 that provide electrical interconnection between the first patterned metal line layer 409 and the second patterned metal line layer 418, wherein the one or more vias 428 are completely aligned with the first patterned metal line layer 409 and the second patterned metal line layer 418. A first dielectric material 410 surrounds the first patterned metal line layer 409 and the plurality of first insulating features 431. A second dielectric material 419 surrounds the second patterned metal line layer 418 and the second insulating features 432. The one or more vias 428 are completely aligned such that the one or more vias 428 directly contact the first patterned metal line layer 409 without overlapping with the first dielectric material 410 or the second dielectric material 419. The one or more vias 428 are formed after patterning the first patterned metal line layer 409 and the second patterned metal line layer 418.

[0085] In some embodiments, the metal interconnect structure further includes a third dielectric material 430 above the recessed via metal fill 429, wherein the top surface of the second patterned metal line layer 418 is covered by the second insulating features 432, and the recessed via metal fill 429 is covered by the third dielectric material 430. In some embodiments, the third dielectric material 430 is the same material as the second insulating features 432. In some embodiments, each of the first dielectric material 410 and the second dielectric material 419 is a low-k dielectric material. The first insulating features 431 and the second insulating features 432 have an etching selectivity different from that of the low-k dielectric material. In some embodiments, the first patterned metal line layer 409 and the second patterned metal line layer 418 include Mo, Ru, Al, or W. In some embodiments, the one or more vias 428 include Mo, Ru, Al, or W, wherein the material of the one or more vias 428 is the same as or different from the materials of the first patterned metal line layer 409 and the second patterned metal line layer 418.

[0086] The processes described herein can be used in conjunction with, for example, lithographic patterning tools or processes for manufacturing semiconductor components, displays, LEDs, photovoltaic panels, and the like.

[0087] Typically, although not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Lithographic patterning of a film generally includes some or all of the following operations, each of which enables multiple viable tools: (1) coating a photoresist on a workpiece, i.e., a substrate, using a spin-coating or spraying tool; (2) curing the photoresist using a hot plate or furnace or ultraviolet curing tool; (3) exposing the photoresist to visible light or ultraviolet or X-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet cleaning station; (5) transferring the resist pattern to the underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as a radio frequency or microwave plasma resist stripper.

[0088] Conclusion

[0089] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the proposed embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations are not described in detail in order not to render the disclosed embodiments difficult to understand. Although the disclosed embodiments are described in conjunction with specific embodiments, it is understood that no limitation of the disclosed embodiments is intended.

[0090] For purposes of clarity of understanding, the foregoing embodiments have been described in detail, but it is understood that certain changes and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems, and devices of the embodiments herein. Accordingly, the embodiments herein are to be considered illustrative and not restrictive, and these embodiments are not limited to the details provided herein.

Claims

1. A method of manufacturing a metal interconnect structure, the method comprising: forming a first patterned metal line layer on a substrate by subtractive patterning; forming a plurality of first insulating features on the first patterned metal line layer; after forming the plurality of first insulating features, forming a first dielectric material in a space between adjacent metal lines of the first patterned metal line layer; forming a second patterned metal line layer above the first patterned metal line layer by subtractive patterning; forming a plurality of second insulating features on the second patterned metal line layer; and after forming the plurality of second insulating features, forming a second dielectric material in a space between adjacent metal lines of the second patterned metal line layer; after forming the second patterned metal line layer, forming one or more vias that provide electrical interconnection between the first patterned metal line layer and the second patterned metal line layer to form the metal interconnect structure, wherein forming the one or more vias comprises: etching through one or more second insulating features, wherein the operation of etching through the one or more second insulating features is selective with respect to the second dielectric material surrounding the one or more second insulating features; etching through the second patterned metal line layer, wherein the operation of etching through the second patterned metal line layer is selective with respect to the second dielectric material surrounding the second patterned metal line layer; etching through one or more first insulating features to form one or more via openings to expose the first patterned metal line layer, wherein the operation of etching through the one or more first insulating features is selective with respect to the first dielectric material surrounding the one or more first insulating features; and depositing a conductive material in the one or more via openings to form the one or more vias on the exposed first patterned metal line layer.

2. The method according to claim 1, wherein forming the one or more vias comprises: forming one or more via openings that penetrate at least the second patterned metal line layer and reach the first patterned metal line layer; and filling the one or more via openings with a conductive material.

3. The method according to claim 1, further comprising: forming a via mask above the plurality of second insulating features and the second dielectric material; and patterning one or more holes in the via mask, wherein each of the one or more holes has a diameter or width greater than a critical dimension (CD) of the second patterned metal line layer and / or the first patterned metal line layer.

4. The method according to claim 3, wherein each of the one or more holes has a diameter or width that is up to 100% greater than the critical dimension of the second patterned metal line layer and / or the first patterned metal line layer.

5. The method according to claim 3, wherein depositing the conductive material comprises: filling with the conductive material the places where the previous first insulating features and the second patterned metal line layer have been etched away.

6. The method according to claim 1, wherein each of the first patterned metal line layer, the second patterned metal line layer, and the conductive material comprises Mo, Ru, Al, or W.

7. The method according to claim 1, wherein each of the first dielectric material and the second dielectric material comprises a low-k dielectric material, and wherein each of the plurality of first insulating features and the plurality of second insulating features has an etch selectivity different from that of the low-k dielectric material.

8. The method according to any one of claims 1-7, wherein the one or more vias are completely aligned with the first patterned metal line layer and the second patterned metal line layer.

9. The method according to any one of claims 1-7, wherein the critical dimension of the first patterned metal line layer and the second patterned metal line layer is equal to or less than 20 nm.

10. The method according to any one of claims 1-7, wherein forming the first patterned metal line layer comprises: depositing a first metal over the substrate; depositing a first mask layer over the first metal; etching the first mask layer to form a plurality of first insulating features over the first metal ； and etching the first metal to form the first patterned metal line layer defined by the plurality of first insulating features; wherein forming the second patterned metal line layer comprises: depositing a second metal over the first patterned metal line layer; depositing a second mask layer over the second metal; etching the second mask layer to form a plurality of second insulating features over the second metal; and etching the second metal to form the second patterned metal line layer defined by the plurality of second insulating features.

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