Integrated chips and methods for forming integrated chips

Abstract

In some embodiments, the present invention relates to a method of forming an integrated chip. The method can be implemented by forming a bonding pad layer on a dielectric structure formed over a substrate. The dielectric structure surrounds a plurality of interconnect layers. A protective layer is formed on the bonding pad layer, and the bonding pad layer and the protective layer are patterned to define bonding pads covered by the protective layer. One or more upper passivation layers are formed over the protective layer. A dry etching process is performed to form openings extending through the one or more upper passivation layers to the protective layer. A wet etching process is performed to remove a portion of the protective layer and expose the upper surface of the bonding pads. Embodiments of this application also relate to integrated chips.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated chips and methods of forming integrated chips. Background Art

[0002] Integrated chip manufacturing is a complex, multi-step process during which electronic circuits are formed on a wafer made of semiconductor material (e.g., silicon). Integrated chip manufacturing can be roughly divided into front-end-of-line (FEOL) processes and back-end-of-line (BEOL) processes. The FEOL process typically involves forming devices (e.g., transistors) within the semiconductor material, while the BEOL process typically involves forming a conductive interconnect layer within a dielectric structure above the semiconductor material. After the BEOL process is completed, bonding pads are formed, and the wafer can then be segmented (e.g., diced) to form multiple individual integrated chip dies. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming an integrated chip, comprising: forming a bonding pad layer on a dielectric structure formed above a substrate, wherein the dielectric structure surrounds a plurality of interconnect layers; forming a protective layer on the bonding pad layer; patterning the bonding pad layer and the protective layer to define a bonding pad covered by the protective layer; forming one or more upper passivation layers above the protective layer; performing a dry etching process to form an opening extending through the one or more upper passivation layers to the protective layer; and performing a wet etching process to remove a portion of the protective layer and expose the upper surface of the bonding pad.

[0004] Other embodiments of the present application provide a method for forming an integrated chip, comprising: forming a bonding pad layer above a substrate; forming a protective layer on the bonding pad layer; patterning the bonding pad layer and the protective layer to define a bonding pad covered by the protective layer; forming one or more upper passivation layers above the protective layer; etching the one or more upper passivation layers to expose the upper surface of the protective layer; performing a wet etching process to remove a portion of the protective layer from the upper surface of the bonding pad; and forming a conductive bump above the bonding pad after performing the wet etching process.

[0005] Still other embodiments of the present application provide an integrated chip, comprising: a plurality of interconnect layers disposed within a dielectric structure above a substrate; a bonding pad disposed above the dielectric structure; one or more upper passivation layers disposed above the dielectric structure and the bonding pad, wherein the one or more upper passivation layers include one or more side walls defining an opening directly above the bonding pad; and a protective layer including a metal directly disposed between the one or more upper passivation layers and the bonding pad, the metal having one or more side walls further defining the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip having a protection layer configured to improve reliability of a bonding pad are shown.

[0008] FIG. 2A to FIG. 2B Additional embodiments of integrated chips having a protection layer configured to improve the reliability of bond pads are shown.

[0009] FIG. 3A to FIG. 3B Cross-sectional views of some additional embodiments of a protective layer disposed on a bonding pad are shown.

[0010] Figure 4 Cross-sectional views of some additional embodiments of integrated chips having a protection layer configured to improve reliability of bond pads are shown.

[0011] Figure 5 Cross-sectional views of some additional embodiments of integrated chips having a protection layer configured to improve reliability of bond pads are shown.

[0012] Figures 6 to 16 Cross-sectional views of some embodiments of methods of forming an integrated chip structure having a protection layer configured to improve reliability of a bond pad are shown.

[0013] Fig.17 A flow chart illustrating some embodiments of a method of forming an integrated chip structure having a protection layer configured to improve reliability of a bond pad. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] During integrated chip manufacturing, a bonding pad may be formed above a dielectric structure surrounding a plurality of conductive interconnect layers. The bonding pad may be formed by depositing a conductive material (e.g., a metal) above the interconnect layer and then patterning the conductive material to define the bonding pad. After defining the bonding pad, one or more passivation layers may be formed on the bonding pad. The one or more passivation layers are then patterned to form an opening exposing the bonding pad.

[0017] The opening may be formed by subjecting one or more passivation layers to a first etching process. The first etching process may use a dry etchant having a fluorine etching chemistry. However, it should be understood that the fluorine from the dry etchant may interact with the metal (e.g., aluminum) of the bonding pad to form fluorinated byproducts (e.g., AlF3) on the bonding pad. The fluorinated byproducts may react with moisture (e.g., from air, a subsequent wet cleaning process, etc.) to form compounds (e.g., to form AlOH3 and 3HF) that may damage the bonding pad and cause electrical failure.

[0018] Therefore, in order to remove the fluorinated byproducts, a non-fluorine-based etchant (e.g., argon) can be used to implement the second etching process. However, although the non-fluorine-based etchant can remove the fluorinated byproducts, the non-fluorine-based etchant can also damage the bonding pad below, thereby giving the bonding pad a rough surface. The rough surface causes poor adhesion and / or electrical connection with the conductor (e.g., solder bump) above. In addition, in order to avoid contamination, a second etching process using a non-fluorine-based etchant can be implemented in a dedicated chamber. However, the use of a dedicated chamber for the second etching process may slow down the yield. Slow yields may cause reliability issues for the bonding pads because the fluorinated byproducts absorb moisture over time and degrade the bonding pads. Therefore, slow yields may result in a violation of the q time requirement of the second etching process (e.g., the etching process may have a q time of approximately 2 hours), thereby driving the rework of the substrate and further damaging the yield and increasing the costs associated with the manufacturing process.

[0019] In some embodiments, the present invention relates to a method for forming an integrated chip with a bonding pad structure, the bonding pad structure including a protective layer disposed on a bonding pad and configured to mitigate the formation of etching byproducts (e.g., fluorine metal byproducts) on the bonding pad. The method can be implemented by forming a plurality of interconnect layers in a dielectric structure formed above a substrate. A bonding pad layer is formed on the dielectric structure, and a protective layer is formed on the bonding pad layer. The bonding pad layer and the protective layer are patterned to define a bonding pad covered by the protective layer. One or more upper passivation layers are formed above the protective layer. A dry etching process is implemented to form an opening extending through one or more upper passivation layers to the protective layer. A wet etching process is then implemented to remove the protective layer and expose the upper surface of the bonding pad. Therefore, the method uses a protective layer to prevent the byproducts of the dry etching process from accumulating on the bonding pad, and thus eliminates the need for subsequently using a non-fluorine-based dry etchant to act on the bonding. In addition, the use of a wet etching process to remove the protective layer mitigates damage to the bonding pad, so that the bonding pad has a smooth upper surface of the bonding pad that provides good reliability.

[0020] Figure 1 A cross-sectional view of some embodiments of an integrated chip 100 having a protection layer configured to improve the reliability of a bonding pad is shown.

[0021] The integrated chip 100 includes a dielectric structure 106 disposed over a substrate 102. In some embodiments, one or more transistor devices 104 may be disposed within the substrate 102. The dielectric structure 106 surrounds a plurality of interconnect layers 108. In some embodiments, the plurality of interconnect layers 108 may be electrically coupled to the one or more transistor devices 104 within the substrate 102. In some embodiments, the plurality of interconnect layers 108 may include a top interconnect layer 108t disposed along an uppermost surface of the dielectric structure 106.

[0022] The bonding pad 110 is disposed above the dielectric structure 106. In some embodiments, the bonding pad 110 may be disposed directly above the top interconnect layer 108t. In other embodiments (not shown), one or more redistribution layers may be disposed between the plurality of interconnect layers 108 and the bonding pad 110. The passivation structure 112 surrounds the bonding pad 110. In some embodiments, the passivation structure 112 may include one or more passivation layers that respectively include different dielectric materials. In some embodiments, the passivation structure 112 may extend from along the sidewall of the bonding pad 110 to directly above the top of the bonding pad 110. The passivation structure 112 has sidewalls that define an opening 113 above the bonding pad 110. The opening 113 extends completely through the passivation structure 112 to the upper surface of the bonding pad 110. The conductive bonding structure 116 is disposed within the opening 113 and on the upper surface 110u of the bonding pad 110. In some embodiments, the conductive bonding structure 116 may include a conductive bump (eg, a solder bump), a conductive pillar (eg, a copper pillar, a copper micro-pillar), an under-bump metallurgy (UBM), or the like.

[0023] The protective layer 114 is vertically disposed between the top of the bonding pad 110 and the passivation structure 112, and has sidewalls that further define the opening 113. The protective layer 114 includes a material having a high etching selectivity relative to the passivation structure 112 and / or the bonding pad 110. The high etching selectivity allows the protective layer 114 to be etched at a different rate (e.g., a higher rate and / or a lower rate) than the passivation structure 112 and / or the bonding pad 110. For example, in some embodiments, the protective layer 114 may include a material that etches at a lower rate than the passivation structure 112 when exposed to a first etchant (e.g., a dry etchant) and etches at a higher rate than the passivation structure 112 when exposed to a second etchant (e.g., a wet etchant). In some embodiments, the protective layer 114 may include a material that also etches at a higher rate than the bonding pad 110 when exposed to the second etchant (e.g., a wet etchant). In some embodiments, the protective layer 114 may include, for example, a metal such as titanium (e.g., TiN).

[0024] The high etching selectivity between the protective layer 114 and the passivation structure 112 allows the opening 113 in the passivation structure 112 to be formed by the first etching process without etching through the protective layer 114. The ability to form the opening 113 in the passivation structure 112 without etching through the protective layer 114 allows the byproducts of the first etching process to be formed on the protective layer 114 and not on the bonding pad 110. In addition, the high etching selectivity between the protective layer 114 and the bonding pad 110 allows a portion of the protective layer 114 to be removed by the second etching process without severely damaging the bonding pad 110, thereby allowing the upper surface 110u of the bonding pad 110 to have the smoothness of the bonding pad 110, which provides good reliability.

[0025] Figure 2A Cross-sectional views of some additional embodiments of an integrated chip 200 having a protection layer configured to improve the reliability of a bonding pad are shown.

[0026] The integrated chip 200 includes a dielectric structure 106 disposed above the substrate 102. The dielectric structure 106 includes a plurality of stacked ILD layers 106a-106d. In some embodiments, the plurality of stacked ILD layers 106a-106d may be separated by an etch stop layer (not shown). In various embodiments, the plurality of stacked ILD layers 106a-106d may include one or more of oxides (e.g., SiO2, SiCO, etc.), fluorosilicate glass, phosphate glass (e.g., borophosphate silicate glass), etc.

[0027] The dielectric structure 106 surrounds the plurality of interconnect layers 108a-108c. The plurality of interconnect layers 108a-108c may include conductive contacts 108a, interconnect wiring 108b, and / or interconnect vias 108c. In various embodiments, the plurality of interconnect layers 108a-108c may include aluminum, copper, tungsten, and / or the like. In some embodiments, the plurality of interconnect layers 108a-108c may be coupled to a transistor device 104 disposed within the substrate 102. In various embodiments, the transistor device 104 may include a MOSFET (metal oxide semiconductor field effect transistor) device, a BJT (bipolar junction transistor) device, a HEMT (high electron mobility transistor) device, and the like.

[0028] The bonding pad 110 is disposed over the dielectric structure 106. The bonding pad 110 includes a conductive material such as aluminum, copper, and / or the like. In various embodiments, the bonding pad 110 may have a thickness of about 8,000 angstroms. and approximately Between, about and approximately Between, about and approximately , or other suitable values. In some embodiments, the glue layer 206 may be disposed between the bonding pad 110 and the top interconnect layer 108t disposed along the uppermost surface of the dielectric structure 106. The glue layer 206 is configured to act as a barrier layer between the bonding pad 110 and the dielectric structure 106. In some embodiments, the glue layer 206 may also improve the adhesion between the bonding pad 110 and the top interconnect layer 108t. In some embodiments, the glue layer 206 may include tantalum nitride, titanium nitride, etc.

[0029] The bonding pad 110 is laterally surrounded by one or more lower passivation layers 202-204. In some embodiments, the bonding pad 110 may include a horizontally extending surface disposed above the one or more lower passivation layers 202-204. In some such embodiments, the bonding pad 110 may include a central region having a first upper surface 110u1 and a peripheral region having a second upper surface 110u2 located above the first upper surface 110u1. In some embodiments, the one or more lower passivation layers 202-204 may include a first lower passivation layer 202 disposed on the dielectric structure 106 and a second lower passivation layer 204 disposed on the first lower passivation layer 202. In some embodiments, the first lower passivation layer 202 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc. In some embodiments, the second lower passivation layer 204 may include an oxide, an undoped silicate glass (USG), a borophosphosilicate glass (BPSG), etc. In some embodiments, the first lower passivation layer 202 may have a thickness of about 100 nm. and approximately Between, about and approximately In some embodiments, the second lower passivation layer 204 may have a thickness in the range of about and approximately Between, about and approximately The thickness is within the range between or other suitable values.

[0030] In some embodiments, one or more upper passivation layers 208-210 are disposed over the bonding pad 110. The one or more upper passivation layers 208-210 may include a first upper passivation layer 208 disposed on the second lower passivation layer 204 and a second upper passivation layer 210 disposed on the first upper passivation layer 208. The one or more upper passivation layers 208-210 have sidewalls defining the opening 113 directly above the bonding pad 110. In some embodiments, the first upper passivation layer 208 may include oxide, USG, BPSG, etc. In some embodiments, the first upper passivation layer 208 may have a thickness of about 100 nm. and approximately Between, about and approximately In some embodiments, the second upper passivation layer 210 may include a nitride (eg, silicon nitride), a carbide (eg, silicon carbide), etc. In some embodiments, the second upper passivation layer 210 may have a thickness in the range of about and approximately Between, about and approximately The thickness is within the range between or other suitable values.

[0031] The protection layer 114 is vertically disposed between the second upper surface 110u2 of the bonding pad 110 and the first upper passivation layer 208. In some embodiments, the protection layer 114 is completely confined above the bonding pad 110. Figure 2B A top view 222 is shown (along Figure 2A The protective layer 114 may extend continuously around the periphery of the bonding pad 110 in a complete path. In some embodiments, the protective layer 114 may include a ring shape.

[0032] In some embodiments, protective layer 114 is or includes a metal or a metal compound. For example, protective layer 114 may include titanium nitride, tantalum nitride, titanium oxide, etc. In some such embodiments, protective layer 114 may have one or more sidewalls that include a metal and further define opening 113. In some embodiments, protective layer 114 may have a thickness of about 100 mm. and approximately Between, about and approximately or other suitable values. The protective layer 114 can prevent the etching process used to form the opening 113 in the one or more upper passivation layers 208-210 from damaging the bonding pad 110. The thickness of the protective layer 114 can be quickly removed to expose the bonding pad 110 with little impact on the production yield.

[0033] The mask layer 212 is vertically disposed between the protective layer 114 and the first upper passivation layer 208. In some embodiments, the protective layer 114 has a bottom surface that contacts the bonding pad 110 and an upper surface that contacts the mask layer 212. In some embodiments, the mask layer 212 may include a nitride (e.g., silicon oxynitride), a carbide (e.g., silicon oxycarbide), etc. In some embodiments, the mask layer 212 may have a thickness of about and approximately Between, about and approximately The thickness is within the range between or other suitable values.

[0034] Protection layer 114 and mask layer 212 each include one or more sidewalls that further define opening 113. In some embodiments, protection layer 114 has sidewalls that are laterally set back from sidewalls of first upper passivation layer 208, second upper passivation layer 210, and / or mask layer 212 by a non-zero distance 214. In some embodiments, non-zero distance 214 may be approximately and approximately Between, about and approximately The lateral indentation of the sidewalls of the protection layer 114 causes the mask layer 212 to overhang the protection layer 114 and form a cavity 216 along one side of the opening 113. The cavity 216 is defined by the second upper surface 110u2 of the bonding pad 110, the sidewalls of the protection layer 114, and the lower surface of the mask layer 212.

[0035] The conductive bonding structure 116 is disposed over the bonding pad 110. In some embodiments, the conductive bonding structure 116 may include a conductive pillar 116a and a capping layer 116b over the conductive pillar 116a. In some embodiments, the conductive pillar 116a may include a copper pillar, a copper micro-pillar, etc. In some embodiments, the capping layer 116b may include one or more of tin, gold, etc. In some embodiments, the conductive pillar 116a may be disposed within the cavity 216. In some embodiments, the conductive pillar 116a may completely fill the cavity 216. In other embodiments, the conductive pillar 116a may not completely fill the cavity 216, thereby leaving a gap (not shown) between the sidewall of the conductive pillar 116a and the sidewall of the protective layer 114.

[0036] In various embodiments, the sidewalls of the protection layer (eg, Figure 2A The protective layer 114 may have different sidewall profiles. For example, in some embodiments, due to the etching process used to etch the protective layer, the sidewall of the protective layer may have a curved sidewall profile. FIG. 3A to FIG. 3B Cross-sectional views of some non-limiting embodiments of protective layer 114 having different sidewall profiles are shown.

[0037] like FIG. 3A to FIG. 3B As shown, protective layer 114 has a curved sidewall profile such that protective layer 114 has sidewalls with a concave curvature defining cavity 216. Mask layer 212 disposed on a top surface of protective layer 114 has sidewalls with a smaller curvature. For example, mask layer 212 may have substantially flat sidewalls.

[0038] In some embodiments, Figure 3A As shown in the cross-sectional view 300 of FIG. 1 , the protective layer 114 may have a curved sidewall 114s1 having a maximum slope curvature at a point vertically located between the top and bottom surfaces of the protective layer 114. In such an embodiment, the curved sidewall 114s1 gives the protective layer 114 a minimum width along a line vertically located between the top and bottom surfaces of the protective layer 114. In other embodiments, such as Figure 3BAs shown in the cross-sectional view 302 of FIG. 3 , the protective layer 114 may have a curved sidewall 114s2 having a maximum slope at a point along the top surface of the protective layer 114. In such an embodiment, the curved sidewall 114s2 may have a curvature that gives the protective layer 114 a minimum width along the top surface of the protective layer 114.

[0039] Figure 4 Cross-sectional views of some additional embodiments of an integrated chip 400 having a protection layer configured to improve the reliability of a bonding pad are shown.

[0040] The integrated chip 400 includes a dielectric structure 106 disposed above the substrate 102. A plurality of interconnection layers are disposed within the dielectric structure 106. In some embodiments, the plurality of interconnection layers may include a lower interconnection layer 402a and an upper interconnection layer 402b. In some embodiments, the lower interconnection layer 402a may be disposed within one or more lower interlayer dielectric (ILD) layers (e.g., low-k dielectric materials, ultra-low-k dielectric materials, etc.) having a first structural integrity. In some embodiments, the upper interconnection layer 402b may be disposed within one or more upper ILD layers having a second structural integrity greater than the first structural integrity. In some embodiments, in order to provide increased structural support below the bonding pad 110, the lower interconnection layer 402a may include a through hole disposed within a through hole array configured to provide structural support to the bonding pad 110. The through hole array 403 has a plurality of through holes disposed between vertically adjacent interconnection wirings, respectively. In some embodiments, the through hole array may not be disposed between vertically adjacent interconnection wirings of the upper interconnection layer 402b.

[0041] In some embodiments, the bonding pad 110 may have a lower sidewall 110s1 coupled to the upper sidewall 110s2 via a horizontally extending lower surface 110h. In some embodiments, the lower sidewall 110s1 is angled such that the width of the lower half of the bonding pad 110 decreases as the distance from the horizontally extending lower surface 110h increases. In some embodiments, the lower sidewall 110s1 is curved. In some embodiments, the upper sidewall 110s2 is angled such that the width of the upper half of the bonding pad 110 decreases as the distance from the horizontally extending lower surface 110h increases.

[0042] One or more upper passivation layers 208-210 are disposed over the bonding pad 110. In some embodiments, the one or more upper passivation layers 208-210 may have rounded outer sidewalls away from the conductive bonding structure 116 disposed over the bonding pad 110. In some embodiments, the one or more upper passivation layers 208-210 may have a greater thickness along the upper surface than along the sidewalls.

[0043] Figure 5Cross-sectional views of some additional embodiments of an integrated chip 500 having a protection layer configured to improve the reliability of a bonding pad are shown.

[0044] The integrated chip includes a bonding pad 110 disposed over a dielectric structure 106 surrounding a plurality of interconnect layers 108. A protective layer 114 is disposed over the bonding pad 110, and a mask layer 212 is disposed over the protective layer 114. Over the mask layer 212 is one or more upper passivation layers 208-210.

[0045] An under-bump metal (UBM) structure 502 is disposed above the bonding pad 110. In some embodiments, the UBM structure 502 includes a diffusion barrier layer and a seed layer. In some embodiments, the diffusion barrier layer may also be used as an adhesion layer (or glue layer). The diffusion barrier layer may include tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof. The seed layer includes a material configured to be capable of depositing metal pillars, solder bumps, and the like. In some embodiments, the UBM structure 502 may define a gap 504 disposed between the sidewalls of the protective layer 114 and the UBM structure 502. In other embodiments, the UBM structure 502 may directly contact the sidewalls of the protective layer 114. A conductive bonding structure 116 (e.g., a solder bump, a copper pillar, a copper micro-pillar, etc.) may be disposed above the UBM structure 502.

[0046] Figures 6 to 16 Cross-sectional views 600-1600 of some embodiments of a method of forming an integrated chip structure having a protective layer configured to improve the reliability of a bonding pad are shown. Figures 6 to 16 , but it should be understood that Figures 6 to 16 The structure disclosed in is not limited to this method, but can exist independently as a structure independent of the method.

[0047] like Figure 6 As shown in the cross-sectional view 600 of , one or more transistor devices 104 are formed in the substrate 102. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer and any other type of semiconductor and / or epitaxial layer associated therewith. In some embodiments, the one or more transistor devices 104 may include a transistor formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric 104a and a gate electrode 104b. The substrate 102 can then be implanted to form a source region 104c and a drain region 104d in the substrate 102 on opposite sides of the gate electrode 104b.

[0048] After forming one or more transistor devices 104, a plurality of interconnect layers 108 are formed within the dielectric structure 106 above the substrate 102. In some embodiments, the dielectric structure 106 may include a plurality of ILD layers. In some embodiments, the plurality of interconnect layers 108 may include conductive contacts 108a, interconnect wirings 108b, and interconnect vias 108c. In some embodiments, the plurality of interconnect layers 108 may be formed by forming one of the plurality of ILD layers, selectively etching the ILD layer to define via holes and / or trenches within the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via holes and / or trenches to fill the openings, and performing a planarization process (e.g., a chemical mechanical planarization process).

[0049] like Figure 7 As shown in cross-sectional view 700 of FIG. 1 , one or more lower passivation layers 202-204 may be formed over the dielectric structure 106. In some embodiments, forming the one or more lower passivation layers 202-204 may include forming a first lower passivation layer 202 over the dielectric structure 106 and subsequently forming a second lower passivation layer 204 over the first lower passivation layer 202. In some embodiments, the first lower passivation layer 202 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc. In some embodiments, the first lower passivation layer 202 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, etc.) to be approximately and approximately Between, about and approximately In some embodiments, the second lower passivation layer 204 may include oxide, silicate glass (e.g., BSG, PSG, etc.). In some embodiments, the second lower passivation layer 204 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, etc.) to have a thickness of about and approximately Between, about and approximately The thickness is within the range between or other suitable values.

[0050] like Figure 8As shown in the cross-sectional view 800 of , one or more lower passivation layers 202-204 are selectively patterned according to a first etching process to form a bonding pad opening 802 extending through the one or more lower passivation layers 202-204. In some embodiments, the bonding pad opening 802 exposes the top interconnect layer 108t in the plurality of interconnect layers 108. In some embodiments, the one or more lower passivation layers 202-204 can be selectively patterned according to a first mask layer 806 by exposing the one or more lower passivation layers 202-204 to a first etchant 804. In some embodiments, the first etchant 804 can include a dry etchant having an etching chemistry including fluorine, chlorine, etc. In some embodiments, the first mask layer 806 can include a photosensitive material (e.g., a photoresist), a hard mask, etc.

[0051] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 8 , a glue material 902 is formed within the bonding pad opening 802 and on the upper surface of the second lower passivation layer 204. In some embodiments, the glue material 902 may include tantalum nitride, titanium nitride, etc. In some embodiments, the glue material 902 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, etc.) and between and The thickness is within the range between or other suitable values.

[0052] A bonding pad layer 904 is formed within the bonding pad opening 802 and over the glue material 902. In some embodiments, the bonding pad layer 904 may include aluminum, copper, etc. In some embodiments, the bonding pad layer 904 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, etc.), a plating process, etc. In various embodiments, the bonding pad layer 904 may be formed to be approximately and approximately Between, about and approximately The thickness is within the range between or other suitable values.

[0053] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a protective layer 114 is formed over the bonding pad layer 904. In some embodiments, the protective layer 114 is or includes a metal or a metal compound. For example, the protective layer 114 may include a metal such as titanium (e.g., titanium nitride, titanium oxide, etc.), tantalum (e.g., tantalum nitride), etc. In some embodiments, the protective layer 114 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, etc.) to be approximately and approximately Between, about and approximately The thickness is within the range between or other suitable values.

[0054] Because the bonding pad layer 904 is formed within the bonding pad opening 802 in the one or more lower passivation layers 202-204, the bonding pad layer 904 has a first upper surface 904u1 and a second upper surface 904u2 above the first upper surface 904u1. In some embodiments, the first upper surface 904u1 of the bonding pad 110 may have a width 906 greater than or equal to about 2 microns. Having a width 906 greater than or equal to about 2 microns may prevent shadows from a deposition process used to form the protective layer 114 from affecting the thickness of the protective layer 114. For example, if the width 906 is less than about 2 microns, a deposition process with a slight angle may result in unevenness of the protective layer 114 that may subsequently block the opening of the bonding pad.

[0055] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a mask layer 212 is formed over the protective layer 114. In some embodiments, the mask layer 212 may include oxynitride (e.g., silicon oxynitride), oxycarbon (e.g., silicon carbonitride), etc. In some embodiments, the mask layer 212 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, etc.) to have a thickness of about 100 mm. and approximately Between, about and approximately The thickness is within the range or suitable value.

[0056] like Fig.12 As shown in the cross-sectional view 1200, the bonding pad layer ( Fig.11 904), adhesive material ( Fig.11 902), the protective layer 114 and the mask layer 212. The second etching process limits the protective layer 114 and the mask layer 212 above the bonding pad 110. In some embodiments, according to the second mask layer 1204, the bonding pad layer ( Fig.11 904), adhesive material ( Fig.11 902), the protective layer 114 and the mask layer 212 are exposed to the second etchant 1202 to selectively pattern the bonding pad layer ( Fig.11 904), adhesive material ( Fig.11 902), the protective layer 114 and the mask layer 212. In some embodiments, the second etchant 1202 may include a dry etchant having an etching chemistry including fluorine, chlorine, etc. In some embodiments, the second mask layer 1204 may include a photosensitive material (e.g., a photoresist), a hard mask, etc.

[0057] like Fig.13As shown in the cross-sectional view 1300 of FIG. 1 , one or more upper passivation layers 208-210 are formed over the mask layer 212. The one or more upper passivation layers 208-210 may include a first upper passivation layer 208 and a second upper passivation layer 210. In some embodiments, the first upper passivation layer 208 may include oxide, USG, BPSG, etc. In some embodiments, the first upper passivation layer 208 may be formed to be approximately and approximately Between, about and approximately In some embodiments, the second upper passivation layer 210 may include a nitride (eg, silicon nitride), a carbide (eg, silicon carbide), etc. In some embodiments, the second upper passivation layer 210 may be formed to have a thickness of about and approximately Between, about and approximately The thickness is within the range between or other suitable values.

[0058] like Fig.14 As shown in the cross-sectional view 1400 of , one or more upper passivation layers 208-210 and mask layer 212 are selectively patterned to form an initial opening 1402 extending through the one or more upper passivation layers 208-210 and mask layer 212. In some embodiments, the initial opening 1402 exposes the upper surface of the protective layer 114. In some embodiments, according to the third mask layer 1406, by exposing the one or more upper passivation layers 208-210 and mask layer 212 to a third etchant 1404, the one or more upper passivation layers 208-210 and mask layer 212 can be selectively patterned. In some embodiments, the third etchant 1404 may include a dry etchant having an etching chemistry including fluorine, chlorine, etc. In some embodiments, the third mask layer 1406 may include a photosensitive material (e.g., a photoresist), a hard mask, etc.

[0059] In some embodiments, the third etchant 1404 may react with the protective layer 114 to form metal byproducts 1408 along the upper surface and / or sidewalls of the protective layer 114 and / or along the sidewalls of one or more upper passivation layers 208-210. In some embodiments, the metal byproducts 1408 may include fluorine. For example, in some embodiments, the metal byproducts 1408 may include titanium fluoride (TiF x ).

[0060] like Fig.15As shown in the cross-sectional view 1500 of FIG. 1 , a wet etching process is performed to remove a portion of the protective layer 114 and to define an opening 113 exposing the upper surface of the bonding pad 110. In some embodiments, the wet etching process can be performed by exposing the protective layer 114 to a wet etchant. In some embodiments, the wet etchant 1502 can include hydrogen peroxide (H2O2). In other embodiments, the wet etchant 1502 can include potassium hydroxide (KOH), hydrofluoric acid (HF), etc. In some embodiments, the wet etchant can be used to remove the metal byproducts ( Fig.14 1408) and removes metal byproducts ( Fig.14 1408).

[0061] The wet etchant 1502 has a high etch selectivity relative to the one or more upper passivation layers 208-210 and the mask layer 212. The high etch selectivity enables the wet etchant 1502 to etch the protective layer 114 faster than the one or more upper passivation layers 208-210 and the mask layer 212. For example, in some embodiments, the etch ratio of the protective layer 114 to the first upper passivation layer 208, the second upper passivation layer 210, and / or the mask layer 212 can be in a range between 10:1 and 100:1, in a range between 50:1 and 100:1, in a range between 100:1 and 1,000:1, or other ranges. In other embodiments, the etch ratio of the protective layer 114 to the first upper passivation layer 208, the second upper passivation layer 210, and / or the mask layer 212 can be greater than about 10:1, greater than about 100:1, or greater than about 1,000:1.

[0062] In some embodiments, wet etchant 1502 may vertically and laterally etch protective layer 114. In some such embodiments, after the wet etching process is completed, mask layer 212 may overhang the sidewalls of protective layer 114 and the space between the sidewalls of mask layer 212. The resulting mask layer 212 extends laterally beyond the sidewalls of protective layer 114 to form a cavity 216 defined by the sidewalls of protective layer 114 and the lower surface of mask layer 212. In some embodiments, protective layer 114 may be laterally recessed a non-zero distance 214 from the sidewalls of first upper passivation layer 208, second upper passivation layer 210, and / or mask layer 212. In some embodiments, non-zero distance 214 may be approximately and approximately Between, about and approximately or other suitable values.

[0063] In some embodiments, wet etchant 1502 may also have a high etch selectivity relative to bonding pad 110. The high etch selectivity allows the wet etchant to etch protective layer 114 faster than bonding pad 110. In some embodiments, wet etchant 1502 may be etched at a rate of about and approximately The protective layer 114 is etched at a first etching rate in a range between 0.004 and 0.010 ... The bonding pad 110 is etched at an etching rate of about 1:1. In some embodiments, the etching ratio of the protective layer 114 to the bonding pad 110 may be greater than about 10:1, greater than about 100:1, or greater than about 1000:1. The low etching rate of the bonding pad 110 enables the bonding pad 110 to have a substantially smooth upper surface (e.g., the upper surface is smoother than a surface obtained by a dry etching process).

[0064] In some embodiments, after the wet etching process is completed, an annealing process may be performed. The annealing process may remove moisture from the bonding pad 110, the protective layer 114, the mask layer 212, and / or one or more upper passivation layers 208-210 to prevent degradation (e.g., oxidation) of the bonding pad 110. The annealing process may further and / or optionally release stress of the metal within the bonding pad 110. In some embodiments, the annealing process may be performed by exposing the substrate 102 to a temperature in the range of between about 100°C and about 750°C, between about 200°C and about 500°C, between about 250°C and about 300°C, or in other suitable ranges.

[0065] like Fig.16 As shown in cross-sectional view 1600 of FIG. 16 , a conductive bonding structure 116 is formed within the opening 113 defined by one or more upper passivation layers 208 - 210 . In some embodiments, the conductive bonding structure 116 may include a conductive bump (eg, a solder bump).

[0066] Fig.17 A flow chart illustrating some embodiments of a method 1700 of forming an integrated chip structure having a protection layer configured to improve reliability of a bond pad.

[0067] Although method 1700 disclosed herein is shown and described as a series of steps or events, it should be understood that the order of showing such steps or events should not be interpreted as limiting. For example, in addition to those steps or events shown and / or described herein, some steps may occur in different orders and / or occur simultaneously with other steps or events. In addition, all the steps shown may not be required to realize one or more aspects or embodiments of the description of this article. In addition, one or more steps described herein may be performed in one or more separate steps and / or stages.

[0068] At 1702, a plurality of interconnect layers are formed within a dielectric structure over a substrate. Figure 6 A cross-sectional view 600 corresponding to some embodiments of step 1702 is shown.

[0069] At 1704, one or more lower passivation layers are formed over the dielectric structure. Figure 7 A cross-sectional view 700 corresponding to some embodiments of step 1704 is shown.

[0070] At 1706 , one or more lower passivation layers are patterned to form bond pad openings. Figure 8 A cross-sectional view 800 corresponding to some embodiments of step 1706 is shown.

[0071] At 1708 , a bond pad layer is formed within the bond pad opening and over the one or more underlying passivation layers. Fig. 9 A cross-sectional view 900 corresponding to some embodiments of step 1708 is shown.

[0072] At 1710 , a protective layer is formed over the bond pad layer. Fig.10 A cross-sectional view 1000 corresponding to some embodiments of step 1710 is shown.

[0073] At 1712, a mask layer is formed over the protective layer. Fig.11 A cross-sectional view 1100 corresponding to some embodiments of step 1712 is shown.

[0074] At 1714 , the mask layer, the protective layer, and the bond pad layer are patterned to define bond pads covered by the protective layer. Fig.12 A cross-sectional view 1200 corresponding to some embodiments of step 1714 is shown.

[0075] At 1716 , one or more upper passivation layers are formed over the bond pads. Fig.13 A cross-sectional view 1300 corresponding to some embodiments of step 1716 is shown.

[0076] At 1718, an etching process is performed to remove a portion of the one or more upper passivation layers and to form an initial opening exposing the protective layer. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of step 1718 is shown.

[0077] At 1720 , a wet etching process is performed to remove a portion of the protective layer and to form an opening exposing an upper surface of the bonding pad. Fig.15 A cross-sectional view 1500 corresponding to some embodiments of step 1720 is shown.

[0078] In 1722, an annealing process is performed. Fig.15A cross-sectional view 1500 corresponding to some embodiments of step 1722 is shown.

[0079] At 1724 , a conductive structure (eg, a conductive bump) is formed on the bond pad. Fig.16 A cross-sectional view 1600 corresponding to some embodiments of step 1724 is shown.

[0080] Thus, in some embodiments, the present invention relates to a bonding pad structure of an integrated chip having a protection layer disposed on a conductive bonding pad and configured to mitigate the formation of etching byproducts (eg, fluorine metal byproducts) on the conductive bonding pad.

[0081] In some embodiments, the present invention relates to a method for forming an integrated chip. The method includes: forming a bonding pad layer on a dielectric structure formed above a substrate, the dielectric structure surrounding a plurality of interconnect layers; forming a protective layer on the bonding pad layer; patterning the bonding pad layer and the protective layer to define a bonding pad covered by the protective layer; forming one or more upper passivation layers above the protective layer; performing a dry etching process to form an opening extending through one or more upper passivation layers to the protective layer; and performing a wet etching process to remove a portion of the protective layer and expose the upper surface of the bonding pad. In some embodiments, the dry etching process uses a dry etchant having an etching chemical including fluorine. In some embodiments, the wet etching process laterally etches the protective layer so that the protective layer is laterally recessed beyond the sidewalls of the one or more upper passivation layers. In some embodiments, the method further includes: before patterning the bonding pad layer and the protective layer, forming a mask layer above the protective layer; forming a first mask layer above the mask layer; and etching the mask layer, the protective layer, and the bonding pad layer according to the first mask layer. In some embodiments, after completing the wet etching process, the mask layer is suspended above the space between the sidewalls of the protective layer and the sidewalls of the mask layer. In some embodiments, the dry etching process forms metal byproducts on one or more sidewalls of the one or more upper passivation layers; and the wet etching process removes the metal byproducts from the one or more sidewalls of the one or more upper passivation layers. In some embodiments, the wet etching process forms sidewalls of the protective layer that further define the opening above the bonding pad. In some embodiments, the protective layer includes titanium nitride. In some embodiments, the dry etching process forms metal byproducts along the top of the protective layer, and the metal byproducts include fluorine and titanium.

[0082] In other embodiments, the present invention relates to a method for forming an integrated chip. The method includes: forming a bonding pad layer above a substrate; forming a protective layer on the bonding pad layer; patterning the bonding pad layer and the protective layer to define a bonding pad covered by the protective layer; forming one or more upper passivation layers above the protective layer; etching one or more upper passivation layers to expose the upper surface of the protective layer; performing a wet etching process to remove a portion of the protective layer from the upper surface of the bonding pad; and after performing the wet etching process, forming a conductive bump above the bonding pad. In some embodiments, the wet etching process is configured to etch the protective layer at a faster rate than the one or more upper passivation layers and the bonding pad. In some embodiments, the one or more upper passivation layers laterally contact the sidewalls of the protective layer. In some embodiments, the method further includes: before forming the one or more upper passivation layers, forming a mask layer above the protective layer. In some embodiments, the protective layer includes a metal.

[0083] In yet other embodiments, the present invention relates to an integrated chip. The integrated chip includes: a plurality of interconnect layers disposed in a dielectric structure above a substrate; a bonding pad disposed above the dielectric structure; one or more upper passivation layers disposed above the dielectric structure and the bonding pad, wherein the one or more upper passivation layers include one or more sidewalls defining an opening directly above the bonding pad; and a protective layer including a metal disposed directly between the one or more upper passivation layers and the bonding pad, the metal having one or more sidewalls further defining the opening. In some embodiments, the one or more upper passivation layers include a lower surface facing the bonding pad and extending over one or more sidewalls of the metal. In some embodiments, the one or more upper passivation layers include: a first upper passivation layer disposed along the sidewall of the bonding pad and directly above the upper surface of the bonding pad; and a second upper passivation layer disposed above the first upper passivation layer, the first upper passivation layer and the second upper passivation layer continuously and laterally extending over the opposite sidewalls of the protective layer. In some embodiments, the protective layer includes titanium nitride. In some embodiments, the integrated chip further comprises: a mask layer disposed above the protection layer and below one or more upper passivation layers, the mask layer laterally extending over one or more sidewalls of the protection layer. In some embodiments, the protection layer has a bottom surface contacting the bonding pad and an upper surface contacting the mask layer.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming an integrated chip, comprising: forming a bonding pad layer on a dielectric structure formed over a substrate, wherein the dielectric structure surrounds a plurality of interconnect layers; forming a protective layer on the bonding pad layer; patterning the bond pad layer and the protective layer to define a bond pad covered by the protective layer; forming one or more upper passivation layers over the protective layer; performing a dry etching process to form an opening extending through the one or more upper passivation layers to the protective layer; and A wet etching process is performed to remove a portion of the protection layer and expose an upper surface of the bond pad, wherein the wet etching process laterally etches the protection layer such that the protection layer is laterally recessed beyond sidewalls of the one or more upper passivation layers.

2. The method according to claim 1, wherein: The dry etching process uses a dry etchant having an etching chemistry including fluorine.

3. The method according to claim 1, wherein: The wet etchant of the wet etching process includes hydrogen peroxide.

4. The method according to claim 1, further comprising: before patterning the bonding pad layer and the protective layer, forming a mask layer over the protective layer; forming a first mask layer over the mask layer; as well as According to the first mask layer, the mask layer, the protection layer, and the bonding pad layer are etched.

5. The method according to claim 4, wherein: After the wet etching process is completed, the mask layer overhangs a space between a sidewall of the protection layer and a sidewall of the mask layer.

6. The method according to claim 1, in, The dry etching process forms metal byproducts on one or more sidewalls of the one or more upper passivation layers; and Wherein, the wet etching process removes the metal byproducts from the one or more sidewalls of the one or more upper passivation layers.

7. The method according to claim 1, wherein: The wet etching process forms sidewalls of the protection layer that further define the opening over the bond pad.

8. The method according to claim 1, wherein: The protective layer includes titanium nitride.

9. The method according to claim 1, wherein: The dry etching process forms metal byproducts along a top portion of the protective layer, the metal byproducts including fluorine and titanium.

10. A method for forming an integrated chip, comprising: forming a bonding pad layer over the substrate; forming a protective layer on the bonding pad layer; forming a mask layer over the protective layer; patterning the bond pad layer, the protective layer, and the mask layer to define a bond pad covered by the protective layer; forming one or more upper passivation layers over the protective layer; etching the one or more upper passivation layers and the mask layer to expose an upper surface of the protective layer; performing a wet etching process to remove a portion of the protective layer from an upper surface of the bonding pad, wherein the mask layer extends laterally beyond a sidewall of the protective layer; as well as After performing the wet etching process, a conductive bump is formed over the bonding pad.

11. The method according to claim 10, wherein: The wet etching process is configured to etch the protective layer at a faster rate than the one or more upper passivation layers and the bond pad.

12. The method according to claim 10, wherein: The one or more upper passivation layers laterally contact sidewalls of the protection layer.

13. The method according to claim 10, wherein: The mask layer includes silicon oxynitride.

14. The method according to claim 10, wherein: The protection layer includes metal.

15. An integrated chip, comprising: a plurality of interconnect layers disposed within the dielectric structure over the substrate; a bonding pad disposed over the dielectric structure; one or more upper passivation layers disposed over the dielectric structure and the bonding pad, wherein the one or more upper passivation layers include one or more sidewalls defining an opening directly over the bonding pad; a protective layer comprising a metal disposed directly between the one or more upper passivation layers and the bond pad, the metal having one or more sidewalls further defining the opening; and A mask layer is disposed over the protective layer and below the one or more upper passivation layers, wherein the mask layer extends laterally beyond the one or more sidewalls of the protective layer.

16. The integrated chip according to claim 15, wherein: The one or more upper passivation layers include a lower surface facing the bond pad and extending over one or more sidewalls of the metal.

17. The integrated chip according to claim 15, wherein: The one or more upper passivation layers include: a first upper passivation layer disposed along the sidewalls of the bonding pad and directly above the upper surface of the bonding pad; and A second upper passivation layer is disposed above the first upper passivation layer, wherein the first upper passivation layer and the second upper passivation layer continuously and laterally extend across opposite sidewalls of the protection layer.

18. The integrated chip according to claim 15, wherein: The protective layer includes titanium nitride.

19. The integrated chip according to claim 15, wherein: The mask layer includes silicon oxynitride.

20. The integrated chip according to claim 19, wherein: The protection layer has a bottom surface contacting the bonding pad and an upper surface contacting the mask layer.

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