Snapback electrostatic discharge (ESD) circuit, ESD protection circuit and manufacturing method thereof

Abstract

A snapback electrostatic discharge (ESD) protection circuit includes: a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well and has a second dopant type different from the first dopant type. The source region is in the first well, has a second dopant type, and is separated from the drain region in a first direction. The gate region is above the first well and the substrate. The second well is embedded in the first well and is adjacent to a portion of the drain region. The second well has a second dopant type. Embodiments of the present invention also relate to an ESD protection circuit and a method for manufacturing a snapback ESD protection circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to a snapback electrostatic discharge (ESD) circuit, an ESD protection circuit, and a method of manufacturing the same. Background Art

[0002] The recent trend of integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide higher speeds than before. The miniaturization process has also increased the device's susceptibility to electrostatic discharge (ESD) events due to various factors, such as thinner dielectric layer thickness and the associated reduced dielectric breakdown voltage. ESD is one of the causes of damage to electronic circuits and a consideration in semiconductor advanced technology. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a snapback electrostatic discharge (ESD) protection circuit is provided, comprising: a first well, located in a substrate, the first well having a first dopant type; a drain region of a transistor, the drain region being in the first well and having a second dopant type different from the first dopant type; a source region of the transistor, the source region being in the first well, having a second dopant type and being separated from the drain region in a first direction; a gate region of the transistor, the gate region being above the first well and the substrate; and a second well, embedded in the first well and adjacent to a portion of the drain region, and the second well having a second dopant type.

[0004] According to another aspect of an embodiment of the present invention, an electrostatic discharge (ESD) protection circuit is provided, including: a first well, located in a substrate, the first well having a first dopant type; a drain region of a first transistor, the drain region being located in the first well and having a second dopant type different from the first dopant type; a source region of the first transistor, the source region being in the first well, having a second dopant type, and being separated from the drain region in a first direction; a gate region of the first transistor, the gate region being above the first well and the substrate; a second well embedded in the first well and adjacent to a portion of the source region, and the second well having a second dopant type; and a tap well, located in the first well and having the first dopant type, and coupled to the source region.

[0005] According to another aspect of an embodiment of the present invention, a method for manufacturing a snapback ESD protection circuit is provided, the method comprising: manufacturing a first well in a substrate, the first well extending in a first direction and having a first dopant type; manufacturing a drain region of a transistor in the first well, the drain region extending in the first direction and having a second dopant type different from the first dopant type; manufacturing a source region of the transistor in the first well, the source region extending in the first direction, having a second dopant type, and being separated from the drain region in a second direction different from the first direction; manufacturing a second well in the first well, the second well extending in the first direction, having the second dopant type, and being adjacent to a portion of the drain region, and manufacturing a gate region of the transistor, the gate region being between the drain region and the source region and above the first well and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a schematic block diagram of an integrated circuit according to some embodiments.

[0008] Figure 1B is a circuit diagram of an equivalent circuit of a portion of an integrated circuit according to some embodiments.

[0009] Figure 2A is a cross-sectional view of an integrated circuit according to some embodiments.

[0010] Figure 2B is a cross-sectional view of an equivalent circuit of an integrated circuit according to some embodiments.

[0011] Figure 2C are waveform diagrams of some embodiments compared with other methods.

[0012] Figure 3A is a block diagram of a snapback device array having a plurality of snapback device cells according to some embodiments.

[0013] Figure 3B is a diagram of a layout design according to some embodiments.

[0014] Figure 4A is a schematic block diagram of an integrated circuit according to some embodiments.

[0015] Figure 4B is a diagram of a layout design according to some embodiments.

[0016] Figure 5Ais a cross-sectional view of an integrated circuit according to some embodiments.

[0017] Figure 5B is a cross-sectional view of an equivalent circuit of an integrated circuit according to some embodiments.

[0018] Figure 5C is a diagram of a layout design according to some embodiments.

[0019] Fig. 6A is a cross-sectional view of an integrated circuit according to some embodiments.

[0020] Figure 6B is a cross-sectional view of an equivalent circuit of an integrated circuit according to some embodiments.

[0021] Figure 6C is a diagram of a layout design according to some embodiments.

[0022] Figure 7A-7C is a corresponding diagram of a corresponding layout design according to some embodiments.

[0023] Figure 8A-8C is a corresponding diagram of a corresponding layout design according to some embodiments.

[0024] Fig. 9 is a flow chart of a method of forming or manufacturing an ESD circuit according to some embodiments.

[0025] Fig. 10A is a functional flow diagram of at least a portion of an integrated circuit design and fabrication flow according to some embodiments.

[0026] Fig. 10B is a functional flow chart of a method of manufacturing an integrated circuit device according to some embodiments.

[0027] Fig.11 is a flow chart of a method of operating a circuit according to some embodiments.

[0028] Fig.12 is a schematic diagram of a system for designing an IC layout and fabricating IC circuits according to some embodiments.

[0029] Fig.13 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0031] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0032] A parameter to be considered in an ESD protection device is the ESD threshold voltage or trigger voltage at which the ESD protection device is turned on, i.e., becomes conductive, to release the voltage and / or current of a high and harmful ESD event away from the circuit to be protected. A high ESD trigger voltage may be harmful to the circuit to be protected, and / or may cause the ESD protection device itself to turn on unevenly and / or fail prematurely. In some embodiments, in order to reduce the ESD threshold voltage or trigger voltage, an additional N-well is added to the P-well of the ESD protection device, thereby increasing the base resistance of the parasitic bipolar junction transistor (BJT) of the ESD protection device.

[0033] In some embodiments, during an ESD event, increasing the base resistance of the parasitic BJT reduces the ESD threshold voltage of the parasitic BJT, thereby causing the parasitic BJT to turn on earlier at a lower ESD trigger voltage, and the ESD voltage can be discharged faster than other methods. In other words, the ESD trigger voltage is reduced, thereby improving ESD performance. Compared with other methods, at least one or more embodiments advantageously provide a layout design or layout solution for reducing the ESD trigger voltage of a snapback device without performing an additional manufacturing process, and having improved ESD performance.

[0034] Figure 1A is a schematic block diagram of an integrated circuit 100A according to some embodiments.

[0035] Integrated circuit 100A includes internal circuit 102, voltage supply terminal 104, reference voltage supply terminal 106, input / output (IO) pad 108, ESD clamp 110, and snapback device 120. In some embodiments, at least integrated circuits 100A, 100B ( Figure 1B ) or 400A( Figure 4A ) are incorporated into a single integrated circuit (IC) or a single semiconductor substrate. In some embodiments, at least the integrated circuit 100A, 100B, or 400A includes one or more ICs incorporated into one or more single semiconductor substrates.

[0036] The internal circuit 102 is coupled to a voltage supply terminal 104 (e.g., VDD), a reference voltage supply terminal 106 (e.g., VSS), and an IO pad 108. The internal circuit 102 is configured to receive a power supply voltage VDD (e.g., VDD) from the voltage supply terminal 104, a reference voltage VSS from the reference voltage supply terminal 106 (e.g., VSS), and an IO signal from the IO pad 108.

[0037] The internal circuit 102 includes a circuit configured to generate or process an IO signal received by or output to the IO pad 108. In some embodiments, the internal circuit 102 includes a core circuit configured to operate at a voltage lower than the power supply voltage VDD of the voltage source terminal 104. In some embodiments, the internal circuit 102 includes at least one n-type or p-type transistor device. In some embodiments, the internal circuit 102 includes at least a logic gate unit. In some embodiments, the logic gate unit includes AND, OR, NAND, NOR, XOR, INV, AOI, OAI, MUX, flip-flop, buffer, latch, delay or clock unit. In some embodiments, the internal circuit 102 includes at least a memory unit. In some embodiments, the memory unit includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM) or a read-only memory (ROM). In some embodiments, the internal circuit 102 includes one or more active or passive elements. Examples of active components include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.), FinFETs, and planar MOS transistors with increased source / drain voltages. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0038] The voltage supply terminal 104 is configured to receive a power supply voltage VDD for normal operation of the internal circuit 102. Similarly, the reference voltage supply terminal 106 is configured to receive a reference power supply voltage VSS for normal operation of the internal circuit 102. In some embodiments, at least the power supply terminal 104 is a voltage source pad. In some embodiments, at least the reference voltage source terminal 106 is a reference voltage source pad. In some embodiments, the pad is at least a conductive surface, pin, node, or bus. The voltage supply terminal 104 or the reference voltage source terminal 106 is also referred to as a power supply voltage bus or a power supply voltage rail. Figure 1A-1B and Figure 4A In the example configuration of , the power supply voltage VDD is a positive power supply voltage, the voltage supply terminal 104 is a positive power supply voltage, the reference power supply voltage VSS is a ground power supply voltage, and the reference voltage supply terminal 106 is a ground voltage terminal. Other power supply arrangements are within the scope of the present disclosure.

[0039] IO pad 108 is coupled to internal circuit 102. IO pad 108 is configured to receive IO signals from internal circuit 102, or is configured to output IO signals to internal circuit 102. IO pad 108 is at least one pin coupled to internal circuit 102. In some embodiments, IO pad 108 is a node, a bus, or a conductive surface coupled to internal circuit 102.

[0040] The ESD clamp 110 is coupled between the voltage source terminal 104 (e.g., power supply voltage VDD) and the reference voltage source terminal 106 (e.g., VSS). If an ESD event occurs, the ESD clamp 110 is configured to provide a shunt path between the voltage source terminal 104 (e.g., power supply voltage VDD) and the reference voltage source terminal 106 (e.g., VSS). When no ESD event occurs, the ESD clamp 110 should be turned off. For example, when no ESD event occurs, the ESD clamp 110 is turned off and is therefore a non-conductive device or circuit during normal operation of the internal circuit 102. When an ESD event occurs, the ESD clamp 110 should be turned on to release the ESD current. For example, when an ESD event occurs, the voltage difference across the ESD clamp 110 is equal to or greater than the threshold voltage of the ESD clamp 110, and the ESD clamp 110 is turned on, thereby conducting current between the voltage source terminal 104 (e.g., VDD) and the reference voltage source terminal 106 (e.g., VSS).

[0041] In some embodiments, the ESD clamp 110 includes a large NMOS transistor configured to carry the ESD current without entering the avalanche breakdown region of the ESD clamp 110. In some embodiments, the ESD clamp 110 is implemented without an avalanche junction inside the ESD clamp 110, also referred to as a "snapback-free protection scheme."

[0042] The snapback device 120 is coupled between the IO pad 108 and the reference voltage source terminal 106. The snapback device 120 is configured to have minimal impact on the normal behavior of the internal circuit 102 or the integrated circuit 100A-100B or 400A (e.g., in the absence of an ESD condition). In other words, the snapback device 120 is turned off or non-conducting in the absence of an ESD event. During normal operation of the internal circuit 102 applied to the IO pad 108, an ESD event occurs when an ESD voltage or current is higher than the expected voltage or current level. In the absence of the snapback device 120, such an ESD event can cause excessive and potential damage to the internal circuit 102 and / or the driver circuit 440 ( Figure 4A) voltage or current in the snapback device 120. Under ESD conditions, the snapback device 120 is configured to be turned on and exhibit snapback. In other words, under ESD conditions, the snapback device 120 is configured to be turned on and operate in the avalanche breakdown region of the snapback device 120, thereby carrying the high current ESD current that will be discharged through the snapback device 120 rather than through the internal circuit 102.

[0043] In some embodiments, the snapback device 120 is configured to be turned on or operated in a positive-VSS (PS) mode when an ESD stress or event occurs. For example, in the PS mode, a positive ESD stress or ESD voltage (at least greater than the reference power supply voltage VSS) is applied to the IO pad 108, while the voltage source terminal 104 (e.g., VDD) is floating and the reference voltage source terminal 106 (e.g., VSS) is grounded. At least in this example, when the ESD voltage is greater than the ESD trigger voltage Vth or the threshold voltage of the snapback device 120, the snapback device 120 is turned on and the ESD voltage on the IO pad 108 is discharged to the reference voltage source terminal 106 (e.g., VSS) through the turned-on snapback device 120, as shown in FIG. Figure 1A As shown by the arrow in “PS mode”.

[0044] In some embodiments, snapback device 120 is disabled or configured to be turned off or inoperative when a negative-VSS (NS) mode of ESD stress or event occurs. In some embodiments, snapback device 120 is turned off or inoperative when a NS mode of ESD stress or event occurs. In NS mode, IO pad 108 receives negative ESD stress while voltage source terminal 104 (e.g., VDD) floats and reference voltage source terminal 106 (e.g., VSS) is grounded.

[0045] In some embodiments, the snapback device 120 includes, but is not limited to, a snapback device having a parasitic NPN BJT, a snapback MOS device, a field oxide device (FOD), a silicon controlled rectifier (SCR), and the like.

[0046] In some embodiments, integrated circuit 100A further includes an additional snapback device (not shown) similar to snapback device 120, but coupled between IO pad 108 and voltage supply terminal 104. In some embodiments, the cross-sectional view of the additional snapback device (not shown) is similar to integrated circuits 200A-200B ( Figure 2A-2B ).

[0047] In some embodiments, the additional snapback device is configured to be turned on or operated in a positive-VDD (PD) mode when an ESD stress or event occurs. For example, in PD mode, a positive ESD stress or ESD voltage (at least greater than the power supply voltage VDD) is applied to the IO pad 108, while the voltage source terminal 104 (e.g., VDD) is grounded and the reference voltage source terminal 106 (e.g., VSS) is floating. At least in this example, when the ESD voltage is greater than the ESD trigger voltage Vth or threshold voltage of the additional snapback device, the additional snapback device is turned on and the ESD voltage on the IO pad 108 is released to the voltage source terminal 104 (e.g., VDD) by the turned-on additional snapback device.

[0048] In some embodiments, when a negative-VDD (ND) mode of ESD stress or ESD event occurs, the additional snapback device is disabled or configured to be turned off or not operate. In some embodiments, when a ND mode of ESD stress or ESD event occurs, the additional snapback device is turned off or not operate. In ND mode, IO pad 108 receives negative ESD stress, while voltage source terminal 104 (e.g., VDD) is grounded and reference voltage source terminal 106 (e.g., VSS) is floating.

[0049] In some embodiments, the additional snapback devices include, but are not limited to, snapback devices with parasitic NPN BJTs, snapback MOS devices, field oxide devices (FODs), silicon controlled rectifiers (SCRs), and the like.

[0050] Figure 1B is a circuit diagram of an equivalent circuit 100B of a portion of the integrated circuit 100A according to some embodiments.

[0051] The equivalent circuit 100B is a variation of the integrated circuit 100A and shows the parasitic transistor 140 of the snapback device 120, so similar detailed description is omitted. For example, according to some embodiments, the equivalent circuit 100B corresponds to Figure 1A The snapback device 120 has a parasitic element (eg, a parasitic transistor 140).

[0052] To Figure 1A-1B , Figure 2B-2C Figure 3 Figures 4A-4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figures 8A-8C and Figure 9-13 One or more identical or similar components in (described below) are given the same reference numerals, and thus their detailed description is omitted.

[0053] The equivalent circuit 100B includes an IO pad 108 , a reference voltage source terminal 106 , a snapback device 120 , and a parasitic transistor 140 .

[0054] The parasitic transistor 140 is a bipolar junction transistor (BJT). In some embodiments, the parasitic transistor 140 is an NPN parasitic transistor. The parasitic transistor 140 includes a collector of the BJT corresponding to the drain region of the snapback device 120, an emitter of the BJT corresponding to the source region of the snapback device 120, a base of the BJT corresponding to the P well and P substrate of the snapback device 120, and a base resistor Rb corresponding to the resistance of the P well and P substrate of the snapback device 120.

[0055] The collector of the parasitic transistor 140 is coupled to the IO pad 108. The base resistor Rb is coupled between the base of the parasitic transistor 140 and the emitter of the parasitic transistor 140. The emitter of the parasitic transistor 140 is also coupled to the reference voltage source terminal 106.

[0056] In some embodiments, during positive ESD stress (eg, PS mode), when the ESD voltage is greater than the ESD trigger voltage Vth or threshold voltage of the parasitic transistor 140 , the parasitic transistor 140 turns on, thereby discharging the ESD voltage to the reference voltage source terminal 106 (eg, VSS).

[0057] The trigger voltage Vth of the parasitic transistor 140 is inversely proportional to each of the base current Ib and the base resistance Rb. For example, a decrease in at least the base current Ib or the base resistance Rb causes an increase in the trigger voltage Vth of the parasitic transistor 140. For example, an increase in at least the base current Ib or the base resistance Rb causes a decrease in the trigger voltage Vth of the parasitic transistor 140. In some embodiments, in order to reduce the ESD trigger voltage Vth, an N-well ( Figure 2A-2B ), which reduces the effective area of ​​the P-transistor. In some embodiments, by reducing the P-well ( Figure 2A-2B ) effective area, so that the base resistance Rb increases, and by reducing the P well ( Figure 2A-2B ) and when the additional N-well ( Figure 2A-2B ), the trigger voltage Vth decreases.

[0058] Compared to other approaches, at least one embodiment advantageously provides a design technology co-optimization solution for reducing the ESD trigger voltage Vth without requiring other manufacturing processes including a tuning process.

[0059] In at least one embodiment, a lower ESD trigger voltage Vth advantageously avoids one or more problems associated with higher ESD trigger voltages Vth in other approaches, including but not limited to potential damage to the circuit to be protected, non-uniform turn-on, or premature failure of the ESD protection device itself.

[0060] Figure 2A is a cross-sectional view of an integrated circuit 200A according to some embodiments. Figure 2B 2 is a cross-sectional view of an equivalent circuit 200B of the integrated circuit 200A according to some embodiments. For example, the equivalent circuit 200B corresponds to the integrated circuit 200A with the parasitic BJT 240. For example, Figure 2B For the sake of convenience, Figure 2A The integrated circuit 200A is not shown Figure 2B The parasitic BJT240. Figure 2C is a waveform diagram 200C of some embodiments compared with other methods.

[0061] The integrated circuit 200A is an embodiment of the snapback device 120 .

[0062] Integrated circuit 200A includes substrate 202. Substrate 202 is a p-type substrate. In some embodiments, substrate 202 is an n-type substrate. In some embodiments, substrate 202 includes elemental semiconductors, including silicon or germanium in a crystalline, polycrystalline or amorphous structure; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature, wherein the Si and Ge composition changes from one ratio at one position of the gradient SiGe feature to another ratio at another position. In some embodiments, alloy SiGe is formed over a silicon substrate. In some embodiments, substrate 202 is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epitaxial layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure.

[0063] The integrated circuit 200A further includes a P-well 204 and an N-well 206 in the substrate 202. The N-well 206 is adjacent to the P-well 204. The P-well 204 has a width W0 in a first direction X, and the N-well 206 has a width W1′ in the first direction X. In some embodiments, the width W0 is greater than the width W1′. The P-well 204 has a doping impurity type opposite to that of the N-well 206. The N-well 206 includes n-type doping impurities, and the P-well includes p-type doping impurities.

[0064] N-well 206 is located on the drain side of transistor 260. In some embodiments, by including N-well 206 in integrated circuit 200A, the effective area of ​​P-well 204 in integrated circuit 200A is reduced, thereby increasing the base resistance Rb of P-well 204 and substrate 202 during an ESD event. The increase in base resistance Rb results in a reduction in the trigger voltage Vth1 of integrated circuit 200A during an ESD event compared to when N-well 206 is not included.

[0065] The integrated circuit 200A further includes a gate structure 230 over the P-well 204. The gate structure 230 includes a gate dielectric 222 and a gate electrode 230a. The integrated circuit 200A further includes sidewalls on opposite sides of the gate structure 230.

[0066] Integrated circuit 200A also includes drain region 212 and source region 214. Source region 214 is an N-type active region with N-type dopants injected into P-well 204. Drain region 212 is an N-type active region with N-type dopants injected into at least P-well 204 or N-well 206. In some embodiments, at least source region 214 or drain region 212 extends above substrate 202. In some embodiments, N-well 206 is embedded in P-well 204. In some embodiments, N-well 206 is adjacent to a portion of drain region 212. In some embodiments, a first element being adjacent to a second element corresponds to the first element being directly next to the second element. In some embodiments, a first element being adjacent to a second element corresponds to the first element not being directly adjacent to the second element. In some embodiments, N-well 206 directly contacts a portion of drain region 212.

[0067] In some embodiments, FIG. 2A to FIG. 2B The drain region 212 and source region 214 of transistor 260 are referred to as oxide definition (OD) regions, which define Figure 4A The source or drain diffusion region of the integrated circuit 200A-200B or the NMOS transistor N1 (described below).

[0068] In some embodiments, integrated circuit 200A further includes a lightly doped drain (LDD) region 218 adjacent to source region 214 and drain region 212 and below sidewall 220. In some embodiments, LDD region 360 helps transistor 260 maintain low leakage current.

[0069] Integrated circuit 200A also includes a P-well tap 216, shallow trench isolation (STI) regions 208 and 210 on P-well 204. STI region 208 is configured to isolate drain region 212 from other portions (not shown) of integrated circuit 200A. STI region 210 is configured to isolate source region 214 from other portions of integrated circuit 200A. In some embodiments, region 210 is configured to isolate source region 214 from tap region 216. FIG. 2A to FIG. 2B Figure 2 to Figure 3B This is an embodiment. Figure 5A-5B STI region 208 is shown within N-well 206, in some embodiments, STI region 208 is not within N-well 206. In some embodiments, STI region 208 is adjacent to or directly adjacent to N-well 206. In an embodiment, N-well 206 is located between drain region 212 and STI region 208. In some embodiments, STI region 208 is not formed in the same region or space as N-well 206. In some embodiments, STI region 208 is not formed in N-well 206. In some embodiments, integrated circuit 200A or 200B does not include STI region 208 or 210.

[0070] In some embodiments, drain region 212, source region 214, LDD region 218, sidewall 220, and gate structure 230 together form transistor 260. In some embodiments, transistor 260 is an NMOS transistor. In some embodiments, transistor 260 is a PMOS transistor. In some embodiments, transistor 260 corresponds to Figure 1A-1B Snapback device 120. In some embodiments, transistor 260 corresponds to Figure 4A Driver device 440.

[0071] In some embodiments, drain region 212 is coupled to IO pad 108, and source region 214 and tap region 216 are coupled to reference voltage source terminal 106 (e.g., voltage VSS). In some embodiments, gate structure 230 is also coupled to source region 214, tap region 216, and reference voltage source terminal 106 (e.g., voltage VSS), and thus corresponds to a grounded gate NMOS (ggNMOS) device.

[0072] In some embodiments, drain region 212 and source region 214 include fins according to FinFET complementary metal-oxide-semiconductor (CMOS) technology. In some embodiments, drain region 212 and source region 214 include nanosheets of a nanosheet transistor. In some embodiments, drain region 212 and source region 214 include nanowires of a nanowire transistor. In some embodiments, drain region 212 and source region 214 do not have fins according to planar CMOS technology. Other types of transistors are within the scope of the present disclosure.

[0073] In some embodiments, drain region 212 is an extended drain region and has a larger size than source region 214. In at least one embodiment, a silicide layer (not shown) covers a portion, but not all, of drain region 212. This partially silicided configuration of drain region 212 improves the self-protection of transistor 260 against ESD events. In at least one embodiment, drain region 212 is fully silicided.

[0074] The gate structure 230 is disposed between the drain region 212 and the source region 214. In some embodiments, the gate electrode 230a includes a conductive material such as metal or polysilicon (also referred to herein as "POLY"). In some embodiments, the gate structure 230 is coupled to the voltage source terminal 104 (e.g., voltage VDD) or the reference voltage source terminal 106 (e.g., voltage VSS). In some embodiments, as relative to Figure 4A As depicted, gate structure 230 is coupled to external control circuitry.

[0075] Figure 2B is a cross-sectional view of an equivalent circuit 200B of the integrated circuit 200A according to some embodiments. Figure 2B compared to, Figure 2A The integrated circuit 200A is not shown Figure 2B The parasitic BJT 240.

[0076] The integrated circuit 200B includes the integrated circuit 200A, a parasitic BJT 240 (hereinafter referred to as “BJT 240 ”), and a parasitic base resistor Rb.

[0077] BJT 240 includes a base 242, a collector 244, and an emitter 246. BJT 240 is an embodiment of parasitic transistor 140, and thus similar detailed description is omitted. Figure 1B Compared with the parasitic transistor 140 of the integrated circuit 100B, the base 242 replaces the base of the parasitic transistor 140, the collector 244 replaces the collector of the parasitic transistor 140, and the emitter 246 replaces the emitter of the parasitic transistor 140, and similar detailed descriptions are omitted. Figure 2B The base resistance Rb corresponds to Figure 1BThe base resistor Rb is shaped like a base resistor, so similar detailed description is omitted.

[0078] BJT 240 is an NPN parasitic BJT formed by at least P-well 204 and N-type drain region 212 and N-type source region 214 in substrate 202. P-well 204 and substrate 202 correspond to base 242 of BJT 240, drain region 212 of transistor 260 corresponds to collector 244 of BJT 240, and source region 214 of transistor 260 corresponds to emitter 246 of BJT 240.

[0079] The IO pad 108 is coupled to the drain region 212 through the conductive region 270, thereby coupling the IO pad 108 to the collector 244 of the BJT 240. The reference voltage source 106 (e.g., VSS) is coupled to the source region 214 and the P-well tap 216 through the conductive region 272, thereby coupling the emitter 246 of the BJT 240 to the reference voltage source 106 (e.g., VSS). In other words, the collector 244 and the emitter 246 are coupled between the IO pad 108 and the reference voltage source 106 (e.g., VSS).

[0080] The base resistor Rb corresponds to at least the resistance of the P-well 204 or the substrate resistance of the substrate 202. The base resistor Rb is coupled between the base 242 and the P-well tap 216. Since the reference voltage source 106 (e.g., VSS) is coupled to the source region 214 and the P-well tap 216, the voltage drop across the base resistor Rb corresponds to the base-emitter voltage Vbe between the base 242 and the emitter 246 of the BJT 240.

[0081] In the absence of an ESD event, the Vbe of BJT 240 is lower than the threshold voltage or trigger voltage of BJT 240, so BJT 240 is turned off. For example, in some embodiments, Vbe is zero, and BJT 240 is turned off. In some embodiments, as described with respect to Figure 1A-1B As described, when the gate structure 230 of the transistor 260 is coupled to the reference voltage source terminal 106 (e.g., VSS), the transistor 260 is also turned off without affecting the normal operation of the internal circuit 140. When the gate structure 230 of the transistor 260 is configured to receive the driver control signal DRV (as shown in FIG. 1 ) from the driver circuit (not shown), the transistor 260 is turned off. Figure 4A ), transistor 260 is turned on or off in response to driver control signal DRV to controllably pull the voltage of IO pad 108 to reference voltage VSS of reference voltage source terminal 106 during normal operation of internal circuit 140.

[0082] During an ESD event, an ESD voltage is applied to the IO pad 108. The ESD voltage on the IO pad 108 is much higher than the voltage of the gate structure 230 and generates a strong electric field. The strong electric field may cause mobile charge carriers to violently collide with closely connected charge carriers, which then break. This process causes new charge carriers to be generated and repeats until avalanche breakdown occurs and an avalanche current is generated. When the ESD voltage is applied to the IO pad 108, the PN junction between the N-type drain region 212 and the P-well 204 is reverse biased until avalanche breakdown occurs. At this point, the drain current increases and the generated holes drift toward the base 242 of the BJT 240. The positively charged hole flow from the avalanche breakdown causes a voltage drop across the base resistor Rb of the BJT 240. As the voltage at base 242 increases, the base-emitter junction of BJT 240 becomes more forward biased, causing the base-emitter junction of BJT 240 to reach a threshold voltage, thereby turning on BJT 240 and discharging ESD current I1 from collector 244 to emitter 246. The high current from the ESD event is redirected away from gate structure 230 of transistor 260. In some embodiments, base resistor Rb controls the speed of triggering the avalanche mode of BJT 240 by reducing the collector-emitter trigger voltage of BJT 240. For example, by increasing base resistor Rb, the speed of triggering the avalanche mode of BJT 240 is increased, thereby turning on BJT 240 at a lower threshold voltage and releasing ESD current I1 faster than other methods.

[0083] In some embodiments, the voltage drop across the base resistor Rb of BJT 240 corresponds to Vbe. The higher the ESD voltage on IO pad 108, the higher Vbe. When Vbe reaches the threshold voltage of BJT 240, BJT 240 turns on and causes ESD current I1 to flow from drain region 212 to source region 214. As a result, the ESD voltage on IO pad 108 is discharged to reference voltage source terminal 106 (e.g., VSS) by turning on BJT 240. The voltage at which Vbe reaches the threshold voltage of BJT 240 is Figure 1A-1B The ESD trigger voltage of the transistor 260 or the snapback device 120 is determined.

[0084] As a result, at the same ESD voltage, Vbe in other approaches is lower than Vbe in the embodiment including N-well 206. In other words, the embodiment including N-well 206 allows Vbe to reach the threshold voltage of BJT 240 at a lower ESD voltage, and therefore has a lower ESD trigger voltage compared to other approaches. In at least one embodiment, the lower ESD trigger voltage advantageously avoids one or more problems associated with higher ESD trigger voltages in other approaches, including but not limited to potential damage to the circuit to be protected, uneven turn-on, and early failure of the ESD protection device itself.

[0085] Figure 2C is a waveform diagram 200C of some embodiments compared with other methods.

[0086] According to some embodiments, the waveform diagram 200C includes a current-voltage (IV) characteristic curve of the integrated circuit 200A. The waveform diagram 200C also includes an IV characteristic curve 282 of other methods.

[0087] like Figure 2C As shown, the x-axis corresponds to the drain voltage and the y-axis corresponds to the drain current.

[0088] like Figure 2C As shown, when the drain voltage has a voltage value Vt1 of curve 280, BJT 240 is turned on, and when the drain voltage of the transistor of other methods has a voltage value Vt2 of curve 282, the parasitic BJT of other methods is turned on. The voltage value Vt1 of curve 280 and the voltage value Vt2 of curve 282 are less than the destructive voltage Vb1 of transistor 260.

[0089] like Figure 2C As shown, once BJT 240 is turned on, there is no high electric field to start the avalanche process to maintain the drain current, which is called snapback. For example, the drain current increases at a drain voltage lower than voltage Vt1. Therefore, the drain voltage decreases to the holding voltage Vh, and snapback behavior is observed. After BJT 240 is turned on, the increase in drain voltage also increases the drain current until thermal damage to transistor 260 occurs at voltage Vt2. In some embodiments, the holding voltage Vh is greater than the power supply voltage VDD, thereby preventing transistor 260 from turning on and preventing latch-up.

[0090] In some embodiments, by including the N-well 206 in the transistor 260, the effective area of ​​the P-well 204 in the transistor 260 is reduced, thereby increasing the base resistance Rb of the P-well 204 and the substrate 202. Compared with other methods at the same ESD trigger voltage, the method results in a reduction in the trigger voltage Vth of the transistor 260 during an ESD event. Compared with other methods, at least one embodiment advantageously provides a design technology co-optimization solution for reducing the ESD trigger voltage Vth without the need for additional manufacturing processes including tuning processes. In at least one embodiment, the lower ESD trigger voltage Vth advantageously avoids one or more problems associated with a higher ESD trigger voltage Vth in other methods, including but not limited to potential damage to the circuit to be protected, uneven conduction, and early failure of the ESD protection device itself.

[0091] Figure 3A is a block diagram of a snapback device array 300' having a plurality of snapback device units (eg, integrated circuits 200A-200B) according to some embodiments. For example, Figure 1A-1B The snapback device 120 and the parasitic transistor 130 or the integrated circuit 200A- 200B of 2A- 2B may be used as one or more snapback devices in the snapback device array 301 .

[0092] The snapback device array 301' includes an array of snapback devices 301[1,1]', 301[1,2]', ..., 301[2,2]', ..., 301[M',N'] having M' rows and N' columns (collectively referred to as the "array of snapback devices 301A'"), where N' is a positive integer corresponding to the number of columns in the array of snapback devices 301A', and M' is a positive integer corresponding to the number of rows in the array of snapback devices 301A'. The rows of cells in the array of snapback devices 301A' are arranged along a first direction X. The columns of cells in the array of snapback devices 301A' are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X.

[0093] In some embodiments, each snapback device 301 [ 1 , 1 ] ′, 301 [ 1 , 2 ] ′, . . . , 301 [ 2 , 2 ] ′, . . . , 301 [M′, N′]′ in the array of snapback devices 301A′ includes a respective transistor 260 .

[0094] In some embodiments, each snapback device 301[1,1]', 301[1,2]', ..., 301[2,2]', ..., 301[M', N']' in the array of snapback devices 301A' located at the periphery of the array includes a circuit similar to the integrated circuit 200A-200B, and each snapback device 301[1,1]', 301[1,2]', ..., 301[2,2]', ..., 301[M', N']' in the array of snapback devices 301A' located at the periphery of the array includes a circuit similar to the integrated circuit 200A-200B without the P-well tap 216, and similar detailed description is therefore omitted.

[0095] Different types of snapback device cells in the snapback device array 301 ′ are within the contemplated scope of the present disclosure.

[0096] Figure 3B is a diagram of a layout design 300B according to some embodiments.

[0097] Layout Design 300B is Figure 3A Layout design 300B can be used to manufacture snapback device array 300A. Figure 3A In some embodiments, a portion of the layout design 300B may be used to manufacture a snapback device array 300A. Figure 1A-1B The snapback device 120 and the parasitic transistor 130 are shown. Figure 1A to Figure 1B Integrated circuits or Figure 2A-2B In some embodiments, Figure 3B include Figure 3A Additional elements not shown.

[0098] At least integrated circuits 100A-100B ( Figure 1A-1B )、200A-200B( Figure 2A-2B )、400A( Figure 4A )、500A-500B( Figure 5A-5B ) or 600A-600B( Figure 6A-6B ) or snapback device array 300A ( Figure 3A ) and the structural relationship (including alignment, distance, length, width and pitch) and configuration with at least layout design 300B ( Figure 3B )、400B( Figure 4B )、500C( Figure 5C )、600C( Figure 6C )、700A-700C( Figures 7A-7C ) or 800A-800C( Figures 8A-8C ) are similar in structure and configuration, and for brevity, similar detailed descriptions will be described in Figure 1A-1B , Figure 2A-2C , Figure 3A-3B , Figures 4A-4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figures 8A-8C and Figure 9-13 Omitted in .

[0099] Layout design 300B includes snapback device layout array 301. Snapback device layout array 301 includes an array of snapback device layout designs 301[1,1], 301[1,2], ..., 301[2,2], ..., 301[M,N] having M rows and N columns (collectively referred to as "array of snapback device layout designs 301A"), where N is a positive integer corresponding to the number of columns in the array of snapback device layout designs 301A, and M is a positive integer corresponding to the number of rows in the array of snapback device layout designs 301A. The rows of cells in the array of snapback device layout designs 301A are arranged along a first direction X. The columns of cells in the array of snapback device layout designs 301A are arranged along a second direction Y. In some embodiments, at least M or N is equal to Figure 4A M' or N'.

[0100] In some embodiments, each snapback device layout design 301[1,1], 301[1,2], ..., 301[2,2], ..., 301[M,N] in the array of snapback device layout designs 301A may be used to manufacture a corresponding snapback device 301[1,1]', 301[1,2]', ..., 301[2,2]', ..., 301[M',N']' in the array of snapback devices 301A'.

[0101] In some embodiments, each snapback device layout design 301 [ 1 , 1 ], 301 [ 1 , 2 ], . . . , 301 [ 2 , 2 ], . . . , 301 [M, N] in the array of snapback device layout designs 301A includes a layout design of a corresponding transistor 260 .

[0102] In some embodiments, each snapback device layout design 301 [ 1 , 1 ], 301 [ 1 , 2], ..., 301 [ 2 , 2], ..., 301 [M, N] in the array of snapback device layout designs 301A includes a respective layout design of a respective integrated circuit 200A- 200B.

[0103] Each layout design in snapback device layout array 301 corresponds to a layout design of integrated circuit 200A or 200B. In some embodiments, a cross-sectional view of integrated circuit 200A or equivalent circuit 200B corresponds to a layout design 300B intersecting plane AA'.

[0104] Figure 3BDetails of snapback device layout designs 301[1,1], 301[1,2], 301[2,2], and 301[2,2] are shown, and for brevity, details of other snapback device layout designs in snapback layout device array 301 are omitted. However, details of other snapback device layout designs in snapback layout device array 301 are similar to those of snapback device layout designs 301[1,1], 301[1,2], 301[2,2], and 301[2,2], and thus similar detailed descriptions are omitted.

[0105] In some embodiments, snapback device layout designs 301 [1, 1] and 301 [1, 2] include active area layout pattern 312a. In some embodiments, snapback device layout designs 301 [2, 1] and 301 [2, 2] include active area layout pattern 312b.

[0106] In some embodiments, snapback device layout designs 301 [1,1] and 301 [2,1] include well layout pattern 316a. In some embodiments, snapback device layout designs 301 [1,1] and 301 [2,1] include gate layout patterns 330a and 330b, and at least a portion of gate layout pattern 330c.

[0107] In some embodiments, snapback device layout designs 301 [1, 2] and 301 [2, 2] include well layout pattern 316b. In some embodiments, snapback device layout designs 301 [1, 2] and 301 [2, 2] include gate layout pattern 330d, and at least portions of gate layout patterns 330c and 330e.

[0108] Different types of snapback device layout designs in the array of snapback device layout designs 301 are within the contemplated scope of the present disclosure.

[0109] The layout design 300B includes at least an active area layout pattern 312 a or 312 b (collectively referred to as “active area layout pattern group 312 ”) extending in the second direction Y. The active area layout patterns 312 a or 312 b of the active area layout pattern group 312 are separated from each other in the second direction Y.

[0110] In some embodiments, an end of each active area layout pattern of the active area layout pattern group 312 is separated from an end of an adjacent active area layout pattern of the active area layout pattern group 312 in the direction Y by a distance D1 .

[0111] In some embodiments, the active area layout pattern 312a can be used to manufacture Figure 2A-2B The active region layout pattern 312b may be used to fabricate the active region of the transistor 260 (eg, the drain region 212 and the source region 214). Figure 2A-2BThe active region of the transistor 260 (eg, the drain region 212 and the source region 214) or Figure 4A The drain region and the source region of the NMOS transistor N1.

[0112] In some embodiments, at least the active area layout pattern 312a or 312b corresponds to the P-well 204. The active area layout pattern 312a or 312b is part of the corresponding row 1 or row 2 of the snapback device layout array 301.

[0113] In some embodiments, at least the active area layout pattern 312 a or 312 b is a continuous layout pattern extending in the first direction X. In some embodiments, at least the active area layout pattern 312 a or 312 b includes at least N discontinuous layout patterns extending in the first direction X, where N corresponds to the number of columns in the snapback device layout array 301 .

[0114] In some embodiments, the active area layout pattern group 312 is located on the first level. In some embodiments, the first level corresponds to the layout design 300B, 400B, 500C, 600C, 700A-700C or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) of one or more active layers or OD layers or integrated circuits 200A-200B, 500A-500B, 600A-600B ( Figure 2A-2B , Figure 5A-5B or Figure 6A-6B ).

[0115] Other configurations, levels, or numbers of patterns in at least the active area layout pattern set 312 are within the scope of the present disclosure.

[0116] The layout design 300B further includes at least gate layout patterns 330a, 330b, 330c, 330d, or 330e (collectively referred to as "gate layout pattern group 330") extending in the second direction Y, respectively. The patterns of the gate layout pattern group 330 are separated from adjacent gate layout patterns of the gate layout pattern group 330 by a first pitch in the first direction X. In some embodiments, an end of each gate layout pattern of the gate layout pattern group 330 is separated from an end of an adjacent gate layout pattern of the gate layout pattern group 330 by a pitch P1 in the first direction X.

[0117] In some embodiments, at least the gate layout patterns 330a, 330b, 330c, 330d, or 330e may be used to manufacture a gate similar to the gate structure 230. In some embodiments, at least the gate layout patterns 330a, 330b, 330c, 330d, or 330e 330e may be used to manufacture a gate similar to the gate structure 230. Figure 4A In some embodiments, at least gate layout patterns 330a, 330c and 330e may be used to manufacture Figure 2A-2B A dummy gate structure (not shown) in FIG.

[0118] The gate layout pattern 330b or 330d is part of the corresponding column 1 or column 2 of the snapback device layout array 301. In some embodiments, at least a portion of the gate layout pattern 330a or 330c is part of column 1 of the snapback device layout array 301. In some embodiments, at least a portion of the gate layout pattern 330c or 330e is part of column 2 of the snapback device layout array 301.

[0119] The gate layout pattern group 330 is located on a second level (POLY) different from the first level. The gate layout pattern group 330 overlaps the active area layout pattern group 312. In some embodiments, the second level corresponds to the layout design 300B, 400B, 500C, 600C, 700A-700C, or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) or integrated circuit 200A-200B, 500A-500B, 600A-600B ( Figure 2A-2B , Figure 5A-5B or Figure 6A-6B ) in one or more POLY levels.

[0120] Other configurations, levels, or numbers of patterns in the gate layout pattern group 330 are within the scope of the present disclosure.

[0121] Layout design 300B also includes at least well layout pattern 316a or 316b (collectively referred to as "well layout pattern group 316") extending in the second direction Y, respectively. Each well layout pattern in well layout pattern group 316 is separated from adjacent well layout patterns of well layout pattern group 316 in the first direction X. Each well layout pattern of well layout pattern group 316 has a width W1 extending in the first direction X. At least well layout pattern 316a or 316b can be used to manufacture N well 206. Width W1 is less than pitch P1. In some embodiments, width W1 is equal to pitch P1.

[0122] In some embodiments, the well layout pattern group 316 overlaps with the active area layout pattern group 312. The well layout pattern 316a is between the gate layout patterns 330b and 330c. The well layout pattern 316b is between the gate layout patterns 330d and 330e. The well layout pattern 316a or 316b is part of the corresponding column 1 or column 2 of the snapback device layout array 301. In some embodiments, at least the well layout pattern 316a or 316b is located on the drain side of the corresponding active area layout pattern 312a or 312b of the snapback device layout array 301. At least the well layout pattern 316a or 316b has a rectangular shape. In some embodiments, at least the well layout pattern 316a or 316b has a polygonal shape.

[0123] In some embodiments, at least the well layout pattern 316 a or 316 b is a continuous well layout pattern extending in the second direction Y. In some embodiments, at least the well layout pattern 316 a or 316 b includes at least M discontinuous well layout patterns extending in the second direction Y, where M corresponds to the number of rows in the snapback device layout array 301 .

[0124] In some embodiments, at least the well layout pattern 316a or 316b divides the active area layout pattern group 312 into discontinuous layout patterns arranged in columns. In some embodiments, at least the well layout pattern 316a or 316b divides the active area layout pattern group 312 into discontinuous layout patterns, thereby dividing the P-well 204 into discontinuous patterns arranged in columns.

[0125] Well layout pattern group 316 is located on the third level. In some embodiments, the third level is different from the first level and the second level. In some embodiments, the third level is the same as the first level. In some embodiments, the third level corresponds to layout design 300B, 400B, 500C, 600C, 700A-700C, or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) or integrated circuit 200A-200B, 500A-500B, 600A-600B ( Figure 2A-2B , Figure 5A-5B or Figure 6A-6B ) in one or more active levels or OD levels.

[0126] Other configurations, levels, or numbers of patterns in the well layout pattern set 316 are within the scope of the present disclosure.

[0127] The layout design 300B further includes at least one tap unit layout pattern 326 extending in the first direction and the second direction Y. The layout pattern 326 surrounds the snapback device layout array 301. The tap unit layout pattern 326 is separated from the snapback device layout array 301 in the first direction X and the second direction Y. In some embodiments, the tap unit layout pattern 326 is a continuous layout pattern extending in the first direction X and the second direction Y.

[0128] The tap cell layout pattern 326 can be used to manufacture Figure 2A-2B In some embodiments, the tap cell layout pattern 326 can be used to manufacture Figure 4A The body terminal of the NMOS transistor N1.

[0129] In some embodiments, the tap cell layout pattern 326 is located on a first level. Other configurations, levels, or numbers of patterns in the tap cell layout pattern 326 are within the scope of the present disclosure.

[0130] Figure 4A is a schematic block diagram of an integrated circuit 400A according to some embodiments.

[0131] Integrated circuit 400A is a variant of integrated circuits 100A-100B, and thus similar detailed descriptions are omitted. For example, according to some embodiments, integrated circuit 400A is Figure 1A The integrated circuit 100A is combined with the driver circuit 440. Figure 4A Portions of integrated circuit 100A are shown in integrated circuit 400A of FIG. 4 , but it should be understood that integrated circuit 400A may be modified to include each feature of integrated circuit 100A combined with a driver circuit 440 similar to that shown in FIG. 4 , and similar detailed descriptions are omitted for brevity.

[0132] Integrated circuit 400A includes internal circuit 102 , IO pad 108 , reference voltage source terminal 106 , snapback device 120 , and driver circuit 440 .

[0133] The driver circuit 440 is an N-type metal oxide semiconductor (NMOS) transistor N1. In some embodiments, the driver circuit 440 is a P-type metal oxide semiconductor (PMOS) transistor.

[0134] The driver circuit 440 is coupled between the IO pad 108 and the reference voltage source terminal 106 (e.g., VSS). The gate of the NMOS transistor N1 is configured to receive the driver signal DRV. The drain of the NMOS transistor N1 is coupled to the I / O pad 108 and the snapback device 120, and the source of the NMOS transistor N1 is coupled to the reference voltage source terminal 106 and the snapback device 120. The source of the NMOS transistor N1 is also coupled to the body of the NMOS transistor N1.

[0135] In some embodiments, the driver circuit 440 is coupled to the internal circuit 102 and is configured to handle signal transmission between the internal circuit 102 , the supply voltage VDD of the reference voltage source terminal 104 , and the reference voltage VSS of the reference voltage source terminal 106 .

[0136] The driver circuit 440 is coupled in parallel with the snapback device 120. In some embodiments, the driver circuit 440 is included as part of the snapback device 120. For example, in some embodiments, the NMOS transistor N1 of the driver circuit 440 corresponds to the NMOS device of the snapback device of the integrated circuit 200A-200B. In the absence of an ESD event, the NMOS transistor N1 is configured to operate as a driver circuit under the control of the driver signal DRV during normal operation of the internal circuit 102. When an ESD event occurs, the NMOS transistor N1 is configured to operate as a snapback device. Figure 1A-1B and Figure 2A-2C In these embodiments, the NMOS transistor N1 of the driver circuit 440 is configured to share the P-well 204 with the integrated circuit 200A or the snapback device 120 .

[0137] The driver circuit 440 has a parasitic capacitance Cgd between the gate of the NMOS transistor N1 and the drain of the NMOS transistor N1. In some embodiments, during a positive ESD stress (e.g., PS mode), the gate of the NMOS transistor N1 is capacitively coupled to the drain of the NMOS transistor N1 and the IO pad 108 through the parasitic capacitance Cgd, thereby receiving the positive ESD stress. By receiving the positive ESD stress during the ESD event, the NMOS transistor N1 is at least slightly turned on, thereby generating a channel current I2 in the p-well of the NMOS transistor N1. In some embodiments, since the NMOS transistor N1 of the driver circuit 440 shares the P-well 204 with the integrated circuit 200A-200B or the snapback device 120, the NMOS transistor N1 of the driver circuit 440 contributes channel current to other devices (e.g., the integrated circuit 200A-200B, the snapback device 120, or other snapback devices in the snapback array 301A′) that also share the P-well 204, thereby generating a higher base current Ib for the integrated circuit 200A-200B or the snapback device 120 than would otherwise be the case. In some embodiments, the earlier turn-on behavior of the driver circuit 440 combined with the higher base current Ib triggers other parallel snapback devices in the snapback array 301A′ to turn on together, thereby also reducing the trigger voltage Vth of the integrated circuits 200A-200B and 400A or the snapback device 120.

[0138] In some embodiments, additional driver circuits (not shown) are coupled between IO pads 108 and Figure 1A The voltage supply terminal 104 of the integrated circuit 100A is connected to the additional driver circuit (not shown) in some embodiments. The additional driver circuit (not shown) is similar to the driver circuit 440 in some embodiments, so similar detailed description is omitted.

[0139] Other configurations or numbers of circuits in integrated circuit 400A are within the scope of the present disclosure.

[0140] Figure 4B is a diagram of a layout design 400B according to some embodiments.

[0141] Layout design 400B is a layout diagram of integrated circuit 400A. Layout design 400B may be used to manufacture integrated circuit 400A. In some embodiments, Figure 4B include Figure 4B Additional elements not shown.

[0142] Layout design 400B is a layout design 300B ( Figure 3B), so similar detailed descriptions are omitted. For example, layout design 400B shows an example of placing driver circuit layout pattern 450 and snapback device layout patterns 301[1,1], ..., 301[M,1] of snapback device layout array 301 in the same P-well column (e.g., column 1).

[0143] In some embodiments, by positioning the driver circuit layout pattern 450 in the same P-well column (e.g., column 1) as the snapback device layout patterns 301 [1, 1], ..., 301 [M, 1] of the snapback device layout array 301, the driver circuit layout pattern 450 shares the P-well 204 with the snapback device layout patterns 301 [1, 1], ..., 301 [M, 1], thus having the same structure as described above for the snapback device layout array 301. Figure 4A The advantages described are similar and will not be repeated here for the sake of brevity.

[0144] Layout Design 400B is Figure 3A Layout design 400B can be used to manufacture snapback device array 300A. Figure 3A The snapback device array 300A.

[0145] Layout design 400B includes layout design 300B and driver circuit layout pattern 450 .

[0146] Driver circuit layout pattern 450 can be used to manufacture Figure 4A In some embodiments, the driver circuit layout pattern 450 corresponds to Figure 4A The driver circuit 440 is located in the embodiment of the present invention. In some embodiments, the driver circuit 440 corresponds to the transistor 260 , and thus the driver circuit layout pattern 450 corresponds to the layout design of the transistor 260 .

[0147] In some embodiments, each layout design in column 1 of snapback device layout array 301 includes driver circuit layout pattern 450 . In some embodiments, at least one of the layout designs in snapback device layout array 301 includes driver circuit layout pattern 450 .

[0148] In some embodiments, at least another column in the snapback device layout array 301 includes a layout pattern similar to the driver circuit layout pattern 450 , and thus similar detailed description is omitted.

[0149] Other configurations or numbers of patterns in driver circuit layout pattern 450 are within the scope of the present disclosure.

[0150] Figure 5A is a cross-sectional view of an integrated circuit 500A according to some embodiments. Figure 5B5 is a cross-sectional view of an equivalent circuit 500B of the integrated circuit 500A according to some embodiments. Figure 5C is a diagram of a layout design 500C according to some embodiments. In some embodiments, the cross-sectional view of integrated circuit 500A or equivalent circuit 500B corresponds to layout design 500C intersecting plane BB'.

[0151] Integrated circuit 500A is an embodiment of snapback device 120 .

[0152] Integrated circuit 500A is a variation of integrated circuit 200A, and thus similar detailed description is omitted. For example, integrated circuit 500A illustrates an example in which an additional N-well (e.g., N-well 506) is added to snapback device 120 or integrated circuit 200A. In some embodiments, by placing the additional N-well (e.g., N-well 506) into a P-well (e.g., P-well 204), the effective area of ​​the P-well (e.g., P-well 204) is also reduced.

[0153] and Figure 2A Compared with the integrated circuit 200A, the integrated circuit 500A further includes an N-well 506. The N-well 506 is similar to the N-well 206, and thus similar detailed descriptions are omitted.

[0154] The P-well 204 and the N-well 506 are in the substrate 202. The N-well 506 is within the P-well 204. The N-well 506 has a width W2' in the first direction X. In some embodiments, the width W2' is different from the width W1'. In some embodiments, the width W2' is equal to the width W1'.

[0155] At least the N-well 506 or 206 has a doping impurity type opposite to that of the P-well 204. The N-well 506 includes n-type doping impurities, and the P-well 204 includes p-type doping impurities. Figure 5A-5B and Figure 6A-6B The STI region 210 is shown to be within the N-well 506, in some embodiments, the STI region 210 is not within the N-well 506. In some embodiments, the STI region 210 is adjacent to or directly adjacent to the N-well 506. In an embodiment, the N-well 506 is between the source region 214 and the STI region 210. In some embodiments, the STI region 210 is not formed in the same region or space as the N-well 506. In some embodiments, the STI region 210 is not formed in the N-well 506. In some embodiments, the integrated circuit 500A or 500B does not include the STI region 208 or 210. In some embodiments, the integrated circuit 600A or 600B does not include the STI region 208 or 210.

[0156] N-well 506 is located on the source side of transistor 260. In some embodiments, by including N-well 506 in integrated circuit 500A, the effective area of ​​P-well 204 in integrated circuit 500A is reduced, thereby increasing the base resistance Rb of P-well 204 and substrate 202 during an ESD event. By increasing the base resistance Rb, the trigger voltage Vth of integrated circuit 500A during an ESD event is reduced compared to when N-well 206 and 506 are not included.

[0157] Other configurations, sizes, or numbers of N-wells 506 are within the scope of the present disclosure.

[0158] Figure 5B 5 is a cross-sectional view of an equivalent circuit 500B of the integrated circuit 500A according to some embodiments. For example, the equivalent circuit 500B corresponds to the integrated circuit 500A with the parasitic BJT 540. For example, Figure 5B For the sake of convenience, Figure 5A The integrated circuit 500A is not shown Figure 5B The parasitic BJT 540.

[0159] Figure 5C is a diagram of a layout design 500C according to some embodiments.

[0160] Layout design 500C is a layout diagram of integrated circuit 500A or equivalent circuit 500B. Layout design 500C may be used to manufacture integrated circuit 500A or equivalent circuit 500B. In some embodiments, Figure 5C Additional elements not shown are included.

[0161] In some embodiments, the cross-sectional view of the integrated circuit 500A or equivalent circuit 500B corresponds to a layout design 500C that intersects the plane BB′.

[0162] Layout design 500C is Figure 3A Layout design 500C can be used to manufacture snapback device array 300A. Figure 3A The snapback device array 300A.

[0163] Layout design 500C is a layout design 300B ( Figure 3B) are variations of the snapback device layout array 301, and thus similar detailed descriptions are omitted. For example, layout design 500C shows an example of adding well layout pattern 516a to column 1 of snapback device layout array 301, and adding well layout pattern 516b to column 2 of snapback device layout array 301. By positioning well layout pattern 516a in column 1 of snapback device layout array 301, and positioning well layout pattern 516b in column 2 of snapback device layout array 301, each snapback device layout pattern in snapback device layout array 301 of layout design 500C can be used to manufacture at least an integrated circuit, similar to integrated circuit 500A-500B having two N-wells (e.g., N-well 206 and N-well 506), thereby also reducing the area of ​​P-well 204, and thus having the same advantages as described above for Figure 5A The advantages described above will not be repeated here for the sake of brevity.

[0164] and Figure 3B Compared to the layout design 300B, the layout design 500C further includes a well layout pattern 516a and a well layout pattern 516b. The well layout pattern 516a or 516b is similar to the corresponding well layout pattern 316a or 316b, and thus similar detailed description is omitted.

[0165] and Figure 3B Compared with the layout design 300B, the well layout pattern group 516 replaces Figure 3B The well layout pattern group 516 includes at least well layout patterns 316a, 316b, 516a or 516b.

[0166] The well layout pattern 516a or 516b each extends in the second direction Y. Each well layout pattern in the first well layout pattern group 516 is separated from the adjacent well layout pattern in the well layout pattern group 516 in the first direction. At least the well layout pattern 516a or 516b has a width W2 extending in the first direction X. In some embodiments, the width W2 is equal to the width W1. In some embodiments, the width W2 is different from the width W1. The width W2 is less than the pitch P1. In some embodiments, the width W2 is equal to the pitch P1.

[0167] At least the well layout pattern 516 a or 516 b may be used to fabricate the N-well 506 .

[0168] The well layout pattern 516a is located between the gate layout patterns 330a and 330b (e.g., on the source side of the corresponding active area layout pattern 312a or 312b of the snapback device layout array 301). The well layout pattern 516b is located between the gate layout patterns 330c and 330d (e.g., on the source side of the corresponding active area layout pattern 312a or 312b of the snapback device layout array 301).

[0169] The well layout pattern 516a or 516b is part of the corresponding column 1 or column 2 of the snapback device layout array 301. In some embodiments, at least the well layout pattern 516a or 516b further divides the active area layout pattern group 312 into additional discontinuous layout patterns arranged in columns. In some embodiments, at least the well layout pattern 516a or 516b further divides the active area layout pattern group 311 into additional discontinuous layout patterns, thereby further dividing the P-well 204 into discontinuous patterns arranged in columns.

[0170] Well layout pattern group 516 is located on the third level.Other configurations, levels, or numbers of patterns in well layout pattern group 516 are within the scope of the present disclosure.

[0171] Fig. 6A is a cross-sectional view of an integrated circuit 600A according to some embodiments. Figure 6B is a cross-sectional view of an equivalent circuit 600B of the integrated circuit 600A according to some embodiments. Figure 6C is a diagram of a layout design 600C according to some embodiments. In some embodiments, the cross-sectional view of the integrated circuit 600A or equivalent circuit 600B corresponds to the layout design 600C intersecting with the plane CC'.

[0172] Integrated circuit 600A is an embodiment of snapback device 120 .

[0173] Integrated circuit 600A is a variation of integrated circuit 500A, and thus similar detailed description is omitted. For example, integrated circuit 600A illustrates an example in which an N-well (eg, N-well 206 ) is not included on the drain side in snapback device 120 or integrated circuit 200A.

[0174] and Figure 5A Compared to the integrated circuit 500A of FIG. 6 , the integrated circuit 600A does not include the N-well 206. Therefore, the integrated circuit 600A does not include an N-well (e.g., N-well 206) on the drain side, but includes an N-well (e.g., N-well 206) on the source side. In some embodiments, by including the N-well 506 on the source side of the integrated circuit 600A, the effective area of ​​the P-well 204 in the integrated circuit 600A is reduced, thereby increasing the base resistance Rb of the P-well 204 and the substrate 202 during an ESD event. The increase in the base resistance Rb results in a reduction in the trigger voltage Vth of the integrated circuit 600A during an ESD event compared to when the N-well 506 is not included.

[0175] Other configurations, sizes, or numbers of elements in integrated circuit 600A are within the scope of the present disclosure.

[0176] Figure 6B6 is a cross-sectional view of an equivalent circuit 600B of the integrated circuit 600A according to some embodiments. For example, the equivalent circuit 600B corresponds to the integrated circuit 600A with the parasitic BJT 640. For example, Figure 6B In order to facilitate the explanation Fig. 6A The integrated circuit 600A is not shown Figure 6B The parasitic BJT 640.

[0177] Figure 6C is a diagram of a layout design 600C according to some embodiments.

[0178] Layout design 600C is a layout diagram of integrated circuit 600A or equivalent circuit 600B. Layout design 600C can be used to manufacture integrated circuit 600A or equivalent circuit 600B. In some embodiments, Figure 6C Additional elements not shown are included.

[0179] In some embodiments, the cross-sectional view of the integrated circuit 600A or equivalent circuit 600B corresponds to a layout design 600C that intersects a plane CC′.

[0180] Layout design 600C is Figure 3A Layout diagram of snapback device array 300A. Layout design 600C can be used to manufacture Figure 3A The snapback device array 300A.

[0181] Layout design 600C is a layout design 500C ( Figure 5C ) variant, so similar detailed description is omitted. Figure 5C Compared to the integrated circuit 500C, the layout design 600C does not include the well layout patterns 316a and 316b. Therefore, the layout design 600C does not include the well layout patterns 316a and 316b on the drain side, but includes the well layout patterns 516a and 516b on the source side of the transistor 260.

[0182] In some embodiments, by positioning well layout pattern 516a or 516b in corresponding column 1 or column 2 of snapback device layout array 301 on the drain side, each snapback device layout pattern in snapback device layout array 301 of layout design 600C can be used to manufacture at least one integrated circuit similar to integrated circuit 600A or equivalent circuit 600B having N-well 506 on the drain side, thereby also reducing the area of ​​P-well 204, thereby having the same advantages as described above. Fig. 6A Similar advantages are not described again here for the sake of brevity.

[0183] Other configurations, levels, or numbers of patterns in layout design 600C are within the scope of the present disclosure.

[0184] Fig. 7Ais a diagram of a layout design 700A according to some embodiments.

[0185] Layout design 700A is a layout diagram of integrated circuit 200A or equivalent circuit 200B. Layout design 700A may be used to manufacture integrated circuit 200A or equivalent circuit 200B. In some embodiments, 7A to 7C The embodiments do not show additional elements.

[0186] In some embodiments, the cross-sectional view of the integrated circuit 200A or equivalent circuit 200B corresponds to at least a layout design 700A intersecting the plane AA′.

[0187] Layout Design 700A is Figure 3A Layout design 700A can be used to manufacture snapback device array 300A. Figure 3A The snapback device array 300A.

[0188] Layout design 700A is a layout design 300B ( Figure 3B ) variant, so similar detailed description is omitted. Figure 3B Compared with the layout design 300B, the layout design 700A further includes a well layout pattern group 730. The well layout pattern group 730 includes at least a well layout pattern 730a or a well layout pattern 730b. At least the well layout pattern 730a or 730b is similar to the well layout pattern 316a or 316b, so similar detailed description is omitted.

[0189] The well layout pattern 730a or 730b each extends in the first direction X. Each well layout pattern in the second well layout pattern group 730 is separated from an adjacent well layout pattern in the second well layout pattern group 730. The well layout pattern 730a has a width W3 extending in the second direction Y, and the well layout pattern 730b has a width W4 extending in the second direction Y. In some embodiments, the width W3 is equal to the width W4. In some embodiments, the width W3 is different from the width W4.

[0190] The well layout pattern 730a is separated from the active area layout pattern 312a by a distance D2 in the second direction Y. The well layout pattern 730b is separated from the active area layout pattern (not shown) in the row M of the snapback device layout array 301 by a distance D2 (not shown) in the second direction Y. In some embodiments, at least the width W3 or the width W4 is equal to the distance D2. In some embodiments, at least the width W3 or the width W4 is different from the distance D2.

[0191] At least well layout pattern 730a or 730b may be used to fabricate a corresponding N-well similar to N-well 506. In some embodiments, at least well layout pattern 730a or 730b may be used to fabricate a corresponding N-well in snapback device array layout 301 and positioned at a location similar to that shown in layout designs 700A-700C.

[0192] At least the well layout pattern 730a or 730b is located outside the snapback device layout array 301. At least the well layout pattern 730a or 730b is located between the snapback device layout array 301 and the well layout pattern 326. The length of at least the well layout pattern 730a or 730b in the first direction X is the same as the length of the snapback device array layout 301 in the first direction X. In some embodiments, the length of at least the well layout pattern 730a or 730b in the first direction X is different from the length of the snapback device array layout 301 in the first direction X.

[0193] In some embodiments, layout designs 700A-700C may be used to fabricate corresponding integrated circuits similar to integrated circuit 300A having an additional N-well (not shown) similar to N-well 316a or 316b by positioning well layout pattern 730a between well layout pattern 326 and active region 312a, and positioning well layout pattern 730b between well layout pattern 326 and active region (not shown) of row M of snapback device layout array 301. This also increases base resistance Rb between P-well tap 216 and each drain of transistor 260 of snapback device array 301A'. The increased base resistance Rb results in a reduced trigger voltage Vth of the integrated circuits fabricated by layout designs 700A-700C during an ESD event compared to when the additional N-well is not included.

[0194] Well layout pattern group 730 is located on the third level. Other configurations, levels, or numbers of patterns in well layout pattern group 730 are within the scope of the present disclosure. For example, in some embodiments, layout design 700A does not include well layout patterns 730a or 730b.

[0195] Figure 7B-7C are diagrams of corresponding layout designs 700B- 700C according to some embodiments.

[0196] At least layout design 700B or 700C is a layout diagram of integrated circuit 200A or equivalent circuit 200B. At least layout design 700B or 700C can be used to manufacture integrated circuit 200A or equivalent circuit 200B.

[0197] At least layout design 700B or 700C is Figure 3A At least one of the layout designs 700B and 700C can be used to manufacture the snapback device array 300A. Figure 3A The snapback device array 300A.

[0198] Figure 7B is a diagram of a corresponding layout design 700B according to some embodiments.

[0199] In some embodiments, the cross-sectional view of the integrated circuit 500A or the equivalent circuit 500B corresponds to at least a layout design 700B intersecting a plane BB′.

[0200] Layout design 700B is a layout design 500C ( Figure 5C ) and layout design 700A( Fig. 7A ) are variations of the layout design, so similar detailed descriptions are omitted. For example, layout design 700B at least shows that well layout patterns 730a and 730b are added to Figure 5C In other words, the layout design 700B includes adding Figure 5C The layout design of 500C Fig. 7A Well layout patterns 730a and 730b.

[0201] Figure 7C is a diagram of a corresponding layout design 700C according to some embodiments.

[0202] In some embodiments, the cross-sectional view of the integrated circuit 600A or equivalent circuit 600B corresponds to a layout design 700C that intersects at least the plane CC′.

[0203] Layout design 700C is a layout design 600C ( Figure 6C ) and layout design 700A( Fig. 7A ) are variations of the layout design, so similar detailed descriptions are omitted. For example, layout design 700C at least shows that well layout patterns 730a and 730b are added to Figure 6C In other words, the layout design 700C includes adding Figure 6C The layout design of 600C Fig. 7A Well layout patterns 730a and 730b.

[0204] At least for the above Fig. 7AFor similar reasons, in some embodiments, by positioning well layout pattern 730a between well layout pattern 326 and active area 312a, and positioning well layout pattern 730b between well layout pattern 326 and active area (not shown) of row M of snapback device layout array 301, layout designs 700B and 700C may be used to fabricate corresponding integrated circuits having increased base resistance Rb between P-well tap 216 and each drain of transistor 260 in snapback device array 301A′, thereby having the same advantages as described above with respect to FIG. Fig. 7A Similar advantages are not described again here for the sake of brevity.

[0205] Other configurations, levels, or numbers of patterns in at least layout design 700B or 700C are within the scope of the present disclosure.For example, in some embodiments, at least layout design 700B or 700C does not include well layout pattern 730a or 730b.

[0206] Fig. 8A is a diagram of a layout design 800A according to some embodiments.

[0207] Layout design 800A is a layout diagram of integrated circuit 200A or equivalent circuit 200B. Layout design 800A may be used to manufacture integrated circuit 200A or equivalent circuit 200B. In some embodiments, FIG. 8A to FIG. 8C Additional elements not shown are included.

[0208] In some embodiments, the cross-sectional view of the integrated circuit 200A or equivalent circuit 200B corresponds to at least a layout design 800A intersecting the plane AA′.

[0209] Layout Design 800A is Figure 3A Layout diagram of snapback device array 300A. Layout design 800A can be used to manufacture Figure 3A The snapback device array 300A.

[0210] Layout design 800A is a layout design 700A ( Fig. 7A ) variant, so similar detailed description is omitted. Fig. 7A Compared to layout design 700A, layout design 800A further includes active region layout patterns 812 and 814 , and gate layout pattern groups 830 and 840 .

[0211] At least the active layout pattern 812 or 814 is similar to the corresponding active layout pattern 312a or 312b, so similar detailed description is omitted. At least the active layout pattern 812 or 814 extends in the second direction Y. The active area layout patterns 812 and 814 are separated from each other in the second direction Y. In some embodiments, at least the active area layout pattern 812 or 814 is on the corresponding well layout pattern 730a or 730b.

[0212] At least the active region layout pattern 812 or 814 is located outside the snapback device layout array 301. At least the active region layout pattern 812 or 814 is located between the snapback device layout array 301 and the well layout pattern 326.

[0213] In some embodiments, the active area layout pattern 312a can be used to manufacture a device similar to Figure 2A-2B The transistor 260 has active regions (eg, drain region 212 and source region 214) of a transistor, but is a dummy transistor.

[0214] In some embodiments, at least the active area layout pattern 812 or 814 is a continuous layout pattern extending in the first direction X. In some embodiments, at least the active area layout pattern 812 or 814 includes a discontinuous layout pattern extending in the first direction X.

[0215] In some embodiments, at least active area layout pattern 812 or 814 is located on a first level.Other configurations, levels, or numbers of patterns in at least active area layout pattern 812 or 814 are within the scope of the present disclosure.

[0216] At least the gate layout pattern group 830 or 840 is similar to the gate layout pattern group 330 , and thus similar detailed description is omitted.

[0217] The gate layout pattern group 830 includes at least gate layout patterns 830a, 830b, ..., 830f or 830g. The gate layout pattern group 840 includes at least gate layout patterns 840a, 840b, ..., 840f or 840g. The gate layout pattern groups 830 and 840 each extend in the second direction Y. Each gate layout pattern of the gate layout pattern group 830 or 840 is separated from the corresponding adjacent gate layout pattern in the corresponding gate layout pattern group 830 or 840 by a second pitch (not shown) in the first direction X.

[0218] In some embodiments, at least gate layout pattern 830a, 830b, ..., 830f or 830g or at least gate layout pattern 840a, 840b, ..., 840f or 840g can be used to manufacture a gate similar to at least gate structure 230 or 830, the gate of NMOS transistor N1, but a dummy gate structure. In some embodiments, the dummy gate structure is a non-functional gate structure.

[0219] In some embodiments, at least the number of gate layout patterns in gate layout pattern group 830 or 840 is the same as the number of gate layout patterns 330. In some embodiments, at least the number of gate layout patterns in gate layout pattern group 830 or 840 is different from the number of gate layout patterns 330.

[0220] The gate layout pattern group 830 or 840 is located on the second level. Other configurations, levels, or numbers of patterns in the gate layout pattern group 830 or 840 are within the scope of the present disclosure.

[0221] In some embodiments, by positioning well layout pattern 730a, active area layout pattern 812, and gate layout pattern group 830 between well layout pattern 326 and active area 312a, and positioning well layout pattern 730b, active area layout pattern group 814, and gate layout pattern group 840 between well layout pattern 326 and active area (not shown) in row M of snapback device layout array 301, layout designs 800A-800C may be used to fabricate corresponding integrated circuits similar to integrated circuit 300A having an additional N-well (not shown) similar to N-well 316a or 316b, thereby also increasing the base resistance Rb between P-well tap 216 and each drain of transistor 260 in snapback device 301A' array. By increasing the base resistance Rb, a reduction in the trigger voltage Vth of the integrated circuits fabricated by layout designs 800A-800C is caused during an ESD event compared to when no additional N-well is included.

[0222] Other configurations, hierarchies, or numbers of patterns in at least layout design 800A are within the scope of the present disclosure. For example, in some embodiments, layout design 800A does not include at least well layout pattern 830a or 830b, active area layout pattern 812 or 814, or gate layout pattern group 830 or 840.

[0223] Figures 8B-8C are diagrams of corresponding layout designs 800B- 800C according to some embodiments.

[0224] At least layout design 800B or 800C is a layout diagram of integrated circuit 200A or equivalent circuit 200B. At least layout design 800B or 800C can be used to manufacture integrated circuit 200A or equivalent circuit 200B.

[0225] At least layout design 800B or 800C is Figure 3A At least one of the layout designs 800B and 800C may be used to manufacture the snapback device array 300A. Figure 3A The snapback device array 300A.

[0226] Figure 8B is a diagram of a corresponding layout design 800B according to some embodiments.

[0227] In some embodiments, the cross-sectional view of the integrated circuit 500A or equivalent circuit 500B corresponds to a layout design 800B that intersects at least the plane BB′.

[0228] Layout design 800B is a layout design 700B ( Figure 7B ) and layout design 800A( Fig. 8A ) and thus similar detailed descriptions are omitted. For example, layout design 800B illustrates at least one embodiment in which active area layout patterns 812 and 814 and gate layout pattern groups 830 and 840 are added to Figure 7B In other words, the layout design 800B includes the addition of Figure 7B The active area layout patterns 812 and 814 in the layout design 700B, and Fig. 8A The gate layout pattern groups 830 and 840 are shown in FIG.

[0229] Figure 8C is a diagram of a corresponding layout design 800C according to some embodiments.

[0230] In some embodiments, the cross-sectional view of the integrated circuit 600A or the equivalent circuit 600B corresponds to at least a layout design 800C intersecting a plane CC′.

[0231] Layout design 800C is a layout design 700C ( Figure 7C ) and layout design 800A( Fig. 8A ) variants, and thus similar detailed descriptions are omitted. For example, layout design 800C illustrates at least one embodiment in which active area layout patterns 812 and 814 and gate layout pattern groups 830 and 840 are added to Figure 7C In other words, the layout design 800C includes the layout design 700C added to Figure 7C The active area layout patterns 812 and 814 in the layout design 700C and Fig. 8A The gate layout pattern groups 830 and 840 are shown in FIG.

[0232] At least due to the above Fig. 8A For reasons similar to those described above, in some embodiments, by positioning well layout pattern 730a, active area layout pattern 812, and gate layout pattern group 830 between well layout pattern 326 and active area 312a, and positioning well layout pattern 730b, active area layout pattern 814, and gate layout pattern group 840 between well layout pattern 326 and active area (not shown) in row M of snapback device layout array 301, layout designs 800B and 800C may be used to manufacture corresponding integrated circuits having an increased base resistance Rb between P-well tap 216 and each drain of transistor 260 in snapback device array 301A', and thus having the same base resistance Rb as described above for the present invention. Fig. 8A The advantages described above are similar to those described above and will not be described again for the sake of brevity.

[0233] Other configurations, levels, or numbers of patterns in at least layout design 800B or 800C are within the scope of the present disclosure. For example, in some embodiments, at least layout design 800B or 800C does not include at least well layout pattern 830a or 830b, active area layout pattern 812 or 814, or gate layout pattern group 830 or 840.

[0234] Fig. 9 is a flow chart of a method 900 of forming or manufacturing an ESD circuit according to some embodiments. It should be understood that Fig. 9 Additional operations may be performed before, during, and / or after the illustrated method 900. Fig. 9 Other operations are shown in FIG. 1 , and only some of the other operations are briefly described here. In some embodiments, method 900 can be used to form an ESD circuit, such as integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B ), 500B( Figure 5B ) or 600B( Figure 6B In some embodiments, method 900 may be used to form a circuit having the same structure as layout design 300B, 400B, 500C, 600C, 700A-700C, or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) in one or more similar structural relationships. In some embodiments, other operation sequences of method 900 are within the scope of the present disclosure. Method 900 includes exemplary operations, but these operations are not necessarily performed in the order shown. According to the spirit and scope of the disclosed embodiments, operations can be appropriately added, replaced, changed in order, and / or eliminated.

[0235] In operation 902 of method 900, a layout design of an ESD circuit is generated. Operation 902 is performed by a processing device (e.g., processor 1202 ( Fig.12 In some embodiments, the layout design is in a Graphics Database System II (GDSII) file format.

[0236] In some embodiments, the ESD circuit of method 900 includes at least integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ), 500B( Figure 5B ) or 600B( Figure 6B ) or equivalent circuit 200B( Figure 2B In some embodiments, the layout design of method 900 includes at least layout designs 300B, 400B, 500C, 600C, 700A-700C, or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ).

[0237] In operation 904 of method 900, the ESD circuit is fabricated based on the layout design. In some embodiments, operation 904 of method 900 includes fabricating at least one mask based on the layout design, and fabricating the ESD circuit based on the at least one mask.

[0238] Fig. 10A is a functional flow chart of at least a portion of an integrated circuit design and manufacturing process 1000A according to some embodiments. It should be understood that in Fig. 10A Additional operations are performed before, during and / or after the method 1000A shown, and only some other processes are briefly described here. In some embodiments, other operation sequences of method 1000A are within the scope of the present disclosure. Method 1000A includes exemplary operations, but these operations are not necessarily performed in the order shown. According to the spirit and scope of the disclosed embodiments, operations can be appropriately added, replaced, changed in order and / or eliminated.

[0239] In some embodiments, method 1000A is an embodiment of operation 902 of method 900. In some embodiments, method 1000A may be used to at least generate or place a layout design 300B, 400B, 500C, 600C, 700A-700C, or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) in one or more layout patterns, such as integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B, Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B ).

[0240] In operation 1002 of method 1000A, an array of snapback device layout designs is generated or placed. In some embodiments, the array of snapback device layout designs of method 1000A includes at least layout designs 300B, 400B, 500C, 600C, 700A-700C, or 800A-800C. In some embodiments, the array of snapback device layout designs of method 1000A includes at least the layout designs in layout designs 301 [1, 1], 301 [1, 2], ..., 301 [2, 2], ..., 301 [M, N]. In some embodiments, operation 1002 includes at least operation 1004, 1006, or 1008.

[0241] In operation 1004 of method 1000A, a first set of active area layout patterns is generated or placed on a first level of the layout design. In some embodiments, the layout design of method 1000A includes at least a layout design. In some embodiments, the first level of method 1000A corresponds to the OD level. In some embodiments, the first level of method 1000A corresponds to the first level described in the specification. In some embodiments, the first set of active area layout patterns of method 1000A includes at least one or more active area layout patterns in at least active area layout pattern group 312.

[0242] In operation 1006 of method 1000A, a first set of gate layout patterns is generated or placed on a second level of the layout design. In some embodiments, the second level of method 1000A corresponds to the POLY level. In some embodiments, the second level of method 1000A corresponds to at least one level described in the specification. In some embodiments, the first gate layout pattern group of method 1000A includes at least one or more gate layout patterns in gate layout pattern group 330.

[0243] In operation 1008 of method 1000A, a first set of well layout patterns is generated or placed on a third level of the layout design. In some embodiments, the third level of method 1000A corresponds to an N-well level. In some embodiments, the third level of method 1000A corresponds to at least one level described in the specification. In some embodiments, the first set of well layout patterns of method 1000A includes at least one or more well layout patterns in at least well layout pattern group 316 or 516.

[0244] In operation 1010 of method 1000A, a second set of well layout patterns is generated or placed on a third level of the layout design. In some embodiments, the second set of well layout patterns of method 1000A includes at least one or more well layout patterns of at least well layout pattern group 730 .

[0245] In operation 1012 of method 1000A, a second set of active area layout patterns is generated or placed on the first level of the layout design. In some embodiments, the second set of active area layout patterns of method 1000A includes at least one or more active area layout patterns in at least active area layout pattern groups 812 or 814 .

[0246] In operation 1014 of method 1000A, a second set of gate layout patterns is generated or placed on a second level of the layout design. In some embodiments, the second set of gate layout patterns of method 1000A includes at least one or more gate layout patterns of at least gate layout pattern group 830 or 840 .

[0247] In operation 1016 of method 1000A, a driver circuit layout pattern group is generated or placed on the layout design. In some embodiments, the driver circuit layout pattern group of method 1000A includes at least one or more portions of well layout pattern 450. In some embodiments, the driver circuit layout pattern group of method 1000A includes at least one or more layout designs of transistor layout designs 301 [1, 1], 301 [1, 2], ..., 301 [2, 2], ..., 301 [M, N] combined with at least a portion of well layout pattern 450.

[0248] In some embodiments, operation 1016 includes one or more operations to generate or place individual columns and rows in the array of snapback device layout patterns 301. In some embodiments, operation 1016 includes placing a driver circuit layout pattern in a first row of the layout design of the snapback ESD protection circuit array, wherein the driver circuit layout pattern corresponds to manufacturing driver circuit 440. In some embodiments, placing the driver circuit layout pattern includes placing a third active area layout pattern of the first set of active layout patterns in the first layout level, the third active area layout pattern extending along the first direction and corresponding to the drain region of the manufacturing driver circuit; and placing a fourth active area layout pattern of the first set of active area layout patterns in the first layout level, the fourth active area layout pattern extending along the first direction and corresponding to the source region of the manufacturing driver circuit, the driver circuit sharing the p-well of the snapback ESD protection circuit with the first snapback ESD protection circuit in the snapback ESD protection circuit array. In some embodiments, the first active area layout pattern and the second active area layout pattern are in a second row of the layout design of the snapback ESD protection circuit array, the second row being adjacent to the first row.

[0249] In operation 1018 of method 1000A, a first well layout pattern is generated or placed on the third level of the layout design. In some embodiments, the first well layout pattern of method 1000A includes at least a portion of well layout pattern 326.

[0250] In some embodiments, one or more operations of method 1000A are performed to generate or place a first layout pattern on a layout design of method 1000A, and then one or more operations of method 1000A are repeated to generate or place other layout patterns on the layout design of method 1000A. In some embodiments, one or more operations of method 1000A are performed to generate or place a first layout design on a layout design of method 1000A, and then one or more operations of method 1000A are repeated to generate or place other layouts on the layout design of method 1000A.

[0251] In some embodiments, at least one or more operations of method 1000A are performed by, for example, Fig.12 In some embodiments, at least one method, such as method 1000A discussed above, is performed in whole or in part by at least one EDA system (including system 1200). In some embodiments, the EDA system may be used as Fig.13 Part of a design room of an IC manufacturing system 1300 .

[0252] One or more operations of method 1000A are performed by a processing device configured to execute instructions for fabricating an integrated circuit of method 1000A. In some embodiments, one or more operations of method 1000A are performed using the same processing device as used in a different one or more operations of method 1000A. In some embodiments, one or more operations of method 1000A are performed by a processing device different from the processing device used to perform the different one or more operations of method 1000A.

[0253] Fig. 10B 1 is a functional flow chart of a method for manufacturing an integrated circuit (IC) device according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1000B shown in FIG. 1, and only some other processes are briefly described here. In some embodiments, other operation sequences of the method 1000B are within the scope of the present disclosure. The method 1000B includes exemplary operations, but these operations are not necessarily performed in the order shown. According to the spirit and scope of the disclosed embodiments, operations may be appropriately added, replaced, reordered, and / or eliminated.

[0254] In some embodiments, method 1000B is an embodiment of operation 904 of method 900. In some embodiments, method 1000B may be used to manufacture or fabricate at least integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B ), or having at least the same layout design as 300B, 400B, 500C, 600C, 700A-700C or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) integrated circuits with similar characteristics.

[0255] In operation 1030 of method 1000B, a first well is fabricated in the substrate. In some embodiments, the first well extends in the second direction Y and has a first dopant type. In some embodiments, the first well of method 1000B includes at least P-well 204. In some embodiments, the substrate of method 1000B includes at least substrate 202.

[0256] In some embodiments, the first well includes a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well includes an epitaxial layer grown on substrate 202. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, after the epitaxial layer is formed, the epitaxial layer is doped by ion implantation. In some embodiments, the first well is formed by doping substrate 202. In some embodiments, the doping is performed by ion implantation. In some embodiments, the dopant concentration of the first well is between 1×10 12 Atom / cm 3 Up to 1×10 14 Atom / cm 3 within the range.

[0257] In operation 1032 of method 1000B, a drain region of a transistor is fabricated in the first well. In some embodiments, the drain region extends in the second direction Y and has a second dopant type. In some embodiments, the drain region of method 1000B includes at least drain region 212, a drain of transistor 260, or a drain of NMOS transistor N1. In some embodiments, the transistor of method 1000B includes at least transistor 260 or NMOS transistor N1.

[0258] In operation 1034 of method 1000B, a source region of the transistor is fabricated in the first well. In some embodiments, the source region extends in the second direction Y, has the second dopant type, and is separated from the drain region in the first direction X. In some embodiments, the source region of method 1000B includes at least source region 214, a source of transistor 260, or a source of NMOS transistor N1.

[0259] In some embodiments, at least operation 1032 or 1034 includes forming a source / drain component in the substrate. In some embodiments, the formation of the source / drain component includes removing a portion of the substrate to form a recess at the edge of each spacer 220a, 220b, and then performing a filling process by filling the recess in the substrate. In some embodiments, after removing the pad oxide layer or the sacrificial oxide layer, the recess is etched, for example, wet etching or dry etching. In some embodiments, an etching process is performed to remove a top surface portion of the active area adjacent to the isolation region (e.g., STI region 208 or 210). In some embodiments, the filling process is performed by epitaxy or epitaxy (epi). In some embodiments, the recess is filled using a growth process performed simultaneously with the etching process, wherein the growth rate of the etching process is greater than the etching rate of the etching process. In some embodiments, a combination of a growth process and an etching process is used to fill the recess. For example, a material layer is grown in the recess, and then an etching process is performed on the grown material to remove a portion of the material. Then, a subsequent growth process is performed on the etched material until the desired material thickness is reached in the recess. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, portions of the well 204 are removed by an isotropic or anisotropic etching process. The etching process selectively etches the well 204 without etching the gate structure 230 and the spacer 220. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching, or other suitable techniques. In some embodiments, semiconductor material is deposited in the recess to form a source / drain component. In some embodiments, an epitaxial process is performed to deposit the semiconductor material in the recess. In some embodiments, the epitaxial process includes a selective epitaxial growth (SEG) process, a CVD process, a molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxial process uses gaseous and / or liquid precursors that interact with the components of the substrate 202. In some embodiments, the source / drain component includes epitaxially grown silicon (epiSi), silicon carbide, or silicon germanium. In some examples, during the epitaxial process, the source / drain components of the IC device associated with the gate structure 230 are in-situ doped or undoped. If the source / drain components are not doped in the Epi process, in some cases the source / drain components are doped in a subsequent process. The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes and / or combinations thereof. In some embodiments, after forming the source / drain components and / or after the subsequent doping process, the source / drain components are also exposed to an annealing process.

[0260] In operation 1036 of method 1000B, a second well is fabricated in the first well. In some embodiments, the second well extends in the second direction Y and has a second dopant type. In some embodiments, the second well is adjacent to a portion of the drain region or one of the portions of the source region. In some embodiments, the second well of method 1000B includes at least N-well 206 or 506. In some embodiments, a plurality of wells are formed before forming the source region and the drain region. In some embodiments, the second well of method 1000B is formed before forming the source region and the drain region of method 1000B. For example, in some embodiments, operation 1036 is performed before operations 1032 and 1034. In some embodiments, operation 1036 is performed after operation 1030, and operations 1032 and 1034 are then performed after operation 1036.

[0261] In some embodiments, at least the second well, the fourth well (described below), or the fifth well (described below) includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the n-type dopant concentration is about 1×10 12 Atom / cm 2 About 1×10 14 Atom / cm 2 In some embodiments, at least the second well, the fourth well, or the fifth well is formed by ion implantation. The power range of the ion implantation is from about 1500k electron volts (eV) to about 8000k eV. In some embodiments, the depth of the double deep well 120 is in the range from about 5 microns (μm) to about 10 μm. In some embodiments, at least the second well, the fourth well, or the fifth well is epitaxially grown. In some embodiments, at least the second well, the fourth well, or the fifth well includes an epitaxial layer grown above the surface. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, after the epitaxial layer is formed, the epitaxial layer is doped by ion implantation and has the above-mentioned dopant concentration.

[0262] In operation 1038 of method 1000B, a gate region of the transistor is fabricated. In some embodiments, the gate region is between the drain region and the source region. In some embodiments, the gate region is above the first well and the substrate. In some embodiments, the gate region of method 1000B includes at least gate structure 230, a gate of transistor 260, or NMOS transistor N1.

[0263] In some embodiments, at least the gate region of manufacturing operation 1038 or the dummy gate region of manufacturing operation 1050 includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition process includes chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, manufacturing the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, manufacturing the gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, manufacturing the gate region includes depositing or growing at least one dielectric layer, such as gate dielectric 222. In some embodiments, the gate region is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, the gate region includes a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0264] In operation 1040 of method 1000B, a third well is fabricated in the first well. In some embodiments, the third well has a first dopant type extending in the second direction Y. In some embodiments, the third well surrounds the second well, the drain region, the source region, and the gate region. In some embodiments, the third well of method 1000B includes at least a P-well tap 216. In some embodiments, fabrication of the third well is similar to at least a portion of operation 1030, and thus similar descriptions are omitted.

[0265] In operation 1042 of method 1000B, a set of conductive regions are deposited over the IC. In some embodiments, operation 1042 includes depositing at least a first conductive region over the drain region to form a drain contact of transistor 260 or NMOS transistor N1, depositing a second conductive region over the source region to form a source contact of transistor 260 or NMOS transistor N1, depositing a third conductive region over the third well to form a tap contact of transistor 260 or NMOS transistor N1, depositing a fourth conductive region over the drain contact to couple the drain contact to IO pad region 108, or depositing a fifth conductive region over the source contact and the tap contact to couple the source contact, the tap contact, and the reference voltage source terminal 106 together. In some embodiments, the fourth conductive region of method 1000B is conductive region 270. In some embodiments, the fifth conductive region of method 1000B is conductive region 272.

[0266] In some embodiments, operation 1042 further includes depositing a sixth conductive region over the gate region to form a gate contact of the transistor 260 or the NMOS transistor N1 .

[0267] In some embodiments, the conductive region group of method 1000B is formed using a combination of photolithography and material removal processes to form an opening in an insulating layer (not shown) above the substrate. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an anti-reflective structure, or another suitable photolithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, an RIE process, laser drilling, or other suitable etching process. The opening is then filled with a conductive material such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material. In some embodiments, CVD, PVD, sputtering, ALD, or other suitable formation processes are used to fill the opening.

[0268] In operation 1044 of method 1000B, a fourth well is fabricated in the first well. In some embodiments, the fourth well has the second dopant type, extends in the second direction Y, and is separated from the second well in the first direction X. In some embodiments, the fourth well is adjacent to the other of a portion of the source region or a portion of the drain region. In some embodiments, the fourth well of method 1000B includes at least N-well 206 or 506.

[0269] In operation 1046 of method 1000B, a fifth well is fabricated in the first well. In some embodiments, the fifth well has a second dopant type, extends in a first direction X, and is separated from the second well in a second direction Y. In some embodiments, the fifth well is between the sides of the third well and the second well. In some embodiments, the fifth well is a corresponding well fabricated by at least well layout pattern 730a or 730b. In some embodiments, the fifth well is at least similar to N well 206 or 506, and similar detailed description is omitted.

[0270] In operation 1048 of method 1000B, a source region group and a drain region group are fabricated in the fourth well. In some embodiments, the source region group and the drain region group have a second dopant type and extend in the second direction Y. In some embodiments, the source region group of method 1000B is a corresponding source region fabricated at least by the active region layout pattern 812 or 814. In some embodiments, the drain region group of method 1000B is a corresponding source region fabricated at least by the active region layout pattern 812 or 814. In some embodiments, the drain region is similar to the drain region of transistor 260, and similar detailed description is omitted. In some embodiments, the source region is similar to the source of transistor 260, and similar detailed description is omitted.

[0271] In operation 1050 of method 1000B, a dummy gate region group is manufactured between the source region group and the drain region group. In some embodiments, the dummy gate region group extends in the second direction Y and is separated from each other in the first direction X. In some embodiments, the source region group, the drain region group, and the dummy gate region group correspond to a dummy transistor group. In some embodiments, the dummy gate region group of method 1000B is a corresponding dummy gate region manufactured by at least gate layout pattern group 830 or 840. In some embodiments, the dummy gate region is similar to the gate of transistor 260, and similar detailed description is omitted.

[0272] In some embodiments, at least one or more operations of method 1000B are performed to manufacture NMOS transistor N1, and these operations are similar to the above operations, so similar detailed descriptions are omitted. In some embodiments, one or more operations of method 1000B are performed to manufacture integrated circuits similar to integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B ) or an integrated circuit having at least the same layout design as 300B, 400B, 500C, 600C, 700A-700C or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) and then repeating one or more operations of method 1000B to manufacture integrated circuits similar to integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B ) or an integrated circuit having at least the same layout design as 300B, 400B, 500C, 600C, 700A-700C or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7Cor Figures 8A-8C ) integrated circuits with similar characteristics.

[0273] In some embodiments, at least one or more operations of method 1000B are performed by Fig.13 In some embodiments, at least one method, such as the method 1000B discussed above, is performed in whole or in part by at least one manufacturing system including the system 1300.

[0274] One or more operations of method 1000B are performed by IC manufacturer 1340 ( Fig.13 ) is performed to manufacture IC device 1360. In some embodiments, one or more operations of method 1000B are performed by manufacturing tool 1352 to manufacture wafer 1342.

[0275] Fig.11 1 is a flow chart of a method 1100 of operating a circuit according to some embodiments. In some embodiments, the circuit of method 1100 includes at least integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B ). It should be understood that additional operations may be performed before, during, and / or after the method 1100 shown in FIG. 1 , and only some other processes are briefly described here. It should be understood that the method 1100 utilizes the integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B )

[0276] In operation 1102 of method 1100 , an ESD voltage is applied to IO pad 108 . In some embodiments, the ESD voltage is greater than a power supply voltage VDD of voltage supply terminal 104 .

[0277] In operation 1104 , in response to applying an ESD voltage to IO pad 108 , a PN junction between drain region 212 of transistor 260 and P-well 204 is caused to be reverse biased until avalanche breakdown occurs.

[0278] In operation 1106, avalanche breakdown occurs in transistor 260, causing an increase in drain current in drain region 212 and generating holes that drift toward base 242 of a parasitic BJT, such as BJT 240. In some embodiments, operation 1106 also includes causing a voltage drop across base resistor Rb of BJT 240 in response to the flow of holes from the avalanche breakdown.

[0279] In operation 1108, in response to the increase in the voltage of the base 242 of the BJT 240, the base-emitter junction of the BJT 240 is forward biased. In some embodiments, operation 1108 also includes causing the substrate current of the holes to flow to the P-well tap 216 of the P-well 204 in the substrate 202, thereby also increasing the base-emitter voltage of the parasitic NPN BJT (e.g., BJT 240). For example, as described with respect to Figure 2B As described, since the low voltage level (e.g., voltage VSS) of reference voltage terminal 106 is coupled to P-well tap 216, the substrate current of holes flows to P-well tap 216 of P-well 204 in substrate 202. The current of holes flowing in P-well 204 and / or substrate 202 increases the voltage drop across base resistor Rb, thereby increasing the base-emitter voltage Vbe of the parasitic NPN BJT (e.g., BJT 240). For example, as described above in Figure 2A-2B As discussed in , adding N-well 206 in at least P-well 204 or on substrate 202 increases the base resistance Rb of BJT 240 or transistor 260 compared to other methods. Therefore, the increased base resistance Rb of BJT 240 causes the base-emitter voltage Vbe of the parasitic NPN BJT (e.g., BJT 240) to increase faster than other methods.

[0280] In operation 1110, a parasitic NPN BJT (e.g., BJT 240) is turned on in response to the base-emitter voltage being equal to or greater than the threshold voltage, thereby causing the ESD current I1 and / or the ESD voltage on the IO pad 108 to be discharged to the reference voltage terminal 106 through the turned-on parasitic NPN BJT. Therefore, the high ESD current I1 from the ESD event is redirected away from the gate structure 230 of the transistor 260. In some embodiments, because the base resistance Rb of the BJT 240 is increased by adding the N-well 206 in at least the P-well 204 or on the substrate 202, the base-emitter voltage Vbe rises faster toward the threshold voltage Vth of the BJT 240, thereby causing the BJT 240 to turn on earlier at the reduced ESD trigger voltage Vth, and the ESD voltage on the IO pad 108 is discharged faster than other methods.

[0281] In some embodiments, at least one or more operations of method 900, 1000A, or 1100 are not performed. FIG. 2A to FIG. 2B Method 1100 is described. It should be understood that method 1100 utilizes Figure 1A-1B and Figure 3A-8C In some embodiments, other operations of method 1100 are performed according to the description and operation of integrated circuit 200A or equivalent circuit 200B.

[0282] At least integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3B ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B ) other transistor types or other numbers of transistors are within the scope of the present disclosure.

[0283] Fig.121 is a schematic diagram of a system 1200 for designing an IC layout design and manufacturing an IC circuit according to some embodiments. In some embodiments, the system 1200 generates or places one or more IC layout designs described herein. The system 1200 includes a hardware processor 1202 and a non-transitory computer-readable storage medium 1204 (e.g., memory 1204) encoded (i.e., storing) with a computer program code 1206 (i.e., a set of executable instructions 1206). The computer-readable storage medium 1204 is configured to interface with a manufacturing machine for producing integrated circuits. The processor 1202 is electrically coupled to the computer-readable storage medium 1204 via a bus 1208. The processor 1202 is also electrically coupled to an I / O interface 1210 via the bus 1208. The network interface 1212 is also electrically coupled to the processor 1202 via the bus 1208. The network interface 1212 is connected to a network 1214 so that the processor 1202 and the computer-readable storage medium 1204 can be connected to external elements via the network 1214. The processor 1202 is configured to execute computer program code 1206 encoded in the computer-readable storage medium 1204 so as to enable the system 1200 to perform at least part or all of the operations in the method 900 or 1000A.

[0284] In some embodiments, processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0285] In some embodiments, computer readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, computer readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disks, computer readable storage medium 1204 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0286] In some embodiments, storage medium 1204 stores computer program code 1206 configured to cause system 1200 to perform at least method 900 or 1000A. In some embodiments, storage medium 1204 also stores information required to perform at least method 900 or 1000A and information generated during the performance of at least method 900 or 1000A, such as layout design 1216, user interface 1218, and manufacturing unit 1220 and / or a set of executable instructions to perform at least the operations of method 900 or 1000A. In some embodiments, layout design 1216 includes at least one layout design 300B, 400B, 500C, 600C, 700A-700C, or 800A-800C ( Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figures 7A-7C or Figures 8A-8C ) in one or more layout patterns.

[0287] In some embodiments, storage medium 1204 stores instructions (e.g., computer program code 1206) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1206) enable processor 1202 to generate manufacturing instructions readable by the manufacturing machine to effectively implement at least method 900 or 1000A in a manufacturing process.

[0288] System 1200 includes an I / O interface 1210. I / O interface 1210 is coupled to external circuitry. In some embodiments, I / O interface 1210 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to processor 1202.

[0289] The system 1200 also includes a network interface 1212 coupled to the processor 1202. The network interface 1212 allows the system 1200 to communicate with a network 1214 to which one or more other computer systems are connected. The network interface 1212 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, at least the method 900 or 1000A is implemented in two or more systems 1200, and information such as layout design and user interface is exchanged between different systems 1200 via the network 1214.

[0290] The system 1200 is configured to receive information related to the layout design through the I / O interface 1210 or the network interface 1212. The information is transmitted to the processor 1202 through the bus 1208 to determine the layout design for generating an integrated circuit (e.g., an integrated circuit), such as the integrated circuits 100A-100B, 200A, 400A, 500A, 600A ( Figure 1A-1B , Figure 2A , Figure 4A , Figure 5A or Fig. 6A ), snapback device array 300A ( Figure 3A ) or equivalent circuit 200B( Figure 2B )、500B( Figure 5B ) or 600B( Figure 6B ). The layout design is then stored in computer-readable medium 1204 as layout design 1216. System 1200 is configured to receive information related to the user interface through I / O interface 1210 or network interface 1212. The information is stored in computer-readable medium 1204 as user interface 1200. System 1200 is configured to receive information related to the manufacturing unit through I / O interface 1210 or network interface 1212. The information is stored in computer-readable medium 1204 as manufacturing unit 1220. In some embodiments, manufacturing unit 1220 includes manufacturing information used by system 1200. In some embodiments, manufacturing unit 1220 includes at least Fig.13 Mask manufacturing 1334 or IC manufacturer 1340

[0291] In some embodiments, at least method 900 or 1000A is implemented as a standalone software application for execution by a processor. In some embodiments, at least method 900 or 1000A is implemented as a software application as part of an additional software application. In some embodiments, at least method 900 or 1000A is implemented as a plug-in for a software application. In some embodiments, at least method 900 or 1000A is implemented as a software application as part of an EDA tool. In some embodiments, at least method 900 or 1000A is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, a layout is generated using a tool such as that available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool. In some embodiments, a layout is generated based on a netlist created based on a schematic design. In some embodiments, at least part of at least one method 900 or 1000A is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by the system 1200. In some embodiments, system 1200 is a manufacturing device that uses a mask set manufactured based on one or more layout designs of the present disclosure to manufacture an integrated circuit. In some embodiments, Fig.12 The system 1200 produces a layout design of an integrated circuit that is smaller than other methods. In some embodiments, Fig.12 The system 1200 generates a layout design of an integrated circuit structure that occupies less area and provides better routing resources than other methods.

[0292] Fig.13 1 is a block diagram of an integrated circuit (IC) manufacturing system 1300 and an IC manufacturing process associated therewith according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, the manufacturing system 1300 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0293] exist Fig.13In the present invention, an IC manufacturing system 1300 (hereinafter referred to as "system 1300") includes entities that interact with each other in the design, development, manufacturing cycle and / or services related to manufacturing IC devices 1360, such as a design room 1320, a mask room 1330, and an IC manufacturer / fab ("fab") 1340. The entities in the system 1300 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more of the other entities. In some embodiments, one or more of the design room 1320, the mask room 1330, and the IC fab 1340 are owned by a single larger company. In some embodiments, one or more of the design room 1320, the mask room 1330, and the IC fab 1340 coexist in a common facility and use common resources.

[0294] The design office (or design team) 1320 generates an IC design layout 1322. The IC design layout 1322 includes various geometric patterns designed for the IC device 1360. The geometric patterns correspond to various components of the IC device 1360 to be manufactured by the patterns constituting the metal layer, oxide layer or semiconductor layer. The various layers are combined to form various IC functions. For example, parts of the IC design layout 1322 include various IC components, such as active areas, gate electrodes, source electrodes and drain electrodes, metal lines or through holes for interlayer interconnection, and openings for pads, which will be formed on a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 1320 implements an appropriate design process to form the IC design layout 1322. The design process includes one or more of a logical design, a physical design or a layout and routing. The IC design layout 1322 is presented in one or more data files with geometric pattern information. For example, the IC design layout 1322 can be expressed in a GDSII file format or a DFII file format.

[0295] The mask room 1330 includes data preparation 1332 and mask manufacturing 1334. The mask room 1330 uses the IC design layout 1322 to manufacture one or more masks 1345, which are used to manufacture various layers of the IC device 1360 based on the IC design layout 1322. The mask room 1330 performs mask data preparation 1332, wherein the IC design layout 1322 is translated into a representative data file ("RDF"). The mask data preparation 1332 provides the RDF to the mask manufacturing 1334. The mask manufacturing 1334 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1345 or a semiconductor wafer 1342. The design layout 1322 is controlled by the mask data preparation 1332 to conform to specific characteristics of the mask writer and / or requirements of the IC wafer factory 1340. In Fig.13 , mask data preparation 1332 and mask manufacturing 1334 are shown as separate elements. In some embodiments, mask data preparation 1332 and mask manufacturing 1334 may be collectively referred to as mask data preparation.

[0296] In some embodiments, mask data preparation 1332 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects (such as OPC adjusts IC design layout 1322), etc. In some embodiments, mask data preparation 1332 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0297] In some embodiments, mask data preparation 1332 includes a mask rule checker (MRC) that checks an IC design layout that has been processed in OPC using a set of mask creation rules that contain some geometry and / or connectivity constraints to ensure sufficient margin to account for issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 1334, which may undo portions of the modifications performed by the OPC to satisfy the mask creation rules.

[0298] In some embodiments, mask data preparation 1332 includes a lithography process check (LPC), which simulates the process to be implemented by IC fab 1340 to manufacture IC device 1360. LPC simulates the process based on IC design layout 1322 to create a simulated manufactured product. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or a combination thereof. In some embodiments, after a simulated manufactured device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further improve the IC design layout 1322.

[0299] It should be understood that the above description of mask data preparation 1332 has been simplified for clarity. In some embodiments, data preparation 1332 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. In addition, the processing applied to IC design layout 1322 during data preparation 1332 can be performed in a variety of different orders.

[0300] After mask data preparation 1332 and during mask manufacturing 1334, a mask 1345 or a mask set 1345 is manufactured based on the modified IC design layout 1322. In some embodiments, mask manufacturing 1334 includes performing one or more photolithographic exposures based on the IC design 1322. In some embodiments, based on the modified IC design layout 1322, a pattern is formed on a mask (photomask or reticle) 1345 using an electron beam (e-beam) or a mechanism of multiple electron beams. The mask 1345 can be formed with various techniques. In some embodiments, the mask 1345 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary form 1345 of the mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated in the opaque area of ​​the binary mask. In another example, a mask 1345 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1345, various features in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The masks produced by mask manufacturing 1334 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, such masks are used in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0301] IC fab 1340 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 1340 is a semiconductor foundry. For example, there may be one manufacturing plant for front-end manufacturing (FEOL) of multiple IC products, while a second manufacturing plant may provide back-end manufacturing (BEOL) IC products for interconnection and packaging, and a third manufacturing plant may provide other services for the foundry entity.

[0302] IC fab 1340 includes a wafer fabrication tool 1352 (hereinafter referred to as "fabrication tool 1352") configured to perform various fabrication operations on semiconductor wafer 1342, thereby fabricating IC device 1360 according to a mask (e.g., mask 1345). In various embodiments, fabrication tool 1352 includes one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication devices capable of performing one or more suitable fabrication processes described herein.

[0303] IC fab 1340 uses mask 1345 made by mask cover 1330 to manufacture IC device 1360. Therefore, IC fab 1340 at least indirectly uses IC design layout 1322 to manufacture IC device 1360. In some embodiments, semiconductor wafer 1342 is formed into IC device 1360 by IC fab 1340 using mask 1345. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based at least indirectly on IC design 1322. Semiconductor wafer 1342 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 1342 also includes one or more of various doped regions, dielectric components, multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0304] System 1300 is shown with design chamber 1320, mask chamber 1330, or IC fab 1340 as separate components or entities. However, it should be understood that one or more of design chamber 1320, mask chamber 1330, or IC fab 1340 are part of the same component or entity.

[0305] With respect to integrated circuit (IC) manufacturing systems (e.g., Fig.13 Details of the system 1300 and the IC manufacturing process associated therewith are found, for example, in U.S. Patent No. 9,256,709 issued on February 9, 2016, Pre-grant Publication No. 20150278429 issued on October 1, 2015, U.S. Pre-grant Publication No. 20140040838 issued on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0306] For example, in U.S. Pat. No. 9,256,709, an IC design layout is generated in a design house (or design team). The IC design layout includes various geometric patterns designed for IC devices. The geometric patterns correspond to the patterns of metal, oxide or semiconductor layers that constitute the various components of the IC device to be manufactured. The various layers are combined to form various IC functions. For example, parts of the IC design layout include various IC components, such as active areas, gate electrodes, source and drain, metal lines or vias for interlayer interconnection, and openings for pads formed in semiconductors, which will be formed in semiconductor substrates (e.g., silicon wafers) and various material layers disposed on the semiconductor substrate. The design house performs appropriate design processes to form the IC design layout. The design process may include logic design, physical design and / or layout and wiring. The IC design layout is presented in one or more data files with geometric pattern information. The mask house uses the IC design layout to manufacture one or more masks, which are used to manufacture the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer, wherein the design layout prepared by the mask data preparation is modified to comply with a specific mask manufacturer and / or mask vendor, and then manufactured. In the present embodiment, mask data preparation and mask manufacturing are illustrated as separate elements, however, mask data preparation and mask manufacturing can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has been processed in OPC, which mask creation rules may contain some geometric and connectivity restrictions to ensure sufficient margin.

[0307] For example, in U.S. pre-grant publication No. 20150278429, in one embodiment, an IC manufacturing system can employ maskless lithography, such as electron beam lithography or optical maskless lithography. In such a system, mask manufacturing is bypassed, and the IC design layout is modified by data preparation suitable for wafer processing using a specific maskless lithography technology. Data preparation modifies the design layout suitable for subsequent operations in the IC manufacturing system. The result of data preparation is represented by one or more data files, such as files in a GDSII file format or a DFII file format. One or more data files include information of geometric patterns, such as polygons representing main design patterns and / or auxiliary components. In the present embodiment, one or more data files also include auxiliary data generated by data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask manufacturing performed by a mask room and wafer exposure performed by an IC manufacturer.

[0308] For example, in pre-grant announcement No. 20140040838, the IC design layout is presented in one or more data files with geometric pattern information. In one example, the IC design layout is represented in a "GDS" format known in the art. In an alternative embodiment, the IC design layout can be transmitted between components in an IC manufacturing system in an alternative file format such as DFII, CIF, OASIS or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include major IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines, interlayer interconnection vias, and openings for pads formed in semiconductors, which will be formed in semiconductor substrates (e.g., silicon wafers) and various material layers disposed on semiconductor substrates. The IC design layout may also include some auxiliary components, such as those used for imaging effects, processing enhancements and / or mask identification information.

[0309] For example, in U.S. Pat. No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; a controller, coupled to the processing tool and the metrology tool, for generating a manufacturing model of the processing tool and calibrating the manufacturing model according to the equipment data, material data, and inspection results of the mask. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs a post-etch inspection or a post-strip inspection and obtains a post-etch inspection result or a post-strip inspection result, respectively. The controller is used for run-to-run control of the processing tool, including feedforward control and feedback control. The controller receives the post-etch or post-strip inspection results from the metrology tool and retrieves the device and material data from the database. The controller connected to the manufacturing execution system generates a manufacturing model of the processing tool and calibrates the manufacturing model according to the equipment data, material data, and inspection results of the mask. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0310] also, Figure 1A-Figure 13 The various PMOS transistors shown in FIG. 1 have specific dopant types (e.g., N-type or P-type) and are for illustration purposes only. The embodiments of the present disclosure are not limited to specific transistor types, and Figure 1A-Figure 13 One or more of the PMOS or NMOS transistors shown in the figure may be replaced with corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also used for illustration. The embodiments of the present disclosure are not limited to specific logic values ​​when the signals are activated and / or deactivated. It is within the scope of the various embodiments to select different logic values. Figure 1A-Figure 13 Selecting a different number of PMOS transistors is within the scope of various embodiments.

[0311] One aspect of the present specification relates to an ESD protection circuit. The snapback ESD protection circuit includes: a first well located in a substrate, the first well having a first dopant type; a drain region of a transistor, the drain region being in the first well and having a second dopant type different from the first dopant type; a source region of the transistor, the source region being in the first well, having a second dopant type and being separated from the drain region in a first direction; a gate region of the transistor, the gate region being above the first well and the substrate; and a second well embedded in the first well and adjacent to a portion of the drain region, the second well having a second dopant type.

[0312] In the above snapback ESD protection circuit, it further includes: a tap well located in the first well and having a first dopant type.

[0313] In the above snapback ESD protection circuit, it further includes: an input / output (IO) pad coupled to the drain region; and a reference power supply voltage terminal coupled to the source region and the tap well.

[0314] The above-mentioned snapback ESD protection circuit also includes: a parasitic bipolar junction transistor (BJT), which is located in the first well, the parasitic BJT having a base, a collector and an emitter, the collector is coupled to the IO pad through the drain region, and the emitter is coupled to the source region; and a parasitic base resistor of the first well and the substrate, the parasitic base resistor having a first end coupled to a reference power supply voltage terminal through the tapped well, and a second end coupled to the base of the parasitic BJT, wherein the parasitic BJT is configured to be turned on in response to the base-emitter voltage of the parasitic BJT being equal to or greater than a threshold voltage applied from the ESD voltage to the IO pad, thereby discharging the ESD voltage to the reference power supply voltage terminal through the parasitic BJT.

[0315] In the above snapback ESD protection circuit, the gate region is coupled to the source region, the tap well, and the reference power supply voltage terminal.

[0316] In the above snapback ESD protection circuit, the first well has a first width in the first direction, and the second well has a second width in the first direction, the second width being smaller than the first width.

[0317] In the above snapback ESD protection circuit, it further includes: a third well embedded in the first well, the third well has the second dopant type and is adjacent to a portion of the source region.

[0318] In the above snapback ESD protection circuit, the third well has a third width in the first direction, and the third width is different from at least the first width or the second width.

[0319] In the above snapback ESD protection circuit, the transistor corresponds to the driver circuit, the gate region corresponds to the gate of the driver circuit; the drain region corresponds to the drain of the driver circuit; and the source region corresponds to the source of the driver circuit.

[0320] Another aspect of the present specification relates to an ESD protection circuit. In some embodiments, the ESD protection circuit includes: a first well located in a substrate, the first well having a first dopant type; a drain region of a first transistor, the drain region located in the first well and having a second dopant type different from the first dopant type; a source region of the first transistor, the source region in the first well, having a second dopant type and separated from the drain region in a first direction; a gate region of the first transistor, the gate region above the first well and the substrate; a second well embedded in the first well and adjacent to a portion of the source region, and the second well having a second dopant type; and a tap well located in the first well and having the first dopant type and coupled to the source region.

[0321] In the above ESD protection circuit, it further includes: an input / output (IO) pad coupled to the drain region; and a reference power supply voltage terminal coupled to the source region and the tap well.

[0322] In the above ESD protection circuit, the gate region is coupled to the source region, the tap well, and the reference power supply voltage terminal.

[0323] In the above-mentioned ESD protection circuit, it also includes: a parasitic bipolar junction transistor (BJT), which is located in the first well, the parasitic BJT has a base, a collector and an emitter, the collector is coupled to the IO pad through the drain region, and the emitter is coupled to the source region; and a parasitic base resistor of the first well and the substrate, the parasitic base resistor has a first end coupled to the reference power supply voltage terminal through the tapped well, and a second end coupled to the base of the parasitic BJT, wherein the parasitic BJT is configured to respond to the base-emitter voltage of the parasitic BJT being equal to or greater than the threshold voltage applied from the ESD voltage to the IO pad, thereby discharging the ESD voltage to the reference power supply voltage terminal through the parasitic BJT.

[0324] In the above-mentioned ESD protection circuit, it also includes: a second transistor, connected in parallel with the first transistor, the second transistor corresponds to the driver circuit, and the second transistor includes: a gate of the second transistor, configured to receive a driver signal; a drain of the second transistor, coupled to the IO pad and the drain region of the first transistor; a body of the second transistor; and a source of the second transistor, coupled to the body of the second transistor, a reference power supply voltage terminal and the source region of the first transistor.

[0325] In the above-mentioned ESD protection circuit, it also includes: a parasitic capacitance between the gate of the second transistor and the drain of the second transistor, wherein the gate of the second transistor is coupled to the drain of the second transistor and the IO pad capacitance through the parasitic capacitance, and during a positive ESD event, the gate receives the ESD voltage applied to the IO pad through the parasitic capacitance, thereby causing the second transistor to turn on and generate a channel current in the first well.

[0326] In the above ESD protection circuit, the first well has a first width in the first direction, and the second well has a second width in the first direction, the second width being smaller than the first width.

[0327] Another aspect of the present specification relates to a method of manufacturing a snapback electrostatic discharge (ESD) protection circuit. In some embodiments, the method includes: manufacturing a first well in a substrate, the first well extending in a first direction and having a first dopant type; manufacturing a drain region of a transistor in the first well, the drain region extending in the first direction and having a second dopant type different from the first dopant type; manufacturing a source region of the transistor in the first well, the source region extending in the first direction, having a second dopant type, and being separated from the drain region in a second direction different from the first direction; manufacturing a second well in the first well, the second well extending in the first direction, having a second dopant type, and being adjacent to a portion of the drain region, and manufacturing a gate region of the transistor, the gate region being between the drain region and the source region, and being above the first well and the substrate.

[0328] In the above method, it also includes: manufacturing a third well in the first well, the third well having a first dopant type, extending in the first direction, and surrounding the second well, the drain region, the source region and the gate region; depositing a first conductive region above the drain region to form a drain contact; depositing a second conductive region above the source region to form a source contact; depositing a third conductive region above the third well to form a tap contact; depositing a fourth conductive region above the drain contact to couple the drain contact to an input / output (IO) pad region; and depositing a fifth conductive region above the source contact and the tap contact to couple the source contact, the tap contact and the reference power supply voltage terminal together.

[0329] In the above method, it also includes: manufacturing a fourth well in the first well, the fourth well has the second dopant type, extends in the first direction, and is separated from the second well in the second direction, and the fourth well is adjacent to a portion of the source region.

[0330] In the above method, it also includes: manufacturing a fourth well in the first well, the fourth well has the second dopant type, extends in the second direction, and is separated from the second well in the first direction, and the fourth well is between the sides of the third well and the second well; manufacturing a source region group and a drain region group in the fourth well, the source region group and the drain region group have the second dopant type and extend in the first direction; and manufacturing a dummy gate region group between the source region group and the drain region group, the dummy gate region group extends in the first direction and is separated from each other in the second direction, the source region group, the drain region group and the dummy gate region group correspond to a dummy transistor group.

[0331] Another aspect of the present specification relates to a method for manufacturing a snapback ESD protection circuit. The method includes generating a layout design of the snapback ESD protection circuit by a processor, and manufacturing the snapback ESD protection circuit based on the layout design of the snapback ESD protection circuit. In some embodiments, generating the layout design of the snapback ESD protection circuit includes: generating a first active area layout pattern extending in a first direction and in a first layout level, the first active area layout pattern corresponding to manufacturing a snapback ESD protection circuit in a p-type well. In some embodiments, generating the layout design of the snapback ESD protection circuit also includes generating a second active area layout pattern extending along the first direction and in the first layout layer, the second active area layout pattern corresponding to manufacturing a snapback ESD protection circuit in a p-well. In some embodiments, generating the layout design of the snapback ESD protection circuit also includes: generating a first well layout pattern extending in a second direction different from the first direction, in the second layout layer and above the first active area layout pattern, the first well layout pattern corresponding to manufacturing a first n-well of the snapback ESD protection circuit, the first n-well being embedded in the p-well and adjacent to a portion of the drain region.

[0332] However, another aspect of the present specification relates to a method for manufacturing a snapback ESD protection circuit. The method includes: placing a layout design of an array of snapback ESD protection circuits by a processor; and manufacturing an array of snapback ESD protection circuits based on the layout design of the array of snapback ESD protection circuits. In some embodiments, the layout design of the array of snapback ESD protection circuits includes placing a first active area layout pattern in a first layout level, the first active area layout pattern extending in a first direction, and corresponding to the first snapback ESD protection circuit in the array of snapback ESD protection circuits in the manufacturing p-well. In some embodiments, the layout design of the array of snapback ESD protection circuits also includes placing a second active area layout pattern in the first layout level, the second active area layout pattern extending in the first direction, and corresponding to the first snapback ESD protection circuit in the array of snapback ESD protection circuits in the manufacturing p-well. In some embodiments, the layout design for placing the snap-back ESD protection circuit array also includes placing a first well layout pattern on the first active area layout pattern or the second active area layout pattern, and in a second layout level, the first well layout pattern extends in a second direction different from the first direction and corresponds to a first n-well for manufacturing a first snap-back ESD protection circuit in the snap-back ESD protection circuit array, the first n-well being embedded in the p-well and adjacent to a portion of the drain region or the source region.

[0333] A number of embodiments have been described. However, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. For example, various transistors (e.g., N-type or P-type metal oxide semiconductor (NMOS or PMOS)) shown as specific dopant types are for illustrative purposes. The embodiments of the present disclosure are not limited to specific types. It is within the scope of various embodiments to select different dopant types for specific transistors. The low or high logic values ​​of the various signals used in the above description are also used for illustration. When the signal is activated and / or deactivated, the various embodiments are not limited to specific logic values. It is within the scope of various embodiments to select different logic values. In various embodiments, the transistor is used as a switch. A switch circuit used instead of a transistor is within the scope of various embodiments. In various embodiments, the source of the transistor may be configured as a drain, and the drain may be configured as a source. In this way, the terms source and drain are used interchangeably. Various signals are generated by corresponding circuits, but for simplicity, the circuits are not shown.

[0334] Various drawings show capacitive circuits for illustration using discrete capacitors. Equivalent circuits may be used. For example, capacitive devices, circuits, or networks (e.g., combinations of capacitors, capacitive elements, devices, circuits, etc.) may be used instead of discrete capacitors. The above illustrations include exemplary steps, but the steps are not necessarily performed in the order shown. Steps may be appropriately added, replaced, changed in order, and / or eliminated, according to the spirit and scope of the disclosed embodiments.

[0335] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A snapback electrostatic discharge protection circuit, comprising: a first well located in the substrate, the first well having a first dopant type; a drain region of a transistor, the drain region being in the first well and having a second dopant type different from the first dopant type; a source region of the transistor, the source region being in the first well, having the second dopant type, and being separated from the drain region in a first direction; a gate region of the transistor, the gate region being above the first well and the substrate; as well as a second well embedded in the first well and adjacent to a portion of the drain region, the second well having the second dopant type; as well as A third well is embedded in the first well, the third well has the second dopant type and is adjacent to a portion of the source region, a top surface of the third well being flush with a top surface of the first well and a top surface of the source region.

2. The snapback electrostatic discharge protection circuit according to claim 1, further comprising: A tap well is located in the first well and has the first dopant type.

3. The snapback electrostatic discharge protection circuit according to claim 2, further comprising: an input / output pad coupled to the drain region; as well as A reference power supply voltage terminal is coupled to the source region and the tap well.

4. The snapback electrostatic discharge protection circuit according to claim 3, further comprising: a parasitic bipolar junction transistor located in the first well, the parasitic bipolar junction transistor having a base, a collector and an emitter, the collector being coupled to the input / output pad through the drain region, and the emitter being coupled to the source region; and a parasitic base resistor of the first well and the substrate, the parasitic base resistor having a first end coupled to the reference power supply voltage terminal through the tapped well and a second end coupled to the base of the parasitic bipolar junction transistor, Wherein, the parasitic bipolar junction transistor is configured to be turned on in response to a base-emitter voltage of the parasitic bipolar junction transistor being equal to or greater than a threshold voltage applied from an electrostatic discharge voltage to the input / output pad, thereby discharging the electrostatic discharge voltage to the reference power supply voltage terminal through the parasitic bipolar junction transistor.

5. The snapback electrostatic discharge protection circuit according to claim 3, wherein: The gate region is coupled to the source region, the tap well, and the reference supply voltage terminal.

6. The snapback electrostatic discharge protection circuit according to claim 1, wherein The first well has a first width in the first direction, and The second well has a second width in the first direction, and the second width is smaller than the first width.

7. The snapback electrostatic discharge protection circuit according to claim 6, wherein: A top surface of the second well is flush with a top surface of the first well and a top surface of the source region.

8. The snapback electrostatic discharge protection circuit according to claim 7, wherein: The third well has a third width in the first direction, and the third width is different from at least the first width or the second width.

9. The snapback electrostatic discharge protection circuit according to claim 1, wherein The transistor corresponds to a driver circuit, The gate region corresponds to a gate of the driver circuit; The drain region corresponds to a drain of the driver circuit; and The source region corresponds to a source of the driver circuit.

10. An electrostatic discharge protection circuit, comprising: a first well located in the substrate, the first well having a first dopant type; a drain region of a first transistor, the drain region being located in the first well and having a second dopant type different from the first dopant type, the drain region being connected to an input / output pad; a source region of the first transistor, the source region being in the first well, having the second dopant type, and being separated from the drain region in a first direction; a gate region of the first transistor, the gate region being above the first well and the substrate; a second well embedded in the first well and adjacent to a portion of the source region, the second well having the second dopant type; as well as a tap well located in the first well and having the first dopant type and coupled to the source region; A second transistor is connected in parallel with the first transistor, the second transistor corresponds to a driver circuit, and the second transistor includes: a gate of the second transistor configured to receive a driver signal; a drain of the second transistor coupled to the input / output pad and the drain region of the first transistor; a parasitic capacitance between the gate of the second transistor and the drain of the second transistor, During a positive electrostatic discharge event, the gate of the second transistor receives the electrostatic discharge voltage applied to the input / output pad through the parasitic capacitor.

11. The electrostatic discharge protection circuit according to claim 10, further comprising: A reference power supply voltage terminal is coupled to the source region and the tap well.

12. The electrostatic discharge protection circuit according to claim 11, wherein The gate region is coupled to the source region, the tap well, and the reference supply voltage terminal.

13. The electrostatic discharge protection circuit according to claim 11, further comprising: a parasitic bipolar junction transistor located in the first well, the parasitic bipolar junction transistor having a base, a collector and an emitter, the collector being coupled to the input / output pad through the drain region, and the emitter being coupled to the source region; and a parasitic base resistor of the first well and the substrate, the parasitic base resistor having a first end coupled to the reference power supply voltage terminal through the tapped well and a second end coupled to the base of the parasitic bipolar junction transistor, Wherein, the parasitic bipolar junction transistor is configured to discharge the electrostatic discharge voltage to the reference power supply voltage terminal through the parasitic bipolar junction transistor in response to a base-emitter voltage of the parasitic bipolar junction transistor being equal to or greater than a threshold voltage applied from an electrostatic discharge voltage to the input / output pad.

14. The electrostatic discharge protection circuit according to claim 11, further comprising: a body of the second transistor; as well as A source of the second transistor is coupled to the body of the second transistor, the reference supply voltage terminal, and the source region of the first transistor.

15. The electrostatic discharge protection circuit according to claim 14, in, The gate of the second transistor is coupled to the drain of the second transistor and the input / output pad capacitance through the parasitic capacitance, causing the second transistor to turn on and generate a channel current in the first well during the positive electrostatic discharge event.

16. The electrostatic discharge protection circuit according to claim 10, wherein: The first well has a first width in the first direction, and The second well has a second width in the first direction, and the second width is smaller than the first width.

17. A method for manufacturing a snapback electrostatic discharge protection circuit, the method comprising: fabricating a first well in a substrate, the first well extending in a first direction and having a first dopant type; fabricating a drain region of a transistor in the first well, the drain region extending in the first direction and having a second dopant type different from the first dopant type; fabricating a source region of the transistor in the first well, the source region extending in the first direction, having the second dopant type, and being separated from the drain region in a second direction different from the first direction; fabricating a second well in the first well, the second well extending in the first direction, having the second dopant type and adjacent to a portion of the drain region, manufacturing a gate region of the transistor, the gate region being between the drain region and the source region and above the first well and the substrate; fabricating a third well in the first well, the third well having the first dopant type, extending in the first direction, and surrounding the second well, the drain region, the source region, and the gate region; fabricating a fourth well in the first well, the fourth well having the second dopant type, extending in the second direction and separated from the second well in the first direction, the fourth well being between the third well and the side of the second well; Producing a source region group and a drain region group in the fourth well, the source region group and the drain region group having the second dopant type and extending in the first direction; as well as A dummy gate region group is fabricated between the source region group and the drain region group, the dummy gate region groups extend in the first direction and are separated from each other in the second direction, the source region group, the drain region group, and the dummy gate region group corresponding to a dummy transistor group.

18. The method according to claim 17, further comprising: depositing a first conductive region over the drain region to form a drain contact; depositing a second conductive region over the source region to form a source contact; depositing a third conductive region over the third well to form a tap contact; depositing a fourth conductive region over the drain contact to couple the drain contact to an input / output pad region; and A fifth conductive region is deposited over the source contact and the tap contact to couple the source contact, the tap contact, and a reference supply voltage terminal together.

19. The method of claim 18, wherein: A top surface of the second well is flush with a top surface of the first well and a top surface of the source region.

20. The method of claim 18, wherein: In the second direction, a width of the third well is different from a width of the second well and a width of the first well.

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