Bidirectional power device and method of manufacturing the same

Abstract

The application discloses a bidirectional power device and a manufacturing method thereof. The bidirectional power device comprises a semiconductor layer, a first doped region in the semiconductor layer, a plurality of trenches in a first trench region, the first doped region being divided into first and second sub-doped regions alternately, a gate dielectric layer covering lower sidewalls of the plurality of trenches in the first trench region, a control gate in the lower part of the plurality of trenches in the first trench region and in contact with the gate dielectric layer, a shielding dielectric layer covering upper sidewalls of the plurality of trenches in the first trench region and on the surface of the control gate, and a first shielding gate in the plurality of trenches in the first trench region and in contact with the shielding dielectric layer. The shielding dielectric layer separates the control gate and the first shielding gate, and the thickness of the shielding dielectric layer on the upper sidewalls of the trenches in the first trench region is inconsistent, so that different voltages can be applied through the gate electrode to achieve the effect of forming different electric fields.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically, to a bidirectional power device and a method for manufacturing the same. Background Technology

[0002] Bidirectional power devices are widely used in charging devices with secondary charging capabilities. Taking a lithium battery charging and discharging device as an example, when the lithium battery charging and discharging device continuously supplies power to the terminal device to a certain level, it is necessary to prevent the lithium battery from over-discharging to avoid the terminal device stopping operation, and it is also necessary to charge the lithium battery in a timely manner. During the charging process, the lithium battery also needs to supply power to the terminal device, while preventing overcharging of the lithium battery. Therefore, in order to manage and control the charging and discharging state of the lithium battery, a charging and discharging protection circuit with bidirectional switching control of current conduction is usually used.

[0003] like Figure 1 As shown, the initial charge / discharge protection circuit uses two single-cell planar gate NMOS transistors M1 and M2 connected to their drains as bidirectional switches. During charging, a high voltage is applied to the gate G1 of M1, turning M1 on, and a low voltage is applied to the gate G2 of M2, turning M2 off. At this time, the current first flows through the parasitic diode D2 of M2 from its source S2 to its drain, and then from the drain of M1 to its source S1. During discharging, a low voltage is applied to the gate G1 of M1, turning M1 off, and a high voltage is applied to the gate G2 of M2, turning M2 on. At this time, the current first flows through the parasitic diode D1 of M1 from its source S1 to its drain, and then from the drain of M2 to its source S2. However, the planar gate NMOS process requires sufficient area to meet higher voltage withstand requirements, and the device has very low conduction efficiency and high power consumption.

[0004] Therefore, it is hoped that the structure of bidirectional power devices can be further optimized to make them smaller in area and higher in performance. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a bidirectional power device and a method for manufacturing the same, wherein a trench is used to divide a first doped region into alternating first-type sub-doped regions and second-type sub-doped regions to form the source and drain regions of the bidirectional power device, thereby reducing the area of ​​the device.

[0006] According to a first aspect of an embodiment of the present application, there is provided a bidirectional power device, comprising: a semiconductor layer; a first doped region in the semiconductor layer; a plurality of trenches of a first trench region in the first doped region, separating the first doped region into alternating first-type sub-doped regions and second-type sub-doped regions; a gate dielectric layer covering lower sidewalls of the plurality of trenches of the first trench region; a control gate in a lower portion of the plurality of trenches of the first trench region and in contact with the gate dielectric layer; a shield dielectric layer covering upper sidewalls of the plurality of trenches of the first trench region and on a surface of the control gate; and a first shield gate in the plurality of trenches of the first trench region and in contact with the shield dielectric layer, wherein the shield dielectric layer separates the control gate and the first shield gate, and the shield dielectric layer has a non-uniform thickness on the upper sidewalls of the plurality of trenches of the first trench region.

[0007] Optionally, when one of the first-type sub-doped regions and the second-type sub-doped regions is a source region and the other is a drain region, the source region and the drain region can be interchangeable.

[0008] Optionally, further comprising a plurality of trenches of a second trench region in the semiconductor layer and separated from the first doped region; the gate dielectric layer is further on sidewalls of the plurality of trenches of the second trench region, and the control gate is further in the plurality of trenches of the second trench region and in contact with the gate dielectric layer; the plurality of trenches of the first trench region and the plurality of trenches of the second trench region are in communication, and the control gate in the plurality of trenches of the first trench region is connected to the control gate in the plurality of trenches of the second trench region.

[0009] Optionally, further comprising a plurality of trenches of a third trench region in the semiconductor layer and separated from the first doped region; the gate dielectric layer further covers lower sidewalls of the plurality of trenches of the third trench region, the control gate further in a lower portion of the plurality of trenches of the third trench region and in contact with the gate dielectric layer, the shield dielectric layer further covers upper sidewalls of the plurality of trenches of the third trench region and on a surface of the control gate, and the first shield gate further in the plurality of trenches of the third trench region and in contact with the shield dielectric layer, the shield dielectric layer separating the control gate and the first shield gate; the plurality of trenches of the first trench region and the plurality of trenches of the third trench region are in communication, the control gate in the plurality of trenches of the first trench region is connected to the control gate in the plurality of trenches of the third trench region, and the first shield gate in the plurality of trenches of the first trench region is connected to the first shield gate in the plurality of trenches of the third trench region.

[0010] Optionally, a second shield gate is further included on top of the plurality of trenches of the first trench region and in contact with the shield dielectric layer, the second shield gate is on and in contact with the first shield gate; and a thickness of the shield dielectric layer is not uniform on the portions in contact with the first shield gate and the second shield gate.

[0011] Optionally, the shield dielectric layer includes a first portion, a second portion, and a third portion, the third portion of the shield dielectric layer surrounds the second shield gate, the second portion of the shield dielectric layer surrounds the first shield gate, and the first portion of the shield dielectric layer is on a surface of the control gate; and the thickness of the first portion, the second portion, and the third portion of the shield dielectric layer decreases in sequence.

[0012] Optionally, the thickness of the second portion of the shield dielectric layer is greater than a thickness of the gate dielectric layer.

[0013] Optionally, a channel region is further included in the semiconductor layer and adjacent to the control gate.

[0014] Optionally, a first contact region is further included in the first type of sub-doped region, a second contact region is further included in the second type of sub-doped region, and a third contact region is further included in the semiconductor layer.

[0015] Optionally, a cover dielectric layer is further included on a surface of the semiconductor layer, and a substrate electrode, a first contact electrode, a second contact electrode, a first gate electrode, and a second gate electrode are further included through the cover dielectric layer, the substrate electrode is connected to the third contact region, the first contact electrode is connected to the first contact region, the second contact electrode is connected to the second contact region, the first gate electrode is connected to the control gate, and the second gate electrode is connected to the first shield gate.

[0016] Optionally, the first gate electrode and the second gate electrode are connected to receive a same control voltage.

[0017] Optionally, the first gate electrode and the second gate electrode are electrically isolated to receive different control voltages.

[0018] Optionally, the thickness of the gate dielectric layer ranges from 0.1 nm to 50 nm.

[0019] Optionally, a depth of the plurality of trenches in the first trench region, the second trench region, and the third trench region ranges from 0.1 μm to 50 μm.

[0020] Optionally, a distance from a surface of the control gate in the first trench region to a surface of the semiconductor layer ranges from 0.1 μm to 49 μm.

[0021] Optionally, a thickness of the first portion of the shielding dielectric layer ranges from 1 nm to 10 nm.

[0022] Optionally, a thickness of the second portion of the shielding dielectric layer ranges from 1 nm to 10 nm.

[0023] Optionally, in a case where the bidirectional power device is off, the shielding gate depletes charges of the first type of sub-doped regions and the second type of sub-doped regions through the shielding dielectric layer to improve a withstand voltage characteristic of the bidirectional power device.

[0024] According to a second aspect of the embodiments of the present application, a manufacturing method of a bidirectional power device is provided, including: forming a first doped region in a semiconductor layer; forming a plurality of trenches in a first trench region, the plurality of trenches of the first trench region being located in the first doped region to separate the first doped region into first type of sub-doped regions and second type of sub-doped regions alternately; forming a gate dielectric layer covering lower sidewalls of the plurality of trenches of the first trench region; forming a control gate in lower portions of the plurality of trenches of the first trench region and in contact with the gate dielectric layer; forming a shielding dielectric layer covering upper sidewalls of the plurality of trenches of the first trench region and a surface of the control gate; and forming a first shielding gate in the plurality of trenches of the first trench region and in contact with the shielding dielectric layer, wherein the shielding dielectric layer separates the control gate and the first shielding gate, and a thickness of the shielding dielectric layer of the upper sidewalls of the trenches of the first trench region is inconsistent.

[0025] Optionally, in a case where one of the first type of sub-doped regions and the second type of sub-doped regions is a source region and the other of the first type of sub-doped regions and the second type of sub-doped regions is a drain region, the source region and the drain region can be interchangeable.

[0026] Optionally, the method further includes: forming a trench in a second trench region, the trench of the second trench region being located in the semiconductor layer and separated from the first doped region; the gate dielectric layer is further formed on sidewalls of the trench of the second trench region, and the control gate is further formed in the trench of the second trench region and in contact with the gate dielectric layer; the trench of the first trench region is in communication with the trench of the second trench region, and the control gate located in the trench of the first trench region is connected to the control gate located in the trench of the second trench region.

[0027] Optionally, further comprising forming a trench in a third trench region, the trench of the third trench region being in the semiconductor layer and separated from the first doped region; the gate dielectric layer is further formed on a lower sidewall of the trench of the third trench region, the control gate is further formed on a lower portion of the trench of the third trench region and in contact with the gate dielectric layer, the shielding dielectric layer is further formed on an upper sidewall of the trench of the third trench region and on a surface of the control gate, the first shielding gate is further formed on an upper portion of the trench of the third trench region and in contact with the shielding dielectric layer, the shielding dielectric layer separates the control gate and the first shielding gate; the trench of the first trench region is in communication with the trench of the third trench region, the control gate in the trench of the first trench region is connected to the control gate in the trench of the third trench region, and the first shielding gate in the trench of the first trench region is connected to the first shielding gate in the trench of the third trench region.

[0028] Optionally, further comprising forming a second shielding gate in contact with the shielding dielectric layer on an upper portion of the trench of the first trench region, the second shielding gate is on and in contact with the first shielding gate; a thickness of the shielding dielectric layer is not uniform in the portion in contact with the first shielding gate and the second shielding gate.

[0029] Optionally, the shielding dielectric layer comprises a first portion, a second portion and a third portion, the third portion of the shielding dielectric layer surrounds the second shielding gate, the second portion of the shielding dielectric layer surrounds the first shielding gate, and the first portion of the shielding dielectric layer is on a surface of the control gate; the thickness of the first portion, the second portion and the third portion of the shielding dielectric layer decreases in sequence.

[0030] Optionally, the thickness of the second portion of the shielding dielectric layer is greater than the thickness of the gate dielectric layer.

[0031] Optionally, further comprising forming a channel region in the semiconductor layer adjacent to the control gate.

[0032] Optionally, further comprising forming a first contact region in the first type of sub-doped region, forming a second contact region in the second type of sub-doped region, and forming a third contact region in the semiconductor layer.

[0033] Optionally, further comprising forming a covering dielectric layer on a surface of the semiconductor layer, and forming a substrate electrode, a first contact electrode, a second contact electrode, a first gate electrode and a second gate electrode through the covering dielectric layer, the substrate electrode is connected to the third contact region, the first contact electrode is connected to the first contact region, the second contact electrode is connected to the second contact region, the first gate electrode is connected to the control gate, and the second gate electrode is connected to the first shielding gate.

[0034] Optionally, the thickness of the gate dielectric layer ranges from

[0035] Optionally, the depth of the plurality of trenches in the first trench region, the second trench region and the third trench region ranges from 0.1 to 50 μm.

[0036] Optionally, the distance from the surface of the control gate in the first trench region to the surface of the semiconductor layer ranges from 0.1 to 49 μm.

[0037] Optionally, the thickness of the first portion of the shield dielectric layer ranges from

[0038] Optionally, the thickness of the second portion of the shield dielectric layer ranges from

[0039] Optionally, the first gate electrode and the second gate electrode are connected to receive the same control voltage.

[0040] Optionally, the first gate electrode and the second gate electrode are electrically isolated to receive different control voltages.

[0041] Optionally, in the case that the bidirectional power device is off, the shield gate depletes the charge of the first type of sub-doped region and the second type of sub-doped region through the shield dielectric layer to improve the withstand voltage characteristic of the bidirectional power device.

[0042] The bidirectional power device and the manufacturing method thereof according to the embodiments of the present application form the first doped region in the epitaxial layer, and make the first doped region be divided into the first type of sub-doped region and the second type of sub-doped region alternately by the trench, and form the first contact region and the second contact region in the first type of sub-doped region and the second type of sub-doped region respectively, thereby constituting two doped regions of the bidirectional power device, which are the source region and the drain region, and reducing the area of the device. By setting the thickness of the shield dielectric layer of the upper sidewall of the trench in the first trench region as the inconsistent structure, different voltages can be applied by the gate electrode to achieve the effect of forming different electric fields.

[0043] More specifically, generally the depth of the first doped region is deep, and in order to achieve the deeper doped junction depth, higher diffusion temperature and longer diffusion time are required. Therefore, according to the requirement of the product parameters, the first doped region is formed in the first step of the manufacturing method, which is beneficial to select the appropriate doping conditions to realize the requirement of the product structure and parameters. In the case that the junction depth requirement of the first doped region is shallow, the formation of the first doped region can not be placed in the first step of the manufacturing method, and the first doped region can be annealed together with other doped regions in the subsequent annealing process of the manufacturing method, thereby realizing the junction depth and parameter requirement required by the device structure.

[0044] Further, by forming the control gate and the shielding gate in the plurality of trenches, the shielding gate depletes the charges of the source region and the drain region through the shielding dielectric layer when the bidirectional power device is off, so as to improve the withstand voltage characteristic of the device; in the case of conduction of the bidirectional power device, the source region and / or the drain region and the channel region provide a low-impedance conduction path.

[0045] Further, in the device structure, the control gate and the shielding gate are separated from each other, the control gates located in the first trench region, the second trench region and the third trench region are connected and led out through electrodes, and the first shielding gates located in the first trench region and the third trench region are connected and led out through electrodes, so as to not only realize the connection of the shielding gate and the control gate through the leading-out electrodes (forming a structure similar to a single polysilicon), but also realize the electrical isolation of the shielding gate and the control gate through the leading-out electrodes separating the shielding gate and the control gate (i.e., the upper polysilicon is separately connected), control the electric field of the upper half, and realize the separate control of the shielding gate, so as to flexibly adjust the shielding effect as needed.

[0046] Further, in the case of conduction of the bidirectional power device, one of the first contact electrode and the second contact electrode is short-circuited with the substrate electrode connected with the substrate, so as to realize the bidirectional selection of the current direction. In the case of short-circuiting the substrate electrode with the first contact electrode, the current flows from the second contact electrode to the first contact electrode through the second type sub-doped region, the channel region and the first type sub-doped region in sequence; in the case of short-circuiting the substrate electrode with the second contact electrode, the current flows from the first contact electrode to the second contact electrode through the first type sub-doped region, the channel region and the second type sub-doped region in sequence.

[0047] Further, the channel length can be reduced by reducing the width of the trench, and then the channel resistance is reduced.

[0048] Further, the device adopts a longitudinal control gate electrode field structure, fully utilizes the charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size in the case of meeting the withstand voltage requirement.

[0049] Further, in the case that the control gate and the shielding gate are located in the same trench, for example, in the first trench region and the third trench region, since the vertical depth of the entire trench is realized at one time, the vertical distance from the center line of the control gate extending along the thickness direction of the substrate to the inner boundary of the shielding dielectric layer located on the two sidewalls of the trench is the same, the vertical distance from the center line of the control gate extending along the thickness direction of the substrate to the outer boundary of the shielding dielectric layer located on the two sidewalls of the trench is the same, i.e., the control gate is located directly below the shielding gate. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some of the embodiments of the present application and do not limit the present application.

[0051] Figure 1 A circuit schematic diagram of a prior art bidirectional power device is shown.

[0052] Figure 2 A circuit schematic diagram of a bidirectional power device of an embodiment of the present application is shown.

[0053] Figures 3a to 3n A structural diagram of some stages of a method of manufacturing a bidirectional power device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0054] The present application will be described in more detail by referring to the attached drawings. Like elements are denoted by like reference numerals throughout the various drawings. Individual parts in the drawings are not drawn to scale for the sake of clarity. Furthermore, certain well-known components can not be shown. For the sake of brevity, a semiconductor structure obtained after several steps can be described in one drawing.

[0055] It should be understood that when a layer, a region is referred to as being "on" or "above" another layer, another region, it can be directly on the other layer, the other region, or an intervening layer or region can also be present. Also, the layer, the region can be "under" or "below" the other layer, the other region if the device is turned over.

[0056] If for the sake of description, a layer, a region is referred to as being "directly on" or "on and adjacent to" another layer, another region, the expression is used.

[0057] Many specific details of the present application are described below in order to provide a thorough understanding of the present application. However, as will be readily understood by one skilled in the art, the present application can be practiced without

[0058] The present application can be presented in various forms, some examples of which will be described below.

[0059] Figure 2 A circuit schematic diagram of a bidirectional power device of an embodiment of the present application is shown.

[0060] A bidirectional power device of an embodiment of the present application is formed of one transistor and has bidirectional conduction function. As shown in FIG. 1, the bidirectional power device of the embodiment of the present application is formed of one transistor 10 and has bidirectional conduction function. Figure 2As shown, the bidirectional power device includes a substrate Sub, two output electrodes S1 and S2 and two parasitic body diodes D1 and D2 on the substrate Sub. In the case of shorting the output electrode S2 and the substrate Sub, a high voltage is applied to the gate G, which is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is turned on, and the current flows from the output electrode S1 to the output electrode S2; in the case of shorting the output electrode S1 and the substrate Sub, a high voltage is applied to the gate G, which is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is turned on, and the current flows from the output electrode S2 to the output electrode S1; in the case of zero voltage of the substrate Sub, a low voltage is applied to the gate G, which is lower than the threshold voltage, and the bidirectional power device is turned off. In the embodiment of the application, the bidirectional power device is a trench type device, which can be a metal oxide semiconductor field effect transistor (MOSFET), an IGBT device or a diode. However, the application is not limited thereto.

[0061] Figures 3a to 3n The structural diagram of the method for manufacturing the bidirectional power device in the embodiment of the application is shown in some stages. It should be noted that the structure of each step of the structural diagram disclosed in the embodiment does not necessarily have to be in one cross section, and can be placed in different areas and directions of the product according to the requirements of the product layout. In the structural diagram, only five trenches, one source region and one drain region are included, but the number of trenches, source regions and drain regions in the actual product can be changed. When one of the first type of sub-doped and second type of sub-doped regions is used as a source region and the other is used as a drain region, the source region and the drain region of the structure can be interchanged according to different working occasions. In the specific embodiment, in order to facilitate understanding of the forming process of the device structure in each step, the main structure of the device is shown in one cross section, but it is not used to limit the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the embodiment, and therefore the protection scope of the embodiment should be subject to the scope defined in the claims of the application.

[0062] In the embodiment, the manufacturing process starts from a semiconductor layer with a specific doping type, such as Figure 3a As shown, the semiconductor layer includes a substrate 101 and an epitaxial layer 110 on the substrate 101, wherein the substrate 101 includes a silicon substrate, a germanium-silicon substrate, a group III-V compound substrate or other semiconductor material substrate known to those skilled in the art, and the silicon substrate is used in the embodiment. More specifically, the silicon substrate used in the embodiment can form a MOS field effect transistor, an IGBT insulated gate field effect transistor, a Schottky semiconductor device and the like.

[0063] The semiconductor layer with a specific doping type refers to an N-type or P-type substrate 101 doped with a certain amount of impurities and an N-type or P-type epitaxial layer 110 with a certain resistivity and thickness according to product characteristics. For example, in the case of a bidirectional power device being an NMOS, the doping type of the substrate 101 and the epitaxial layer 110 is P-type; in the case of a bidirectional power device being a PMOS, the doping type of the substrate 101 and the epitaxial layer 110 is N-type.

[0064] Further, a first doped region 120 is formed in the epitaxial layer 110, as shown in Figure 3a .

[0065] In this step, the first doped region 120 is formed by one or more of implantation doping, diffusion source doping, and coating doping, wherein the implantation energy is 20-800 KeV, the implantation dose is 1E11-1E16 cm 2 , and the annealing temperature is 600-1200 degrees.

[0066] In this embodiment, the bidirectional power device has a first trench region 103, a second trench region 104, and a third trench region 105, the first doped region 120 is located in the first trench region 103 and has a doping type opposite to that of the epitaxial layer 110, for example, in the case of a bidirectional power device being a PMOS, the doping type of the first doped region 120 is P-type, and the doping impurity is usually B+; in the case of a bidirectional power device being an NMOS, the doping type of the first doped region 120 is N-type, and the doping impurity is usually As+ or P+. The first trench region 103, the second trench region 104, and the third doped region are separated, and the second trench region 104 and the third doped region 105 are located in the epitaxial layer 110.

[0067] Further, a plurality of trenches 111a-111e are formed, as shown in Figure 3b .

[0068] In this step, a barrier layer 10 is first formed on the surface of the epitaxial layer 110 by thermal oxidation or deposition, etc., and then the barrier layer 10 is selectively removed by lithography and etching processes to form an opening 11, and then the semiconductor layer is etched through the opening 11 to form the trenches, and the regions where the barrier layer 10 remains are not formed with trenches.

[0069] Figure 3bAs shown in the sectional view, the plurality of trenches includes five trenches, i.e., trench 111a, trench 111b, trench 111c, trench 111d and trench 111e. The trench 111a, 111b and 111c are located in the first trench region 103, the trench 111b is located in the second trench region 104, the trench 111e is located in the third trench region 105, and the bottom of the trench 111a to 111e is located in the epitaxial layer 110. Specifically, the trench 111a is located in the first doped region 120, the trench 111d and the trench 111c are located at the boundary of the first doped region 120, and the three trenches separate the first doped region 120 into the first type of sub-doped region 121 and the second type of sub-doped region 122. The trench 111c and the trench 111d are located on both sides of the first doped region 120 and contact the first doped region 120, for example, the trench 111c contacts the second type of sub-doped region 122, and the trench 111d contacts the first type of sub-doped region 121. The trench 111b and the trench 111e are located in the epitaxial layer 110 and are separated from the first doped region 120, wherein the trench 111e is located between the trench 111c and the trench 111b. In the plane perpendicular to the thickness direction of the substrate 101, the trench 111d, the trench 111a, the trench 111c located in the first trench region 103, the trench 111e located in the third trench region 105 and the trench 111b located in the second trench region 104 are connected, for example, sequentially connected in an "S" shape, but the embodiment of the present application is not limited thereto, and at least two trenches can be separated according to the needs of those skilled in the art.

[0070] In the embodiment, the width of the plurality of trenches 111a to 111e is determined according to the product structure and process capability, and the depth h1 of the plurality of trenches 111a to 111e is determined according to the product parameters such as voltage resistance. Specifically, the width of the plurality of trenches 111a to 111e ranges from 0.05 to 5 μm, and the depth h1 ranges from 0.1 to 50 μm. However, the embodiment of the present application is not limited thereto, and those skilled in the art can match the depth h1 and the width of the plurality of trenches 111a to 111e according to the needs of the product in combination with the conditions such as epitaxy, voltage resistance, doping, gate oxide thickness and the like. Those skilled in the art can also make other settings to the number of trenches located in the first trench region 103, so that the plurality of trenches separates the first doped region 120 into a plurality of first type of sub-doped regions 121 and second type of sub-doped regions 122 alternately.

[0071] Further, a channel region 130 is formed in the epitaxial layer 110 through the bottom of the plurality of trenches 111a to 111e, as shown in the sectional view. Figure 3c

[0072] ​In this step, for example, doping is first performed on the bottom of multiple trenches 111a to 111e through the opening 11 of the barrier layer 10 to form a channel region 130 in the epitaxial layer 110, and then the barrier layer 10 is removed. For example, a zero-angle implantation process is used to form the channel region 130 at the bottom of multiple trenches 111a to 111e to adjust the threshold voltage of the device, wherein the implantation energy is 20 to 800 keV and the implantation dose is 1E11 to 1E16 cm⁻¹. 2 The annealing temperature is 600–1200 degrees Celsius.

[0073] In this embodiment, the channel region 130 is in contact with the first type of sub-doped region 121 and the second type of sub-doped region 122, respectively. The channel region 130 has the same doping type as the first type of sub-doped region 121 and the second type of sub-doped region 122. For example, when the bidirectional power device is a PMOS transistor, the doping type of the channel region 130 is P-type, and the doping impurity is usually B+; when the bidirectional power device is an NMOS transistor, the doping type of the channel region 130 is N-type, and the doping impurity is usually As+ or P+.

[0074] Furthermore, a first dielectric layer 141a is formed on the inner surfaces of the plurality of trenches 111a to 111e, the surface of the epitaxial layer 110, the surface of the first type of sub-doped region 121, and the surface of the second type of sub-doped region 122, such as Figure 3d As shown.

[0075] In this step, for example, one or more of the following processes are used to form the first dielectric layer 141a: oxidation growth, chemical vapor deposition, LPCVD, SACVD, HTO, and SRO. In some preferred embodiments, the first dielectric layer 141a is formed using an oxidation growth process, and in subsequent steps, the first dielectric layer 141a will form the gate dielectric layer 141. The thickness T1 of the first dielectric layer 141a should be considered in conjunction with the required threshold voltage of the product, the depth of the trench in the device structure, the doping concentration of the first doped region 120, and the junction depth. The range of T1 includes...

[0076] Furthermore, a first conductive layer 142a is formed on the first dielectric layer 141a located on the surface of the epitaxial layer 110 and in the plurality of trenches 111a to 111e, such as Figure 3e As shown.

[0077] In this step, the first conductive layer 142a is formed by, for example, a deposition process, so that the first conductive layer 142a fills the plurality of trenches 111a-111e, and the first conductive layer 142a and the first dielectric layer 141a are in contact with each other. The material of the first conductive layer 142a includes in-situ doped polysilicon. In some other embodiments, undoped polysilicon can be deposited first, and then doped with impurities by ion implantation. In a subsequent step, the first conductive layer 142a will form a control gate 142.

[0078] In this embodiment, the doping type of the first conductive layer 142a is P-type when the bidirectional power device is a PMOS, and the doping type of the first conductive layer 142a is N-type when the bidirectional power device is an NMOS.

[0079] Further, the first conductive layer 142a on the surface of the first dielectric layer 141a is removed, and the first conductive layer 142a in the trenches of the first trench region 103 and the trenches of the third trench region 105 is selectively removed, as shown in Figure 3f .

[0080] In this step, the first conductive layer 142a outside the plurality of trenches 111a-111e is removed by, for example, a combination of one or more of dry etching, wet etching, and CMP processes, so that the first dielectric layer 141a on the surface of the epitaxial layer 110 is exposed, and the first conductive layer 142a in the plurality of trenches 111a-111e and the first dielectric layer 141a on the surface of the epitaxial layer 110 are flush. Then, the first conductive layer 142a in the trenches 111a, 111c, 111d of the first trench region 103 and the trench 111e of the third trench region 105 is selectively removed by a lithography and etching process, so that the depth of the first conductive layer 142a in the trenches 111a, 111c, 111d, and 111e from the surface of the epitaxial layer 110 is h2. The remaining first conductive layer 142a in the plurality of trenches 111a-111e serves as a control gate 142. The control gate 142 is located in the lower portions of the trenches 111a, 111c, 111d, and 111e of the first trench region 103 and the third trench region 105 and the entire trench 111b of the second trench region 104, wherein the control gates 142 in the trenches of the first trench region 103, the second trench region 104, and the third trench region 105 are connected.

[0081] In this embodiment, the depth h2 of the control gate 142 in the trenches 111a, 111c, 111d, and 111e from the surface of the epitaxial layer 110 needs to be matched in combination with the epitaxy, withstand voltage, doping, gate oxide thickness, etc. of the product, and the depth h2 ranges from 0.1 to 49 μm. In this embodiment, the first dielectric layer 141a is retained after the formation of the control gate 142, which can simplify the entire process.

[0082] In some other embodiments, after forming the control gate 142, a wet etching process or the like can be further employed to remove the first dielectric layer 141a on the sidewalls of the trenches 111a, 111c, 111d and 111e and the surface of the epitaxial layer 110.

[0083] Further, a second dielectric layer 143a is formed on the upper sidewalls of the trenches 111a, 111c, 111d and 111e, the surface of the control gate 142 and the first dielectric layer 141a on the surface of the epitaxial layer 110, as shown in Figure 3g .

[0084] In this step, the second dielectric layer 143a is formed by one or more of the following processes: oxidation growth process, chemical vapor deposition process: LPCVD, SACVD, HTO, SRO process, etc. In some preferred embodiments, the oxidation growth process is employed to form the second dielectric layer 143a. In this case, the thickness of the second dielectric layer 143a grown on the surface of the control gate 142 is T2, and the thickness of the second dielectric layer 143a grown on the upper sidewalls of the trenches 111a, 111c, 111d and 111e is T3. Under the same oxidation growth conditions, T2 is usually greater than T3. In this case, the range of T2 includes The range of T3 should be considered in combination with the required voltage of the product, the depth of the trenches in the device structure, the doping concentration of the first doped region and the junction depth, and the range of T3 includes and T3 > T1.

[0085] In this embodiment, the oxidation growth process is employed to form the second dielectric layer 143a, and in this process, part of the exposed control gate 142 is oxidized to form a part of the second dielectric layer 143a. In the subsequent step, the second dielectric layer 143a on the surface of the control gate 142 and on the upper sidewalls of the trenches 111a, 111c, 111d and 111e forms a shielding dielectric layer 143.

[0086] Further, a second conductive layer 144a is formed to cover the second dielectric layer 143a and fill in the trenches 111a, 111c, 111d and 111e, as shown in Figure 3h .

[0087] In this step, the second conductive layer 144a is formed by a deposition process. In this case, the material of the second conductive layer 144a includes in-situ doped polysilicon, and in some other embodiments, undoped polysilicon can be first deposited, and then doped impurities are implanted. In the subsequent step, the second conductive layer 144a will form a first shielding gate 144.

[0088] In the embodiment, the second conductive layer 144a is P-type doped when the bidirectional power device is PMOS, and is N-type doped when the bidirectional power device is NMOS.

[0089] Further, the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a on the surface of the epitaxial layer 110 are removed, as shown in Figure 3i

[0090] In this step, the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a outside the plurality of trenches 111a-111e are removed by one or more of dry etching, wet etching, CMP process, etc., so that the surface of the epitaxial layer 110, the first type of sub-doped region 121 and the second type of sub-doped region 122 are exposed.

[0091] In some embodiments, the second conductive layer 144a above the epitaxial layer 110 is removed by a combination of CMP and dry etching, or by dry etching only. The second dielectric layer 143a above the epitaxial layer 110 is removed by a combination of CMP and wet etching, and a portion of the second dielectric layer 143a remains on the top of the trench 111b.

[0092] In the embodiment, the remaining first dielectric layer 141a in the trenches 111a-111e serves as the gate dielectric layer 141. The gate dielectric layer 141 is located on the inner surface of the lower part of the trenches 111a, 111c, 111d, 111e in the first trench region 103 and the third trench region 105, and the entire inner surface of the trench 111b in the second trench region 104.

[0093] Further, the second conductive layer 144a at the opening of the trenches 111a, 111c, 111d in the first trench region 103 is removed to expose the second dielectric layer 143a near the opening. The remaining second conductive layer 144a in the trenches 111a, 111c, 111d, 111e serves as the first shielding gate 144, as shown in Figure 3i

[0094] In this step, part of the second conductive layer 144a in the trenches 111a, 111c, 111d is removed by lithography and etching, so that the remaining second conductive layer 144a in the trenches 111a, 111c, 111d has a depth h3 below the surface of the epitaxial layer 110. In some embodiments, h3 is in the range of

[0095] ​​Further, the second dielectric layer 143a exposed at the opening of the trench 111a, 111c, 111d is thinned, as shown in FIG. 1I. Figure 3j

[0096] In this step, the photoresist reserved in the previous step is used as a protective layer to protect the area where the trench 111b and 111e are located. For the area not protected by the photoresist, a wet etching process is used to remove the second dielectric layer 143a exposed at the top of the trench 111a, 111c, 111d to a certain thickness, so that the top sidewall of the trench 111a, 111c, 111d remains a second dielectric layer 143a with a thickness of T4, and T4 < T3. Since the area where the trench 111b and 111e are located is protected, the structure in the trench 111b and 111e is not affected.

[0097] In this embodiment, the remaining second dielectric layer in the trench 111a, 111c, 111d forms a shielding dielectric layer 143, including a first part 1431 located on the surface of the control gate 142, a second part 1432 located on the sidewall of the trench and surrounding the first shielding gate 144, and a third part 1433 located on the sidewall of the trench and on the first shielding gate 144. In the trench 111a, 111c, 111d, due to the inconsistent thickness of the second part 1432 and the third part 1433, the effect of forming different electric fields by applying different voltages to the gate electrode can be achieved. The remaining second dielectric layer in the trench 111e forms a shielding dielectric layer 143, including a first part 1431 located on the surface of the control gate 142, and a second part 1432 located on the sidewall of the trench and surrounding the first shielding gate 144. The thickness T2 and T3 of the shielding dielectric layer 143 is greater than the thickness T1 of the first gate dielectric layer 141.

[0098] Further, the second shielding gate 146 is filled in the top of the trench 111a, 111c, 111d, as shown in FIG. 1K. Figure 3k

[0099] In this embodiment, the material of the second shielding gate 146 can be the same as that of the first shielding gate 144. The second shielding gate 146 is connected to the first shielding gate 144, and the second shielding gate 146 is surrounded by the third part 1433 of the shielding dielectric layer 143.

[0100] ​​In the case that the control gate 142 and the shield gate 144 are located in the same trench, for example, in the first trench region 103 and the third trench region 105, since the vertical depth of the whole trench is realized at one time, the control gate 142 is located directly below the shield gate 144, the vertical distance from the center line of the control gate 142 extending along the thickness direction of the substrate 101 to the inner boundary of the shield dielectric layer 143 located on the two sidewalls of the trench is the same, i.e., d1=d2, and the vertical distance from the center line of the control gate 142 extending along the thickness direction of the substrate 101 to the outer boundary of the shield dielectric layer 143 located on the two sidewalls of the trench is the same, i.e., d3=d4.

[0101] Further, the first contact region 151 is formed in the first type of sub-doped region 121, the second contact region 152 is formed in the second type of sub-doped region 122, and the third contact region 153 is formed in the epitaxial layer 110, as shown in Figure 3l .

[0102] In this step, the first type of sub-doped region 121, the second type of sub-doped region 122, and the epitaxial layer 110 are doped by implantation and diffusion through a photolithography mask. The implantation energy of the doping process is 20-180 Kev, and the implantation dose is 1E11-1E16 cm 2 .

[0103] In this embodiment, the doping type of the first contact region 151 and the second contact region 152 is the same as that of the first type of sub-doped region 121, and the doping type of the third contact region 153 is the same as that of the epitaxial layer 110. For example, in the case that the bidirectional power device is a PMOS, the doping type of the first contact region 151 and the second contact region 152 is P type, and the doping type of the third contact region 153 is N type; in the case that the bidirectional power device is an NMOS, the doping type of the first contact region 151 and the second contact region 152 is N type, and the doping type of the third contact region 153 is P type. The P type contact region doping commonly uses B+ / BF2+, and the N type contact region doping commonly uses As+ and P+.

[0104] Further, the covering dielectric layer 102 is formed on the epitaxial layer 110, and a plurality of contact holes 102a extending from the surface of the covering dielectric layer 102 to the substrate direction 101 are formed, as shown in Figure 3m .

[0105] In this step, a covering medium layer 102 is formed by a chemical vapor deposition process, such as LPCVD, SACVD, HTO, SRO, or a combination of one or more of these processes. The material of the covering medium layer 102 includes one or more of undoped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, boron and phosphorus co-doped silicon dioxide, undoped polysilicon, silicon nitride, silicon oxynitride, or a combination of these materials. Then, a plurality of contact holes 102a are formed by a photolithography and etching process, and the contact holes 102a extend to a depth h3 in the first contact region 151, the second contact region 152, the third contact region 153, the control gate 142, and the first shielding gate 144, respectively. The depth h3 is in a range of

[0106] Further, a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164, and a second gate electrode 165 are formed in the contact holes, respectively, as shown in FIG. 2. Figure 3n

[0107] In this step, a metal conductive layer is deposited on the covering medium layer 102, and the metal conductive layer extends from the surface of the covering medium layer 102 to the contact holes. Finally, the first contact electrode 161, the second contact electrode 162, the substrate electrode 163, the first gate electrode 164, and the second gate electrode 165 are formed by a photolithography and etching process. The first contact electrode 161 and the second contact electrode 162 are source electrodes and drain electrodes, respectively, and can be interchangeable.

[0108] The first contact electrode 161 is connected to the first contact region 151, the second contact electrode 162 is connected to the second contact region 152, the substrate electrode 163 is connected to the third contact region 153, the first gate electrode 164 is connected to the control gate 142, and the second gate electrode 165 is connected to the first shielding gate 144. The material of the metal conductive layer can be one or more of Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, Ni, or a combination of these materials. The metal etching process can be one or more of wet etching and plasma etching, and the substrate electrode 163, the first contact electrode 161, the second contact electrode 162, the first gate electrode 164, and the second gate electrode 165 are formed by the etching process. The five electrodes are used to apply voltage or current, and the performance of the device is achieved.

[0109] ​In the embodiment, the first gate electrode 164 is positioned corresponding to the trench 111b, and the second gate electrode 165 is positioned corresponding to the trench 111e. However, the embodiment is not limited to this, because the plurality of trenches 111a-111e are connected, so that the control gates 142 in the plurality of trenches 111a-111e are connected to each other, the first shield gates 144 in the plurality of trenches are connected to each other, and the second shield gates 146 in the plurality of trenches are connected to each other, the second gate electrode 165 can also be positioned corresponding to the trench 111a and / or 111c and / or the trench 111d. In this case, the control gates 142 in the first trench area 103, the second trench area 104 and the third trench area 105 are led out by the first gate electrode 164, and the first shield gates 144 in the first trench area 103 and the third trench area 105 are led out by the second gate electrode 165.

[0110] In some specific embodiments, the first gate electrode 164 and the second gate electrode 165 are connected to connect the control gates 142 and the first shield gates 144, so that a single polycrystal structure is formed, the first shield gates 144 overlap the first type of sub-doped region 121 and the second type of sub-doped region 122, and a parasitic capacitor exists. When the voltage of the control gates 142 and the first shield gates 144 is raised, the parasitic capacitor is charged, and the bidirectional power device is turned on; when the voltage of the control gates 142 and the first shield gates 144 is lowered, the parasitic capacitor is discharged, and the bidirectional power device is turned off. When the bidirectional power device is switched at a high speed, the charging and discharging time of the parasitic capacitor reduces the switching frequency, and the charging and discharging of the parasitic capacitor generates additional power consumption.

[0111] In other specific embodiments, the first gate electrode 164 and the second gate electrode 165 can also be separated to receive different control voltages, that is, the upper polycrystal is separately connected to control the electric field of the upper half. For example, the second gate electrode 165 and the substrate electrode 163 are connected to connect the first shield gate 144 and the substrate 101, and the voltage of the first shield gate 144 is fixed during the switching process of the device, so that the charging and discharging of the parasitic capacitor caused by the change of the voltage of the first shield gate 144 can be avoided, the switching frequency of the bidirectional power device can be improved, and the power consumption can be reduced. In some application scenarios that require the bidirectional power device to have not only as low resistance as possible but also small parasitic capacitor, the bidirectional power device can be used for high-speed switching.

[0112] Further, the embodiment discloses a bidirectional power device and a manufacturing method thereof, and the resistance of the device during use can be reduced to the lowest by increasing the metal layers and optimizing the wiring mode and method, so that the signal interference is reduced to the greatest extent.

[0113] Further, the embodiment discloses a bidirectional power device and a manufacturing method thereof, and the device can be protected and the reliability can be enhanced by adding a passivation layer, a polyimide structure and the like in combination with the actual use of the product.

[0114] Further, the embodiment of the present application discloses a bidirectional power device and a manufacturing method thereof, which can form the structure required by products through thinning, back evaporation and other post-processes to realize functions.

[0115] Further, the bidirectional power device with bidirectional conduction function realized by the embodiment of the present application can lead out the first gate electrode 164, the second gate electrode 165, the substrate electrode 163, the first contact electrode 161 and the second contact electrode 162 from the surface of the semiconductor structure, and can meet the packaging requirements of chip-scale packaging (CSP).

[0116] Further, the embodiment of the present application discloses a bidirectional power device and a manufacturing method thereof, which can be applied to power MOSFET, CMOS, BCD, high-power transistor, IGBT and Schottky products.

[0117] According to the bidirectional power device and the manufacturing method thereof provided by the embodiment of the present application, the first doped region is formed in the epitaxial layer, and the first doped region is separated into the first type of sub-doped region and the second type of sub-doped region alternately by the groove, and the first contact region and the second contact region are respectively formed in the first type of sub-doped region and the second type of sub-doped region, so as to constitute two doped regions of the bidirectional power device, and the two doped regions are source region and drain region, and the area of the device is reduced. The thickness of the shielding medium layer of the upper sidewall of the groove of the first groove region is set to be inconsistent, so that different voltages can be applied by the gate electrode to achieve the effect of forming different electric fields.

[0118] More specifically, generally, the depth of the first doped region is deep, and in order to achieve a deeper doping junction depth, a higher diffusion temperature and a longer diffusion time are required. Therefore, according to the requirements of product parameters, the first doped region is formed in the first step of the manufacturing method, which is beneficial to select appropriate doping conditions to realize the requirements of product structure and parameters. In the case that the junction depth of the first doped region is required to be shallow, the formation of the first doped region can not be placed in the first step of the manufacturing method, and the first doped region can be annealed together with other doped regions in the subsequent annealing process of other doped regions, so as to realize the requirements of junction depth and parameters required by the device structure.

[0119] Further, by forming the control gate and the shielding gate in the plurality of grooves, the shielding gate depletes the charges of the source region and the drain region through the shielding medium layer when the bidirectional power device is cut off, so as to improve the withstand voltage characteristics of the device; in the case that the bidirectional power device is turned on, the source region and / or the drain region and the channel region provide a low-impedance conduction path.

[0120] Further, the control gate and the shielding gate are separated from each other in the device structure, the control gates located in the first trench region, the second trench region and the third trench region are connected and led out through electrodes, the first shielding gates located in the first trench region and the third trench region are connected and led out through electrodes, the connection of the shielding gate and the control gate can be realized through the leading-out electrodes (forming a structure similar to single poly), the shielding gate and the control gate can be electrically isolated through the leading-out electrodes separating the shielding gate and the control gate (i.e. the upper segment of the poly is connected separately), the electric field of the upper half segment is controlled, the shielding gate is controlled separately, and the shielding effect can be flexibly adjusted according to needs.

[0121] Further, when the bidirectional power device is turned on, the substrate electrode connected with the substrate is short-circuited with one of the first contact electrode and the second contact electrode, and the bidirectional selection of the current direction is realized. In the case that the substrate electrode is short-circuited with the first contact electrode, the current flows from the second contact electrode to the first contact electrode through the second type sub-doped region, the channel region and the first type sub-doped region in sequence; in the case that the substrate electrode is short-circuited with the second contact electrode, the current flows from the first contact electrode to the second contact electrode through the first type sub-doped region, the channel region and the second type sub-doped region in sequence.

[0122] Further, the channel length can be reduced by reducing the width of the trench, and the channel resistance is further reduced.

[0123] Further, the device adopts a longitudinal control gate field structure, fully utilizes the charge balance mechanism, and effectively improves the on-state efficiency and reduces the chip size under the condition that the withstand voltage requirement is met.

[0124] Further, in the case that the control gate and the shielding gate are located in the same trench, for example, in the first trench region and the third trench region, since the vertical depth of the entire trench is realized at one time, the vertical distance from the center line of the control gate extending along the thickness direction of the substrate to the inner boundary of the shielding dielectric layer located on the two sidewalls of the trench is the same, the vertical distance from the center line of the control gate extending along the thickness direction of the substrate to the outer boundary of the shielding dielectric layer located on the two sidewalls of the trench is the same, i.e. the control gate is located directly below the shielding gate.

[0125] The above describes the embodiments of the present application. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A method for manufacturing a bidirectional power device, comprising: A first doped region is formed in the semiconductor layer; Multiple trenches are formed in the first trench region, and the multiple trenches in the first trench region are located in the first doped region, dividing the first doped region into alternating first type sub-doped regions and second type sub-doped regions; A gate dielectric layer is formed that covers the lower sidewalls of multiple trenches in the first trench region; A control gate that contacts the gate dielectric layer is formed in the lower part of a plurality of trenches in the first trench region; A shielding dielectric layer is formed covering the upper sidewalls of multiple trenches covering the first trench area and the surface of the control gate; as well as A first shielding grid is formed in multiple trenches of the first trench region to contact the shielding medium layer. The shielding medium layer separates the control gate and the first shielding gate, and the thickness of the shielding medium layer on the upper sidewall of the trench in the first trench region is inconsistent.

2. The manufacturing method according to claim 1, wherein, When one of the first type of sub-doped region and the second type of sub-doped region is used as the source region, the other of the first type of sub-doped region and the second type of sub-doped region is used as the drain region.

3. The manufacturing method according to claim 1, wherein, It also includes forming trenches in a second trench region, wherein the trenches in the second trench region are located in the semiconductor layer and are separated from the first doped region; The gate dielectric layer is also formed on the sidewall of the trench in the second trench region, and the control gate is also formed in the trench of the second trench region and in contact with the gate dielectric layer; The trenches in the first trench area are connected to the trenches in the second trench area, and the control gate located in the trench of the first trench area is connected to the control gate located in the trench of the second trench area.

4. The manufacturing method according to claim 3, wherein, It also includes forming a trench in a third trench region, the trench in the third trench region being located in the semiconductor layer and separated from the first doped region; The gate dielectric layer is also formed on the lower sidewall of the trench in the third trench region, the control gate is also formed in the lower part of the trench in the third trench region and contacts the gate dielectric layer, the shielding dielectric layer is also formed on the upper sidewall of the trench in the third trench region and is located on the surface of the control gate, the first shielding gate is also formed in the upper part of the trench in the third trench region and contacts the shielding dielectric layer, and the shielding dielectric layer separates the control gate and the first shielding gate; The trenches in the first trench area are connected to the trenches in the third trench area. The control gate in the trench of the first trench area is connected to the control gate in the trench of the third trench area. The first shielding gate in the trench of the first trench area is connected to the first shielding gate in the trench of the third trench area.

5. The manufacturing method according to claim 1, wherein, It also includes forming a second shielding grid on the upper part of a plurality of trenches in the first trench region, which is in contact with the shielding medium layer. The second shielding grid is located on the first shielding grid and is in contact with the first shielding grid. The thickness of the shielding medium layer is inconsistent at the portion that contacts the first shielding grid and the second shielding grid.

6. The manufacturing method according to claim 5, wherein, The shielding medium layer includes a first part, a second part, and a third part, wherein the third part of the shielding medium layer surrounds the second shielding grid, the second part of the shielding medium layer surrounds the first shielding grid, and the first part of the shielding medium layer is located on the surface of the control grid. The thickness of the first, second, and third portions of the shielding medium layer decreases sequentially.

7. The manufacturing method according to claim 6, wherein, The thickness of the second portion of the shielding dielectric layer is greater than the thickness of the gate dielectric layer.

8. The manufacturing method according to any one of claims 1-7, wherein, It also includes forming a channel region adjacent to the control gate in the semiconductor layer.

9. The manufacturing method according to any one of claims 1-7, wherein, Also includes: A first contact region is formed in the first type of sub-doped region; A second contact region is formed in the second type of sub-doped region; as well as A third contact region is formed in the semiconductor layer.

10. The manufacturing method according to claim 9, wherein, Also includes: A covering dielectric layer is formed on the surface of the semiconductor layer; as well as A substrate electrode, a first contact electrode, a second contact electrode, a first gate electrode, and a second gate electrode are formed through the covering dielectric layer. The substrate electrode is connected to the third contact region, the first contact electrode is connected to the first contact region, the second contact electrode is connected to the second contact region, the first gate electrode is connected to the control gate, and the second gate electrode is connected to the first shielding gate.

11. The manufacturing method according to any one of claims 1-7, wherein, The thickness of the gate dielectric layer ranges from 10 to 9999 Å.

12. The manufacturing method according to claim 4, wherein, The depth range of the multiple trenches in the first trench area, the second trench area and the third trench area includes 0.1~50μm.

13. The manufacturing method according to any one of claims 1-7, wherein, The distance from the surface of the control gate located in the first trench region to the surface of the semiconductor layer includes 0.1~49μm.

14. The manufacturing method according to claim 6, wherein, The thickness of the first portion of the shielding medium layer ranges from 30 to 20,000 Å.

15. The manufacturing method according to claim 6, wherein, The thickness of the second portion of the shielding medium layer ranges from 20 to 10,000 Å.

16. The manufacturing method according to claim 10, wherein, The first gate electrode is connected to the second gate electrode to receive the same control voltage.

17. The manufacturing method according to claim 10, wherein, The first gate electrode is electrically isolated from the second gate electrode to receive different control voltages.

18. The manufacturing method according to any one of claims 1-7, wherein, When the bidirectional power device is turned off, the shielding gate depletes the charge of the first type of sub-doped region and the second type of sub-doped region through the shielding dielectric layer, thereby improving the breakdown voltage characteristics of the bidirectional power device.

19. A bidirectional power device, formed using the manufacturing method according to any one of claims 1 to 18, the bidirectional power device comprising: Semiconductor layer; The first doped region is located in the semiconductor layer; Multiple trenches in the first trench region are located in the first doped region, dividing the first doped region into alternating first type sub-doped regions and second type sub-doped regions. A gate dielectric layer covers the lower sidewalls of multiple trenches in the first trench region; A control gate is located at the bottom of a plurality of trenches in the first trench region and is in contact with the gate dielectric layer; A shielding dielectric layer covers the upper sidewalls of multiple trenches in the first trench region and is located on the surface of the control gate; as well as The first shielding grid is located in a plurality of trenches in the first trench region and is in contact with the shielding medium layer. The shielding medium layer separates the control gate and the first shielding gate, and the thickness of the shielding medium layer on the upper sidewall of the trench in the first trench region is inconsistent.

20. The bidirectional power device according to claim 19, wherein, When one of the first type of sub-doped region and the second type of sub-doped region is used as the source region, the other of the first type of sub-doped region and the second type of sub-doped region is used as the drain region.

21. The bidirectional power device according to claim 19, wherein, It also includes trenches in a second trench region, located in the semiconductor layer and separated from the first doped region; The gate dielectric layer is also located on the sidewall of the trench in the second trench region, and the control gate is also located in the trench of the second trench region and in contact with the gate dielectric layer; The trenches in the first trench area are connected to the trenches in the second trench area, and the control gate located in the trench of the first trench area is connected to the control gate located in the trench of the second trench area.

22. The bidirectional power device according to claim 21, wherein, It also includes trenches in a third trench region, located in the semiconductor layer and separated from the first doped region; The gate dielectric layer also covers the lower sidewall of the trench in the third trench region, the control gate is also located in the lower part of the trench in the third trench region and is in contact with the gate dielectric layer, the shielding dielectric layer also covers the upper sidewall of the trench in the third trench region and is located on the surface of the control gate, the first shielding gate is also located in the upper part of the trench in the third trench region and is in contact with the shielding dielectric layer, and the shielding dielectric layer separates the control gate and the first shielding gate; The trenches in the first trench area are connected to the trenches in the third trench area. The control gate in the trench of the first trench area is connected to the control gate in the trench of the third trench area. The first shielding gate in the trench of the first trench area is connected to the first shielding gate in the trench of the third trench area.

23. The bidirectional power device according to claim 19, wherein, It also includes a second shielding grid, which is located on the upper part of a plurality of trenches in the first trench area and in contact with the shielding medium layer. The second shielding grid is located on the first shielding grid and in contact with the first shielding grid. The thickness of the shielding medium layer is inconsistent at the portion that contacts the first shielding grid and the second shielding grid.

24. The bidirectional power device according to claim 23, wherein, The shielding medium layer includes a first part, a second part, and a third part, wherein the third part of the shielding medium layer surrounds the second shielding grid, the second part of the shielding medium layer surrounds the first shielding grid, and the first part of the shielding medium layer is located on the surface of the control grid. The thickness of the first, second, and third portions of the shielding medium layer decreases sequentially.

25. The bidirectional power device according to claim 24, wherein, The thickness of the second portion of the shielding dielectric layer is greater than the thickness of the gate dielectric layer.

26. The bidirectional power device according to any one of claims 19-25, wherein, It also includes a channel region located in the semiconductor layer and adjacent to the control gate.

27. The bidirectional power device according to any one of claims 19-25, wherein, Also includes: The first contact region is located in the first type of sub-doped region; The second contact region is located in the second type of sub-doped region; as well as The third contact area is located in the semiconductor layer.

28. The bidirectional power device according to claim 27, wherein, Also includes: A covering dielectric layer is located on the surface of the semiconductor layer; as well as The substrate electrode, first contact electrode, second contact electrode, first gate electrode, and second gate electrode pass through the covering dielectric layer. The substrate electrode is connected to the third contact area, the first contact electrode is connected to the first contact area, the second contact electrode is connected to the second contact area, the first gate electrode is connected to the control gate, and the second gate electrode is connected to the first shielding gate.

29. The bidirectional power device according to claim 28, wherein, The first gate electrode is connected to the second gate electrode to receive the same control voltage.

30. The bidirectional power device according to claim 28, wherein, The first gate electrode is electrically isolated from the second gate electrode to receive different control voltages.

31. The bidirectional power device according to any one of claims 19-25, wherein, The thickness of the gate dielectric layer ranges from 10 to 9999 Å.

32. The bidirectional power device according to claim 22, wherein, The depth range of the multiple trenches in the first trench area, the second trench area and the third trench area includes 0.1~50μm.

33. The bidirectional power device according to any one of claims 19-25, wherein, The distance from the surface of the control gate located in the first trench region to the surface of the semiconductor layer includes 0.1~49μm.

34. The bidirectional power device according to claim 24, wherein, The thickness of the first portion of the shielding medium layer ranges from 30 to 20,000 Å.

35. The bidirectional power device according to claim 24, wherein, The thickness of the second portion of the shielding medium layer ranges from 20 to 10,000 Å.

36. The bidirectional power device according to any one of claims 19-25, wherein, When the bidirectional power device is turned off, the shielding gate depletes the charge of the first type of sub-doped region and the second type of sub-doped region through the shielding dielectric layer, thereby improving the breakdown voltage characteristics of the bidirectional power device.

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