Negative pressure generating circuit

Abstract

The present invention discloses a negative voltage generating circuit, comprising: a step-down module, an oscillator circuit, a clock buffer circuit and a charge pump circuit; the oscillator circuit is connected to the clock buffer circuit; the clock buffer circuit is connected to the charge pump circuit; the step-down module comprises: N field effect tubes connected in series, and the sum of the source-drain withstand voltage values ​​of N+1 field effect tubes is higher than the power supply level; the power input end of the step-down module is connected to the power supply, and the power output end of the step-down module is respectively connected to the oscillator circuit and the clock buffer circuit. By implementing the embodiments of the present invention, the complexity of the negative voltage generating circuit can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a negative voltage generating circuit. Background Art

[0002] Most electronic devices are powered by positive voltage, but in some special circuits, negative voltage may be more helpful for circuit performance. For example, in RF switching circuits, using negative voltage for biasing can improve the switching power handling capability, thereby optimizing the performance of the entire RF system.

[0003] like Figure 1 As shown, the existing negative voltage generating circuit is generally composed of an oscillator circuit, a clock buffer circuit and a charge pump circuit. The oscillator generates an oscillation signal, which is then passed through the clock buffer circuit to generate a two-phase non-overlapping clock, and finally the charge pump circuit generates the required negative voltage signal. The oscillator and clock buffer circuit in the existing negative voltage generating circuit are generally composed of inverter cascades, and the inverter formed by only one PMOS and one NMOS has limited voltage tolerance. Therefore, a step-down circuit composed of a low-dropout linear regulator (LDO) needs to be added to the high power level circuit to reduce the power supply voltage to power the oscillator circuit, the clock buffer and the charge pump circuit to ensure the normal operation of the circuit.

[0004] However, the above solution needs to add an additional step-down circuit composed of a low voltage drop linear regulator, which makes the entire negative voltage generating circuit too complicated. Summary of the invention

[0005] An embodiment of the present invention provides a negative voltage generating circuit, which can reduce the complexity of the negative voltage generating circuit.

[0006] An embodiment of the present invention provides a negative voltage generating circuit, comprising: a voltage step-down module, an oscillator circuit, a clock buffer circuit and a charge pump circuit;

[0007] The oscillator circuit is connected to the clock buffer circuit; the clock buffer circuit is connected to the charge pump circuit;

[0008] The step-down module comprises: N PMOS tubes connected in series; wherein the gates of the N PMOS tubes are connected to each other and are externally connected to a low-level signal; except for the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, the source of the first PMOS tube is the power input end of the step-down module, and the drain of the Nth PMOS tube is the power output end of the step-down module.

[0009] Optionally, the step-down module includes: N NMOS tubes connected in series; wherein the gates of the N NMOS tubes are interconnected and externally connected to a high-level signal; except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, the drain of the first NMOS tube is the power input terminal of the step-down module, and the source of the Nth NMOS tube is the power output terminal of the step-down module.

[0010] Optionally, the step-down module includes: M NMOS tubes and W PMOS tubes;

[0011] Wherein, M+W equals N; the gates of M NMOS tubes are connected to each other and are connected to a high level signal; the gates of W PMOS tubes are connected to each other and are connected to a low level signal;

[0012] Except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, the drain of the first NMOS tube is the power input terminal of the buck module, and the source of the Mth NMOS tube is connected to the source of the first PMOS tube;

[0013] Except for the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, and the drain of the Wth PMOS tube is the power output end of the buck module.

[0014] Optionally, the step-down module includes: M NMOS tubes and W PMOS tubes;

[0015] Wherein, M+W equals N; the gates of M NMOS tubes are connected to each other and are connected to a high level signal; the gates of W PMOS tubes are connected to each other and are connected to a low level signal;

[0016] Except for the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, the source of the first PMOS tube is the power input terminal of the buck module, and the drain of the Wth PMOS tube is connected to the drain of the first NMOS tube;

[0017] Except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, and the source of the Mth NMOS tube is the power output end of the buck module.

[0018] Further, the oscillator circuit includes: a first inverter, a second inverter, a third inverter, a first resistor, a second resistor and a first capacitor;

[0019] The power input terminals of the first inverter, the second inverter and the third inverter are all connected to the power output terminal of the step-down module;

[0020] The signal output end of the first inverter is connected to the signal input end of the second inverter, the signal output end of the second inverter is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the signal input end of the third inverter, and the signal output end of the third inverter is connected to the signal output end of the first inverter and the signal input end of the clock buffer circuit.

[0021] Furthermore, the clock buffer circuit includes: a fourth inverter, a first NOR gate logic unit, a second NOR gate logic unit, a first inverter group and a second inverter group; the first inverter group and the second inverter group are both formed by connecting a plurality of inverters in series;

[0022] The power input end of the fourth inverter, the power input end of the first NOR gate logic unit, the power input end of the second NOR gate logic unit, the power input end of each inverter in the first inverter group, and the power input end of each inverter in the second inverter group are all connected to the power output end of the step-down module;

[0023] The signal input end of the fourth inverter is the signal input end of the clock buffer circuit, and the signal output end of the fourth inverter is connected to the first signal input end of the second NOR gate logic unit;

[0024] The first signal input terminal of the first NOR gate logic unit is connected to the signal input terminal of the fourth inverter, the second signal input terminal of the first NOR gate logic unit is connected to the signal output terminal of the second inverter group, and the signal output terminal of the first NOR gate logic unit is connected to the signal input terminal of the first inverter group;

[0025] The signal output end of the first inverter group is the first signal output end of the clock buffer circuit, and the signal output end of the first inverter group is connected to the second signal input end of the second NOR gate logic unit;

[0026] The signal output terminal of the second NOR gate logic unit is connected to the signal input terminal of the second inverter group;

[0027] The signal output terminal of the second inverter group is the second signal output terminal of the clock buffer circuit.

[0028] Further, the charge pump circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a second capacitor, a third capacitor and a fourth capacitor;

[0029] A first end of the second capacitor is connected to the first signal output end of the clock buffer circuit, and a second end of the second capacitor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor respectively;

[0030] The source of the first PMOS tube is grounded, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube;

[0031] The source of the first NMOS transistor is connected to the source of the second NMOS transistor and the first end of the fourth capacitor respectively; the second end of the fourth capacitor is grounded;

[0032] The drain of the second NMOS tube is connected to the drain of the second PMOS tube and the gate of the first NMOS tube;

[0033] The source of the second PMOS tube is grounded, the gate of the second PMOS tube is connected to the gate of the second NMOS tube, and the gate of the second PMOS tube is also connected to the second end of the second capacitor;

[0034] A first end of the third capacitor is connected to the drain of the second NMOS tube and the drain of the second PMOS tube, and a second end of the third capacitor is connected to the second signal output end of the clock buffer circuit.

[0035] The following beneficial effects are achieved by implementing the embodiments of the present invention:

[0036] The embodiment of the present invention reduces the power supply voltage by connecting N field effect transistors in series to form a step-down module, so that the negative voltage generating circuit can be suitable for circuits with high power supply levels. Compared with the prior art, the step-down module proposed in the embodiment of the present invention has a simple structure and is much less complex than a step-down circuit based on a low-dropout linear regulator (LDO). Therefore, the structure of the overall negative voltage generating circuit is simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural schematic diagram of a negative pressure generating circuit in the prior art.

[0038] Figure 2 A schematic structural diagram of a negative voltage generating circuit provided by an embodiment of the present invention.

[0039] Figure 3 A schematic structural diagram of another negative voltage generating circuit provided by an embodiment of the present invention.

[0040] Figure 4 A schematic structural diagram of another negative voltage generating circuit provided by an embodiment of the present invention.

[0041] Figure 5A schematic structural diagram of another negative voltage generating circuit provided by an embodiment of the present invention.

[0042] Figure 6 A schematic structural diagram of another negative voltage generating circuit provided by an embodiment of the present invention.

[0043] Figure 7 A schematic structural diagram of an oscillator circuit provided by an embodiment of the present invention.

[0044] Figure 8 A schematic structural diagram of a clock buffer circuit provided by an embodiment of the present invention.

[0045] Fig. 9 A schematic structural diagram of a charge pump circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] like Figure 2 As shown, an embodiment of the present invention provides a negative voltage generating circuit, a voltage reduction module, an oscillator circuit, a clock buffer circuit and a charge pump circuit;

[0048] The oscillator circuit is connected to the clock buffer circuit; the clock buffer circuit is connected to the charge pump circuit;

[0049] The step-down module includes: N field effect transistors connected in series, and the sum of the source-drain withstand voltage values ​​of N+1 field effect transistors is higher than the power supply level (i.e., the level of the power supply VDD); the power input end of the step-down module is connected to the power supply (VDD), and the power output end of the step-down module is respectively connected to the oscillator circuit and the clock buffer circuit.

[0050] This embodiment of the present invention connects N series field effect transistors in series to form a step-down module to reduce the power supply voltage to power the oscillator circuit, the clock buffer and the charge pump circuit to ensure the normal operation of the circuit. Compared with the step-down circuit based on low voltage difference linear regulator (LDO), the step-down module provided by the present invention has a simple structure and is much less complex than the step-down circuit based on low voltage difference linear regulator (LDO), thereby making the structure of the overall negative voltage generating circuit simpler and reducing the complexity of the negative voltage generating circuit at a high power supply level.

[0051] It should be noted that the number N of field effect transistors can be roughly determined according to the source-drain withstand voltage value of the transistors in the process and the power supply level, and it should be ensured that the sum of the source-drain withstand voltage values ​​of the (n+1) transistors is higher than the power supply level.

[0052] The buck module is described in detail below. In the present invention, the buck module can select 4 different structures;

[0053] The first type: Figure 3 As shown, in an optional embodiment, the buck module includes: N PMOS tubes connected in series; wherein the gates of the N PMOS tubes are connected to each other and are externally connected to a low-level signal Except for the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, the source of the first PMOS tube is the power input terminal of the buck module, and the drain of the Nth PMOS tube is the power output terminal of the buck module. In this embodiment, the buck module is formed by connecting N PMOS tubes in series.

[0054] The second type, such as Figure 4 As shown, in an optional embodiment, the buck module includes: N NMOS tubes connected in series; wherein the gates of the N NMOS tubes are connected to each other and are externally connected to a high-level signal (ENABLE); except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, the drain of the first NMOS tube is the power input end of the buck module, and the source of the Nth NMOS tube is the power output end of the buck module. In this embodiment, the buck module is formed by connecting N NMOS tubes in series.

[0055] The third type, such as Figure 5 As shown, in an optional embodiment, the buck module includes: M NMOS tubes and W PMOS tubes; wherein M+W equals N; the gates of the M NMOS tubes are connected to each other and are externally connected to a high level signal (ENABLE); the gates of the W PMOS tubes are connected to each other and are externally connected to a low level signal Except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, the drain of the first NMOS tube is the power input terminal of the step-down module, and the source of the Mth NMOS tube is connected to the source of the first PMOS tube; except for the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, and the drain of the Wth PMOS tube is the power output terminal of the step-down module. In this embodiment, the step-down module is formed by connecting M NMOS tubes and W PMOS tubes in series, and the drain of the NMOS tube is used as the power input terminal of the step-down module, and the drain of the PMOS tube is used as the power output terminal of the step-down module.

[0056] The fourth type, such as Figure 6As shown, in an optional embodiment, the buck module includes: M NMOS tubes and W PMOS tubes; wherein M+W equals N; the gates of the M NMOS tubes are connected to each other and are externally connected to a high level signal (ENABLE); the gates of the W PMOS tubes are connected to each other and are externally connected to a low level signal Except for the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, the source of the first PMOS tube is the power input terminal of the buck module, and the drain of the Wth PMOS tube is connected to the drain of the first NMOS tube; except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, and the source of the Mth NMOS tube is the power output terminal of the buck module. In this embodiment, the buck module is also formed by connecting M NMOS tubes and W PMOS tubes in series, which is different from the third case in that the source of the PMOS tube is used as the power input terminal of the buck module, and the source of the NMOS tube is used as the power output terminal of the buck module.

[0057] For oscillator circuits, such as Figure 7 As shown, the oscillator adopts an inverter cascade structure, wherein the values ​​of resistors R1, R2 and capacitor C1 can be designed according to the required oscillation signal frequency. Since the working voltage of the oscillator is stepped down by the step-down module, the transistors of the inverter in the oscillator can work normally and finally generate an oscillation signal (ClK). In a preferred embodiment, the oscillator circuit includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a first resistor R1, a second resistor R2 and a first capacitor C1;

[0058] The power input terminals of the first inverter, the second inverter and the third inverter are all connected to the power output terminal of the step-down module;

[0059] The signal output end of the first inverter is connected to the signal input end of the second inverter, the signal output end of the second inverter is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the signal input end of the third inverter, and the signal output end of the third inverter is connected to the signal output end of the first inverter and the signal input end of the clock buffer circuit.

[0060] For clock buffer circuits, such as Figure 8 As shown, in a preferred embodiment, the clock buffer circuit includes: a fourth inverter INV4, a first NOR gate logic unit NOR1, a second NOR gate logic unit NOR2, a first inverter group 1 and a second inverter group 2; the first inverter group and the second inverter group are both formed by connecting a plurality of inverters in series;

[0061] The power input terminal of the fourth inverter, the power input terminal of the first NOR gate logic unit, the power input terminal of the second NOR gate logic unit, the power input terminals of each inverter in the first inverter group, and the power input terminals of each inverter in the second inverter group are all connected to the power output terminal of the step-down module;

[0062] The signal input end of the fourth inverter is the signal input end of the clock buffer circuit, and the signal output end of the fourth inverter is connected to the first signal input end of the second NOR gate logic unit;

[0063] The first signal input terminal of the first NOR gate logic unit is connected to the signal input terminal of the fourth inverter, the second signal input terminal of the first NOR gate logic unit is connected to the signal output terminal of the second inverter group, and the signal output terminal of the first NOR gate logic unit is connected to the signal input terminal of the first inverter group;

[0064] The signal output end of the first inverter group is the first signal output end of the clock buffer circuit, and the signal output end of the first inverter group is connected to the second signal input end of the second NOR gate logic unit;

[0065] The signal output terminal of the second NOR gate logic unit is connected to the signal input terminal of the second inverter group;

[0066] The signal output terminal of the second inverter group is the second signal output terminal of the clock buffer circuit.

[0067] It should be noted that the number of inverters in the first inverter combination and the second inverter is an even number, for example, 2, 4, 6, etc. Similarly, the working voltage of the clock buffer circuit can ensure the normal operation of each gate circuit after voltage reduction, and finally generate two non-overlapping clock signals (Clk1 and Clk2).

[0068] For a charge pump circuit, such as Fig. 9 As shown, in a preferred embodiment, the charge pump circuit includes: a first PMOS transistor M1, a second PMOS transistor M3, a first NMOS transistor M2, a second NMOS transistor M4, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4;

[0069] A first end of the second capacitor is connected to the first signal output end of the clock buffer circuit, and a second end of the second capacitor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor respectively;

[0070] The source of the first PMOS tube is grounded, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube;

[0071] The source of the first NMOS tube is connected to the source of the second NMOS tube and the first end of the fourth capacitor respectively; the second end of the fourth capacitor is grounded;

[0072] The drain of the second NMOS tube is connected to the drain of the second PMOS tube and the gate of the first NMOS tube;

[0073] The source of the second PMOS tube is grounded, the gate of the second PMOS tube is connected to the gate of the second NMOS tube, and the gate of the second PMOS tube is also connected to the second end of the second capacitor;

[0074] A first end of the third capacitor is connected to the drain of the second NMOS tube and the drain of the second PMOS tube, and a second end of the third capacitor is connected to the second signal output end of the clock buffer circuit.

[0075] The charge pump circuit uses a CMOS switch to charge and discharge the capacitor. When Clk1 is high, Clk2 is 0, M1 and M4 are turned on, Clk1 continues to charge C2, and C4 is still 0; when Clk1 is 0, Clk2 is high, M3 and M2 are turned on, Clk2 continues to charge C3. Since the voltage on capacitor C2 cannot change suddenly, when the voltage on the upper plate of C2 is 0, the lower plate becomes negative voltage, and C4 is charged through the turned-on M2 tube. Repeating this process, the charge pump can finally output a stable negative voltage.

[0076] The above are preferred embodiments of the present invention. It should be noted that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A negative voltage generating circuit, characterized in that: include: A step-down module, an oscillator circuit, a clock buffer circuit and a charge pump circuit; the step-down module includes: M NMOS tubes and W PMOS tubes; The oscillator circuit is connected to the clock buffer circuit; the clock buffer circuit is connected to the charge pump circuit; The step-down module comprises: N field effect tubes connected in series, and the sum of the source-drain withstand voltage values ​​of N+1 field effect tubes is higher than the power supply level; The power input end of the step-down module is connected to the power supply, and the power output end of the step-down module is respectively connected to the oscillator circuit and the clock buffer circuit; wherein, M+W equals N; the gates of the M NMOS tubes are connected to each other and externally connected to a high-level signal; the gates of the W PMOS tubes are connected to each other and externally connected to a low-level signal; except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, the drain of the first NMOS tube is the power input end of the step-down module, and the source of the Mth NMOS tube is connected to the source of the first PMOS tube; except for the first P MOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, and the drain of the Wth PMOS tube is the power output end of the step-down module; or, except the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, the source of the first PMOS tube is the power input end of the step-down module, and the drain of the Wth PMOS tube is connected to the drain of the first NMOS tube; except the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, and the source of the Mth NMOS tube is the power output end of the step-down module.

2. The negative voltage generating circuit according to claim 1, characterized in that: The step-down module comprises: N PMOS tubes connected in series; wherein the gates of the N PMOS tubes are connected to each other and are externally connected to a low-level signal; except for the first PMOS tube, the source of each PMOS tube is connected to the drain of the previous PMOS tube, the source of the first PMOS tube is the power input end of the step-down module, and the drain of the Nth PMOS tube is the power output end of the step-down module.

3. The negative voltage generating circuit according to claim 1, characterized in that: The step-down module comprises: N NMOS tubes connected in series; wherein the gates of the N NMOS tubes are connected to each other and are externally connected to a high-level signal; except for the first NMOS tube, the drain of each NMOS tube is connected to the source of the previous NMOS tube, the drain of the first NMOS tube is the power input end of the step-down module, and the source of the Nth NMOS tube is the power output end of the step-down module.

4. The negative voltage generating circuit according to claim 1, characterized in that: The oscillator circuit comprises: a first inverter, a second inverter, a third inverter, a first resistor, a second resistor and a first capacitor; The power input terminals of the first inverter, the second inverter and the third inverter are all connected to the power output terminal of the step-down module; The signal output end of the first inverter is connected to the signal input end of the second inverter, the signal output end of the second inverter is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the signal input end of the third inverter, and the signal output end of the third inverter is connected to the signal output end of the first inverter and the signal input end of the clock buffer circuit.

5. The negative voltage generating circuit according to claim 4, characterized in that: The clock buffer circuit comprises: a fourth inverter, a first NOR gate logic unit, a second NOR gate logic unit, a first inverter group and a second inverter group; the first inverter group and the second inverter group are both formed by connecting a plurality of inverters in series; The power input end of the fourth inverter, the power input end of the first NOR gate logic unit, the power input end of the second NOR gate logic unit, the power input end of each inverter in the first inverter group, and the power input end of each inverter in the second inverter group are all connected to the power output end of the step-down module; The signal input end of the fourth inverter is the signal input end of the clock buffer circuit, and the signal output end of the fourth inverter is connected to the first signal input end of the second NOR gate logic unit; The first signal input terminal of the first NOR gate logic unit is connected to the signal input terminal of the fourth inverter, the second signal input terminal of the first NOR gate logic unit is connected to the signal output terminal of the second inverter group, and the signal output terminal of the first NOR gate logic unit is connected to the signal input terminal of the first inverter group; The signal output end of the first inverter group is the first signal output end of the clock buffer circuit, and the signal output end of the first inverter group is connected to the second signal input end of the second NOR gate logic unit; The signal output terminal of the second NOR gate logic unit is connected to the signal input terminal of the second inverter group; The signal output terminal of the second inverter group is the second signal output terminal of the clock buffer circuit.

6. The negative voltage generating circuit according to claim 5, characterized in that: The charge pump circuit comprises: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a second capacitor, a third capacitor and a fourth capacitor; A first end of the second capacitor is connected to the first signal output end of the clock buffer circuit, and a second end of the second capacitor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor respectively; The source of the first PMOS tube is grounded, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube; The source of the first NMOS transistor is connected to the source of the second NMOS transistor and the first end of the fourth capacitor respectively; the second end of the fourth capacitor is grounded; The drain of the second NMOS tube is connected to the drain of the second PMOS tube and the gate of the first NMOS tube; The source of the second PMOS tube is grounded, the gate of the second PMOS tube is connected to the gate of the second NMOS tube, and the gate of the second PMOS tube is also connected to the second end of the second capacitor; A first end of the third capacitor is connected to the drain of the second NMOS tube and the drain of the second PMOS tube, and a second end of the third capacitor is connected to the second signal output end of the clock buffer circuit.

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