Joint assembly including side joint structure and method of manufacturing the same

Abstract

The present invention discloses a bonding assembly, which includes: a first stack, the first stack including a first semiconductor die bonded to a second semiconductor die along a stacking direction; a first external bonding pad formed in the first semiconductor die; and bonding wires. Each of the bonding wires extends above a sidewall of the first semiconductor die and protrudes through the sidewall of the first semiconductor die into the first semiconductor die to contact a corresponding one of the first external bonding pads.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 372,908, filed on April 2, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to a bonding assembly and method of making the same using a side bonding structure located on a sidewall of a semiconductor die. Background Art

[0004] Multiple semiconductor dies may be bonded together to provide a bonded assembly. Providing reliable electrical connections across multiple semiconductor dies may be a challenge because external bond pads of the semiconductor dies on the top surface of the semiconductor dies are typically physically exposed for attaching the external bond pads to bond wires. The staggered configuration of the semiconductor dies results in a lateral expansion of the size of the bonded assembly. Limiting the lateral size of the bonded assembly requires reducing the die size of the semiconductor dies stacked at the upper end. Summary of the invention

[0005] According to one embodiment of the present disclosure, a bonding assembly includes: a first stack including a first semiconductor die bonded to a second semiconductor die along a stacking direction; first external bonding pads formed within the first semiconductor die; and bonding wires. Each of the bonding wires extends over a sidewall of the first semiconductor die and protrudes through the sidewall of the first semiconductor die into the first semiconductor die to contact a corresponding one of the first external bonding pads.

[0006] According to another embodiment of the present disclosure, a method for forming a bonding assembly is provided, the method comprising: forming a first external bonding pad on the front side of a first semiconductor die; forming a first bonding pad on the first semiconductor die so that a bonding side surface of the first bonding pad is farther from a substrate of the first semiconductor die than a front side surface of the first external bonding pad is from the substrate; forming a first sacrificial pad covering structure above the first external bonding pad; bonding a second semiconductor die to the first semiconductor die so that the first bonding pad of the first semiconductor die is bonded to a second bonding pad of the second semiconductor die; forming a first side cavity by removing the first sacrificial pad covering structure from a side wall of the first semiconductor die; and forming a bonding connection wire by directly injecting a bonding wire material into the first side cavity on the first external bonding pad and by continuously extracting the bonding wire material above the side wall of the first semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of a first semiconductor die after forming a first bond pad, an outer bond pad, and a sacrificial pad cover structure according to an embodiment of the present disclosure.

[0008] Figure 2 is a schematic vertical cross-sectional view of a second semiconductor die after forming a second bond pad according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of the first exemplary structure after bonding a second semiconductor die to the first semiconductor die according to an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of the first exemplary structure after thinning the substrate of the second semiconductor die according to an embodiment of the present disclosure.

[0011] Figure 5 is a vertical cross-sectional view of a first exemplary structure after optional lateral polishing according to an embodiment of the present disclosure.

[0012] Figure 6 is a vertical cross-sectional view of the first exemplary structure after removal of a sacrificial pad covering structure according to an embodiment of the present disclosure.

[0013] Figure 7 is a vertical cross-sectional view of the first exemplary structure after forming a bonding connection line in a cavity formed by removing a sacrificial pad cover structure according to an embodiment of the present disclosure.

[0014] Figure 8 is a vertical cross-sectional view of a first alternative configuration of the first exemplary structure according to an embodiment of the present disclosure.

[0015] Fig.9A and Fig. 9B are vertical cross-sectional views of a second alternative configuration and a third alternative configuration of the first exemplary structure according to an embodiment of the present disclosure.

[0016] Fig. 10A is a vertical cross-sectional view of a region of a first semiconductor die after forming external bond pads according to an embodiment of the present disclosure.

[0017] Fig. 10B yes Fig. 10A A top view of a region of a first semiconductor die.

[0018] Fig.11A is a vertical cross-sectional view of a region of a first semiconductor die after forming an uppermost insulating layer and bonding pads according to an embodiment of the present disclosure.

[0019] Fig. 11B yes Fig.11A A top view of a region of a first semiconductor die.

[0020] Fig. 12A is a vertical cross-sectional view of a region of a first semiconductor die after forming a patterned photoresist layer according to an embodiment of the present disclosure.

[0021] Fig. 12B yes Fig. 12A A top view of a region of a first semiconductor die.

[0022] Fig.13A is a vertical cross-sectional view of a region of a first semiconductor die after forming a recessed region according to an embodiment of the present disclosure.

[0023] Fig. 13B yes Fig.13A A top view of a region of a first semiconductor die.

[0024] Fig.14A is a vertical cross-sectional view of a region of a first semiconductor die after depositing a layer of sacrificial fill material according to an embodiment of the present disclosure.

[0025] Fig. 14B yes Fig.14A A top view of a region of a first semiconductor die.

[0026] Fig.15A is a vertical cross-sectional view of a region of a first semiconductor die after forming a sacrificial pad cover structure according to an embodiment of the present disclosure.

[0027] Fig. 15B yes Fig.15A A top view of a region of a first semiconductor die.

[0028] Fig.16A yes Figure 3 A vertical cross-sectional view of a region of a first exemplary structure.

[0029] Fig. 16B is along Fig.16A A horizontal cross-sectional view of the area taken on a horizontal plane BB'.

[0030] Fig.17A yes Figure 5 A vertical cross-sectional view of a region of a first exemplary structure.

[0031] Fig. 17B is along Fig.17A A horizontal cross-sectional view of the area taken on a horizontal plane BB'.

[0032] Fig.18A yes Figure 6 A vertical cross-sectional view of a region of a first exemplary structure.

[0033] Fig.18B is along Fig.18A A horizontal cross-sectional view of the area taken on a horizontal plane BB'.

[0034] Fig.19A yes Figure 7 - A vertical cross-sectional view of a region of one of the first exemplary structures of FIG. 9 .

[0035] Fig.19B is along Fig.19A A horizontal cross-sectional view of the area taken on a horizontal plane BB'.

[0036] Fig. 20 According to the embodiments of the present disclosure Fig.9A , Fig. 9B , Fig.18A and Fig.18B A cross-sectional view of a second exemplary structure including a plurality of bonded semiconductor dies at a processing step of FIG.

[0037] Figure 21-24 According to the embodiments of the present disclosure Figure 7 -Figure 9, Fig.19A and Fig.19B Sequential cross-sectional views of a second exemplary structure including a plurality of bonded semiconductor dies at processing steps of FIG.

[0038] Fig.25 According to the embodiments of the present disclosure Figure 7 -Figure 9, Fig.19A and Fig.19B 0014] A cross-sectional view of an alternative embodiment of a second exemplary structure including a plurality of bonded semiconductor dies after processing steps.

[0039] Fig.26A is a top view of a first exemplary layout of bonding wires according to an embodiment of the present disclosure.

[0040] Fig.26B yes Fig.26A Side view of the structure.

[0041] Fig.27A is a top view of a second exemplary layout of bonding wires according to an embodiment of the present disclosure.

[0042] Fig.27B yes Fig.27A Side view of the structure. DETAILED DESCRIPTION

[0043] As described above, embodiments of the present disclosure relate to a bonding assembly and a method for manufacturing the same using a side bonding structure located on the sidewall of a semiconductor die, various embodiments of which are described below. Embodiments of the present disclosure may be used to form a bonding assembly comprising at least one memory die and at least one logic die and optionally comprising a packaging substrate. Embodiments disclosed herein provide a structure and method that provide electrical connections across multiple semiconductor dies without requiring a lateral dimension expansion of the bonding assembly or a gradual reduction in the die size in the upper semiconductor die. The accompanying drawings are not drawn to scale. Multiple instances of an element may be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first", "second" and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of the present disclosure. The same figure number represents the same element or a similar element. Unless otherwise specified, elements with the same figure number are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element may be positioned on the outside of a surface of the second element or on the inside of the second element. As used herein, a first element is positioned "directly" on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is a conductive path composed of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0044] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0045] As used herein, a first surface and a second surface are "vertically coincident" with each other if the second surface is above or below the first surface and there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends in a straight line in a direction that deviates less than 5 degrees from the vertical direction. A vertical plane or a substantially vertical plane is straight in a vertical direction or a substantially vertical direction and may or may not include curvature in a direction perpendicular to the vertical direction or the substantially vertical direction.

[0046] A monomeric three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate such as a semiconductor wafer without a substrate in between. The term "monomeric" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monomeric memory device. For example, as described in U.S. Patent No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monomeric stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory level before bonding, but since the memory level is initially formed above a separate substrate, such memory is not a true monomeric three-dimensional memory array. Various three-dimensional memory devices disclosed herein include monomeric three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein.

[0047] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are integrally bonded, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands as the total number of planes therein at the same time. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0048] refer to Figure 1 , shows a first semiconductor die 700 according to an embodiment of the present disclosure. The first semiconductor die 700 may be a logic die or a memory die. The first semiconductor die 700 may include a first semiconductor device 710 formed on a first semiconductor substrate 106. The first semiconductor device 710 may include a field effect transistor and / or a memory device, such as a three-dimensional memory array. A first dielectric material layer 760 may be formed above the first semiconductor device 710, and a first metal interconnect structure 780 may be formed within the first dielectric material layer 760. A first bonding pad 788 may be formed in or on the uppermost layer of the first dielectric material layer 760. The first bonding pad 788 may be a die-to-die bonding pad configured to bond to another semiconductor die (such as Figure 2 A first external bonding pad 80 formed within a corresponding first sacrificial pad cap structure 96 may be formed on the first semiconductor die 700 .

[0049] The side of the first semiconductor die 700 including the first dielectric material layer 760 and the first bonding pads 788 (which are first die-to-die bonding pads) is referred to herein as the front side of the first semiconductor die 700. The side of the first semiconductor die 700 including the first semiconductor substrate 106 is referred to herein as the back side of the first semiconductor die 700. Each of the first bonding pads 788 can be a metal bonding pad that can form a metal-to-metal bond. For example, the first bonding pads 788 can include copper, and its material composition provides a copper-to-copper bond.

[0050] Each of the first external bonding pads 80 may be formed within a corresponding first sacrificial pad covering structure 96. The first bonding pad 788 may be formed on the first semiconductor die 700 such that a bonding side surface of the first bonding pad 788 is farther from the first semiconductor substrate 106 (i.e., the substrate of the first semiconductor die 700) than a surface of the first external bonding pad 80 is from the first semiconductor substrate 106. In other words, the first external bonding pad 80 is vertically recessed relative to a horizontal plane including a top surface of the first bonding pad 788. Each first sacrificial pad covering structure 96 may be formed above a corresponding first external bonding pad 80 and may have a top surface located within a horizontal plane including a top surface of the first bonding pad 788. A method of forming an external bonding pad such as the first bonding pad 788 of the first semiconductor die 700 is described in detail later.

[0051] refer to Figure 2, showing a second semiconductor die 900 according to an embodiment of the present disclosure. The second semiconductor die 900 may be a logic die or a memory die. The second semiconductor die 900 may include a second semiconductor device formed on a second semiconductor substrate 906. The second semiconductor device may include a field effect transistor and / or a memory device, such as a three-dimensional memory array. In an illustrative example, the second semiconductor device may include an alternating stack of insulating layers 32 and conductive layers 46 used as word lines, and a memory stack structure 58 extending vertically through the alternating stack. In this case, each of the memory stack structures 58 may include a corresponding vertical semiconductor channel and a corresponding memory film. Each memory film may include a layer stack of a charge storage layer and a tunneling dielectric layer. Each vertical semiconductor channel may be connected to a source region at one end (such as a bottom end) and may be connected to a drain region at another end (such as a top end). A backward stepped dielectric material portion 65 may be formed on the stepped surface of the alternating stack. A second dielectric material layer 960 may be formed above the second semiconductor device, and a second metal interconnect structure 980 may be formed in the second dielectric material layer 960. In the case where the second semiconductor die 900 includes a three-dimensional array of memory elements, the second metal interconnect structure 980 may include a drain contact via structure 88 contacting the drain region, and a bit line 108 extending laterally in a horizontal direction perpendicular to the longitudinal direction of the word line, such as being embodied as a conductive layer 46.

[0052] The second bonding pad 988 may be formed in or on the uppermost layer of the second dielectric material layer 960. The second bonding pad 988 may be a die-to-die bonding pad configured to bond to another semiconductor die (such as Figure 1 In one embodiment, the second semiconductor die 900 may have a die-to-die bonding pad of the first semiconductor die 700 shown. In one embodiment, the second bonding pad 988 may have an image pattern that is a mirror image of the pattern of the first bonding pad 788. In one embodiment, the second semiconductor die 900 may be a memory die including a three-dimensional array of memory elements, and the first semiconductor die 700 may include peripheral circuits that control the operation of the three-dimensional array of memory elements. In one embodiment, the first semiconductor die 700 and the second semiconductor die 900 may be memory dies.

[0053] refer to Figure 3, the second bonding pad 988 can be bonded to the first bonding pad 788 to form a bonded assembly, which includes a stack 800 of two bonded tube cores, which include a first semiconductor tube core 700 and a second semiconductor tube core 900. One side of the bonded assembly, such as the side including the second semiconductor substrate 906, is referred to as the front side in this article, and the other side of the bonded assembly, such as the side including the first semiconductor substrate 106, is referred to as the back side in this article. Therefore, the first bonding pad 788 of the first semiconductor tube core 700 is referred to as the front side bonding pad of the first semiconductor tube core 700 (which is located on the front side of the first semiconductor tube core 700 in the bonded state), and the second bonding pad 988 of the second semiconductor tube core 900 is referred to as the back side bonding pad of the second semiconductor tube core 900 (which is located on the back side of the second semiconductor tube core 900 in the bonded state). Therefore, the front side bonding pad of the first semiconductor tube core 700 is bonded to the back side bonding pad of the second semiconductor tube core 900.

[0054] refer to Figure 4 The second semiconductor substrate 906, i.e., the substrate of the second semiconductor die 900, may be thinned, for example, by grinding, polishing, an isotropic etching process, and / or an anisotropic etching process. In one embodiment, the thickness of the second semiconductor substrate 906 may be in the range of 1 micron to 60 microns, so that a through-substrate contact via structure may be subsequently formed through the second semiconductor substrate 906.

[0055] refer to Figure 5 , the bonded assembly including the stack 800 may optionally be thinned on one or more sides of the bonded assembly including the first sacrificial pad covering structure 96. If the first sacrificial pad covering structure 96 is only disposed on one side of the bonded assembly, the side of the bonded assembly including the first sacrificial pad covering structure 96 may be thinned. If the first sacrificial pad covering structure 96 is disposed on multiple sides, each side including the first sacrificial pad covering structure 96 may be thinned or may not be thinned. Portions of the first semiconductor die 700 and the second semiconductor die 900 adjacent to each thinned side may be removed during the thinning process. The thinning process may use polishing, grinding, an isotropic etching process, and / or an anisotropic etching process. In embodiments in which the first sacrificial pad covering structure 96 is physically exposed to any sidewall of the bonded assembly, such side may be thinned or may not be thinned. If any of the first sacrificial pad covering structures 96 is Figure 4If the sidewalls of the first sacrificial pad covering structure 96 are not physically exposed in the bonding assembly, such sidewalls may be thinned until each buried first sacrificial pad covering structure 96 may be physically exposed. In one embodiment, after thinning or without thinning in the case of omitting the thinning process, the sidewalls of the first sacrificial pad covering structure 96 may be physically exposed, and the sidewalls of the first external bonding pad 80 may not be physically exposed. In another embodiment, after thinning or without thinning in the case of omitting the thinning process, the sidewalls of the first sacrificial pad covering structure 96 may be physically exposed, and the sidewalls of the first external bonding pad 80 may be physically exposed.

[0056] refer to Figure 6 , the first sacrificial pad covering structure 96 may be removed selectively with respect to the material of the first dielectric material layer 760, the second dielectric material layer 960, and the first external bonding pad 80. The first side cavity 97 may be formed in the volume from which the first sacrificial pad covering structure 96 is removed. In one embodiment, the removal of the first sacrificial pad covering structure 96 from the sidewalls of the first semiconductor die 700 may be achieved by isotropically removing the material of the first sacrificial pad covering structure 96 selectively with respect to the material of the first external bonding pad 80 and the dielectric material layers of the first semiconductor die 700 and the second semiconductor die 900 (which include the pad-level dielectric material layer in which the front side bonding pad has been formed).

[0057] refer to Figure 7 , a metal bonding material may be applied to each of the first side cavities 97, and the metal bonding material may then be extracted to form a bonding wire 98. The bonding wire 98 may be anchored to the first external bonding pad 80 by filling the distal sidewall of the first external bonding pad 80. The bonding wire 98 may extend continuously to another semiconductor die (which may or may not be another bonding component including the stack 800) and / or another substrate, such as a package substrate (not shown), and may be bonded to a corresponding external bonding pad located on the semiconductor die or substrate. Figure 7 An embodiment is shown in which the sidewalls of the first external bond pad 80 vertically coincide with the sidewalls of the first semiconductor die 700 and the second semiconductor die 900. As used herein, a first surface and a second surface vertically coincide with each other if there is a vertical plane including the first surface and the second surface, and if the second surface overlies above or below the first surface.

[0058] Figure 8A first alternative configuration of a bonded assembly including a stack 800 of the first exemplary structure is shown, wherein the outer sidewalls of the first external bond pads 80 are laterally recessed relative to the nearest sidewalls of the first semiconductor die 700 and the second semiconductor die 900, and the bond connection wires 98 partially fill the first side cavities 97 formed by removing the first sacrificial pad cover structure 96. This configuration is advantageous because it can reduce stress on the bond wires as will be described below.

[0059] Fig.9A A second alternative configuration of a bonding assembly including a stack 800 of the first exemplary structure is shown, wherein the outer sidewalls of the first external bonding pad 80 are laterally recessed relative to the nearest sidewalls of the first semiconductor die 700 and the second semiconductor die 900, and the bonding connection wire 98 completely fills the first side cavity 97 formed by removing the first sacrificial pad covering structure 96. Fig. 9B A third alternative configuration of a bonded assembly including a stack 800 of the first exemplary structure is shown in which the bond connection wires 98 do not extend over the inner sidewalls of the first outer bond pads 80 .

[0060] Generally speaking, each bonding wire 98 can be formed as follows: by injecting bonding wire material directly into the corresponding first side cavity 97 on the corresponding first external bonding pad 80, and by continuously extracting the bonding wire material over the sidewalls of the bonding component (for example, over the sidewalls of the stack 800), such as the sidewalls of the first semiconductor tube core 700 and / or the sidewalls of the second semiconductor tube core 900.

[0061] Figures 10A-19B A series of zoomed-in views show the Figure 1 - Processing steps of Figure 9.

[0062] refer to Fig. 10A and Fig. 10B , respectively, illustrate a region of the first semiconductor die 700 after forming the first external bonding pad 80 in a vertical cross-sectional view and a top view. The interconnect-level dielectric material layer 761 may be formed at Figure 110. The first semiconductor device 710 on the first semiconductor substrate 106 is shown. The interconnect-level dielectric material layer 761 includes a subset of layers within the first dielectric material layer 760, which does not include a subsequently formed pad-level dielectric material layer. The first metal interconnect structure 780 may be formed within the interconnect-level dielectric material layer 761. The first external bonding pad 80 may be formed simultaneously with the formation of the subset of the first metal interconnect structure 780, or may be formed in a separate processing step. In one embodiment, the first external bonding pad 80 may include at least one conductive material different from the material of the first metal interconnect structure 780. In one embodiment, the first external bonding pad 80 may include at least one metal material optimized for bonding with a bonding connection wire. For example, the first external bonding pad 80 may include a metal pad 80A (such as a copper pad or an aluminum pad) and an under-bump metallurgy (UBM) stack 80B. The exemplary UBM stack 80B includes a body metal layer (such as a nickel layer) and a passivation metal layer (such as a gold layer and / or a palladium layer) with a thickness ranging from 100nm to 3000nm from bottom to top.

[0063] refer to Fig.11A and Fig. 11B , a pad-level dielectric material layer 762 may be formed over the interconnect-level dielectric material layer 761. The combination of the interconnect-level dielectric material layer 761 and the pad-level dielectric material layer 762 constitutes a first dielectric material layer 760. The various constituent layers of the first dielectric material layer 760 include corresponding dielectric materials, such as silicon oxide, silicon nitride, or organic silicate glass. The thickness of the pad-level dielectric material layer 762 may be in the range of 400nm to 8000nm, but smaller and larger thicknesses may also be used. The first bonding pad 788 may be formed on or in the pad-level dielectric material layer 762.

[0064] refer to Fig. 12A and Fig. 12B , a photoresist layer 763 may be applied over the pad-level dielectric material layer 762 and may be photolithographically patterned to form an opening over the area of ​​the first external bonding pads 80. In one embodiment, the shape of the opening in the photoresist layer 763 may be selected so that the entire area of ​​each first external bonding pad 80 is completely within the perimeter of the overlying opening in the photoresist layer 763. In a plan view along a direction perpendicular to the top surface of the first external bonding pad 80, i.e., in a plan view along a vertical direction, each opening in the patterned photoresist layer 763 may have a perimeter that is located outside the perimeter of the first external bonding pad 80 below and laterally encapsulates the perimeter of the first external bonding pad. A limited lateral offset may be provided between the perimeter of each first external bonding pad 80 and the perimeter of the overlying opening in the photoresist layer 763. All first bonding pads 788 may be covered by the photoresist layer 763.

[0065] refer to Fig.13A and Fig. 13B , an anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer 763 through the entire thickness of the pad level dielectric material layer 762. Portions of the pad level dielectric material layer 762 may be vertically recessed around each first external bonding pad 80 so that the front side surface of each first external bonding pad 80 is physically exposed. The entire top surface of each first external bonding pad 80 may be physically exposed by the anisotropic etching process.

[0066] Optionally, the anisotropic etching process may be extended after the top surface of the first external bonding pad 80 is physically exposed. The chemistry of the anisotropic etching process may be selected so that the anisotropic etching process etches the material of the interconnect-level dielectric material layer 761 selectively to the material of the first external bonding pad 80. The top surface of the interconnect-level dielectric material layer 761 may be vertically recessed relative to the top surface of the first external bonding pad 80. In this case, the pad-level dielectric material layer 762 is anisotropically etched in the area of ​​the opening in the patterned photoresist layer 763 so that the sidewalls of the first external bonding pad 80 are physically exposed. Recessed areas 89 may be formed above each first external bonding pad 80. Each recessed area 89 may have an area of ​​an overlying opening in the photoresist layer 763. The photoresist layer 763 may then be removed, for example, by ashing or by an organic solvent to avoid oxidation.

[0067] refer to Fig.14A and Fig. 14B , a sacrificial filling material layer 96L may be deposited in the recessed area 89 and above the first dielectric material layer 760. The sacrificial filling material layer 96L includes a material that can be subsequently selectively removed for the material of the first dielectric material layer 760 and the first external bonding pad 80. In one embodiment, the sacrificial filling material layer 96L may include a polymer material layer that can be subsequently selectively dissolved for the material of the first dielectric material layer 760 and the first external bonding pad 80. For example, the sacrificial filling material layer 96L may include polyimide. Alternatively, the sacrificial filling material layer 96L may include a material that can be selectively removed for the material of the first dielectric material layer 760 and the first external bonding pad 80 by ashing. For example, the sacrificial filling material layer 96L may include amorphous carbon or a carbon-based material. The thickness of the sacrificial filling material layer 96L may be greater than the maximum depth of the recessed area 89 so that the recessed area 89 is completely filled.

[0068] refer to Fig.15A and Fig. 15B, the excess portion of the sacrificial fill material overlying the horizontal plane including the top surface of the first dielectric material layer 760 and the first bonding pad 788 can be removed by a planarization process such as chemical mechanical planarization. Each remaining portion of the sacrificial fill material filling the recessed area 89 constitutes a sacrificial pad covering structure. Each first external bonding pad 80 can be covered by a corresponding sacrificial pad covering structure, which has a top surface that is coplanar with the top surface of the first dielectric material layer 760 and the physically exposed front side surface of the first bonding pad 788. Upon completion Fig.15A and Fig. 15B After the processing steps, it can provide Figure 1 The first semiconductor die 700 is provided.

[0069] refer to Fig.16A and Fig. 16B , executable Figure 3 and Figure 4 The processing steps are as follows to form a bonded assembly of the first semiconductor die 700 and the second semiconductor die 900 , and optionally thin the second semiconductor substrate 906 and / or thin the first semiconductor substrate 106 .

[0070] refer to Fig.17A and Fig. 17B , the sidewalls of the bonding assembly may be optionally thinned on any side or each side including the first external bonding pad 80. The sidewalls of each sacrificial pad covering structure in the sacrificial pad covering structure may be physically exposed. The first external bonding pad 80 and therefore the sacrificial pad covering structure may be disposed on one side, two sides, three sides or four sides of the first semiconductor die 700. Each of the first external bonding pads 80 may or may not have physically exposed sidewalls, depending on the degree of thinning of the sidewalls of the bonding assembly of the first semiconductor die 700 and the second semiconductor die 900. In this step, the cutting saw (e.g., a laser saw) does not cut into the metal of the first external bonding pad 80. This reduces the amount of metal dust generated during cutting, thereby reducing the chance of short circuits caused by metal dust. Therefore, in one embodiment, the first external bonding pad 80 may be spaced a certain distance laterally from the cutting line to reduce or avoid the generation of metal dust during cutting.

[0071] refer to Fig.18A and Fig.18B , the sacrificial pad covering structure can be removed selectively with respect to the materials of the first dielectric material layer 760, the second dielectric material layer 960, and the first external bonding pad 80. For example, if the sacrificial pad covering structure includes polyimide or another polymer material that is soluble in an organic solvent, the removal of the sacrificial pad covering structure can be performed by dissolving the sacrificial pad covering structure in such an organic solvent. Alternatively, the sacrificial pad covering structure can be removed by ashing.

[0072] refer to Fig.19Aand Fig.19B , a metal bonding material may be applied to each of the first side cavities 97, and the metal bonding material may then be extracted to form bonding wires 98. The bonding wires 98 may extend continuously to another semiconductor die (which may or may not be the second semiconductor die 900) and / or another substrate, such as a package substrate (not shown), and may be bonded to corresponding external bonding pads located on the semiconductor die or substrate.

[0073] The bonding wire 98 may include a protruding portion 98P that may protrude into an opening through the sidewall of the first semiconductor die 700 and contact the first external bonding pad 80, and an inter-die connection portion 98I that is connected to the protruding portion 98P. The protruding portion 98P contacts the front side surface of the first external bonding pad 80 facing the second semiconductor die 900. The protruding portion 98P contacts the proximal sidewall 8P of the first external bonding pad 80 facing the inter-die connection portion 98I, and contacts the distal sidewall 8D of the first external bonding pad 80 facing away from the inter-die connection portion 98I. As shown in the cross-sectional view of FIG. 19, the bonding wire 98 may surround the first external bonding pad 80 so as to anchor the bonding wire 98 above and around the first external bonding pad 80 in a secure manner. The secure anchoring of the bonding wire 98 may provide an anti-peeling feature for the bonding wire 98.

[0074] refer to Fig. 20 ,exist Fig.9A , Fig. 9B , Fig.18A and Fig.18B A second exemplary structure including an assembly 1100 including a plurality of stacks 800 is shown at processing step . Fig. 20 The second exemplary structure of the assembly 1100 can be formed by stacking the plurality of stacks 800 and the optional packaging substrate 1000 described above. The stacks 800 can be connected to each other by glue and / or mechanical fasteners to form the assembly 1100. Each of the plurality of stacks 800 is connected to the packaging substrate 1000. Figure 6 , Fig.18A and Fig.18BThe first semiconductor die 700 shown includes a corresponding set of external bonding pads and a corresponding set of side cavities in the same manner. Multiple stacks 800 may include memory dies, logic dies (such as support dies for memory dies), or a combination of memory and logic dies. For example, each stack 800 may include a second semiconductor die 900 bonded to a logic support die as described in the previous embodiments. For example, at least two stacks, such as three to twenty stacks, for example seven stacks 800 (e.g., 800A, 800B, 800C, 800D, 800E, 800F, and 800G) may be stacked with a corresponding main surface of a stack (e.g., 800A) contacting a main surface on an adjacent stack (e.g., 800B), and the outer sidewalls are exposed.

[0075] Executable Fig.9A , Fig. 9B , Fig.18A and Fig.18B The processing steps are performed to form side cavities in each stack in the stack 800 so that the side cavities are exposed before or after stacking the stacks 800 together. The packaging substrate 1000 can be attached to the first stack 800A. The packaging substrate 1000 can be any packaging substrate known in the art. If used, the packaging substrate 1000 can be a laminated packaging substrate or a ceramic packaging substrate. Each stack 800 in the assembly includes a corresponding set of external bonding pads that are physically exposed to a corresponding set of side cavities.

[0076] refer to Fig.21 , the wire extraction device 300 can be used to inject the bonding wire material into the side cavity located on the first external bonding pad 80, and the bonding connection wire 98 will be connected to the first external bonding pad. In one embodiment, the bonding wire material can be squeezed into the side cavity through the top end 398 of the wire extraction device 300.

[0077] refer to Fig. 22 , the bond wire material is continuously extracted over the sidewalls of stack 800 (eg, the supporting die of stack 800G) that form the initial portion of the bond connection wire toward the next side cavity that is adjacent to the next external bond pad that will subsequently be bonded.

[0078] refer to Fig.23 , the bond wire material is continuously extracted to form a next portion that fills the second side cavity and contacts a second external bond pad in the next semiconductor die of the next stack 800F.

[0079] refer to Fig.24 , repeatable Fig.23The process steps are repeated until the bond wires 98 extend continuously across all stacks 800 and optionally to the package substrate 1000 and provide electrical connections across a set of external bond pads distributed across multiple stacks 800 and optionally in the package substrate 1000. In one embodiment, the bond wires 98 may be formed with loops so that the bond wires 98 do not contact the sidewalls of the stacks 800 outside of the area where the bond wires 98 protrude into the side cavity of the stacks 800.

[0080] refer to Fig.25 , shows an alternative embodiment of the second exemplary structure, in which bonding wires 98 are formed directly on the insulating sidewalls of the stack 800.

[0081] refer to Fig.26A and Fig.26B , a plurality of bonding wires 98 may be used to provide electrical connections across the plurality of stacks 800. At least one bonding wire and / or each bonding wire in the bonding wires 98 may provide electrical connections across a corresponding set of external bonding pads located in the plurality of stacks 800.

[0082] refer to Fig.27A and Fig.27B , showing an alternative layout for bonding wires 98. In this case, at least one bonding wire and / or each bonding wire in the plurality of bonding wires 98 may provide an electrical connection between a single external bonding pad on one of the plurality of stacks 800 and another external bonding pad located on another structure, such as package substrate 1000.

[0083] With reference to all the drawings and in accordance with various embodiments of the present disclosure, there is provided a bonding assembly comprising: a stack 800 (e.g., a first stack 800A) comprising at least a first semiconductor die 700, first external bonding pads 80 formed within the first semiconductor die 700, and bonding wires 98, the first semiconductor die being bonded to a second semiconductor die 900 along a stacking direction. Each of the bonding wires 98 extends over a sidewall of the first semiconductor die 700 and protrudes through the sidewall of the first semiconductor die 700 into the first semiconductor die 700 to contact a corresponding one of the first external bonding pads 80. As used herein, the stacking direction refers to a direction perpendicular to a bonding interface between two semiconductor dies.

[0084] In one embodiment, the first semiconductor die 700 includes front side bonding pads having respective planar surfaces perpendicular to the stacking direction, the second semiconductor die 900 includes back side bonding pads having respective planar surfaces perpendicular to the stacking direction, and the back side bonding pads are bonded to the front side bonding pads.

[0085] In one embodiment, each of the bonding wires 98 includes: an inter-die connection portion 98I, which is located outside the first semiconductor die 700 and extends above the side wall of the first semiconductor die 700 along the stacking direction; and a first protrusion portion, which protrudes into an opening through the side wall of the first semiconductor die 700 and contacts a corresponding one of the first external bonding pads 90.

[0086] In one embodiment, the first protrusion includes a first flat surface and a second flat surface, wherein the first flat surface contacts the top surface of a corresponding one of the first external bonding pads 80 perpendicular to the stacking direction (which may be a surface of the UBM stack 80B), and the second flat surface is spaced a uniform distance from the first flat surface and contacts the flat dielectric surface of the second semiconductor die 900.

[0087] In one embodiment, the second flat surface may be within the same two-dimensional plane as the bonding surface of the front side bonding pad; and the top surface of a corresponding one of the first external bonding pads 80 perpendicular to the stacking direction is offset along the stacking direction from the plane including the bonding surface of the front side bonding pad by the thickness of a segment of the first protrusion of the bonding connection line 98.

[0088] In one embodiment, the bonding assembly includes second external bonding pads formed within the second stack 800B. Each of the bonding connection wires 98 provides an electrical connection between a corresponding one of the first external bonding pads 80 and a corresponding one of the second external bonding pads by extending over the sidewalls of the first stack 800A and the second stack 800B and protruding into the second stack 800B to contact a corresponding one of the second external bonding pads.

[0089] exist Fig.24 In one embodiment shown, each of the bond wires 98 includes a second protruding portion that can protrude into an opening through a sidewall of the second stack 800B and contact a corresponding one of the second external bond pads.

[0090] In one embodiment, the first protrusion may contact the front side surface of a corresponding one of the first external bonding pads 80 facing the second stack 800B, and the second protrusion may contact the front side surface of a corresponding one of the second external bonding pads facing away from the first stack 800A.

[0091] In one embodiment, the first protrusion may contact the proximal side wall 8P of a corresponding one of the first external bonding pads 80 facing the inter-die connection portion 98I; and the second protrusion may contact the proximal side wall 8P of a corresponding one of the second external bonding pads facing the inter-die connection portion 98I.

[0092] In one embodiment, the first protrusion may contact the distal side wall 8D of a corresponding one of the first external bonding pads 80 that faces away from the inter-die connection portion 98I; and the second protrusion may contact the distal side wall 8D of a corresponding one of the second external bonding pads that faces away from the inter-die connection portion 98I.

[0093] In one embodiment, the inter-die connection portion 98I extends continuously on the outer sidewall of the first stack 800A and on the outer sidewall of the second stack 800B between the first protruding portion and the second protruding portion, as shown in FIG. Fig.25 shown.

[0094] In one embodiment, the first external bond pad 80 is spaced apart from the sidewall of the first semiconductor die 700 in the stack 800 by a lateral offset distance, such as Figure 8 Figure 9 Fig.24 and Fig.25 shown.

[0095] In one embodiment, the first external bonding pads 80 may be physically exposed and have sidewalls that are in the same two-dimensional plane as the sidewalls of the first semiconductor die 700, such as Figure 7 shown. Fig.24 and Fig.25 The second exemplary structure may be modified to provide this feature.

[0096] In one embodiment, the first outer bonding pad 80 may be arranged along the stacking direction from Figure 7-9B The second semiconductor die 900 in FIG. 1 is offset by a greater vertical offset distance than the backside surface of the frontside bond pad is offset from the second semiconductor die 900 .

[0097] In one embodiment, the bonded assembly includes a package substrate 1000 attached to the first stack 800A, wherein the bond connection wires 98 may be bonded to bond pads of the package substrate 1000 by wire bonding.

[0098] Various structures and methods of the embodiments of the present disclosure can be used to provide electrical connections using the sidewall surfaces of the semiconductor die in the bonding assembly. Since the bonding wire hooking area does not have to extend outward from the adjacent stack 800, the die size can be reduced. In addition, expensive through-silicon vias (TSVs) can be omitted. The protruding portion 98P of the bonding wire 98 can contact the sidewalls (8P, 8D) of the external bonding pad to provide protection to prevent the protruding portion 98P from sliding (i.e., pulling out) from the side cavity. By using the side surfaces of the bonding assembly, high-density wiring connections can be provided on the bonding assembly without excessively limiting the die size or the total number of dies that can be stacked in the bonding assembly.

[0099] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A joining assembly, comprising: a first stack comprising a first semiconductor die bonded to a second semiconductor die along a stacking direction, a first external bonding pad formed within the first semiconductor die; and bonding wires, wherein each of the bonding wires extends over a sidewall of the first semiconductor die and protrudes through the sidewall of the first semiconductor die into the first semiconductor die to contact a respective one of the first external bonding pads, and wherein a first sacrificial pad covering structure is formed above the first external bonding pad; forming a first side cavity by removing the first sacrificial pad covering structure from a sidewall of the first semiconductor die; as well as The bond wire is formed by injecting a bond wire material directly into the first side cavity on the first external bond pad and by continuously extracting the bond wire material over the sidewall of the first semiconductor die.

2. The joint assembly of claim 1, wherein: the first semiconductor die including front side bonding pads having respective planar surfaces perpendicular to the stacking direction; the second semiconductor die comprising backside bond pads having respective planar surfaces perpendicular to the stacking direction; and The backside bonding pad is bonded to the frontside bonding pad.

3. The bonding assembly of claim 2, wherein each of the bonding connection lines comprises: an inter-die connection portion located outside the first semiconductor die and extending over the sidewall of the first semiconductor die in the stacking direction; and A first protruding portion protrudes into the opening through the sidewall of the first semiconductor die and contacts the corresponding one of the first external bonding pads.

4. The joint assembly of claim 3, wherein: The first protruding portion includes a first flat surface and a second flat surface, the first flat surface contacts a top surface of the corresponding one of the first external bonding pads perpendicular to the stacking direction, and the second flat surface is spaced apart from the first flat surface by a uniform distance; The second planar surface is in the same two-dimensional plane as the bonding surface of the front side bonding pad; and The top surface of the corresponding one of the first external bonding pads perpendicular to the stacking direction is offset from a plane including a bonding surface of the front-side bonding pad by a thickness of a section of the first protrusion in the stacking direction.

5. The bonding assembly according to claim 3 further comprises second external bonding pads formed within a second stack of two bonding dies, wherein each of the bonding connection wires provides an electrical connection between the corresponding one of the first external bonding pads and the corresponding one of the second external bonding pads by extending over the sidewalls of the first stack and over the sidewalls of the stack and protruding into the second stack to contact a corresponding one of the second external bonding pads.

6. The bonding assembly of claim 5, wherein each of the bonding wires comprises a second protruding portion that protrudes into an opening through the sidewall of the second stack and contacts the corresponding one of the second external bonding pads.

7. The joint assembly of claim 6, wherein: The first protruding portion contacts a front side surface of a corresponding one of the first external bonding pads facing the second stack, and The second protrusion contacts a front side surface of a corresponding one of the second external bonding pads facing away from the first stack.

8. The joint assembly of claim 7, wherein: the first protruding portion contacts a proximal sidewall of a corresponding one of the first external bonding pads facing the inter-die connection portion; and The second protruding portion contacts a proximal sidewall of a corresponding one of the second external bonding pads facing the inter-die connection portion.

9. The joint assembly of claim 8, wherein: the first protruding portion contacts a distal sidewall of a corresponding one of the first external bonding pads facing away from the inter-die connection portion; and The second protruding portion contacts a distal sidewall of a corresponding one of the second external bonding pads facing away from the inter-die connecting portion.

10. The bonded assembly of claim 6, wherein the inter-die connection portion extends continuously on an outer sidewall of the first stack and on an outer sidewall of the second stack between the first protruding portion and the second protruding portion. 11 . The bond assembly of claim 1 , wherein the first external bond pad is spaced apart from the sidewall of the first semiconductor die by a lateral offset distance. 12 . The bond assembly of claim 1 , wherein the first external bond pad is physically exposed and has a sidewall that is within the same two-dimensional plane as the sidewall of the first semiconductor die. 13 . The bond assembly of claim 1 , wherein the first external bond pad is offset from the second semiconductor die in the stacking direction by a greater vertical offset distance than a backside surface of the frontside bond pad is offset from the second semiconductor die. 14 . The bonded assembly of claim 1 , further comprising a package substrate attached to the first stack, wherein the bond connection wires are bonded to bond pads of the package substrate by wire bonding.

15. The bonded assembly of claim 1, further comprising a second stack of bonded dies, the second stack bonded to the first stack via the bond wires.

16. A method of forming a joint assembly, the method comprising: forming a first external bond pad on the front side of the first semiconductor die; forming a first bonding pad on the first semiconductor die such that a bonding side surface of the first bonding pad is further from a substrate of the first semiconductor die than a front side surface of the first external bonding pad is from the substrate; forming a first sacrificial pad cover structure over the first external bonding pad; bonding a second semiconductor die to the first semiconductor die such that the first bond pad of the first semiconductor die is bonded to a second bond pad of the second semiconductor die; forming a first side cavity by removing the first sacrificial pad covering structure from a sidewall of the first semiconductor die; as well as A bond wire connection is formed by injecting a bond wire material directly into the first side cavity on the first external bond pad and by continuously extracting the bond wire material over the sidewall of the first semiconductor die.

17. The method according to claim 16, further comprising: depositing a layer of pad-level dielectric material over the first external bonding pad, wherein the first bonding pad is formed on or in the layer of pad-level dielectric material; forming a recessed region by recessing a portion of the pad level dielectric material layer around the external bonding pad so that the front side surface of the first external bonding pad is physically exposed; as well as The first sacrificial pad covering structure is formed in the recessed area on the front side surface of the first external bonding pad. 18 . The method of claim 17 , wherein removing the first sacrificial pad covering structure from the sidewall of the first semiconductor die comprises isotropically removing material of the first sacrificial pad covering structure selective to material of the first external bond pad and the pad level dielectric material layer.

19. The method of claim 17, wherein recessing the portion of the pad level dielectric material layer around the outer bonding pad comprises: forming a patterned photoresist layer in a plan view along a direction perpendicular to a top surface of the first external bonding pad, the patterned photoresist layer comprising an opening having a perimeter located outside a perimeter of the first external bonding pad and laterally enclosing the perimeter of the first external bonding pad; as well as Portions of the pad level dielectric material layer are anisotropically etched in the area of ​​the opening in the patterned photoresist layer such that sidewalls of the first external bonding pads on which the bonding connection wires are formed are physically exposed.

20. The method according to claim 16, further comprising: forming a second external bond pad on the second semiconductor die; before bonding the second semiconductor die to the first semiconductor die, forming a second sacrificial pad cover structure on the second external bonding pad; forming a second side cavity by removing the second sacrificial pad covering structure from the sidewalls of the second semiconductor die; as well as The bond wire material is injected directly into the second side cavity on the second outer bond pad and is extracted continuously over a sidewall of the second semiconductor die and over the sidewall of the first semiconductor die to the first side cavity.

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