Comparator for power and high speed applications

Abstract

In certain aspects, a comparator (100) includes a first inverter (110) having an input, an output, and a voltage supply input (112), wherein the input of the first inverter and the output of the first inverter are coupled together, and the voltage supply input (112) of the first inverter is configured to receive a first comparison voltage (VI). The comparator further includes a second inverter (120) having an input, an output, and a voltage supply input (122), wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input (122) of the second inverter is configured to receive a second comparison voltage (V2).

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to non-provisional application No. 16 / 375,734 filed with the U.S. Patent and Trademark Office on April 4, 2019, and provisional application No. 62 / 780,761 filed with the U.S. Patent and Trademark Office on December 17, 2018, the contents of which are incorporated herein by reference for all applicable purposes as if they were listed in full herein. Technical Field

[0003] The various aspects of this disclosure generally relate to comparators, and more specifically, to comparators for power and high-speed applications. Background Technology

[0004] A comparator can be configured to compare two input voltages and output a signal indicating which of the two input voltages is higher. Comparators can be used in a variety of devices, including analog-to-digital converters (ADCs), time-to-digital converters (TDCs), delay-locked loops (DLLs), and others. Summary of the Invention

[0005] The following is a simplified overview of one or more implementations to provide a basic understanding of such implementations. This invention is not a broad overview of all anticipated implementations, nor is it intended to identify key elements or components of all implementations, nor to depict a scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that follows.

[0006] The first aspect relates to a comparator. The comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input and output of the first inverter are coupled together, and the voltage supply input of the first inverter is configured to receive a first comparison voltage. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input of the second inverter is configured to receive a second comparison voltage.

[0007] The second aspect relates to a comparator. The comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input and output of the first inverter are coupled together. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter. The comparator further includes a first voltage-controlled resistor coupled between a voltage supply rail and the voltage supply input of the first inverter; and a second voltage-controlled resistor coupled between a voltage supply rail and the voltage supply input of the second inverter. Attached Figure Description

[0008] Figure 1 An example of a comparator according to certain aspects of this disclosure is shown.

[0009] Figure 2 An exemplary implementation of an inverter in a comparator according to certain aspects of this disclosure is shown.

[0010] Figure 3 An example of a comparator including an output buffer is shown according to certain aspects of this disclosure.

[0011] Figure 4 An example of a comparator including a hysteresis circuit is shown according to certain aspects of this disclosure.

[0012] Figure 5 An example of a timing diagram illustrating the operation of a hysteresis circuit according to certain aspects of this disclosure is shown.

[0013] Figure 6 An exemplary embodiment of a hysteresis circuit according to certain aspects of this disclosure is shown.

[0014] Figure 7 An example of a comparator including an enable switch is shown according to certain aspects of this disclosure.

[0015] Figure 8 An example of a comparator including a voltage-controlled resistor is shown according to certain aspects of this disclosure.

[0016] Figure 9 An example of a comparator including a preamplifier is shown according to certain aspects of this disclosure.

[0017] Figure 10 Another example of a comparator including a voltage-controlled resistor is shown according to certain aspects of this disclosure.

[0018] Figure 11 An exemplary implementation of a voltage-controlled resistor according to certain aspects of this disclosure is shown.

[0019] Figure 12 An exemplary implementation of a preamplifier according to certain aspects of this disclosure is shown.

[0020] Figure 13 An example of a comparator used to compare two supply voltages is shown according to certain aspects of this disclosure. Detailed Implementation

[0021] The detailed description set forth below with reference to the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. Specific details are included to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0022] One type of comparator includes a differential pair amplifier. This differential pair amplifier may require a bias circuitry system, multiple stages for rail-to-rail comparison, and large NMOS and PMOS stages for rail-to-rail comparison. Furthermore, differential pair amplifiers may be too slow for low-voltage, high-speed differential applications with rail-to-rail outputs.

[0023] Another type of comparator includes the clock-controlled strong-arm latch. This type of latch requires a high-frequency clock for high-speed comparison. Furthermore, clock-controlled strong-arm latches can be susceptible to clock feedthrough and can inject noise into nearby circuitry.

[0024] Another type of comparator is the threshold inverter quantization (TIQ) comparator. TIQ comparators compare only one voltage with a fixed voltage, thus limiting their use and applications.

[0025] Figure 1 An example of a comparator 100 according to certain aspects of this disclosure is shown. The comparator 100 is configured to compare a first voltage (labeled "V1") with a second voltage (labeled "V2"), and outputs an output signal at the output (labeled "OUT") of the comparator 100 indicating which of the first voltage V1 and the second voltage V2 is higher. Because the first voltage V1 and the second voltage V2 are the voltages that the comparator 100 is comparing, they can be referred to as the first comparison voltage V1 and the second comparison voltage V2, respectively.

[0026] Comparator 100 includes a first inverter 110 and a second inverter 120. The first inverter 110 and the second inverter 120 may be identical or substantially identical. A first voltage V1 is input to the voltage supply input 112 of the first inverter 110, while a second voltage V2 is input to the voltage supply input 122 of the second inverter 120. In other words, the voltage supply input 112 of the first inverter 110 is configured to receive the first voltage V1, and the voltage supply input 122 of the second inverter 120 is configured to receive the second voltage V2. In one example, the first voltage V1 and the second voltage V2 are the supply voltages that comparator 100 compares to perform a supply voltage comparison.

[0027] The output 116 of the first inverter 110 is coupled to its input 114, which causes the first inverter 110 to self-bias in the high-gain region and output a reference voltage (denoted as "Vref"). The reference voltage Vref can be approximately equal to the midpoint of the first voltage V1 (i.e., approximately equal to V1 / 2). The reference voltage Vref is input to the input 124 of the second inverter 120. The output 126 of the second inverter 120 provides the output of the comparator 100.

[0028] The second inverter 120 has an inverter threshold voltage, which is associated with its input 124. When the voltage input to the second inverter 120 (i.e., Vref) intersects the inverter threshold voltage, the output of the second inverter 120 toggles its logic state. Because the voltage input to the second inverter 120, V2, supplies input 122, the inverter threshold voltage is a function of the second voltage V2. In one example, the inverter threshold voltage can be approximated as V2 / 2. Do not confuse the inverter threshold voltage with the threshold voltage of a transistor.

[0029] In operation, if the reference voltage Vref is lower than the inverter threshold voltage of the second inverter 120, the second inverter 120 outputs logic 1, and if the reference voltage Vref is higher than the inverter threshold voltage of the second inverter 120, the second inverter 120 outputs logic 0. Since the reference voltage Vref is a function of the first voltage V1 (e.g., approximately equal to V1 / 2) and the inverter threshold voltage is a function of the second voltage V2 (e.g., approximately equal to V2 / 2), the logic state at the output 126 of the second inverter 120 depends on the first voltage V1 and the second voltage V2.

[0030] In one example, when the first voltage V1 and the second voltage V2 are equal, the reference voltage Vref (e.g., V1 / 2) and the inverter threshold voltage (e.g., V) of the second inverter 120 are equal. 2 / 2) Equal. In this example, when the first voltage V1 is higher than the second voltage V2, the reference voltage Vref is higher than the inverter threshold voltage. In this case, the second inverter 120 outputs logic zero. When the first voltage V1 is lower than the second voltage V2, the reference voltage Vref is lower than the inverter threshold voltage. In this case, the second inverter 120 outputs logic 1. Therefore, in this example, when the first voltage V1 is higher than the second voltage V2, the comparator 100 outputs logic 0, and when the first voltage V1 is lower than the second voltage V2, the comparator 100 outputs logic 1.

[0031] Unlike comparators that use differential pair amplifiers, comparator 100 does not require an external bias circuitry. This is because the first inverter 110 is self-biased in the high-gain region by connecting its input 114 and output 116 together.

[0032] Unlike comparators that use clock-controlled strong-arm latches, comparator 100 does not require a high-frequency clock. As a result, comparator 100 does not suffer from some of the disadvantages associated with high-frequency clocks, such as clock feedthrough and noise injection into nearby circuitry caused by high-frequency clocks.

[0033] Unlike the TIQ comparator, comparator 100 is not limited to comparing a single voltage with a fixed voltage. While comparator 100 can be used to compare a single voltage with a fixed voltage, it can also be used to compare two non-fixed voltages.

[0034] Figure 2 An example is shown in which each of the first inverter 110 and the second inverter 120, according to certain aspects of this disclosure, is implemented using a complementary metal-oxide-semiconductor (CMOS) inverter. In this example, the first inverter 110 includes a first p-type metal-oxide-semiconductor (PMOS) transistor 210 and a first n-type metal-oxide-semiconductor (NMOS) transistor 215. The source of the first PMOS transistor 210 is coupled to the voltage supply input 112 of the first inverter 110, the drain of the first PMOS transistor 210 is coupled to the output 116 of the first inverter 110, and the gate of the first PMOS transistor 210 is coupled to the input 114 of the first inverter 110. The drain of the first NMOS transistor 215 is coupled to the output 116 of the first inverter 110, the gate of the first NMOS transistor 215 is coupled to the input 114 of the first inverter 110, and the source of the first NMOS transistor 215 is coupled to ground. In one example, the dimensions of the first PMOS transistor 210 and the first NMOS transistor 215 are designed such that the reference voltage Vref is approximately equal to V1 / 2.

[0035] The first inverter 110 is self-biased in a high-gain region where the current of the first PMOS transistor 210 is approximately equal to the current of the first NMOS transistor 215. As discussed above, the first inverter 110 is self-biased in the high-gain region by tying its input 114 and output 116 together.

[0036] The second inverter 120 includes a second PMOS transistor 220 and a second NMOS transistor 225. The source of the second PMOS transistor 220 is coupled to the voltage supply input 122 of the second inverter 120, the drain of the second PMOS transistor 220 is coupled to the output 126 of the second inverter 120, and the gate of the second PMOS transistor 220 is coupled to the input 124 of the second inverter 120. The drain of the second NMOS transistor 225 is coupled to the output 126 of the second inverter 120, the gate of the second NMOS transistor 225 is coupled to the input 124 of the second inverter 120, and the source of the second NMOS transistor 225 is coupled to ground. In one example, the dimensions of the second PMOS transistor 220 and the second NMOS transistor 225 are designed such that the inverter threshold voltage of the second inverter 120 is approximately equal to V² / 2.

[0037] In some respects, comparator 100 can be calibrated such that when the first voltage V1 and the second voltage V2 are equal for different process-dependent offsets and temperature-dependent offsets, the reference voltage Vref and the inverter threshold voltage of the second inverter 120 are approximately equal. In this regard, the first PMOS transistor 210 can be implemented by a plurality of PMOS transistors coupled in parallel, wherein the number of PMOS transistors enabled at a given time is digitally controlled to control the strength of the first PMOS transistor 210. During calibration, the first voltage V1 and the second voltage V2 are set to the same voltage level. The number of enabled PMOS transistors is then adjusted until the output of comparator 100 switches (i.e., the logic state is toggled). At this point, the reference voltage Vref is approximately equal to the inverter threshold voltage of the second inverter 120, and calibration is complete. It should be understood that any one of the transistors in comparator 100 can be implemented by a plurality of transistors coupled in parallel.

[0038] Figure 3 Another example of a comparator 300 according to certain aspects of this disclosure is shown. Comparator 300 includes those discussed above. Figure 2 The comparator 100 is included in the first part. The comparator 300 also includes a third inverter 310, which is coupled to the output 126 of the second inverter 120. In this example, the third inverter 310 acts as an output buffer stage to increase the gain.

[0039] The voltage supply input 312 of the third inverter 310 is configured to receive the second voltage V2, the input 314 of the third inverter 310 is coupled to the output 126 of the second inverter 120, and the output 316 of the third inverter 310 provides the output (labeled "OUT") of the comparator 300. In this example, due to the addition of the third inverter 310, the output of the comparator 300 is... Figure 2 The logic inversion of the output of comparator 100.

[0040] exist Figure 3 In the example, the third inverter 310 is a CMOS inverter, which includes a third PMOS transistor 320 and a third NMOS transistor 325. The source of the third PMOS transistor 320 is coupled to the voltage supply input 312 of the third inverter 310, the drain of the third PMOS transistor 320 is coupled to the output 316 of the third inverter 310, and the gate of the third PMOS transistor 320 is coupled to the input 314 of the third inverter 310. The drain of the third NMOS transistor 325 is coupled to the output 316 of the third inverter 310, the gate of the third NMOS transistor 325 is coupled to the input 314 of the third inverter 310, and the source of the third NMOS transistor 325 is coupled to ground.

[0041] Figure 4 Another example of a comparator 400 according to certain aspects of this disclosure is shown. Comparator 400 includes those discussed above. Figure 3 The comparator 300 is included in the comparator 400. The comparator 400 also includes a hysteresis circuit 410, which is configured to add hysteresis to the comparator 400. As discussed further below, the hysteresis helps prevent the comparator output (labeled "OUT") from changing multiple times due to noise when the first voltage V1 and the second voltage V2 are close.

[0042] In this example, the hysteresis circuit 410 includes a fourth PMOS transistor 415, a first switch 420, and a second switch 425. The fourth PMOS transistor 415 is coupled in parallel with the first PMOS transistor 210, wherein the source of the fourth PMOS transistor 415 is coupled to the source of the first PMOS transistor 210, and the drain of the fourth PMOS transistor 415 is coupled to the drain of the first PMOS transistor 210.

[0043] A first switch 420 is coupled between the source and gate of the fourth PMOS transistor 415, and a second switch 425 is coupled between the gate and drain of the fourth PMOS transistor 415. During operation, one of switches 420 and 425 is turned on at a time. When the first switch 420 is turned off (i.e., opened) and the second switch 425 is turned on (i.e., closed), the second switch 425 short-circuits the gate and drain of the fourth PMOS transistor 415. In this case, the fourth PMOS transistor 415 is turned on (i.e., enabled) in parallel with the first PMOS transistor 210. As a result, the fourth PMOS transistor 415 pulls up the reference voltage Vref. As discussed further below, the dimensions of the fourth PMOS transistor 415 can be designed such that the fourth PMOS transistor 415 pulls up the reference voltage Vref by a small amount when enabled.

[0044] When the first switch 420 is turned on (i.e., closed) and the second switch 425 is turned off (i.e., turned on), the first switch 420 short-circuits the source and gate of the fourth PMOS transistor 415. In this case, the fourth PMOS transistor 415 is turned off (i.e., disabled), and the fourth PMOS transistor 415 does not pull up the reference voltage Vref.

[0045] Therefore, in this example, the fourth PMOS transistor 415 pulls up the reference voltage Vref slightly when the fourth PMOS transistor 415 is enabled, and does not pull up the reference voltage Vref when the fourth PMOS transistor 415 is disabled. In some aspects, the first switch 420 and the second switch 425 are controlled by the output of the comparator 400. In these aspects, the first switch 420 is configured to be off, and the second switch 425 is configured to be on when the comparator 400 has a first logic value (e.g., a). When the output of the comparator 400 has a second logic value (e.g., zero), the first switch 420 is configured to be on and the second switch 425 is configured to be off. Therefore, in this example, the fourth PMOS transistor 415 is enabled when the output has a first logic value (e.g., a) and disabled when the output has a second logic value (e.g., zero).

[0046] Now, for reference Figure 5 The timing diagram in the figure describes an exemplary operation of the hysteresis circuit 410. Figure 5 An example of the comparator output 510, a first voltage V1, and a second voltage V2 over time is shown. In this example, the first voltage V1 is constant, while the second voltage V2 rises or falls at an angle, as shown... Figure 5 As shown. In this example, the fourth PMOS transistor 415 is enabled when the comparator output 510 is high (i.e., one), and the fourth PMOS transistor 415 is disabled when the comparator output 510 is low (i.e., zero).

[0047] Initially, the second voltage V2 is lower than the first voltage V1, and the comparator output 510 is high (i.e., one). Furthermore, since the comparator output 510 is high, the fourth PMOS transistor 415 is enabled. The second voltage V2 then rises at a sloping rate and eventually crosses the first voltage V1. In this example, the comparator output 510 does not transition from high to low until the second voltage V2 rises to a small voltage offset 520 above the first voltage V1 at time T1. This is due to the fact that the fourth PMOS transistor 415 slightly pulls up the reference voltage Vref when it is enabled, as discussed above.

[0048] When comparator output 510 goes low at time T1, the fourth PMOS transistor 415 is disabled. At time T2, the second voltage V2 begins to drop at a sloping rate. When the second voltage V2 crosses below the first voltage V1, comparator output 510 transitions from low to high. In this case, because the fourth PMOS transistor 415 is disabled (i.e., turned off), the voltage offset 520 is not present, and therefore the small pull-up to the reference voltage Vref discussed above is not observed.

[0049] Therefore, when the second voltage V2 is rising, the comparator output 510 will not transition from high to low until the second voltage V2 rises above the first voltage V1 by a small voltage offset 520. When the second voltage V2 is falling, the comparator output 510 transitions from low to high when the second voltage V2 crosses below the first voltage V1. When the first voltage V1 and the second voltage V2 are close, the small voltage offset 520 helps prevent noise (e.g., noise on the first voltage V1 and / or the second voltage V2) from causing multiple transitions in the comparator output 510, assuming the noise is less than the voltage offset 520. The voltage offset 520 can be adjusted (e.g., by adjusting the size of the fourth PMOS transistor 415 relative to the size of the first PMOS transistor 210) so that the desired noise is within the voltage offset 520.

[0050] Although the first voltage V1 is Figure 5 The example shown is fixed to illustrate hysteresis, but it should be understood that the first voltage V1 can be non-fixed. Furthermore, it should be understood that, for ease of explanation, Figure 5 No noise is shown on the first voltage V1 and the second voltage V2.

[0051] In the example above, the output of the second inverter 120 is the logical inverse of the output of the comparator 400. Therefore, in this example, when the output of the second inverter 120 has a first logic value (e.g., a), the first switch 420 is configured to be on and the second switch 425 is configured to be off, and when the output of the second inverter 120 has a second logic value (e.g., zero), the first switch 420 is configured to be off and the second switch 425 is configured to be on.

[0052] Figure 6 An example is shown where, according to certain aspects of this disclosure, a first switch 420 is implemented by a switching PMOS transistor 610 and a second switch 425 is implemented by a switching NMOS transistor 620. In this example, the source of the switching PMOS transistor 610 is coupled to the source of a fourth PMOS transistor 415, the gate of the switching PMOS transistor 610 is coupled to the output of a comparator 400, and the drain of the switching PMOS transistor 610 is coupled to the gate of the fourth PMOS transistor 415. The drain of the switching NMOS transistor 620 is coupled to the gate of the fourth PMOS transistor 415, the gate of the switching NMOS transistor 620 is coupled to the output of the comparator 400, and the source of the switching NMOS transistor 620 is coupled to the drain of the fourth PMOS transistor 415.

[0053] When the output of comparator 400 is high, switching PMOS transistor 610 is turned off and switching NMOS transistor 620 is turned on. In this case, fourth PMOS transistor 415 is enabled, wherein switching NMOS transistor 620 shorts the gate and drain of fourth PMOS transistor 415.

[0054] When the output of comparator 400 is low, switching PMOS transistor 610 is turned on and switching NMOS transistor 620 is turned off. In this case, the fourth PMOS transistor 415 is disabled (i.e., turned off) because switching PMOS transistor 610 short-circuits the source and gate of the fourth PMOS transistor 415.

[0055] In some cases, the switching PMOS transistor 610 may be partially turned on when the output of comparator 400 is high. This is because the voltage at the output of comparator 400 is approximately equal to the second voltage V2, while in some cases, the second voltage V2 may be lower than the first voltage V1. In these cases, when the output of comparator 400 is high, the source-to-gate voltage of the switching PMOS transistor 610 is greater than zero volts, which may cause the switching PMOS transistor 610 to be partially turned on rather than completely turned off when the output of comparator 400 is high. To prevent this from happening, a voltage shifter 630 can be added between the output of comparator 400 and the gate of the switching PMOS transistor 610, such as... Figure 6 As shown. In this example, when the output of comparator 400 is high, voltage shifter 630 can be configured to level-shift the voltage at the output of comparator 400 upwards to a level-shifted voltage equal to or greater than the first voltage V1, and input the level-shifted voltage to the gate of switching PMOS transistor 610. This voltage level shift helps ensure that switching PMOS transistor 610 is turned off when the output of comparator 400 is high.

[0056] Figure 7 Another example of a comparator 700 according to certain aspects of this disclosure is shown. Comparator 700 includes those discussed above. Figure 4 Comparator 400 is included in the system. Comparator 700 also includes an enable switch 710 for selectively enabling comparator 700 based on an enable signal (labeled "Enable"). Figure 7 In the example, the enable switch 710 is implemented by a fourth NMOS transistor, wherein the drain of the fourth NMOS transistor is coupled to the source of the first NMOS transistor 215, the second NMOS transistor 225 and the third NMOS transistor 325, the source of the fourth NMOS transistor is coupled to ground, and the enable signal is input to the gate of the fourth NMOS transistor.

[0057] When the enable signal has a first logic state (e.g., 'a'), the enable switch 710 is turned on (i.e., closed). In this case, the enable switch 710 couples the sources of the first NMOS transistor 215, the second NMOS transistor 225, and the third NMOS transistor 325 to ground and enables the comparator 700. When enabled, the comparator 700 operates as discussed above. The comparator 700 can be enabled when needed.

[0058] When the enable signal has a second logic state (e.g., zero), the enable switch 710 is turned off (i.e., turned on). In this case, the enable switch 710 decouples the sources of the first NMOS transistor 215, the second NMOS transistor 225, and the third NMOS transistor 325 from ground and disables the comparator 700. The comparator 700 can be disabled when it is not needed to save power.

[0059] An additional PMOS transistor 720 can be added to help ensure that the output of comparator 700 has a well-defined logic state when comparator 700 is disabled. Figure 7In the example, the source of PMOS transistor 720 is coupled to a second voltage V2, the drain of PMOS transistor 720 is coupled to the output of comparator 700, and the gate of PMOS transistor 720 receives an enable signal. When the enable signal is high (i.e., comparator 700 is enabled), PMOS transistor 720 is turned off. When the enable signal is low (i.e., comparator 700 is disabled), PMOS transistor 720 is turned on. This causes PMOS transistor 720 to pull the output of comparator 700 high, thereby giving the output of comparator 700 a clearly defined logic state one.

[0060] In some applications (e.g., signal comparison), it is desirable for the comparator input to have high impedance so that the comparator input draws little or no current from the sources of the first voltage V1 and the second voltage V2. This is because the current drawn by the comparator input can affect the voltage being compared. For example, if one of the voltages being compared is on a signal line, the current drawn by the corresponding input of the comparator may cause an IR drop on the signal line, which reduces the voltage. To address this issue, aspects of this disclosure provide comparators with high input impedance, as further discussed below.

[0061] Figure 8 An example of a comparator 800 with high input impedance according to certain aspects of this disclosure is shown. The comparator 800 includes a first inverter 110 and a second inverter 120 discussed above, wherein the input 114 and output 116 of the first inverter 110 are coupled together, the input 124 of the second inverter 120 is coupled to the output 116 of the first inverter 110, and the output 126 of the second inverter 120 provides the output of the comparator 800. The first inverter 110 and the second inverter 120 can be used... Figure 2 This is achieved using a CMOS inverter as shown.

[0062] Comparator 800 also includes a first voltage-controlled resistor 820 and a second voltage-controlled resistor 830. The first voltage-controlled resistor 820 is coupled between the voltage supply rail 810 and the voltage supply input 112 of the first inverter 110. The second voltage-controlled resistor 830 is coupled between the voltage supply rail 810 and the voltage supply input 122 of the second inverter 120. The supply voltage on the supply rail 810 is Vdd.

[0063] The first voltage-controlled resistor 820 has a control input 825 for controlling the resistance of the first voltage-controlled resistor 820. The resistance of the first voltage-controlled resistor 820 is between the supply rail 810 and the supply input 112 of the first inverter 110. Figure 8In the example, a first voltage V1 is input to control input 825 to control the resistance of the first voltage-controlled resistor 820. The voltage at supply input 112 of the first inverter 110 (labeled "V") s1 The voltage drop across the first voltage-controlled resistor 820 is approximately equal to Vdd minus the voltage drop across the first voltage-controlled resistor 820. The voltage drop across the first voltage-controlled resistor 820 is a function of the resistance of the first voltage-controlled resistor 820, which is controlled by the first voltage V1. Therefore, the voltage V at the supply input 112 of the first inverter 110 is approximately equal to Vdd minus the voltage drop across the first voltage-controlled resistor 820. s1 It is a function of the first voltage V1. Voltage V s1 The supply voltage V can be considered as the supply input 112 input to the first inverter 110, where the supply voltage V s1 The supply voltage V is equal to the supply voltage at rail 810 minus the voltage drop across the first voltage-controlled resistor 820. s1 Adjustment is achieved by adjusting the resistance of the first voltage-controlled resistor 820.

[0064] The second voltage-controlled resistor 830 has a control input 835 for controlling its resistance. The resistance of the second voltage-controlled resistor 830 is located between the supply rail 810 and the supply input 122 of the second inverter 120. Figure 8 In the example, the second voltage V2 is input to control input 835 to control the resistance of the second voltage-controlled resistor 830. The voltage at supply input 122 of the second inverter 120 (labeled "V") s2 The voltage drop across the second voltage-controlled resistor 830 is approximately equal to Vdd minus the voltage drop across the second voltage-controlled resistor 830. The voltage drop across the second voltage-controlled resistor 830 is a function of the resistance of the second voltage-controlled resistor 830, which is controlled by the second voltage V2. Therefore, the voltage V at the supply input 122 of the second inverter 120 is approximately equal to Vdd minus the voltage drop across the second voltage-controlled resistor 830. s2 It is a function of the second voltage V2. Voltage V s2 The supply voltage V can be considered as the supply input 122 input to the second inverter 110, where the supply voltage V s2 The supply voltage V is equal to the supply voltage at rail 810 minus the voltage drop across the second voltage-controlled resistor 830. s2 Adjustment is achieved by adjusting the resistance of the second voltage-controlled resistor 830.

[0065] In one example, each of the first voltage-controlled resistor 820 and the second voltage-controlled resistor 830 is configured to decrease its resistance as the voltage at the corresponding control input decreases, and to increase its resistance as the voltage at the corresponding control input increases. In this example, each of the first voltage-controlled resistor 820 and the second voltage-controlled resistor 830 can be implemented using a corresponding PMOS transistor, as discussed further below.

[0066] In this example, when the first voltage V1 is higher than the second voltage V2, the resistance of the first voltage-controlled resistor 820 is greater than the resistance of the second voltage-controlled resistor 830. As a result, the voltage drop across the first voltage-controlled resistor 820 is greater than the voltage drop across the second voltage-controlled resistor 830, and the voltage V at the supply input 112 of the first inverter 110 is... s1 The voltage V at the supply input 122 of the second inverter 120 is lower than the voltage V. s2 In this case, the reference voltage Vref output by the first inverter 110 is lower than the inverter threshold voltage of the second inverter 120, thereby causing the comparator 800 to output one.

[0067] When the first voltage V1 is lower than the second voltage V2, the resistance of the first voltage-controlled resistor 820 is less than the resistance of the second voltage-controlled resistor 830. As a result, the voltage drop across the first voltage-controlled resistor 820 is less than the voltage drop across the second voltage-controlled resistor 830, and the voltage V at the supply input 112 of the first inverter 110 is... s1 The voltage V at the supply input 122 of the second inverter 120 is higher than the voltage V at the supply input 122. s2 In this case, the reference voltage Vref output by the first inverter 110 is higher than the inverter threshold voltage of the second inverter 120, causing the comparator 800 to output zero.

[0068] Therefore, in the example above, comparator 800 outputs one when the first voltage V1 is higher than the second voltage V2, and outputs zero when the first voltage V1 is lower than the second voltage V2.

[0069] In another example, each of the first voltage-controlled resistors 820 and the second voltage-controlled resistor 830 is configured to increase its resistance as the voltage at the corresponding control input decreases, and decrease its resistance as the voltage at the corresponding control input increases. In this example, comparator 800 outputs zero when the first voltage V1 is higher than the second voltage V2, and outputs one when the first voltage V1 is lower than the second voltage V2. Therefore, the output of comparator 800 in this example is logically inverted compared to the output of comparator 800 in the previous example.

[0070] In some aspects, the control inputs 825 and 835 of the voltage-controlled resistors 820 and 835 have high impedance to provide a high input impedance to the comparator 800. For example, each voltage-controlled resistor 820 and 830 can be implemented by a corresponding transistor (e.g., a PMOS transistor or an NMOS transistor) having a channel coupled between the supply rail 810 and the voltage supply input of the corresponding inverter. In this example, the resistance of each voltage-controlled resistor 820 and 830 corresponds to the channel resistance of the corresponding transistor, which is controlled by the gate voltage of the corresponding transistor. In this example, the control input of each voltage-controlled resistor 820 and 830 with high input impedance is located at the gate of the corresponding transistor.

[0071] In contrast, those with low input impedance Figure 2 Each input of the comparator 100 shown is located at the source of either the first PMOS transistor 210 or the second PMOS transistor 220. In this case, the channel widths of the first PMOS transistor 210 and the first NMOS transistor 215 can be reduced to keep the current drawn by the first inverter 110 small. In the second inverter 120, the second PMOS transistor 220 or the second NMOS transistor 225 is turned off when V1 and V2 are not equal. Therefore, the second inverter 120 can draw very little or no current most of the time. The current drawn by the comparator 100 may not be a problem for the supply voltage comparison because the supply rail providing the supply voltage being compared can be configured to provide a relatively large current (i.e., much larger than the current drawn by the comparator 100). In this case, the effect of the current drawn by the comparator 100 on the supply voltage being compared is negligible.

[0072] Figure 9 Another example of a comparator 900 according to certain aspects of this disclosure is shown. Comparator 900 includes the features referenced above. Figure 8 The comparator 800 under discussion. Additionally, comparator 900 includes a preamplifier 910 that provides additional gain at the comparator input. Preamplifier 910 includes a first input 915, a second input 920, a first output 930, and a second output 935. Figure 9In this example, a first voltage V1 is input to the first input 915 of the preamplifier 910, while a second voltage V2 is input to the second input 920 of the preamplifier 910. The first output 930 of the preamplifier 910 is coupled to the control input 825 of the first voltage-controlled resistor 820, and the second output 935 of the preamplifier 910 is coupled to the control input 835 of the second voltage-controlled resistor 830. Therefore, in this example, the voltage at the first output 930 of the preamplifier 910 controls the resistance of the first voltage-controlled resistor 820, and the voltage at the second output 935 of the preamplifier 910 controls the resistance of the second voltage-controlled resistor 830.

[0073] Preamplifier 910 generates voltages at first output 930 and second output 935 based on a first voltage V1 input to preamplifier 910 and a second input V2. In one example, preamplifier 910 amplifies the first voltage V1 with a first gain to generate a voltage at the first output 930 of preamplifier 910, and amplifies the second voltage V2 with a second gain to generate a voltage at the second output 935 of preamplifier 910. The first gain and the second gain may be approximately the same. In this example, the voltage at the first output 930 can be V1·G1 or (V1·G1) + V b1 Given, where G1 is the first gain of preamplifier 910 and V b1 This is the first bias voltage of the preamplifier 910. Furthermore, in this example, the voltage at the second output 935 can be determined by V2·G2 or (V2·G2) + V. b2 Given, where G2 is the second gain of preamplifier 910, and V b2 This is the second bias voltage of the preamplifier 910. The first bias voltage and the second bias voltage can be approximately the same.

[0074] In another example, preamplifier 910 amplifies the first differential voltages V1 and V2 with a first gain to generate a voltage at the first output 930 of preamplifier 910, and amplifies the second differential voltage V2 of V1 and V2 with a second gain to generate a voltage at the second output 935 of preamplifier 910. The first gain and the second gain can be approximately the same. In this example, the first differential voltage can be approximately equal to V1 - V2, and the second differential voltage can be approximately equal to V2 - V1, and vice versa. In this example, the voltage at the first output 930 can be determined by V1 - V2. diff_1 ·G1 or (V diff_1 ·G1)+V b1 Given, where V diff_1 G1 is the first differential voltage, and G1 is the first gain of the preamplifier 910. b1 This is the first bias voltage of the preamplifier 910. Furthermore, in this example, the voltage at the second output 935 can be determined by V.diff_2 ·G2 or (V diff_2 ·G2)+V b2 Given, where V diff_2 It is the second differential voltage, G2 is V b2 It is the second gain of the preamplifier 910, V b2 This is the second bias voltage of the preamplifier 910. The first bias voltage and the second bias voltage can be approximately the same.

[0075] Figure 10 Another example of a comparator 1000 according to certain aspects of this disclosure is shown. The comparator 1000 includes... Figure 9 The comparator 900 is shown. Additionally, comparator 1000 includes a third voltage-controlled resistor 1020 and a fourth voltage-controlled resistor 1030. The third voltage-controlled resistor 1020 is coupled between the first inverter 110 and ground. The third voltage-controlled resistor 1020 has a control input 1025 for controlling the resistance of the third voltage-controlled resistor 1020, wherein the resistance of the third voltage-controlled resistor 1020 is between the first inverter 110 and ground. The fourth voltage-controlled resistor 1030 is coupled between the second inverter 120 and ground. The fourth voltage-controlled resistor 1030 has a control input 1035 for controlling the resistance of the fourth voltage-controlled resistor 1030, wherein the resistance of the fourth voltage-controlled resistor 1030 is between the second inverter 120 and ground. As further discussed below, the third voltage-controlled resistor 1020 and the fourth voltage-controlled resistor 1030 are used to increase the speed of comparator 1000 to provide higher speed comparison.

[0076] In this example, the preamplifier 1010 includes the first input 915, the second input 920, the first output 930, and the second output 935 discussed above. For this purpose, the preamplifier 1010 can be referenced above. Figure 9 The discussed method is based on generating voltages at the first output 930 and the second output 935 using the first voltage V1 and the second voltage V2. Additionally, the preamplifier 1010 includes a third output 1040 coupled to the control input 1025 of the third voltage-controlled resistor 1020; and a fourth output 1045 coupled to the control input 1035 of the fourth voltage-controlled resistor 1030. Therefore, as further discussed below, the preamplifier 1010 controls the resistance of the third voltage-controlled resistor 1020 and the resistance of the fourth voltage-controlled resistor 1030.

[0077] In operation, the preamplifier 1010 is configured to adjust the resistance of the third voltage-controlled resistor 1020 in the opposite direction to the resistance of the first voltage-controlled resistor 820. For example, when the preamplifier 1010 decreases the resistance of the first voltage-controlled resistor 820 due to a change in the first voltage V1 and / or the second voltage V2, the preamplifier 1010 increases the resistance of the third voltage-controlled resistor 1020. Decreasing the resistance of the first voltage-controlled resistor 820 increases the voltage V at the supply input 112 of the first inverter 110. s1 This increases the reference voltage Vref (i.e., shifts Vref upwards). Increasing the resistance of the third voltage-controlled resistor 1020 increases the resistance between the first inverter 110 and ground, thereby reducing the current flowing from the first inverter 110 to ground. This allows the first voltage-controlled resistor 820 to pull up the voltage Vref more quickly. s1 Because the first voltage-controlled resistor 820 is resisting a smaller current from the first inverter 110 to ground to increase the voltage V s1 Therefore, by adjusting the resistance of the third voltage-controlled resistor 1020 in the opposite direction to the resistance of the first voltage-controlled resistor 820, the preamplifier 1010 can more quickly shift the voltage V at the supply input 112 of the first inverter 110 in response to changes in the first voltage V1 and / or the second voltage V2. s1 This increases the speed of comparator 1000.

[0078] The preamplifier 1010 is also configured to adjust the resistance of the fourth voltage-controlled resistor 1030 in the opposite direction to the resistance of the second voltage-controlled resistor 830. This allows the preamplifier 1010 to move the voltage V at the supply input 122 of the second inverter 120 more quickly in response to changes in the first voltage V1 and / or the second voltage V2. s2 .

[0079] Figure 11 An exemplary implementation of a first inverter 110, a second inverter 120, a first voltage-controlled resistor 820, a second voltage-controlled resistor 830, a third voltage-controlled resistor 1020, and a fourth voltage-controlled resistor 1030 according to aspects of this disclosure is shown. In this example, the first inverter 110 and the second inverter 120 are connected via... Figure 2 The corresponding CMOS inverter implementation is shown above. (See above for reference.) Figure 2 The detailed description of the CMOS inverter provided applies to Figure 11 The CMOS inverter shown is omitted here for the sake of simplicity.

[0080] In this example, the first voltage-controlled resistor 820 is implemented via a fifth PMOS transistor 1120, wherein the control input 825 of the first voltage-controlled resistor 820 is located at the gate of the fifth PMOS transistor 1120. The source of the fifth PMOS transistor 1120 is coupled to the supply rail 810, the drain of the fifth PMOS transistor 1120 is coupled to the voltage supply input 112 of the first inverter 110, and the gate of the fifth PMOS transistor 1120 is coupled to the first output 930 of the preamplifier 1010. In this example, the preamplifier 1010 decreases the resistance of the fifth PMOS transistor 1120 by decreasing the gate voltage of the fifth PMOS transistor 1120 (labeled "nm_b"), and increases the resistance of the fifth PMOS transistor 1120 by increasing the gate voltage nm_b of the fifth PMOS transistor 1120.

[0081] The second voltage-controlled resistor 830 is implemented via a sixth PMOS transistor 1130, wherein the control input 835 of the second voltage-controlled resistor 830 is located at the gate of the sixth PMOS transistor 1130. The source of the sixth PMOS transistor 1130 is coupled to the supply rail 810, the drain of the sixth PMOS transistor 1130 is coupled to the voltage supply input 122 of the second inverter 120, and the gate of the sixth PMOS transistor 1130 is coupled to the second output 935 of the preamplifier 1010. In this example, the preamplifier 1010 decreases the resistance of the sixth PMOS transistor 1130 by decreasing its gate voltage (labeled "nm_a") and increases its resistance by increasing its gate voltage nm_a.

[0082] The third voltage-controlled resistor 1020 is implemented via a fifth NMOS transistor 1140, wherein the control input 1025 of the third voltage-controlled resistor 1020 is located at the gate of the fifth NMOS transistor 1140. The drain of the fifth NMOS transistor 1140 is coupled to the source of the first NMOS transistor 215, the source of the fifth NMOS transistor 1140 is coupled to ground, and the gate of the fifth NMOS transistor 1140 is coupled to the third output 1040 of the preamplifier 1010. In this example, the preamplifier 1010 decreases the resistance of the fifth NMOS transistor 1140 by increasing the gate voltage of the fifth NMOS transistor 1140 (labeled "pm_a"), and increases the resistance of the fifth NMOS transistor 1140 by decreasing the gate voltage pm_a.

[0083] The fourth voltage-controlled resistor 1030 is implemented via the sixth NMOS transistor 1150, wherein the control input 1035 of the fourth voltage-controlled resistor 1030 is located at the gate of the sixth NMOS transistor 1150. The drain of the sixth NMOS transistor 1150 is coupled to the source of the second NMOS transistor 225, the source of the sixth NMOS transistor 1150 is coupled to ground, and the gate of the sixth NMOS transistor 1150 is coupled to the fourth output 1045 of the preamplifier 1010. In this example, the preamplifier 1010 decreases the resistance of the sixth NMOS transistor 1150 by increasing the gate voltage of the sixth NMOS transistor 1150 (labeled "pm_b"), and increases the resistance of the sixth NMOS transistor 1150 by decreasing the gate voltage pm_b of the sixth NMOS transistor 1150.

[0084] Figure 12 An exemplary implementation of a preamplifier 1010 according to certain aspects of this disclosure is shown. The preamplifier 1010 generates control voltages nm_a, pm_a, nm_b, and pm_b for voltage-controlled resistors 820, 830, 1020, and 1030 based on a first voltage V1 and a second voltage V2. As further discussed below, the preamplifier 1010 has a fast switching speed, which allows the preamplifier 1010 to rapidly change the voltages nm_a, pm_a, nm_b, and pm_b in response to changes in V1 and / or V2 for high-speed comparison.

[0085] The preamplifier 1010 includes a bias inverter 1205 that is self-biased to generate a bias voltage (denoted as "vabal") for the preamplifier 1010, as further discussed below. Figure 12 As shown, inverter 1205 is self-biased by tying its input 1212 and output 1218 together. The bias voltage vabal is provided at the output 1218 of the bias inverter 1205 and can be approximately equal to Vdd / 2, where Vdd is the voltage at the supply rail 810.

[0086] exist Figure 12In the example, the bias inverter 1205 includes a seventh PMOS transistor 1210 and a seventh NMOS transistor 1215. The source of the seventh PMOS transistor 1210 is coupled to the supply rail 810, the drain of the seventh PMOS transistor 1210 is coupled to the output 1218 of the bias inverter 1205, and the gate of the seventh PMOS transistor 1210 is coupled to the input 1212 of the bias inverter 1205. The drain of the seventh NMOS transistor 1215 is coupled to the output 1218 of the bias inverter 1205, the gate of the seventh NMOS transistor 1215 is coupled to the input 1212 of the bias inverter 1205, and the source of the seventh NMOS transistor 1215 is coupled to ground.

[0087] The preamplifier 1010 also includes an eighth PMOS transistor 1220, a first resistor circuit 1240, and an eighth NMOS transistor 1225. The first resistor circuit 1240 is coupled between the drain of the eighth PMOS transistor 1220 and the drain of the eighth NMOS transistor 1225. The source of the eighth PMOS transistor 1220 is coupled to the supply rail 810, and the gate of the eighth PMOS transistor 1220 is biased by a bias voltage vabal. The source of the eighth NMOS transistor 1225 is coupled to ground, and the gate of the eighth NMOS transistor 1225 is biased by a bias voltage vabal. As discussed above, the bias voltage vabal is provided at the output 1218 of the bias inverter 1205. For ease of illustration, Figure 12 The connection between the output 1218 of the bias inverter 1205 and the gates of the eighth PMOS transistor 1220 and the eighth NMOS transistor 1225 is not explicitly shown.

[0088] As discussed above, a first resistor circuit 1240 is coupled between the drain of the eighth PMOS transistor 1220 and the drain of the eighth NMOS transistor 1225. The resistance of the first resistor circuit 1240 is controlled by a first voltage V1 and a second voltage V2. The resistor generates a control voltage nm_a at node 1242 and a control voltage pm_a at node 1244, where node 1242 is located between the first resistor circuit 1240 and the drain of the eighth PMOS transistor 1220, and node 1244 is located between the first resistor circuit 1240 and the drain of the eighth NMOS transistor 1225. The differential voltages nm_a and pm_a can be centered around approximately vacuum (e.g., Vdd / 2). The control voltages nm_a and pm_a are controlled by the resistance of the first resistor circuit 1240, which is in turn controlled by the first voltage V1 and the second voltage V2. Increasing the resistance will shift the control voltage nm_a upward and the control voltage pm_a downward (i.e., increase the differential voltage between nm_a and pm_a). Decreasing the resistance shifts the control voltage nm_a downwards and the control voltage pm_a upwards (i.e., decreases the differential voltage between nm_a and pm_a). In this example, as... Figure 11 As shown, node 1242 (which provides nm_a) is coupled to the control input 835 of the second voltage-controlled resistor 830, and node 1244 (which provides pm_a) is coupled to the control input 1025 of the third voltage-controlled resistor 1020.

[0089] The preamplifier 1010 also includes a ninth PMOS transistor 1230, a second resistor circuit 1260, and a ninth NMOS transistor 1235. The second resistor circuit 1260 is coupled between the drain of the ninth PMOS transistor 1230 and the drain of the ninth NMOS transistor 1235. The source of the ninth PMOS transistor 1230 is coupled to the supply rail 810, and the gate of the ninth PMOS transistor 1230 is biased by a bias voltage vabal. The source of the ninth NMOS transistor 1235 is coupled to ground, and the gate of the ninth NMOS transistor 1235 is biased by a bias voltage vabal. For ease of illustration, Figure 12 The connection between the output 1218 of the bias inverter 1205 and the gates of the ninth PMOS transistor 1230 and the ninth NMOS transistor 1235 is not explicitly shown.

[0090] As discussed above, the second resistor circuit 1260 is coupled between the drain of the ninth PMOS transistor 1230 and the drain of the ninth NMOS transistor 1235. The resistance of the second resistor circuit 1260 is controlled by a first voltage V1 and a second voltage V2. The resistor generates a control voltage nm_b at node 1262 and a control voltage pm_b at node 1264, where node 1262 is located between the second resistor circuit 1260 and the drain of the ninth PMOS transistor 1230, and node 1264 is located between the second resistor circuit 1260 and the drain of the ninth NMOS transistor 1235. The differential voltages nm_b and pm_b can be centered around approximately vacuum (e.g., Vdd / 2). The control voltages nm_b and pm_b are controlled by the resistance of the second resistor circuit 1260, which is in turn controlled by the first voltage V1 and the second voltage V2. Increasing the resistance will shift the control voltage nm_b upward and the control voltage pm_b downward (i.e., increase the differential voltage between nm_b and pm_b). Reducing the resistance shifts the control voltage nm_b downwards and the control voltage pm_b upwards (i.e., reduces the differential voltage between nm_b and pm_b). In this example, as... Figure 11 As shown, node 1262 (which provides nm_b) is coupled to the control input 825 of the first voltage-controlled resistor 820, and node 1264 (which provides pm_b) is coupled to the control input 1035 of the third voltage-controlled resistor 1030.

[0091] In some respects, in response to a change in the first voltage V1 and / or the second voltage V2, the resistance of the second resistor circuit 1260 moves in the opposite direction to the resistance of the first resistor circuit 1240. Therefore, when the resistance of the first resistor circuit 1240 increases, the resistance of the second resistor circuit 1260 decreases, and vice versa.

[0092] In one example, when the second voltage V2 is higher than the first voltage V1, the resistance of the first resistor circuit 1240 is greater than the resistance of the second resistor circuit 1260, and when the first voltage V1 is higher than the second voltage V2, the resistance of the first resistor circuit 1240 is less than the resistance of the second resistor circuit 1260. In this example, when the second voltage V2 is higher, the differential voltage between nm_a and pm_a is greater than the differential voltage between nm_b and pm_b, where the two differential voltages are centered approximately around a constant (e.g., Vdd / 2). As a result, the control voltage nm_a is greater than the control voltage nm_b, and the control voltage pm_b is greater than the control voltage pm_a. This causes the reference voltage Vref to be higher than the inverter threshold voltage of the second inverter 120, and the comparator 1000 outputs zero. In this example, when the first voltage V1 is higher, the differential voltage between nm_b and pm_b is greater than the differential voltage between nm_a and pm_a, where both differential voltages are centered approximately around a constant (e.g., Vdd / 2). As a result, the control voltage nm_b is greater than the control voltage nm_a, and the control voltage pm_a is greater than the control voltage pm_b. This causes the reference voltage Vref to be lower than the inverter threshold voltage of the second inverter 120, and the comparator 1000 outputs one.

[0093] exist Figure 12 In the example, the first resistor circuit 1240 includes a tenth PMOS transistor 1250, an eleventh PMOS transistor 1252, a tenth NMOS transistor 1254, and an eleventh NMOS transistor 1256. The tenth PMOS transistor 1250 and the eleventh PMOS transistor 1252 are coupled in series, with the source of the tenth PMOS transistor 1250 coupled to node 1242, the drain of the tenth PMOS transistor 1250 coupled to the source of the eleventh PMOS transistor 1252, and the drain of the eleventh PMOS transistor 1252 coupled to node 1244. A second voltage V2 is input to the gates of the tenth PMOS transistor 1250 and the eleventh PMOS transistor 1252.

[0094] The tenth NMOS transistor 1254 and the eleventh NMOS transistor 1256 are coupled in series, with the drain of the tenth NMOS transistor 1254 coupled to node 1242, the source of the tenth NMOS transistor 1254 coupled to the drain of the eleventh NMOS transistor 1256, and the source of the eleventh NMOS transistor 1256 coupled to node 1244. A first voltage V1 is input to the gates of the tenth NMOS transistor 1254 and the eleventh NMOS transistor 1256.

[0095] The first resistor circuit 1240 has a high bandwidth, thus enabling a rapid response to changes in the first voltage V1 and / or the second voltage V2. This is because the source of the eleventh PMOS transistor 1252 provides a low-impedance load at the drain of the tenth PMOS transistor 1250, while the source of the tenth NMOS transistor 1254 provides a low-impedance load at the drain of the eleventh NMOS transistor 1256. This low load impedance increases bandwidth at the cost of reduced gain. However, the inverters 110 and 120 in the next stage provide high gain, thus compensating for the lower gain of the preamplifier 1010. As discussed further below, the high bandwidth of the preamplifier 1010 allows the comparator 1000 to achieve high speed.

[0096] exist Figure 12 In the example, the second resistor circuit 1260 includes a twelfth PMOS transistor 1270, a thirteenth PMOS transistor 1272, a twelfth NMOS transistor 1274, and a thirteenth NMOS transistor 1276. The twelfth PMOS transistor 1270 and the thirteenth PMOS transistor 1272 are coupled in series, with the source of the twelfth PMOS transistor 1270 coupled to node 1262, the drain of the twelfth PMOS transistor 1270 coupled to the source of the thirteenth PMOS transistor 1272, and the drain of the thirteenth PMOS transistor 1272 coupled to node 1264. A first voltage V1 is input to the gates of the twelfth PMOS transistor 1270 and the thirteenth PMOS transistor 1272.

[0097] The twelfth NMOS transistor 1274 and the thirteenth NMOS transistor 1276 are coupled in series, with the drain of the twelfth NMOS transistor 1274 coupled to node 1262, the source of the twelfth NMOS transistor 1274 coupled to the drain of the thirteenth NMOS transistor 1276, and the source of the thirteenth NMOS transistor 1276 coupled to node 1264. A second voltage V2 is input to the gates of the twelfth NMOS transistor 1274 and the thirteenth NMOS transistor 1276.

[0098] For reasons similar to the first resistor circuit 1240 discussed above, the second resistor circuit 1260 has a high bandwidth. Figure 12In the example, the structure of the second resistor circuit 1260 is the same as that of the first resistor circuit 1240, except that the input of the second resistor circuit 1260 is the inverse of the input of the first resistor circuit 1240. More specifically, the second voltage V2 is input to the PMOS transistors 1250 and 1252 of the first resistor circuit 1240, while the second voltage V2 is input to the NMOS transistors 1274 and 1276 of the second resistor circuit 1260. The first voltage V1 is input to the NMOS transistors 1254 and 1256 of the first resistor circuit 1240, while the first voltage V1 is input to the PMOS transistors 1270 and 1272 of the second resistor circuit 1260. In response to a change in the first voltage V1 and / or the second voltage V2, the inverted input causes the resistance of the first resistor circuit 1240 and the resistance of the second resistor circuit 1260 to move in opposite directions.

[0099] exist Figure 12 In the example, the node between the tenth NMOS transistor 1254 and the eleventh NMOS transistor 1256 is coupled to the node between the twelfth NMOS transistor 1274 and the thirteenth NMOS transistor 1276. The node between the tenth PMOS transistor 1250 and the eleventh PMOS transistor 1252 is coupled to the node between the twelfth PMOS transistor 1270 and the thirteenth PMOS transistor 1272. This helps to center the first resistor circuit 1240 and the second resistor circuit 1260.

[0100] Figure 12 The exemplary preamplifier 1010 shown allows the comparator 1000 to achieve high speed (e.g., propagation delay less than 400 ps) and high accuracy (e.g., resolution of 2 mV).

[0101] As discussed above, comparator 100 can be used to compare two supply voltages. In this respect, Figure 13 An example is shown in which the voltage supply input 112 of the first inverter 110 is coupled to the first voltage supply rail 1310 and the voltage supply input 122 of the second inverter 120 is coupled to the second voltage supply rail 1320. The first voltage supply rail 1310 provides a first voltage V1, which in this example is the first supply voltage. The second voltage supply rail 1320 provides a second voltage V2, which in this example is the second supply voltage.

[0102] Any references to elements in this document, such as “first,” “second,” etc., do not generally restrict the number or order of those elements. Rather, these references serve as a convenient way to distinguish two or more elements or instances of elements. Therefore, references to a first element and a second element do not imply that only two elements can be used, or that the first element must precede the second element.

[0103] In this disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect electrical coupling between two structures. As used herein, the term “about” means within 10% of the value (i.e., between 90% and 110% of the value).

[0104] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and other variations may be applied without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A comparator, comprising: A first inverter has an input, an output, and a voltage supply input, wherein the input and the output of the first inverter are coupled together; A second inverter has an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter; A first voltage-controlled resistor is coupled between the voltage supply rail and the voltage supply input of the first inverter; A second voltage-controlled resistor is coupled between the voltage supply rail and the voltage supply input of the second inverter; as well as Preamplifier, where: The preamplifier has a first input, a second input, a first output, and a second output; The first input is configured to receive a first comparison voltage; The second input is configured to receive a second comparison voltage; The first output is coupled to the control input of the first voltage-controlled resistor; The second output is coupled to the control input of the second voltage-controlled resistor; The preamplifier is configured to generate a first control voltage at the first output based on either the first comparison voltage or both the first comparison voltage and the second comparison voltage; and The preamplifier is configured to generate a second control voltage at the second output based on the second comparison voltage or both the second comparison voltage and the first comparison voltage.

2. The comparator according to claim 1, wherein: The first voltage-controlled resistor includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a source, a gate, and a drain, wherein the source of the first PMOS transistor is coupled to the voltage supply rail, and the drain of the first PMOS transistor is coupled to the voltage supply input of the first inverter. as well as The second voltage-controlled resistor includes a second PMOS transistor having a source, a gate, and a drain, wherein the source of the second PMOS transistor is coupled to the voltage supply rail, and the drain of the second PMOS transistor is coupled to the voltage supply input of the second inverter.

3. The comparator according to claim 2, wherein: The gate of the first PMOS transistor is configured to receive a first comparison voltage; and The gate of the second PMOS transistor is configured to receive a second comparison voltage.

4. The comparator according to claim 1, wherein: The first voltage-controlled resistor has a control input configured to receive a first comparison voltage; and The second voltage-controlled resistor has a control input configured to receive a second comparison voltage.

5. The comparator of claim 1, wherein the preamplifier is configured to: The first control voltage is generated based on the first difference between the first comparison voltage and the second comparison voltage; and The second control voltage is generated based on the second difference between the first comparison voltage and the second comparison voltage.

6. The comparator according to claim 1, wherein: The first voltage-controlled resistor includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a source, a gate, and a drain, wherein the source of the first PMOS transistor is coupled to the voltage supply rail, the control input of the first voltage-controlled resistor is located at the gate of the first PMOS transistor, and the drain of the first PMOS transistor is coupled to the voltage supply input of the first inverter. as well as The second voltage-controlled resistor includes a second PMOS transistor having a source, a gate, and a drain, wherein the source of the second PMOS transistor is coupled to the voltage supply rail, the control input of the second voltage-controlled resistor is located at the gate of the second PMOS transistor, and the drain of the second PMOS transistor is coupled to the voltage supply input of the second inverter.

7. The comparator of claim 1, wherein the preamplifier comprises: A first p-type metal-oxide-semiconductor (PMOS) transistor has a source, a gate, and a drain, wherein the source of the first PMOS transistor is coupled to the voltage supply rail, and the gate of the first PMOS transistor is biased by a bias voltage. A first n-type metal-oxide-semiconductor (NMOS) transistor has a source, a gate, and a drain, wherein the source of the first NMOS transistor is coupled to ground, and the gate of the first NMOS transistor is biased by the bias voltage. as well as A first resistor circuit is coupled between the drain of the first PMOS transistor and the drain of the first NMOS transistor, wherein the first resistor circuit is coupled to the first input and the second input of the preamplifier, the resistance of the first resistor circuit is controlled by the first comparison voltage and the second comparison voltage, and the first output of the preamplifier is coupled to the node between the drain of the first PMOS transistor and the first resistor circuit.

8. The comparator of claim 7, wherein the first resistor circuit comprises: A second PMOS transistor has a source, a drain, and a gate, wherein the source of the second PMOS transistor is coupled to the drain of the first PMOS transistor, and the gate of the second PMOS transistor is coupled to the second input of the preamplifier; A third PMOS transistor has a source, a drain, and a gate, wherein the source of the third PMOS transistor is coupled to the drain of the second PMOS transistor, the gate of the third PMOS transistor is coupled to the second input of the preamplifier, and the drain of the third PMOS transistor is coupled to the drain of the first NMOS transistor. A second NMOS transistor has a source, a drain, and a gate, wherein the drain of the second NMOS transistor is coupled to the drain of the first PMOS transistor, and the gate of the second NMOS transistor is coupled to the first input of the preamplifier; as well as A third NMOS transistor has a source, a drain, and a gate, wherein the drain of the third NMOS transistor is coupled to the source of the second NMOS transistor, the gate of the third NMOS transistor is coupled to the first input of the preamplifier, and the source of the third NMOS transistor is coupled to the drain of the first NMOS transistor.

9. The comparator of claim 7, wherein the preamplifier comprises: A second PMOS transistor has a source, a gate, and a drain, wherein the source of the second PMOS transistor is coupled to the voltage supply rail, and the gate of the second PMOS transistor is biased by the bias voltage. A second NMOS transistor has a source, a gate, and a drain, wherein the source of the second NMOS transistor is coupled to the ground, and the gate of the second NMOS transistor is biased by the bias voltage; as well as A second resistor circuit is coupled between the drain of the second PMOS transistor and the drain of the second NMOS transistor, wherein the second resistor circuit is coupled to the first input and the second input of the preamplifier, the resistance of the second resistor circuit is controlled by the first comparison voltage and the second comparison voltage, and the second output of the preamplifier is coupled to the node between the drain of the second PMOS transistor and the second resistor circuit.

10. The comparator of claim 9, wherein the resistors of the first resistor circuit and the second resistor circuit are configured to move in opposite directions in response to a change in the first comparison voltage, a change in the second comparison voltage, or a change in both the first comparison voltage and the second comparison voltage.

11. The comparator according to claim 1, further comprising: The third voltage-controlled resistor is coupled between the first inverter and ground; as well as A fourth voltage-controlled resistor is coupled between the second inverter and the ground.

12. The comparator of claim 11, further comprising a preamplifier, wherein the preamplifier is configured to: Receive the first comparison voltage and the second comparison voltage; The resistance of the first voltage-controlled resistor and the resistance of the third voltage-controlled resistor are adjusted in reverse based on the first comparison voltage or both the first comparison voltage and the second comparison voltage; and The resistance of the second voltage-controlled resistor and the resistance of the fourth voltage-controlled resistor are adjusted in reverse based on the second comparison voltage or both the second comparison voltage and the first comparison voltage.

13. The comparator according to claim 11, wherein: The first voltage-controlled resistor includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a source, a gate, and a drain, wherein the source of the first PMOS transistor is coupled to the voltage supply rail, and the drain of the first PMOS transistor is coupled to the voltage supply input of the first inverter. as well as The second voltage-controlled resistor includes a second PMOS transistor having a source, a gate, and a drain, wherein the source of the second PMOS transistor is coupled to the voltage supply rail, and the drain of the second PMOS transistor is coupled to the voltage supply input of the second inverter.

14. The comparator according to claim 13, wherein: The third voltage-controlled resistor includes a first n-type metal-oxide-semiconductor (NMOS) transistor having a source, a gate, and a drain, wherein the drain of the first NMOS transistor is coupled to the first inverter, and the source of the first NMOS transistor is coupled to ground; and The fourth voltage-controlled resistor includes a second NMOS transistor having a source, a gate, and a drain, wherein the drain of the second NMOS transistor is coupled to the second inverter, and the source of the second NMOS transistor is coupled to the ground.

15. The comparator of claim 1, wherein the first inverter comprises: A first p-type metal-oxide-semiconductor (PMOS) transistor has a source, a gate, and a drain, wherein the source of the first PMOS transistor is coupled to the voltage supply input of the first inverter, the drain of the first PMOS transistor is coupled to the output of the first inverter, and the gate of the first PMOS transistor is coupled to the input of the first inverter; as well as A first n-type metal-oxide-semiconductor (NMOS) transistor has a source, a gate, and a drain, wherein the drain of the first NMOS transistor is coupled to the output of the first inverter, the gate of the first NMOS transistor is coupled to the input of the first inverter, and the source of the first NMOS transistor is coupled to ground.

16. The comparator of claim 15, wherein the second inverter comprises: The second PMOS transistor has a source, a gate, and a drain, wherein the source of the second PMOS transistor is coupled to the voltage supply input of the second inverter, the drain of the second PMOS transistor is coupled to the output of the second inverter, and the gate of the first PMOS transistor is coupled to the input of the second inverter; as well as The second NMOS transistor has a source, a gate, and a drain, wherein the drain of the second NMOS transistor is coupled to the output of the second inverter, the gate of the second NMOS transistor is coupled to the input of the second inverter, and the source of the second NMOS transistor is coupled to ground.

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