Staggered software synchronization

Abstract

The present application discloses staggered software synchronization. Methods according to various embodiments can reduce scheduling delays caused by concurrent processing requests, which may involve VSync in a multi-streaming system. By offsetting the initial synchronization signal, the software synchronization signals can be staggered relative to each other. These software synchronization signals can be readjusted over time so that each synchronization signal can maintain the same relative offset relative to other applications or containers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 968,716, filed on January 31, 2020, entitled “Staggered Software VSync for Higher Quality of Service in Streaming Servers,” the entire contents of which are incorporated herein by reference for all purposes. Background Art

[0003] Recently, a streaming solution has been proposed that enables a server to have a feature that can be streamed to multiple clients. According to the proposed implementation, the processing unit of the server has the capacity to support 64 or more simultaneous clients. This usage model allows clients with mobile devices to interact remotely with the server more comprehensively. Although the raw computing power of the processing unit (e.g., a combination of a central processing unit (CPU) and a graphics processing unit (GPU)) may be sufficient to serve all clients, in some cases, the quality of service provided to each client may be inconsistent or unsatisfactory due to many potential simultaneous requests for resources.

[0004] One previous approach uses container objects and runs a single operating environment container for each client or end user. The container can be a complete operating system (OS), and the client will interact with the OS as if the client is interacting with a physical system, rather than the container acting as a virtual representation of the system. Although the client can interact with the server as if it were a real dedicated system, there may be multiple containers running on the system, and each container may have a separate display frame buffer allocated for that container. In addition, since the viewing of the content is done remotely, the OS container executing on the server may not have an attached display. Despite the lack of an attached physical display, the traditional idea of ​​being able to run a game at 30fps or 60fps still works fine. Otherwise, a single container may completely occupy one or more processing units, running thousands of frames per second (fps) without any benefit to the client or end user. To address this issue and allow all components in the operating system to work seamlessly, a pseudo vertical synchronization ("VSync") signal is generated at the desired frame rate (e.g., 30 / 60Hz).

[0005] The work performed on the processing unit is driven by this VSync signal, even in the case of a single GPU and / or a single application attached to a physical monitor. In a typical non-streaming system, after each VSync signal is received, a VSync operation is performed during which the render buffer and the displayable buffer are swapped. The previous display buffer becomes "free" for "rendering" to be used to perform the next frame. The swapping of the display buffer and the render buffer is done at VSync intervals to ensure tear-free animation. Once the render buffer becomes available, the operating system and / or driver releases the application rendering loop to start compositing the next frame of animation.

[0006] While software VSync works in a similar way, one problem with this approach in a multi-streaming system is that since all streaming containers generate (and schedule) their own VSyncs independently, the VSyncs may all be aligned with each other or may be very close to each other (within a few milliseconds of each other). This can also happen since the containers may be executing the same code and their software sync scheduling calculations may follow the same algorithm. If all streaming containers schedule their VSync operations to execute at the same time, all applications will unblock at the same time and will start composing their next frames at the same time. This may still be fine if the number of processors in the system is equal to the number of applications (for example, in a traditional one-to-one client-server configuration). However, in a multi-streaming solution, there are usually many fewer processors than clients or application instances. For example, there may be only eight CPUs servicing 64 different clients. This means that in some cases, there are not enough CPUs to schedule all application instances together, even if they should unblock at the same time. This may cause VSync notifications for some containers to be delayed. In addition, applications in some containers are scheduled on CPUs much later than software VSync, which may cause some applications to fail to fully compose a frame before the next VSync, resulting in lost frames. This can result in an unstable end-user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0008] Figure 1 A system for providing content according to at least one embodiment is shown;

[0009] Figure 2 illustrates example task synchronization according to at least one embodiment;

[0010] Figure 3 illustrates interleaved task synchronization according to at least one embodiment;

[0011] Figure 4A and Figure 4B shows an example of synchronization signal staggering according to at least one embodiment;

[0012] Figure 5 A process for managing tasks for multiple streams according to at least one embodiment is shown;

[0013] Figure 6 A process for determining offsets for individual streams according to at least one embodiment is shown;

[0014] Figure 7 An example data center system is shown in accordance with at least one embodiment;

[0015] Figure 8 A computer system according to at least one embodiment is shown;

[0016] Fig. 9 A computer system according to at least one embodiment is shown;

[0017] Fig.10 illustrates at least a portion of a graphics processor according to one or more embodiments; and

[0018] Fig.11 At least a portion of a graphics processor is shown in accordance with one or more embodiments. DETAILED DESCRIPTION

[0019] Methods according to various embodiments may alleviate scheduling issues for multiple concurrent workloads. In at least one embodiment, this may include a method for data or content streaming that enables a streaming service provider to provide streaming clients with a higher and more consistent end-user quality of experience by alleviating scheduling issues inherent in multi-streaming platforms. This may include, for example, staggering or offsetting synchronization signals, or providing offset or staggering commands based on one or more synchronization signals, for workloads or tasks that might otherwise attempt to process simultaneously or nearly simultaneously using a fixed group of processing resources.

[0020] Figure 1An example computer system 100 is shown that can be used to implement various aspects of various embodiments. In this example, a content server 102 can provide content to one or more client devices 150, 160 via at least one network 140. The content can be generated by one or more applications 104, 106, 108, 110 or instances of one or more applications. For example, there may be an application that provides content to each client device, but each client device may have a dedicated instance of the application, such as running in an application container or a virtual machine. In the content server 102, there are a fixed number of processors 114, 116, 118 that can be used to perform tasks or process data for these applications. These processors can be any suitable processing components, such as a central processing unit (CPU), a graphics processing unit (GPU), or a combination thereof. It should be understood that for simplicity, unless otherwise specifically stated, "application" can also refer to an instance of an application or "application instance" as used herein. In operation, an application 104 can request to perform a task, where the request can be directed to a resource manager 112, which can select an available processor to perform the task. The request may then be sent to a selected processor, which may perform the task and generate appropriate output to send to a corresponding client device. In at least some applications, such as for graphics applications, data may be sent only at specific intervals or points in time, such that the output may first be sent to a data manager 120 to be cached in a local buffer 122. At the appropriate time, the data may then be sent from the buffer to a corresponding client device, such as streamed to the client device via one or more networks 140 as directed by a transfer manager 124 or other such system or service. In this exemplary arrangement, the client devices may include various types of computing devices, such as may include a desktop computer, a laptop computer, a set-top box, a streaming media player, a gaming console, a smartphone, a tablet computer, a virtual reality (VR) headset, an augmented reality (AR) goggles, a wearable computer, or a smart TV. The one or more networks 104 may include at least one wired or wireless network, such as may include the Internet, an Ethernet network, a local area network (LAN), a peer-to-peer network, connection or cellular network, and other such options.

[0021] In such a content server 102, there may be more applications that need to be processed than the processors that provide the processing. In such a case, the resource manager 112 can manage the task allocation to the processor based on various allocation or balancing algorithms or methods, such as FIFO buffers or other such methods can be included. If the processor is available, these requests can be sent to the processor for processing when these requests are received. However, when concurrent requests or pending requests are more than the requests that these processors can handle, the resource manager may cause at least some of these requests to be delayed until such processing capacity is available. If these tasks are time-sensitive, this may cause unacceptable or undesirable performance degradation. For example, in a graphics application, when the data of one or more frames cannot be completed in time, for example, during the refresh cycle of a display device (which may correspond to the frame rate of a display device of one of the client devices), this may cause frame loss.

[0022] Methods according to various embodiments may attempt to minimize scheduling delays that are at least partially due to the presence of multiple concurrent workloads on the system. As an example, such a workload may correspond to video frames that will be sent to various client devices as part of a video game or content streaming service. As mentioned, new content frames are displayed by various display devices at a frame rate determined for each device, such as 30, 60, or 90 frames per second (fps). In this method, the content of the next frame must be received no later than the display time of the next frame, which corresponds to a refresh period of approximately 16.67ms for 60fps. In various systems, this is achieved by placing the video frame data into a buffer and then sending the frame data from the buffer at regular intervals (corresponding to the refresh period). This means that the data must all be in the buffer before the next transmission time, and the data of the subsequent frame cannot be placed in the buffer before the data of the previous frame has been transmitted from the buffer. Various systems manage this timing by using timing signals (such as VSync signals) that are used to synchronize the frame rate of an application (such as a video game) with the refresh rate of a display monitor. The VSync signal can be used to limit the frame rate output to the refresh rate of the display.

[0023] In various cases, the time to process the data of a frame will be much less than the refresh time, for example, the time to process data in a 16.67ms refresh time may correspond to approximately 2ms or 4ms. In one possible case, the display devices can all be synchronized to substantially the same time, for example, the VSync signals of the various displays are all received substantially at the same time. Figure 2A graph 200 is shown of this situation for a limited number of applications or instances. As discussed above, these tasks need not be graphics or video related, and may be related to any computerized task that may be performed at a particular time or interval, etc. In this example, each "cycle" may refer to a refresh cycle in a graphics environment. If the synchronization signals are all similar, then the applications may all wish to perform their tasks substantially simultaneously, which will not be possible if the number of applications exceeds the number of processors available to handle those tasks. Even if only a subset of the applications are so synchronized, this may still result in tasks exceeding processing capabilities at different times, which may result in at least some of these tasks being delayed. If any of these tasks are subsequently delayed beyond a target result time, such as the next refresh cycle, this may result in discarded data or data loss, or other such performance issues.

[0024] In one example, client applications are freed to work near the beginning of a cycle, and all clients can request to start execution at the same time. It should be noted that it is not limited to clients that may wish to run simultaneously, as other parts of the system (e.g., operating system window managers) may be driven by the same or similar events. As shown, there may be requests from four different containers to queue their execution. Since the resource manager can be single-threaded, any request received for system resources (e.g., memory allocation) will cause the clients to have to wait for each other.

[0025] In at least some embodiments, a time slicing approach can be utilized that can take advantage of the fact that for an application, there are certain portions within each refresh cycle during which the application will generally not require processing capacity. In at least one embodiment, the synchronization signals can be staggered, or offsets applied, so that at least some of these tasks can start at different times to reduce the amount of processing capacity required and to smooth the workload over time.

[0026] Figure 3 Shows Figure 2 300 for a workload of , but with staggering applied. In this example graph, it can be seen that by staggering the synchronization signals for these applications, no two applications request to process their workloads at the same time. Although in many cases it is possible to delay Figure 2 In the method of processing, Figure 3 This staggered approach provides more control over the timing of processing. Although there may be some initial synchronization signal misalignment, these signals may drift over time and lose at least some of this misalignment, which may result in applications still requesting work to be completed at the same time.

[0027] In at least one embodiment, this can be used to minimize scheduling delays due to concurrent vertical synchronization signals or "VSyncs" in a multi-streaming system. Embodiments include at least two aspects of the annotation. The first aspect is to stagger software VSyncs from each other by offsetting the initial VSync. The second aspect is to readjust software VSyncs over time (such as continuously or periodically) so that each VSync maintains the same relative offset relative to other applications, application containers, or other sources of processing tasks to be performed.

[0028] An example calculation of when to generate VSync is when the various containers evaluate to zero (current time % VSync period). If each container performs the same exact calculation, the timing of these calculations will all align. However, as previously discussed, alignment of these tasks can lead to problems such as dropped frames. Therefore, at least one embodiment can add an offset to at least one software VSync time. For example, if the next VSync time is calculated as:

[0029] Next VSync time = (current time / display cycle) * display cycle + display cycle, then the VSync time of container N can be calculated as follows:

[0030] Next VSync time_N = Next VSync time + Offset_N

[0031] Where offset_N is selected for the Nth container to distribute clients, and offset_N is uniquely calculated for each container.

[0032] Different methods for calculating such an offset may be utilized within the scope of various embodiments. One such method utilizes a randomizer to determine a random offset, where a seed for a random number is initialized based on some data (e.g., a parameter) that is unique to an application, instance, or container (e.g., the least significant bit of the current clock time). In this method, the client does not rely on any global information.

[0033] A method according to another embodiment may calculate the initial offset by exploiting the following observation: since the number of clients is finite, it is possible to calculate the initial offset by staggering the clients and having a more predictable distribution (e.g. Figure 3The distribution can be achieved using the distribution shown in ). For example, if there are only two clients, if the first client (instance ID is 0) starts at some time 0 at the beginning of the cycle, the second client (instance ID is 1) will ideally start in the middle of the cycle or 1 / 2*cycle time. Under this timing, the two clients will be out of phase with each other with respect to timing within a given cycle. If a third client (instance ID is 2) is added, instead of trying to adjust the offset, an offset can be applied to the third client, placing it between the first two clients, for example 1 / 4*cycle time. The fourth client can then be similarly added to 3 / 4*cycle time. In this approach, the intervals between the start times of the clients are automatically reduced without having to readjust the previous set of clients. In this approach, each client can request an "instance ID" from a central resource manager or other alternative device, and can use that instance ID to determine its offset. The calculation of the offset can be accomplished by utilizing the binary representation of a number, as shown below:

[0034]

[0035]

[0036] Figure 4A A table 400 is shown showing various instances or offsets of instance IDs using this approach. As mentioned, in some embodiments, these values ​​may be predetermined and the identifiers may be assigned appropriately.

[0037] Figure 4B Another graph 450 is provided which shows the Figure 4A These instances of the table are spaced and ordered over the duration of the period. In at least one embodiment, this "power of two" approach enables new streams to be dynamically added to the system at well-distributed locations in the VSync interval without affecting the scheduling of existing streams. Figure 4B As shown, in a VSync interval (expressed as a range between 0.0 and 1.0), the first stream in the system may have a VSync signal sent at the earliest available time slot, e.g., the start of the VSync interval (e.g., time = t1). The second stream is offset by 1 / 2 of the VSync interval (e.g., time = t2). Each subsequent stream that is added will be scheduled to receive a VSync signal at the midpoint between the largest remaining subinterval between two scheduled VSyncs within the VSync interval.

[0038] In at least one embodiment, such a process may also attempt to maintain this phase shift between clients. The initial offset may be remembered, where the offset may be calculated by a random method or binary division or other such method. Since this is a software generated VSync signal, it may not be precise enough due to factors such as OS scheduling delays. If a process only generates the next VSync within a period of time offset from the current position, the clients may eventually no longer be staggered due to the passage of time. In order to maintain the stagger, the initial offset may continue to be used in the two equations described previously to calculate the next VSync. In at least one embodiment, the next VSync time may be calculated as follows:

[0039] Next VSync time = (current time / display cycle) * display cycle + display cycle

[0040] Next VSync time_N = Next VSync time + Offset_N

[0041] Continuing to use the formula not only for the initial sync, but also for subsequent VSyncs ensures that the end-user experience does not degrade over time.

[0042] In at least one embodiment, this approach can be used to enable a single server to stream content to multiple clients simultaneously. In one embodiment, the server's CPU and GPU can have enough power to enable sixty-four or more simultaneous clients. This usage model can enable clients with mobile devices (for example) to interact remotely with a game server. Although the raw power of the CPU and GPU is sufficient to serve all clients, the quality of service to individual clients is very important, and this staggered approach can help ensure this quality of service over time.

[0043] In at least one embodiment, the system can utilize Android container objects and run an individual Android container for each end user or client device. The container can represent a fully running Android system, each container having a separate display frame buffer allocated for the container. In at least some embodiments, the management of task processing may include using SurfaceFlinger for Android applications (or the display window manager (DWM) for Windows, etc.). Components such as SurfaceFlinger may be responsible for combining all applications and system surfaces into a single buffer, which is provided for display on client devices, etc. Certain embodiments may utilize the DiscSync module in SurfaceFlinger to periodically resynchronize with the hardware. Using such a module can prevent the system from having to send a VSync signal for each frame. In at least some embodiments, an interface within SurfaceFlinger can be used to transmit a VSync signal, and in some embodiments, a hardware composer module can be used to generate this signal to simulate a physical display signal. In at least some embodiments, these offsets will be relative to the system clock signal.

[0044] Since the viewing of the content is done remotely, the Android container will have no display attached. The traditional idea of ​​being able to run a game at 30fps or 60fps works well even without an attached physical display, because otherwise a single container might completely occupy the GPU running thousands of frames without any benefit to the end user. In order for all components in the Android system to run seamlessly, a pseudo VSync signal is generated at 30Hz or 60Hz or other desired frame rate.

[0045] In at least one embodiment, the work done on the CPU and GPU is driven by this VSync signal. This is true even in the case of a single GPU or a single application attached to a physical monitor. In a real system for a non-streaming system, the render buffer and the displayable buffer are swapped at VSync. The previous display buffer becomes "free" to "render" the next frame. The swap of the display buffer and the render buffer is done at VSync to ensure tear-free animation. Once the render buffer becomes available, the operating system or driver will release the application rendering loop to start compositing the next frame of animation.

[0046] One problem with the exchange sequence of display buffers and render buffers in a streaming architecture is that since all streaming containers are generating their own VSync signals, the VSyncs can all be aligned or a few milliseconds apart from each other. This is also likely to happen because these containers are executing the same code and their software synchronization calculations may follow the same algorithm. If all streaming containers generate their VSync at the same time, all applications will be unblocked at the same time to start composing their next frame. This may still be fine if the number of processors in the system is equal to the number of applications. However, in a typical streaming solution, there are fewer CPUs than clients. For example, there may be only eight CPUs serving 64 clients. This means that even if all applications are unblocked at the same time, there are not enough CPUs to schedule all applications together. This causes some applications to be scheduled very late after VSync, and may cause some applications to not be able to fully compose a frame before the next VSync. This may cause dropped frames, resulting in an unsettled end-user experience.

[0047] However, as previously mentioned, such methods can be used outside of graphics and video applications and can provide benefits for any system in which tasks are assigned or scheduled to be processed by one or more processors, particularly systems in which multiple concurrent tasks may exceed the number of processors. For streaming workloads, timing is important, so streaming workloads may particularly benefit from such methods. In systems where hardware signals are typically used for synchronization, these signals can be emulated in software, which can stagger these signals or apply offsets to ensure that the timing of these signals has at least some distribution. As described above, offsets can be applied to tasks from any appropriate source, such as applications, processes, containers, virtual machines, systems, services, etc.

[0048] Figure 5An example process 500 for managing scheduling in a multi-streaming system according to various embodiments is shown. It should be understood that for this process and other processes presented herein, unless otherwise specifically stated, there may be additional, fewer, or alternative steps performed in a similar or alternative order or at least partially in parallel within the scope of various embodiments. In this example, multiple individual streams are allocated 502 for providing content via a multi-streaming system. In at least one embodiment, each stream can send content to a different client device and can also receive the content from various applications, instances, or containers discussed herein. Initial offset values ​​(e.g., initial VSync offsets) can be calculated 504 for these individual streams, where at least some different streams will have different offsets assigned within the synchronization interval. In at least one embodiment, each stream will have a unique offset. These initial VSync offsets can then be stored 506 for each stream. Appropriately, the time to the next VSync can be scheduled 508 for each stream using the corresponding VSync offset. For each stream, when a duration equal to the time to the next VSync has passed for the individual stream, a signal to perform a VSync operation can be sent 510.

[0049] Figure 6 An example process 600 is shown that can be used to determine these offsets according to at least one embodiment. In this example, individual streams of a multi-stream system are determined 602, where the streams have a synchronization period. To assign an offset, such as a VSync offset, a first stream is selected 604 and a first offset is assigned, in which case the first offset corresponds to a 0 offset for the first stream. Offsets can be assigned to entities or objects other than streams, which may correspond to other communication channels or paths. For multiple streams, a next stream can be selected 608, where the next stream can be a newly added stream after other offsets have been assigned. For the stream, a maximum window between offsets that have been assigned within the synchronization period can be determined 610. If there is more than one such period, the process can select the first such period encountered. A synchronization offset can then be assigned 612 to the stream, where the offset corresponds to the midpoint of the determined window. It can be determined 614 whether there are more streams to assign offsets, and if so, the process can continue to the next step. As described above, this may occur when additional streams are added to the system for management. If all current streams are assigned offsets, those offset assignments may be stored 616 for use in performing subsequent operations on those respective streams. As discussed herein, these offsets may be maintained 618 over time to account for drift or other such factors.

[0050] Data Center

[0051] Figure 7An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0052] In at least one embodiment, Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be a server having one or more of the above computing resources.

[0053] In at least one embodiment, the grouped computing resources 714 may include a separate grouping of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CRs within the grouped computing resources 714 may include computing, network, memory or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules and network switches in any combination.

[0054] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 712 may include hardware, software, or some combination thereof.

[0055] In at least one embodiment, Figure 7As shown, the framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, the framework layer 720 may include a framework that supports software 732 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 728 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 722 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720 including Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 can manage cluster or group computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the cluster or group computing resources may include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0056] In at least one embodiment, software 732 included in software layer 730 may include software used by at least a portion of node CRs 716(1)-716(N), grouped computing resources 714, and / or distributed file system 728 of framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0057] In at least one embodiment, the applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0058] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 700 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0059] In at least one embodiment, the data center 700 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 700. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, information may be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to the data center 700.

[0060] In at least one embodiment, the data center can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0061] Such a component can be used to stagger synchronization signals in order to distribute the workload across a group of processors.

[0062] Computer Systems

[0063] Figure 8800, which may include execution units to execute instructions. In at least one embodiment, in accordance with the present disclosure, such as the embodiments described herein, the computer system 800 may include, but is not limited to, components, such as a processor 802, whose execution units include logic to execute algorithms for process data. In at least one embodiment, the computer system 800 may include a processor, such as a processor 802 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , CoreTM or The computer system 800 may be configured to execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0064] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0065] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0066] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 802. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

[0067] In at least one embodiment, an execution unit 808, including but not limited to logic to perform integer and floating point operations, is also located in the processor 802. In at least one embodiment, the processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macro instructions. In at least one embodiment, the execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809 in the instruction set of the general purpose processor 802, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general purpose processor 802. In one or more embodiments, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations one data element at a time.

[0068] In at least one embodiment, execution unit 808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0069] In at least one embodiment, the system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can initiate data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via a high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814.

[0070] In at least one embodiment, the computer system 800 can use the system I / O 822 as a proprietary hub interface bus to couple the MCH 816 to an I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 can provide direct connections to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 820, the chipset, and the processor 802. Examples can include, but are not limited to, an audio controller 829, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data storage 824, a traditional I / O controller 823 including user input and a keyboard interface 825, a serial expansion port 827 (e.g., a universal serial bus (USB)), and a network controller 834. The data storage device 824 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0071] In at least one embodiment, Figure 8 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 8 An exemplary system on a chip ("SoC") may be shown. In at least one embodiment, the devices may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using a Compute Express Link (CXL) interconnect.

[0072] Such a component can be used to stagger synchronization signals in order to distribute the workload across a group of processors.

[0073] Fig. 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0074] In at least one embodiment, system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface, such as a Ic bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig. 9 A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig. 9 An exemplary system on a chip ("SoC") may be shown. In at least one embodiment, Fig. 9 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig. 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0075] In at least one embodiment, Fig. 9 The display 924, the touch screen 925, the touch pad 930, the near field communication unit ("NFC") 945, the sensor hub 940, the thermal sensor 946, the fast chipset ("EC") 935, the trusted platform module ("TPM") 938, the BIOS / firmware / flash memory ("BIOS, FW Flash") 922, the DSP 960, the drive 920 (such as a solid state disk ("SSD") or a hard disk drive ("HDD")), the wireless local area network unit ("WLAN") 950, the Bluetooth unit 952, the wireless wide area network unit ("WWAN") 956, the global positioning system (GPS) 955, the camera ("USB 3.0 camera") 954 (such as a USB 3.0 camera) and / or the low power double data rate ("LPDDR") storage unit ("LPDDR3") 915 implemented in, for example, the LPDDR3 standard. Each of these components can be implemented in any suitable manner.

[0076] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components discussed above. In at least one embodiment, the accelerometer 941, ambient light sensor (“ALS”) 942, compass 943, and gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, the thermal sensor 939, fan 937, keyboard 946, and touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, the speaker 963, earphone 964, and microphone (“mic”) 965 may be communicatively coupled to the audio unit (“audio codec and class D amplifier”) 962, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 964 may include, for example, but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, the SIM card (“SIM”) 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF).

[0077] Such a component can be used to stagger synchronization signals in order to distribute the workload across a group of processors.

[0078] Fig.10 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1002 or processor cores 1007. In at least one embodiment, system 1000 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0079] In at least one embodiment, the system 1000 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the system 1000 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 1000 may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0080] In at least one embodiment, one or more processors 1002 each include one or more processor cores 1007 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a specific instruction set 1009. In at least one embodiment, the instruction set 1009 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing through very long instruction words (VLIW). In at least one embodiment, multiple processor cores 1007 can each process a different instruction set 1009, which can include instructions that help emulate other instruction sets. In at least one embodiment, the processor core 1007 can also include other processing devices, such as a digital signal processor (DSP).

[0081] In at least one embodiment, the processor 1002 includes a cache memory 1004. In at least one embodiment, the processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between various components of the processor 1002. In at least one embodiment, the processor 1002 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share the logic between the processor cores 1007 using known cache coherence techniques. In at least one embodiment, the processor 1002 additionally includes a register file 1006, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 1006 may include general registers or other registers.

[0082] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between the processor 1002 and other components in the system 1000. In at least one embodiment, the interface bus 1010 can be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface 1010 is not limited to a DMI bus, and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, the memory controller 1016 facilitates communication between storage devices and other components of the system 1000, while the platform controller hub (PCH) 1030 provides connections to I / O devices through a local I / O bus.

[0083] In at least one embodiment, the storage device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have appropriate performance to be used as a process memory. In at least one embodiment, the storage device 1020 may be used as a system memory of the system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, the memory controller 1016 is also coupled to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 in the processor 1002 to perform graphics and media operations. In at least one embodiment, the display device 1011 may be connected to the processor 1002. In at least one embodiment, the display device 1011 may include one or more internal display devices, such as in a mobile electronic device or portable computer device or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 1011 may include a head mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0084] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to be connected to the storage device 1020 and the processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, and a data storage device 1024 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, the touch sensor 1025 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 1034 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1010. In at least one embodiment, the audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, the system 1000 includes an optional traditional I / O controller 1040 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, the platform controller hub 1030 can also be connected to one or more universal serial bus (USB) controllers 1042, which connect input devices such as a keyboard and mouse 1043 combination, a camera 1044, or other USB input devices.

[0085] In at least one embodiment, instances of memory controller 1016 and platform controller hub 1030 may be integrated into a discrete external graphics processor, such as external graphics processor 1012. In at least one embodiment, platform controller hub 1030 and / or memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, system 1000 may include external memory controller 1016 and platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 1002.

[0086] Such a component can be used to stagger synchronization signals in order to distribute the workload across a group of processors.

[0087] Fig.11is a block diagram of a processor 1100 having one or more processor cores 1102A-1102N, an integrated memory controller 1114, and an integrated graphics processor 1108 in accordance with at least one embodiment. In at least one embodiment, the processor 1100 may include additional cores up to and including the additional core 1102N represented by the dashed box. In at least one embodiment, each processor core 1102A-1102N includes one or more internal cache units 1104A-1104N. In at least one embodiment, each processor core may also have access to one or more shared cache units 1106.

[0088] In at least one embodiment, the internal cache units 1104A-1104N and the shared cache unit 1106 represent a cache memory hierarchy within the processor 1100. In at least one embodiment, the cache memory units 1104A-1104N may include at least one level of instructions and data within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 1106 and 1104A-1104N.

[0089] In at least one embodiment, the processor 1100 may also include a set of one or more bus controller units 1116 and a system agent core 1110. In at least one embodiment, the one or more bus controller units 1116 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 1110 provides management functions for various processor components. In at least one embodiment, the system agent core 1110 includes one or more integrated memory controllers 1114 to manage access to various external memory devices (not shown).

[0090] In at least one embodiment, one or more processor cores 1102A-1102N include support for multiple threads simultaneously. In at least one embodiment, system agent core 1110 includes components for coordinating and operating cores 1102A-1102N during multithreaded processing. In at least one embodiment, system agent core 1110 may additionally include a power control unit (PCU) that includes logic and components to adjust one or more power states of processor cores 1102A-1102N and graphics processor 1108.

[0091] In at least one embodiment, the processor 1100 additionally includes a graphics processor 1108 to perform graphics processing operations. In at least one embodiment, the graphics processor 1108 is coupled to a shared cache unit 1106 and a system agent core 1110 including one or more integrated memory controllers 1114. In at least one embodiment, the system agent core 1110 also includes a display controller 1111 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 1111 may also be a separate module coupled to the graphics processor 1108 via at least one interconnect, or may be integrated within the graphics processor 1108.

[0092] In at least one embodiment, a ring-based interconnect unit 1112 is used to couple the internal components of the processor 1100. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 1108 is coupled to the ring interconnect 1112 via an I / O link 1113.

[0093] In at least one embodiment, I / O link 1113 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 1118 (e.g., eDRAM modules). In at least one embodiment, each of processor cores 1102A-1102N and graphics processor 1108 uses embedded memory modules 1118 as a shared last level cache.

[0094] In at least one embodiment, the processor cores 1102A-1102N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 1102A-1102N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1102A-1102N execute a common instruction set, while one or more other processor cores 1102A-1102N execute a subset of a common instruction set or a different instruction set. In at least one embodiment, the processor cores 1102A-1102N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 1100 can be implemented on one or more chips or as a SoC integrated circuit.

[0095] Such a component can be used to stagger synchronization signals in order to distribute the workload across a group of processors.

[0096] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the disclosure as defined by the appended claims.

[0097] Unless otherwise noted, unless otherwise noted or clearly contradicted by the context, the use of the terms "a", "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and the plural, and not as definitions of the terms. The terms "comprising", "having", "including" and "containing" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" when unmodified refers to a physical connection and should be understood as part or all of being contained in, connected to or connected together, even if there are any intervening. Unless otherwise noted herein, the reference to numerical ranges herein is intended only to be used as a shorthand method of referring to each individual value falling within the range separately, and each individual value is incorporated into the specification as if it were recited separately herein. Unless otherwise indicated or contradicted by the context, the use of the term "set" (e.g., "a set of items") or "subset" should be interpreted as a non-empty set including one or more members. In addition, unless otherwise indicated or contradicted by the context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but a subset and a corresponding set may be equal.

[0098] Unless otherwise expressly indicated or clearly contradicted by the context, conjunction language such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" is understood in the context to be generally used to refer to items, and the term etc. can be A or B or C, or any non-empty subset of the set of A and B and C. For example, in a set having three members, the conjunction phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such conjunction language is generally not intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. In addition, unless otherwise stated or contradicted by the context, the term "plurality" indicates a plural state (e.g., "plurality items" means a plurality of items). The plural is at least two items, but can be a plurality when explicitly or by the context indicates. In addition, unless otherwise stated or clear from the context, the phrase "based on" means "based at least in part on" rather than "based only on".

[0099] Unless otherwise indicated herein or clearly contradictory to the environment, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or their variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions, and are implemented as codes (e.g., executable instructions, one or more computer programs, or one or more applications) that are jointly executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program that includes a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include a transient signal (e.g., a transient electrical or electromagnetic transmission of a propagation), but includes a non-transitory data storage circuit (e.g., a buffer, a cache, and a queue) in a transceiver of a transient signal. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having executable instructions stored thereon (or other memory to store executable instructions), and when executed (i.e., due to being executed) by one or more processors of a computer system, the computer system performs the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media and one or more single non-transitory storage media of the plurality of non-transitory computer-readable storage media lacking all codes, while the plurality of non-transitory computer-readable storage media collectively store all codes. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0100] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software capable of implementing the operations. In addition, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment, is a distributed computer system that includes multiple devices that operate in different ways, so that the distributed computer system performs the operations described herein, and so that a single device does not perform all operations.

[0101] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise stated. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0102] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference.

[0103] In the description and claims, the terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms may not be intended as synonyms for each other. On the contrary, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0104] Unless otherwise specifically stated, it is understood that throughout the specification, terms such as "processing", "calculating", "computing", "determining", etc. refer to the actions and / or processes of a computer or computing system or similar electronic computing device to process and / or convert data represented as physical quantities (e.g., electronic) in registers and / or memories of the computing system into other data similarly represented as physical quantities in memories, registers or other such information storage, transmission or display devices of the computing system.

[0105] In a similar manner, the term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Moreover, each process may refer to multiple processes to execute instructions sequentially or in parallel, continuously or intermittently. Because a system may embody one or more methods and a method may be considered a system, the terms "system" and "method" are used interchangeably herein.

[0106] In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, a computer system or a computer-implemented machine. Obtaining, acquiring, receiving or inputting analog and digital data may be accomplished in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In some embodiments, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data via a serial or parallel interface. In another embodiment, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending or presenting analog or digital data may be accomplished by transmitting data as an input or output parameter of a function call, an application programming interface or an inter-process communication mechanism.

[0107] Although the above discussion sets forth example implementations of the described techniques, other architectures may be used to implement the described functionality and are intended to be within the scope of the present disclosure. In addition, although specific responsibility allocations are defined above for discussion purposes, various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0108] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A method comprising: For each stream in a multi-stream system, Calculating an initial VSync offset for a stream, wherein each stream of the multi-stream system is adjusted to have a different initial VSync offset within a VSync interval; storing the initial VSync offset for the stream; Scheduling a next VSync time for the stream using the initial VSync offset; as well as When a duration equal to the time to the next VSync has elapsed, a signal is sent to perform a VSync operation for the stream.

2. The method of claim 1 , wherein calculating the initial VSync offset for the stream comprises: Based on the number of streams in the multi-streaming system, the initial VSync offset for the stream is staggered without rescheduling to a time of a next VSync for any other stream in the multi-streaming system.

3. The method of claim 2, wherein calculating the initial VSync offset for the stream comprises: Determine the maximum remaining subinterval between any two initial VSync offsets in a single VSync interval; as well as The initial VSync offset is assigned to be substantially equal to half the time between the maximum remaining subintervals. The method of claim 1 , wherein each stream corresponds to a separate container, the separate container corresponding to a separate instance of the operating environment.

5. The method of claim 1 , wherein calculating the initial VSync offset for the stream comprises: A randomizer is applied using a seed initialized based on a value unique to the individual stream.

6. The method of claim 1 , wherein calculating the initial VSync offset for the stream comprises: dividing each processing period by the number of streams corresponding to the multi-stream system to determine a quotient; Assigning a different stream identifier to each stream; as well as A different coefficient is assigned to each stream identifier, wherein an initial VSync offset for any individual stream of the multi-streaming system is a product of the quotient and the coefficient of the stream identifier corresponding to the individual stream.

7. The method according to claim 6, wherein the number of streams corresponding to the multi-streaming system is equal to the number of streams that the multi-streaming system can support.

8. The method of claim 7, wherein the number of streams that the multi-streaming system can support exceeds the number of processing units of the multi-streaming system.

9. The method according to claim 1, further comprising: determining a new stream for the multi-stream system; Calculating an initial VSync offset for the new stream; as well as A staggered VSync schedule is maintained by dynamically adjusting the initial VSync offset of at least one other stream of the multi-stream system.

10. The method of claim 1, wherein sending the signal to perform a VSync operation indicates availability of a buffer for performing a rendering operation associated with the stream.

11. A system comprising: a network interface for communicating data with a plurality of client devices over a network on a corresponding plurality of streams; as well as One or more processing units, configured to perform, for each of the plurality of streams: calculating an initial VSync offset for a stream in a VSync interval, wherein the respective streams of the plurality of streams are adjusted to have different initial VSync offsets within the VSync interval; storing the initial VSync offset for the stream; Scheduling a next VSync time for the stream using the initial VSync offset; as well as When a duration equal to the time to the next VSync has elapsed, a signal is sent to perform a VSync operation for the stream.

12. The system of claim 11, wherein at least one of the one or more processing units performs calculation of the initial VSync offset by staggering the initial VSync offset of the stream based on the number of streams in the plurality of streams without rescheduling to a next VSync time for any other stream in the plurality of streams.

13. The system of claim 12, wherein at least one of the one or more processing units is configured to calculate an initial VSync offset for the stream by: determining a maximum remaining sub-interval between any two initial VSync offsets in the VSync interval; and The initial VSync offset is assigned to be substantially equal to half the time between the maximum remaining subintervals.

14. The system of claim 11, wherein each stream corresponds to a separate container, the separate container corresponding to a separate instance of the operating environment.

15. The system of claim 14, wherein the operating environment comprises an operating system.

16. The system of claim 15, wherein the operating environment further comprises at least one of a driver or an application programming interface (API) for the processing unit.

17. The system of claim 11, wherein at least one of the one or more processing units performs the calculation of the initial VSync offset for the stream by applying a randomizer using a seed initialized based on a value unique to the individual stream.

18. The system of claim 11, wherein at least one of the one or more processing units calculates the initial VSync offset for the stream by: dividing each processing cycle by the number of flows corresponding to the plurality of flows to determine a quotient; assigning a different stream id to each stream; and A different coefficient is assigned to each stream id, wherein an initial VSync offset for any individual stream of the plurality of streams is a product of the quotient and the coefficient corresponding to the stream id of the individual stream.

19. The system of claim 18, wherein the number of streams is equal to the number of streams that the server can support.

20. The system of claim 19, wherein the number of streams that the server can support exceeds the number of central processing units (CPUs) of the server.

21. The system of claim 11, wherein at least one of the one or more processing units performs the sending of the signal to perform a VSync operation when a buffer of the processing unit for performing a rendering operation associated with the stream is available.

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