Power semiconductor device and method for manufacturing a power semiconductor device

Abstract

A power semiconductor device comprises: a die carrier; a power semiconductor chip, which is coupled to the die carrier through a first solder joint; a sleeve for a pin, which is coupled to the die carrier through a second solder joint; and a seal, which mechanically attaches the sleeve to the die carrier, the seal being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the seal does not cover the power semiconductor chip.

Description

Technical Field

[0001] The present disclosure relates generally to power semiconductor devices, and to methods for manufacturing power semiconductor devices. Background Art

[0002] A power semiconductor device may include contact pins configured to electrically couple different components within the power semiconductor device to each other, or to provide contact to the outside of the power semiconductor device (e.g., to a circuit board). Such pins may be inserted into a sleeve that is electrically coupled and mechanically fixed to a substrate of the power semiconductor device, for example, via a solder joint. Mechanical stresses applied to these solder joints, for example, during the manufacture of the power semiconductor device, may cause electrical and / or mechanical failure of the solder joints. Therefore, it may be desirable to eliminate or at least reduce the mechanical stresses to which these solder joints are subjected. Improved power semiconductor devices and improved methods for manufacturing power semiconductor devices may help address these and other problems.

[0003] The problem on which the invention is based is solved by the features of the independent claims. Further advantageous examples are described in the dependent claims. Summary of the invention

[0004] Various aspects relate to a power semiconductor device comprising: a die carrier; a power semiconductor chip coupled to the die carrier via a first solder joint; a sleeve for a pin, the sleeve coupled to the die carrier via a second solder joint; and a seal mechanically attaching the sleeve to the die carrier, the seal being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the seal does not cover the power semiconductor chip.

[0005] Various aspects relate to a method for manufacturing a power semiconductor device, the method comprising: providing a die carrier; soldering a power semiconductor chip to the die carrier, thereby forming a first solder joint; soldering a sleeve for a pin to the die carrier, thereby forming a second solder joint; and mechanically attaching the sleeve to the die carrier with a seal, the seal being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, wherein the seal does not cover the power semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings illustrate examples and, together with the description, are used to explain the principles of the present disclosure. Other examples of the present disclosure and many expected advantages will be readily understood as they become better understood by reference to the following specific embodiments. The elements in the accompanying drawings are not necessarily to scale with respect to each other. The same reference numerals indicate corresponding similar parts.

[0007] Figure 1A and Figure 1BA cross-sectional view of a power semiconductor device is shown, wherein a seal is arranged around a sleeve for a lead.

[0008] Figure 2 A detailed view of the pins and the seal disposed around the pins is shown.

[0009] Figure 3 A cross-sectional view of another power semiconductor device including pins and a seal and also including a frame is shown.

[0010] FIG. 4A to FIG. 4F Cross-sectional views of a power semiconductor device at various stages of fabrication are shown according to an example of a method for fabricating a power semiconductor device.

[0011] Figure 5 is a flow chart of a method for manufacturing a power semiconductor device. DETAILED DESCRIPTION

[0012] In the following detailed description, directional terms such as "top", "bottom", "left", "right", "upper", "lower", etc. are used with reference to the orientation of (one or more) figures being described. In addition, to the extent that the terms "including", "having", "with" or other variations thereof are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "including". The terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact, or they are not in direct contact with each other; intervening elements or layers may be provided between the elements being "engaged", "attached" or "connected". However, it is also possible that the elements being "engaged", "attached" or "connected" are in direct contact with each other.

[0013] Examples of power semiconductor devices described below may use various types of semiconductor chips or circuits incorporated in semiconductor chips, among which there are AC / DC or DC / DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (junction gate field effect transistors), power bipolar transistors, logic integrated circuits, analog integrated circuits, power integrated circuits, etc. Examples may also use semiconductor chips including vertical transistor structures, such as IGBT (insulated gate bipolar transistor) structures, or generally transistor structures in which at least one electrical contact pad is arranged on a first main face of the semiconductor chip and at least one other electrical contact pad is arranged on a second main face of the semiconductor chip opposite to the first main face of the semiconductor chip.

[0014] The power semiconductor device described below may include one or more semiconductor chips. As an example, one or more power semiconductor chips may be included. In addition, one or more logic integrated circuits may be included in the device. The logic integrated circuit may be configured to control an integrated circuit of other semiconductor chips, such as an integrated circuit of a power semiconductor chip. The logic integrated circuit may be implemented in a logic chip.

[0015] A "seal" as understood in this disclosure may be a deposited plug, eg, a polymer, which mechanically secures the sleeve to the die carrier.

[0016] Figure 1A and Figure 1B A power semiconductor device 100 is shown comprising a die carrier 110, a power semiconductor chip 120 and a sleeve 130. Furthermore, the power semiconductor device 100 comprises a seal 140, wherein the seal 140 mechanically attaches the sleeve 130 to the die carrier 110.

[0017] exist Figure 1A In FIG. 1 , the seal 140 is shown in a transparent representation so that the entire sleeve 130 can be seen. Figure 1B In FIG. 1 , seal 140 is shown in an opaque representation.

[0018] The power semiconductor chip 120 is coupled to the die carrier 110 through a first solder joint 150, and the sleeve 130 is coupled to the die carrier 110 through a second solder joint 160. The seal 140 is arranged at a lower end 131 of the sleeve 130, wherein the lower end 131 faces the die carrier 110. In addition, the seal 140 is arranged in the power semiconductor device 100 such that the seal 140 does not cover the power semiconductor chip 120.

[0019] The power semiconductor device 100 may be, for example, a power semiconductor package, and it may include an encapsulant encapsulating a power semiconductor chip 120. The power semiconductor device 100 may include an external contact configured to connect the power semiconductor chip 120 to the outside of the encapsulant.

[0020] The die carrier 110 may, for example, include Al, Cu or Fe, or may consist of Al, Cu or Fe. The die carrier 110 may, for example, be a direct copper bonding (DCB), direct aluminum bonding (DAB), active metal brazing (AMB) or similar type of substrate. The die carrier 110 may in particular include an upper side 111 and an opposite lower side 112. The upper side 111 may include conductive traces, which may, for example, be configured to electrically couple the power semiconductor chip 120 to a pin inserted into the sleeve 130.

[0021] The underside 112 of the die carrier 110 may also be electrically conductive. The underside 112 may be an outer surface of the power semiconductor device 100. According to an example, the die carrier 110 may be arranged on a substrate such that the underside 112 faces the substrate.

[0022] The power semiconductor chip 120 may be configured to operate at a high voltage and / or a high current. The power semiconductor chip 120 may include a power electrode or a control electrode electrically coupled to a pin inserted into the sleeve 130. The power semiconductor device 100 may include several sleeves 130, wherein different electrodes of the power semiconductor chip 120 are coupled to pins inserted into different sleeves 130.

[0023] According to an example, the power semiconductor device 100 includes several power semiconductor chips 120. These power semiconductor chips 120 can be coupled to each other to form a circuit, such as a half-bridge circuit, an inverter circuit, or a converter circuit. In addition, different power semiconductor chips 120 can be coupled to different pins.

[0024] Sleeve 130 may be configured to have pins (eg, connector pins) inserted therein. Sleeve 130 may include or consist of any material that may be soldered to die carrier 110. For example, sleeve 130 may include or consist of a metal such as Al, Cu, or Fe.

[0025] The sleeve 130 may include a lower end 131, and the sleeve 130 may include an upper end 132 opposite the lower end 131. The upper end 132, or an upper quarter of the sleeve 130, or an upper third of the sleeve 130, or an upper half of the sleeve 130 may extend beyond the seal 140. However, it is also possible that the seal 140 covers the entire length of the sleeve 130 or nearly the entire length.

[0026] The sleeve 130 may be arranged on the upper side 111 of the die carrier 110. The sleeve 130 may be spaced apart from the power semiconductor chip 120. For example, the sleeve 130 may be spaced apart from the power semiconductor chip 120 by more than 1 mm, more than 5 mm, more than 10 mm, or more than 15 mm. The sleeve 130 may be arranged substantially vertically with respect to the upper side 111 of the die carrier 110.

[0027] The seal 140 may, for example, include or consist of a polymer. For example, the seal 140 may include or consist of a polyimide. According to another example, the seal 140 includes or consists of a non-polymeric material. The seal 140 may include or consist of an electrically insulating material. The seal 140 may include a single material or it may include a material composition. The seal 140 may be configured to provide a rigid mechanical support and securely fasten the sleeve 130 to the die carrier 110. The seal 140 may be particularly configured to couple the sleeve 130 to the die carrier 110 with a mechanical strength greater than that of the second solder joint 160 (e.g., twice as strong or three times as strong).

[0028] Applying the seal 140 to the sleeve 130 may include depositing the seal 140 in liquid form (e.g., a polymer dissolved in a solvent), for example, by using a dispensing process, an inkjet process, or a spraying process. Applying the seal 140 may also include curing the seal 140, for example, by applying heat or radiation such as UV.

[0029] The seal 140 may be particularly configured to mechanically couple the sleeve 130 to the die carrier 110 with sufficient stability. Due to the presence of the seal 140, the sleeve 130 may be coupled to the die carrier 110 with greater mechanical strength than if the seal 140 is not used and the sleeve 130 is mechanically coupled to the die carrier 110 only via the second solder joint 160.

[0030] like Figure 1A As shown in , the sleeve 130 may include a widened rim at its lower end 131, which may be completely covered by the seal 140. This may increase the bonding strength between the sleeve 130 and the seal 140 (and thus also between the sleeve 130 and the die carrier 110).

[0031] The seal 140 may completely surround and cover the lower end 131 of the sleeve 130. The seal 140 may completely surround and cover the second solder joint 160. The seal 140 may, for example, have the form of a bead. The seal 140 may be centered on the sleeve 130. The seal 140 may be in direct contact with the sleeve 130 and in direct contact with the upper side 111 of the die carrier 110. The seal 140 may, for example, have a diameter d of 1.5 mm or more, or 2 mm or more, or 2.5 mm or more, or 3 mm or more, or 4 mm or more.

[0032] The seal 140 may have a substantially hemispherical shape, wherein the sleeve 130 extends out of the top of the hemispherical shape (see FIG. Figure 1A and Figure 1B). However, it is also possible that the seal 140 takes the form of a meniscus surrounding the sleeve 130.

[0033] The power semiconductor chip 120, the sleeve 130 and the seal 140 may be arranged on the die carrier 110 in such a way that the seal 140 does not contact the power semiconductor chip 120. There may be a gap x between the seal 140 and the power semiconductor chip 120, which may be greater than 1 mm, or greater than 1.5 mm, or greater than 2 mm, or greater than 3 mm, for example.

[0034] According to an example, the power semiconductor device 100 may include several sleeves 130 and corresponding seals 140. The sleeves 130 and corresponding seals 140 may be arranged, for example, along one or more edges of the die carrier. In addition, the power semiconductor device 100 may include several power semiconductor chips 120, which may be arranged substantially in the center of the die carrier 110.

[0035] Figure 2 An example of a sleeve 200 is shown in more detail. The sleeve 200 can be similar or identical to the sleeve 130. The sleeve 200 includes a lower end 201 and an opposite upper end 202. The sleeve 200 also includes a hollow core 203 configured to accommodate pins (i.e., contact pins) of a semiconductor device such as the power semiconductor device 100. The sleeve 200 can include a widened edge at the lower end 201 and another widened edge at the upper end 202.

[0036] The sleeve 200 may be symmetrical from above the upper end 202 and below the lower end 201. In particular, the two ends 201 and 202 may be open so that the pin can be inserted from either end. This also means that when forming the second solder joint 160, the solder material may spread into the hollow core 203. For example, if too much solder material is used to create the second solder joint 160 and the solder material thus fills the hollow core 203, this may be problematic. This may prevent the pin from being fully inserted into the sleeve 200. For example, for this reason, it may be beneficial to mechanically join the sleeve 200 (or sleeve 130) to the die carrier 110 using the seal 140 rather than increasing the amount of solder material to form a larger and more secure solder joint 160.

[0037] The widened edges at the lower end 201 and the upper end 202 of the sleeve 200 may have a diameter w1 of, for example, 1.5 mm or more, or 1.8 mm or more, or 2 mm or more. The diameter w1 of the widened edges may be smaller than the diameter d of the seal 140 (compare Figure 1B), for example, 1 mm or more, 2 mm or more, or 3 mm or more. The diameter w2 of the central portion of the sleeve 200 can be, for example, in the range of about 0.9 mm to about 1.5 mm. The diameter w3 of the hollow core 203 can be, for example, in the range of about 0.7 mm to about 1.2 mm. The sleeve 200 can have any suitable length l, for example, 5 mm or more, or 1 cm or more, or 1.5 cm or more.

[0038] The seal 140 may be arranged around the sleeve 200 such that it completely covers the widened rim at the lower end 201. At least the upper half of the sleeve 200 may extend beyond the seal 140. However, according to the example, it is also possible that more than the lower half of the sleeve 200 is covered by the seal 140. For example, the seal 140 may cover the sleeve 200 (almost) up to the widened rim at the upper end 202. Figure 2 In the example shown, the seal has the form of a meniscus surrounding the sleeve 200 .

[0039] Figure 3 An example of another power semiconductor device 300 is shown, which may be similar or identical to the power semiconductor device 100 except for the differences described below.

[0040] The power semiconductor device 300 comprises a die carrier 110 , at least one power semiconductor chip 120 and at least one sleeve 130 and a corresponding encapsulation 140 as described with reference to the power semiconductor device 100 .

[0041] The power semiconductor device 300 may further include a frame 310, which may be, for example, a plastic frame. The frame 310 may, for example, include sidewalls 311 and a cover 312. The power semiconductor device 300 may further include one or more pins 320 inserted into (one or more) sleeves 130 and / or an encapsulant 330 encapsulating (one or more) power semiconductor chips 120.

[0042] The frame 310 may be configured to provide a cavity in which the power semiconductor chip 120 , the sleeve 130 , the seal 140 , and the encapsulant 330 are arranged. Figure 3 In the example shown in , the frame 310 is arranged on the upper side of the die carrier 110. However, it is also possible that the power semiconductor device 300 comprises a substrate, wherein the frame 310 is arranged on the substrate, and the die carrier 110 is completely arranged in the cavity (e.g., Figure 4F The power semiconductor device 300').

[0043] The pins 320 may be configured to extend out of the frame 310, for example, out of the cover 312. The pins 320 may be configured to electrically couple the power semiconductor chip 120 to the outside of the power semiconductor device 300. According to an example, the power semiconductor device 300 may be configured to have a circuit board, for example, a PCB, arranged on the cover 312, wherein the pins 312 are configured to couple the power semiconductor chip 120 to the circuit board.

[0044] Closing the cover 312 may include inserting the pins 320 into holes in the cover 312, and coupling the power semiconductor chip 120 to the circuit board may include inserting the pins into through-hole connectors of the circuit board. For example, due to manufacturing tolerances, this may cause the pins 320 to be arranged on the die carrier 110 in an inclined orientation, which may apply lateral forces (forces along the plane of the die carrier 110) to the second solder joint 160 that couples the sleeve 130 to the die carrier 110. Strong lateral forces may cause cracks in the second solder joint 160 and thus cause electrical and / or mechanical failure of the semiconductor device.

[0045] However, by using the seal 140, such strong lateral forces may be avoided, as explained in more detail below. The seal 140 may substantially provide a mechanical bond between the sleeve 130 and the die carrier 110, while the second solder joint 160 may only be necessary to provide an electrical connection between the sleeve 130 (i.e., the pin 320) and the die carrier 110.

[0046] The encapsulant 330 may be configured to protect the power semiconductor chip 120 from external influences. The encapsulant 330 may be, for example, a gel. The encapsulant 330 is different from the sealant 140, and the encapsulant 330 may be composed of a material or material composition different from the sealant 140. For example, the sealant 140 may be composed of a material or material composition that is not ductile or almost not ductile, while the encapsulant 330 may be easily ductile. In addition, the sealant 140 may be relatively strongly bonded to the die carrier 110, and the encapsulant 330 may be relatively weakly bonded to the die carrier 110. The sealant 140 may have a higher tensile strength than the encapsulant 330, for example, twice the tensile strength or three times the tensile strength.

[0047] FIG. 4A to FIG. 4F 1 shows power semiconductor devices 300 and 300' at various stages of manufacture according to an example of a method for manufacturing a power semiconductor device. It should be noted that the power semiconductor device need not be FIG. 4A to FIG. 4F The manufacturing stages are shown in the order of manufacture.

[0048] like Figure 4AAs shown in , a die carrier 110 is provided. A power semiconductor chip 120 and a sleeve 130 are arranged on an upper side 111 of the die carrier 110 and soldered to the die carrier 110, thereby forming a first solder joint 150 and a second solder joint 160. The sleeve 130 may be soldered to the die carrier 110 simultaneously with the power semiconductor chip 120, or they may be soldered to the die carrier 110 before or after the power semiconductor chip 120.

[0049] like Figure 4B As shown in FIG. 1 , the seal 140 is disposed on the die carrier 110 around the sleeve 130. Disposing the seal 140 on the die carrier 110 may include depositing the seal material in liquid form, for example, by dispensing, by using an inkjet, or by spraying. The deposition may include depositing one or more droplets of the liquid seal material at or around the sleeve 130, or it may include depositing a continuous film of the liquid seal material around the sleeve 130.

[0050] After the liquid seal material has been deposited, it can be cured to produce the seal 140. Curing the liquid seal material can include applying heat (e.g., a temperature of up to 200° C.) and / or applying radiation (e.g., UV light). According to an example, the curing process can take up to about 10 minutes, up to about 30 minutes, or up to about 1 hour.

[0051] After the curing process, the seals 140 are mechanically strong, and they may significantly reduce or even eliminate any mechanical stress that may be applied to the second solder joint 160. This may prevent electrical and / or mechanical failure of the second solder joint 160.

[0052] like Figure 4C As shown in , the pin 320 can be inserted into the sleeve 130. The pin 320 and the sleeve 130 can be configured, for example, to form a press fit connection. According to an example, the pin 320 is inserted into the sleeve 130 after the seal 140 has been formed.

[0053] like Figure 4D , the frame 310 may be arranged over the die carrier 110. According to an example, only the sidewalls 311 of the frame 310 are arranged over the die carrier at this time, so that the encapsulant 330 may be filled into the cavity formed by the frame 310. As further described above, it is also possible that the frame 310 is not arranged over the upper side 111 of the die carrier 110, but over a substrate, wherein the die carrier 110 is attached to the substrate, and wherein the die carrier 110 is completely arranged in the cavity formed by the frame 310.

[0054] according to Figure 4DIn the example shown in , the encapsulant 330 can encapsulate the seal 140. However, this is not necessarily the case. According to another example, the encapsulant 330 only encapsulates the power semiconductor chip 120, but it does not contact the seal 140. According to another example, the encapsulant 330 only partially encapsulates the seal 140. According to yet another example, the power semiconductor device 300 does not include the encapsulant 330.

[0055] like Figure 4E As shown in , the cover 312 can be arranged on the side wall 311, thereby closing the cavity formed by the frame 310. Arranging the cover 312 on the side wall 311 may include inserting the pins 320 into the holes in the cover 312. However, it is also possible to insert the pins 320 into the sleeve 130 after the cover 312 has been put in place. According to an example, the power semiconductor device 300 may also include a circuit board arranged on the cover 312. When the cover 312 and / or the circuit board are nailed to the pins 320, the seal 140 can help prevent cracks from forming in the second solder joint 160.

[0056] Figure 4F An example of a power semiconductor device 300' is shown, which may be identical to the power semiconductor device 300, except that the power semiconductor device 300' comprises a substrate 340, wherein the die carrier 110 is attached to the substrate 340 by a third solder joint 350. Furthermore, a frame 310 is arranged over the substrate 340 such that the die carrier 110 is completely arranged within a cavity formed by the frame 310.

[0057] The third solder joint 350 may be formed, for example, after the first solder joint 150 and the second solder joint 160 have been formed. However, when the third solder joint 350 is formed, the solder material forming the first solder joint 150 and the second solder joint 160 may liquefy again. In this case, the seal 140 may help to keep the sleeve 130 and therefore the pin 320 in the correct position and orientation. To do so, the material of the seal 140 may have a temperature stability that is higher than the soldering temperature of the third solder joint 350. For example, the seal 140 may be stable at a temperature of about 300° C. or higher.

[0058] Figure 5 is a flow chart of a method 500 for manufacturing a power semiconductor device. The method 500 may be used, for example, to manufacture the power semiconductor devices 100, 300, and 300'.

[0059] Method 500 includes: at 501, an action of providing a die carrier; at 502, an action of soldering a power semiconductor chip to the die carrier to form a first solder joint; at 503, an action of soldering a sleeve for a pin to the die carrier to form a second solder joint; and at 504, an action of mechanically attaching the sleeve to the die carrier with a seal, the seal being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier and wherein the seal does not cover the power semiconductor chip.

[0060] According to an example of method 500, a seal may be provided after the first solder joint and the second solder joint have been formed. In addition, the act of mechanically attaching the sleeve may also include dispensing a seal around the lower end of the sleeve and subsequently curing the seal, for example, by heating the seal to a temperature of 200° C. or less or by applying UV light. Method 500 may also include an act of soldering the die carrier to the substrate, thereby forming a third solder joint.

[0061] Example

[0062] Below, a power semiconductor device and a method for manufacturing the power semiconductor device are further described using specific examples.

[0063] Example 1 is a power semiconductor device, comprising: a die carrier, a power semiconductor chip, the power semiconductor chip being coupled to the die carrier via a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier via a second solder joint, and a seal, the seal mechanically attaching the sleeve to the die carrier, the seal being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the seal does not cover the power semiconductor chip.

[0064] Example 2 is a power semiconductor device according to Example 1, wherein the sealing member covers the second solder joint.

[0065] Example 3 is a power semiconductor device according to Example 1 or Example 2, wherein the encapsulant includes a polymer.

[0066] Example 4 is a power semiconductor device according to one of the preceding examples, wherein the sealing member does not contact the power semiconductor chip.

[0067] Example 5 is a power semiconductor device according to one of the aforementioned examples, further comprising: an encapsulant encapsulating the power semiconductor chip, wherein the encapsulant has a different material composition from that of the sealant.

[0068] Example 6 is a power semiconductor device according to Example 5, wherein the sealant has a higher tensile strength than the encapsulant.

[0069] Example 7 is a power semiconductor device according to one of the preceding examples, wherein the die carrier is a DAB, a DCB, or an AMB.

[0070] Example 8 is the power semiconductor device of Example 7, wherein the sleeve is disposed on the upper conductive layer of the die carrier, and wherein the encapsulation is at least partially disposed on the upper conductive layer.

[0071] Example 9 is a power semiconductor device according to one of the preceding examples, further comprising: a substrate, wherein the die carrier is attached to the substrate by a third solder joint.

[0072] Example 10 is a power semiconductor device according to one of the preceding examples, further comprising: a plastic frame, wherein the power semiconductor chip is arranged in a cavity formed by the plastic frame, and wherein the pins are configured to extend out of the plastic frame.

[0073] Example 11 is a method for manufacturing a power semiconductor device, the method comprising: providing a die carrier, soldering a power semiconductor chip to the die carrier to form a first solder joint, soldering a sleeve for a pin to the die carrier to form a second solder joint, and mechanically attaching the sleeve to the die carrier with a seal, the seal being arranged at the lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the seal does not cover the power semiconductor chip.

[0074] Example 12 is the method of Example 11, wherein the seal is provided after the first solder joint and the second solder joint have been formed.

[0075] Example 13 is the method of example 11 or example 12, wherein mechanically attaching the sleeve includes dispensing a seal around a lower end of the sleeve, and curing the seal.

[0076] Example 14 is the method of Example 13, wherein curing includes heating the seal to a temperature of 200° C. or less, or wherein curing includes applying UV light.

[0077] Example 15 is the method of one of Examples 11 to 14, further comprising soldering the die carrier to the substrate to form a third solder joint.

[0078] Example 16 is an apparatus comprising means for performing the method according to one of Examples 11 to 15.

[0079] Although the present disclosure has been shown and described with respect to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components or structures (assemblies, devices, circuits, systems, etc.), unless otherwise indicated, the terms used to describe these components (including references to "modules") are intended to correspond to any component or structure (e.g., functionally equivalent) that performs the specified functions of the components, even if structurally not equivalent to the disclosed structures that perform the functions in the exemplary embodiments shown herein of the present disclosure.

Claims

1. A power semiconductor device, comprising: die carrier, a power semiconductor chip coupled to the die carrier via a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier via a second solder joint, a seal that mechanically attaches the sleeve to the die carrier, the seal being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the seal does not cover the power semiconductor chip, and An encapsulant encapsulates the power semiconductor chip, wherein the encapsulant has a different material composition from that of the sealing member.

2. The power semiconductor device according to claim 1, wherein: The seal covers the second solder joint.

3. The power semiconductor device according to claim 1 or claim 2, wherein: The seal comprises a polymer.

4. The power semiconductor device according to claim 1 or claim 2, wherein: The sealing member does not contact the power semiconductor chip.

5. The power semiconductor device according to claim 1, wherein: The seal has a higher tensile strength than the encapsulant.

6. The power semiconductor device according to claim 1 or claim 2, wherein: The die carrier is a DAB, DCB or AMB.

7. The power semiconductor device according to claim 6, wherein: The sleeve is arranged on an upper conductive layer of the die carrier, and wherein the encapsulation is also at least partially arranged on the upper conductive layer.

8. The power semiconductor device according to claim 1 or claim 2, further comprising: A substrate, wherein the die carrier is attached to the substrate via a third solder joint.

9. The power semiconductor device according to claim 1 or claim 2, further comprising: A plastic frame, wherein the power semiconductor chip is arranged in a cavity formed by the plastic frame, and wherein the pins are configured to extend out of the plastic frame.

10. A method for manufacturing a power semiconductor device, the method comprising: providing a die carrier, soldering a power semiconductor chip to the die carrier to form a first solder joint, soldering a sleeve for a lead to the die carrier to form a second solder joint, mechanically attaching the sleeve to the die carrier with a seal, the seal being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, wherein the seal does not cover the power semiconductor chip, and The power semiconductor chip is encapsulated with an encapsulant, wherein the encapsulant has a different material composition than the encapsulant.

11. The method according to claim 10, wherein: The seal is provided after the first solder joint and the second solder joint have been formed.

12. The method according to claim 10 or claim 11, wherein: Mechanically attaching the sleeve comprises: dispensing the seal about the lower end of the sleeve, and The seal is cured.

13. The method according to claim 12, wherein: The curing comprises heating the seal to a temperature of 200° C. or less, or wherein the curing comprises applying UV light.

14. The method according to claim 10 or claim 11, further comprising: The die carrier is soldered to a substrate, thereby forming a third solder joint.

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