Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes an insert, a die, and a sealant. Each die includes an active surface, a back surface, and side surfaces. The back surface is opposite the active surface. The side surfaces join the active surface to the back surface. The sealant includes a first material and laterally encapsulates the die. The die is electrically connected to the insert and is arranged side by side on the insert, wherein the respective back surfaces face away from the insert. At least one die includes an external corner. A rounded corner structure is formed at the external corner. The rounded corner structure includes a second material different from the first material. The external corner is formed by the back surface and a pair of adjacent side surfaces of at least one die. The side surfaces in the pair of adjacent side surfaces have a common first edge. Each side surface in the pair of adjacent side surfaces does not face other dies and has a second edge common with the back surface of at least one die.

Description

BACKGROUND OF THE INVENTION

[0001] Semiconductor devices and integrated circuits in various electronic devices for, e.g., mobile phones and other mobile electronic devices are typically fabricated on a single semiconductor wafer. The die of the wafer can be processed and packaged at the wafer level together with other semiconductor devices or dies, and various technologies and applications have been developed for wafer-level packaging. The integration of multiple semiconductor devices has become a challenge in the art. SUMMARY OF THE INVENTION

[0002] According to some embodiments of the present disclosure, a semiconductor package includes an insert, a semiconductor die, and a sealant. Each semiconductor die includes an active surface, a back surface, and side surfaces. The back surface is opposite the active surface. The side surfaces couple the active surface to the back surface. The sealant includes a first material and laterally wraps the semiconductor die. The semiconductor die is electrically connected to the insert and is disposed side-by-side on the insert, wherein the respective back surfaces face away from the insert. At least one of the semiconductor dies includes an external corner. A rounded corner structure is formed at the external corner of at least one of the semiconductor dies. The rounded corner structure includes a second material different from the first material. The external corner is formed by a pair of adjacent side surfaces of the back surface and the side surfaces of at least one of the semiconductor dies. The side surfaces in the pair of adjacent side surfaces have a common first edge. Each side surface in the pair of adjacent side surfaces does not face other semiconductor dies and has a second edge common with the back surface of at least one of the semiconductor dies.

[0003] According to some embodiments of the present disclosure, a semiconductor package includes a first semiconductor substrate, semiconductor dies, an underfill, a corner pad, and a sealant. The first semiconductor substrate has semiconductor vias formed therethrough. The semiconductor dies are disposed side-by-side on the first semiconductor substrate and are electrically connected to the semiconductor vias. The underfill is disposed between the first semiconductor substrate and the semiconductor dies. The corner pad is in physical contact with one of the semiconductor dies. The corner pad is disposed on the underfill corresponding to the external corner of one of the semiconductor dies. The corner pad includes a first material. The sealant includes a second material different from the first material. The sealant is disposed on the first semiconductor substrate. The sealant laterally wraps the semiconductor dies, the corner pad, and the underfill.

[0004] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor package includes at least the following steps. A semiconductor die is electrically connected to an insert via a connector. The connector is disposed at an active surface of the semiconductor die. A filler material is dispensed on the insert around the connector and in a gap between adjacent semiconductor dies. The filler material is cured to form an underfill. A rounded corner structure is formed on a backside surface of a first semiconductor die among the semiconductor dies. The backside surface is opposite to the active surface of the first semiconductor die. The rounded corner structure includes a first material. A sealant is formed to laterally encapsulate the semiconductor die and the underfill. The sealant includes a second material. The rounded corner structure contacts the sealant. The first material is different from the second material. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or reduced.

[0006] Figures 1A to 1K is a schematic cross-sectional view showing a manufacturing process of a semiconductor package according to some embodiments of the present disclosure.

[0007] Figure 1L is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2 is a schematic cross-sectional view showing a manufacturing process of a semiconductor package according to some embodiments of the present disclosure.

[0009] Figure 3 is a perspective view of a semiconductor package according to some embodiments of the present disclosure.

[0010] Figures 4A to 4D is a schematic top view of a semiconductor package according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] The following disclosure provides multiple different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first feature is formed in direct contact with the second feature, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, for ease of description, spatial relative terms may be used herein, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship of one element or feature shown in the drawings to another element or feature. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0013] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packages or 3D IC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of the 3D package or 3D IC, the use of probes and / or probe cards, etc. Verification testing may be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in combination with test methods having intermediate verification of known good dies to increase yield and reduce cost.

[0014] Figures 1A to 1L is a schematic cross-sectional view showing a manufacturing process of a semiconductor package 10 and a semiconductor device 15 according to some embodiments of the present disclosure. Referring to Figure 1A , an insert 100a is provided. In some embodiments, the insert 100a includes a semiconductor substrate 110a, a through semiconductor via (TSV) 120, and a contact pad 130. In some embodiments, the insert 100a includes a silicon wafer. In some embodiments, the semiconductor substrate 110a may be made of a semiconductor material (such as a semiconductor material of Group III-V of the periodic table). In some embodiments, the semiconductor substrate 110a includes: an elemental semiconductor material, such as silicon or germanium; a compound semiconductor material, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or an alloy semiconductor material, such as silicon germanium, silicon carbide germanium, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate 110a includes active components (such as transistors or the like) and optionally includes passive components (such as resistors, capacitors, inductors, or the like) formed therein.

[0015] In some embodiments, as Figure 1AAs shown, the TSV 120 is formed in the semiconductor substrate 110a, and the contact pad 130 is formed on the semiconductor substrate 110a corresponding to the TSV 120. In some embodiments, the contact pad 130 partially extends on the top surface 110t of the semiconductor substrate 110a. In some embodiments, the top surface 110t of the semiconductor substrate 110a on which the contact pad 130 is formed is regarded as the top surface 100t of the insert 100a. In some embodiments, the contact pad 130 is formed on the end 120a of the TSV 120, and the other end 120b of the same TSV 120 is embedded in the semiconductor substrate 110a. That is, the TSV 120 extends from the contact pad 130 into the semiconductor substrate 110a without reaching the bottom surface 110b of the semiconductor substrate 110a (temporarily, the bottom surface 100b of the insert 100a). It should be understood that Figure 1A the number of the TSVs 120 shown is only for illustration, and the present disclosure is not limited thereto. In some embodiments, the insert 100a may include fewer or more TSVs 120. In some embodiments, the materials of the TSV 120 and the contact pad 130 respectively include aluminum, titanium, copper, nickel, tungsten, and / or their alloys. The TSV 120 and the contact pad 130 can be formed by, for example, electroplating, deposition, and / or photolithography and etching.

[0016] Referring to Figure 1B , in some embodiments, the semiconductor dies 200A to 200D are disposed on the insert 100a. In the present disclosure, when it is not necessary to distinguish between the semiconductor dies 200A to 200D, the semiconductor dies 200A to 200D can be collectively referred to as the semiconductor die 200. In some embodiments, each semiconductor die 200 includes a semiconductor substrate 210, a contact pad 220, and a passivation layer 230. The contact pad 220 can be formed on the front surface 210a of the semiconductor substrate 210. The passivation layer 230 can cover the front surface 210a of the semiconductor substrate 210 and has a plurality of openings exposing at least a part of each contact pad 220. In some embodiments, the semiconductor die 200 may further include a plurality of contact posts 240 filling the openings of the passivation layer 230 and electrically connected to the contact pads 220, and a protective layer 250 surrounding the contact posts 240.

[0017] The semiconductor substrate 210 is made of a semiconductor material similar to the semiconductor material discussed for the semiconductor substrate 110a of the previous reference insert 100a. In some embodiments, the semiconductor substrate 210 includes active components (e.g., transistors or the like) and optionally includes passive components (e.g., resistors, capacitors, inductors or the like) formed therein. In certain embodiments, the contact pad 220 includes an aluminum pad, a copper pad or other suitable metal pad. In some embodiments, the passivation layer 230 can be a single-layer structure or a multi-layer structure, including a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a dielectric layer formed of other suitable dielectric materials or a combination thereof. In some embodiments, the material of the contact post 240 includes copper, a copper alloy or other conductive materials, and can be formed by deposition, plating or other suitable techniques. In some embodiments, any of the semiconductor dies 200 disposed on the insert 100a can exhibit characteristics similar to the semiconductor dies just discussed. Each semiconductor die 200 can be independent or include a logic die, such as a central processing unit (CPU) die, a graphic processing unit (GPU) die, a microcontrol unit (MCU) die, an input-output (I / O) die, a baseband (BB) die or an application processor (AP) die. In some embodiments, one or more semiconductor dies 200 can be memory dies. The present disclosure is not limited by the type or number of semiconductor dies 200 disposed on the insert 100a.

[0018] In some embodiments, the semiconductor die 200 is bonded to the insert 100a via a connector 300. In some embodiments, the connector 300 is a microbump mounted on the contact post 240 and sandwiched between the contact post 240 and the contact pad 130 or the TSV 120 (in the case where the contact pad 130 is not formed in the insert 100a). According to some embodiments, the semiconductor die 200 is disposed such that the active surface 200a (the surface exposing the contact post 240 or the contact pad 220 when the contact post 240 is not included) faces the insert 100a. The back surface 200b opposite to the active surface 200a can be disposed further away from the insert 100a. In some embodiments, the back surface 210b of the semiconductor substrate 210 constitutes the back surface 200b of the corresponding semiconductor die 200. The semiconductor dies 200A to 200D can additionally have side surfaces 200s that join the back surface 210b to the opposing front surface 210a.

[0019] In some embodiments, semiconductor dies 200A to 200D are disposed on an insert in an array configuration. For example, semiconductor dies 200A to 200D may be arranged in a row, with semiconductor die 200A and semiconductor die 200D at the head and tail of the row, and semiconductor dies 200B and 200C disposed in the middle. For example, semiconductor die 200B may be disposed between semiconductor die 200A and semiconductor die 200C, and semiconductor die 200C may be disposed between semiconductor die 200B and semiconductor die 200D. In some embodiments, semiconductor dies 200A and 200D include at least two side surfaces 200s that share an edge and do not face other semiconductor dies 200A to 200D. Thus, semiconductor dies 200A and 200D may be referred to as external semiconductor dies. On the other hand, semiconductor dies 200B and 200C do not include side surfaces 200s that share an edge and do not face other semiconductor dies 200A to 200D. Thus, semiconductor dies 200B and 200C may be referred to as internal semiconductor dies. In some embodiments, semiconductor dies 200A to 200D may have an elongated shape and may be disposed on insert 100a parallel to each other. In some embodiments, semiconductor dies 200A to 200D may each exhibit a different shape. In some embodiments, the facing side surfaces 200s of semiconductor dies 200A to 200D may form a minute gap G between adjacent semiconductor dies 200A to 200D in the array. For example, Figure 1B The gap G between the facing side surfaces 200s of semiconductor dies 200B and 200C is indicated. A similar gap G is also formed between semiconductor die 200A and semiconductor die 200B and between semiconductor die 200C and semiconductor die 200D. In some embodiments, the width of gap G is regarded as the distance between the side surfaces 200s of the semiconductor dies (e.g., semiconductor dies 200B and 200C) that form gap G. The side surfaces 200s are regarded as the surfaces that join the active surfaces 200a of semiconductor dies 200A to 200D to the corresponding backside surfaces 200b.

[0020] In some embodiments, referring to Figure 1C and Figure 1D, an underfill 400 can be disposed between semiconductor die 200A to semiconductor die 200D and the insert 100a to protect the connection member 300 from thermal stress or physical stress and to ensure electrical connection between semiconductor die 200A to semiconductor die 200D and the insert 100a. In some embodiments, the underfill 400 is formed by capillary underfill filling (CUF). A dispenser (not shown in the figure) can apply a filling material 400a along the perimeter of semiconductor die 200A to semiconductor die 200D. In some embodiments, heating and / or reduced pressure can be applied to cause the filling material 400a to penetrate by capillary action into the void defined by the connection member 300 between semiconductor die 200A to semiconductor die 200D and the insert 100a. In some embodiments, the filling material 400a further penetrates into the gap G between adjacent semiconductor die 200A to semiconductor die 200D. The extent to which the filling material 400a fills the gap G can depend on the viscosity of the filling material 400a, as well as the size and shape of the gap G, and the conditions employed in the dispensing step. In some embodiments, a curing process (schematically represented by the curved arrow in Figure 1C is performed to consolidate the filling material 400a and form the underfill 400. In some embodiments, as shown in Figure 1D , a single underfill 400 can extend under semiconductor die 200A to semiconductor die 200D depending on the spacing and relative orientation of semiconductor die 200A to semiconductor die 200D above the insert 100a. In some alternative embodiments, multiple underfill portions (not shown in the figure) are formed, each portion securing the connection member 300 of semiconductor die 200A to semiconductor die 200D. In some embodiments, the filling material 400a includes an organic polymer. In some embodiments, the filling material 400a includes an epoxy resin, a phenol resin, a polyolefin, an acrylic resin, a polyimide, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymeric dielectric material. In some embodiments, the viscosity of the filling material 400a can be in the range between 0.1 (Pa s) and 10 (Pa s) at a temperature of 150°C. In some embodiments, the curing temperature of the filling material 400a can be in the range between 100°C and 400°C. In some embodiments, the filling material 400a can be a polyimide.

[0021] In some embodiments, referring to Figure 1E, a corner padding material 500a can be disposed on the outer corners OC of the external semiconductor die 200A and the external semiconductor die 200D. In some embodiments, the corner padding material 500a extends over a portion of the backside surface 210b of the semiconductor substrate 210 adjacent to the outer corner OC, and extends along the side surface 200s that forms the outer corner OC with the backside surface 210b. In some embodiments, the corner padding material 500a is disposed on the outer corners OC of the external semiconductor die 200A and the external semiconductor die 200D. The outer corner OC is formed by adjacent side surfaces 200s that share an edge and do not face other semiconductor dies 200A to 200D of the array. For example, in Figure 1E 's cross-sectional view, the external semiconductor dies are the semiconductor die 200A and the semiconductor die 200D because each of the semiconductor die 200A and the semiconductor die 200D includes at least a pair of adjacent side surfaces 200s that do not face other semiconductor dies 200A to 200D of the array. For example, the semiconductor die 200A has at least a pair of adjacent side surfaces 200s that do not face other semiconductor dies 200B to 200D of the array. Similarly, the semiconductor die 200D has at least a pair of adjacent side surfaces 200s that do not face other semiconductor dies 200A to 200C of the array. Taking the semiconductor die 200A as an example, the outer corner OC is formed by the backside surface 210b of the semiconductor substrate 210, by the Figure 1E 's left side surface 200s of the semiconductor die 200A in Figure 1E and by the Figure 1E 's side surface 200s facing the viewing point in Figure 1E . The second outer corner of the semiconductor die 200A ( Figure 1Eis not shown) is formed. In some embodiments, a dispenser (not shown in the figures) can apply the corner pad material 500a onto the outer corners OC of the external semiconductor die 200A and the external semiconductor die 200D. In some embodiments, the corner pad material 500a can be applied by a screen printing process or other suitable process. In some embodiments, the corner pad material 500a can have a spherical shape with a rounded outer contour. In some embodiments, the corner pad material 500a comprises an organic polymer. In some embodiments, the corner pad material 500a comprises an epoxy resin, a phenol resin, a polyolefin, an acrylic resin, a polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymeric dielectric material. In some embodiments, the viscosity of the corner pad material 500a can be in the range of 0.1 (Pa s) to 10 (Pa s) at a temperature of 150 °C. In some embodiments, the corner pad material 500a can be selected to have a higher viscosity than the fill material 400a ( Figure 1C shown). In some embodiments, the higher viscosity of the corner pad material 500a allows the corner pad material 500a to maintain its shape until a subsequent curing process is performed. In some embodiments, refer to Figure 1E and Figure 1F , a curing process (schematically represented by the arrow in Figure 1E ) is performed to consolidate the corner pad material 500a and form a cured corner pad material 500b. In some embodiments, the curing temperature of the corner pad material 500a can be in the range between 100 °C and 400 °C. In some embodiments, the corner pad material 500a is selected to have a higher curing temperature than the fill material 400a.

[0022] In some embodiments, refer to Figure 1F, a sealing material 600a can be disposed on the insert 100a to seal the semiconductor die 200A to the semiconductor die 200D, the underfill 400, and the cured corner pad material 500b. In some embodiments, the sealing material 600a includes a molding compound, a molding underfill, a resin (such as an epoxy resin), or the like. In some embodiments, the sealing material 600a includes an epoxy resin. Additionally, the sealing material 600a may include a filler 610 doped therein. The filler 610 may be spherical or angular particles, may have a nanoscale size, and may be made of silica, metal oxide, glass fiber, or the like. In some embodiments, the filler 610 may be included in the sealing material 600a, while the cured corner pad material 500b and the underfill 400 may not include the filler. In some embodiments, the sealing material 600a is formed by an over-molding process. In some embodiments, the sealing material 600a is formed by a compression molding process. In some embodiments, the sealing material 600a completely covers the semiconductor die 200A to the semiconductor die 200D, the underfill 400, and the cured corner pad material 500b. Refer to Figure 1F and Figure 1G , in some embodiments, a portion of the sealing material 600a is removed by a planarization process until the backside surfaces 200b of the semiconductor die 200A to the semiconductor die 200D are exposed, thereby forming a seal body 600. In some embodiments, the planarization of the sealing material 600a includes performing a mechanical grinding process and / or a chemical mechanical polishing (CMP) process. In some embodiments, a portion of the cured corner pad material 500b is also removed during the planarization process to form the corner pad 500. That is, the corner pad 500 may have a truncated spherical shape. After planarization, the backside surfaces 200b of the semiconductor die 200A to the semiconductor die 200D may be substantially coplanar with the top surface 600t of the seal body 600 and substantially coplanar with the top surface 500t of the corner pad 500.

[0023] Refer to Figure 1H , in some embodiments, Figure 1G The structure of can be flipped over above the support frame SF to expose the bottom surface 110b of the insert 100a for further processing. Refer to Figure 1H and Figure 1I, in some embodiments, the semiconductor substrate 110a is thinned from the sides of the bottom surface 100b to form the semiconductor substrate 110. In some embodiments, a portion of the semiconductor substrate 110a is removed until the TSV 120 is exposed. In some embodiments, the end 120b of the TSV 120 may be substantially flush with the thinned semiconductor substrate 110. In some alternative embodiments (not shown in the figures), after the semiconductor substrate 110a is thinned, the TSV 120 may protrude relative to the bottom surface 110b of the semiconductor substrate 110. That is, the end 120b of the TSV 120 may be located at a higher level than the bottom surface 110b of the semiconductor substrate 110. In some embodiments, the portion of the semiconductor substrate 110a may be removed by an etching process. The etching process includes, for example, an isotropic etching process and / or an anisotropic etching process. For example, the semiconductor substrate 110a may be thinned by a wet etching process, a dry etching process, or a combination thereof. In some embodiments, a portion of the TSV 120 may also be removed during the thinning of the semiconductor substrate 110a.

[0024] Reference Figure 1J, in some embodiments, the redistribution structure 700 is formed on the bottom surface 100b of the insert 100. In some embodiments, the redistribution structure 700 includes a dielectric layer 702, redistribution conductive layers 704, and a plurality of under-bump metals 706. For simplicity, the dielectric layer 702 is shown as a single dielectric layer, and the redistribution conductive layers 704 are shown as being embedded in the dielectric layer 702. Nevertheless, from a manufacturing process perspective, the dielectric layer 702 is composed of at least two dielectric layers. The redistribution conductive layers 704 can be composed of a plurality of redistribution conductive patterns distributed in one or more metallization tiers. The redistribution conductive patterns of the redistribution conductive layers 704 are sandwiched between two adjacent dielectric layers. Some of the redistribution conductive patterns can extend vertically through the dielectric layer 702 to establish electrical connections between different metallization tiers of the redistribution structure 700. In addition, some of the redistribution conductive patterns extend through the dielectric layer 702 to reach the TSV 120 and establish an electrical connection with the TSV 120. That is, the (bottommost) dielectric layer 702 can include an opening exposing the end 120b of the TSV 120, and the redistribution conductive layer 704 can extend within the opening of the (bottommost) dielectric layer 702 to contact the TSV 120. In some embodiments, the (outermost) dielectric layer 702 can be patterned to expose the underlying redistribution conductive layer 704. The under-bump metals 706 can be conformally formed in the opening of the (outermost) dielectric layer 702 exposing the redistribution conductive layer 704 as appropriate. In some embodiments, the under-bump metals 706 further extend above a portion of the exposed surface of the (outermost) dielectric layer 702. In some embodiments, the under-bump metals 706 include a plurality of stacked layers. For example, the under-bump metals 706 can include one or more metal layers stacked on a seed layer.

[0025] In some embodiments, the materials of the redistribution conductive layers 704 and the under-bump metals 706 include aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The redistribution conductive layers 704 and the under-bump metals 706 can be formed by, for example, electroplating, deposition, and / or photolithography and etching. In some embodiments, the material of the dielectric layer 702 includes polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymeric dielectric material. The dielectric layer 702 can be formed, for example, by suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. In some embodiments, the redistribution structure 700 can be manufactured by a semi-additive process, a damascene process, a dual damascene process, or a similar process.

[0026] It should be noted thatFigure 1J The number of dielectric layers 702 shown, the number of metallization levels of the redistribution conductive layers 704, and the number of under-bump metals 706 are for illustrative purposes only, and the present disclosure is not limited thereto. In some alternative embodiments, fewer or more dielectric layers 702, fewer or more metallization levels of the redistribution conductive layers 704, and fewer or more under-bump metals 706 may be formed depending on the circuit design. When more metallization levels of the redistribution conductive layers 704 and more layers of dielectric layers 702 are required, the metallization levels of the redistribution conductive layers 704 are still stacked alternately with the respective layers of the dielectric layers 702.

[0027] In some embodiments, the conductive terminals 800 are formed on the redistribution structure 700. In some embodiments, the conductive terminals 800 are formed on the under-bump metals 706 and are connected to the TSVs 120 and the semiconductor dies 200A to 200D via the redistribution conductive layers 704. In some embodiments, the conductive terminals 800 are attached to the under-bump metals 706 by solder. In some embodiments, the conductive terminals 800 are controlled collapse chip connection (C4) bumps. In some embodiments, the conductive terminals 800 comprise a conductive material having a low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi, or an alloy thereof. In some embodiments, the redistribution structure 700 is optionally present and may be omitted, and the conductive terminals 800 may be formed directly on the TSVs 120.

[0028] In some embodiments, after removing the support frame SF, the semiconductor package 10 is obtained. In some embodiments, Figures 1A to 1K the steps shown may be referred to as “chip on wafer (CoW) level packaging”. As Figure 1K shown, the semiconductor dies 200A to 200D are disposed on the insert 100. In other words, a plurality of semiconductor dies 200A to 200D are integrated into a single semiconductor package 10. Thus, the semiconductor package 10 may be referred to as a “system on integrated circuit (SOIC) package”. In some embodiments, through Figures 1A to 1K the adaptation steps presented, heterogeneous or homogeneous semiconductor components can be effectively integrated into a single semiconductor package at a lower cost. For example, known good dies can be effectively integrated with a semiconductor wafer or another semiconductor die at a low cost.

[0029] In some embodiments, semiconductor package 10 includes semiconductor dies 200A to 200D connected to insert 100 via connector 300. Underfill 400 is disposed between semiconductor dies 200A to 200D and insert 100 to protect connector 300 from thermal stress and physical stress. Semiconductor dies 200A to 200D may be disposed on insert 100 in an array configuration. Corner pads 500 may be disposed at outer corners OC of outer semiconductor die 200A and outer semiconductor die 200D. In some embodiments, corner pads 500 partially cover side surfaces 200s of outer semiconductor die 200A and outer semiconductor die 200D that form outer corner OC. In some embodiments, underfill 400 may also partially cover the same side surfaces 200s covered by corner pads 500. In some embodiments, underfill 400 is at least partially inserted between corner pads 500 and side surfaces 200s. That is, underfill 400 may have an inclined surface 400s extending from side surfaces 200s to insert 100, and corner pads 500 may be disposed on an initial section (closer to semiconductor die 200A or semiconductor die 200D) of inclined surface 400s. Corner pads 500 also directly contact underfill 400 and encapsulant 600. In some embodiments, corner pads 500 have a truncated spherical shape and form a rounded corner structure RCS for corresponding semiconductor die 200A and semiconductor die 200D (outer semiconductor dies among semiconductor dies 200A to 200D). In some embodiments, rounded corner structure RCS alleviates mechanical corner stress that may occur at an interface between semiconductor substrates 210 of outer semiconductor die 200A and outer semiconductor die 200D and encapsulant 600. In some embodiments, by providing rounded corner structure RCS at outer corners OC of outer semiconductor die 200A and outer semiconductor die 200D, mechanical stress experienced by encapsulant 600 corresponding to outer corner OC can be reduced, and occurrence of cracks can be reduced. That is, by providing rounded corner structure RCS of outer semiconductor die 200A and outer semiconductor die 200D, mechanical stability of semiconductor package 10 can be enhanced, and reliability and lifespan of semiconductor package 10 can be increased. In some embodiments, even when semiconductor package 10 is a large-scale semiconductor package, mechanical corner stress can be effectively reduced by providing rounded corner structure RCS (e.g., by including corner pads 500).

[0030] Reference Figure 1L, in some embodiments, the semiconductor package 10 can be integrated into a larger semiconductor device 15. For example, the semiconductor package 10 can be connected to a circuit substrate 900 via conductive terminals 800. In some embodiments, the conductive terminals 800 establish electrical contact with contact pads 902 formed on the surface of the circuit substrate 900. In some embodiments, the circuit substrate 900 can be a mother board, a printed circuit board, or the like. In some embodiments, the semiconductor device 15 can be referred to as a Chip on Wafer on Substrate (CoWoS) semiconductor device. In some embodiments, an underfill 1000 can be disposed on the circuit substrate 900 to protect the conductive terminals 800 from thermal stress or mechanical stress. In some embodiments, the material of the underfill 1000 can be different from the material of the underfill 400 included in the semiconductor package 10.

[0031] Figure 2 is a schematic cross-sectional view of a structure generated during a method of manufacturing the semiconductor package 10 according to some alternative embodiments. Figure 2 The structure of can be obtained by the following according to Figure 1B the structure shown in: Without performing an intermediate curing step, a filler material 400a is provided on the insert 100a and corner pad materials 500a are provided on the semiconductor die 200A and the semiconductor die 200D. That is, the filler material 400a can be dispensed on the insert 100a similarly to the operation described with respect to Figure 1C and the corner pad materials 500a can be placed on the semiconductor die 200A, the semiconductor die 200D, and the filler material 400a before the filler material 400a cures. That is, the corner pad materials 500a and the filler material 400a can be cured together during the same curing step. In some embodiments, a suitable material combination can be selected to cure the filler material 400a and the corner pad materials 500a together. For example, a first polyimide can be selected for the filler material 400a and a second polyimide can be selected for the corner pad materials 500a. In some embodiments, at 150 °C, the viscosity of the second polyimide can be higher than the viscosity of the first polyimide. In this case, the filler material 400a and the corner pad materials 500a can be cured together, for example, at a curing temperature included in the range of 100 °C to 400 °C for a time included in the range of 2 hours to 12 hours. After curing, the manufacturing process of the semiconductor package 10 can follow the steps described above with reference to Figures 1F to 1K described.

[0032] Figure 3 is a schematic perspective view of the semiconductor package 10 according to some embodiments of the present disclosure. Figure 4Ais a schematic top view of a semiconductor package 10 in accordance with some embodiments of the present disclosure. Figures 1A to 1K The cross-sectional view of Figure 4A is taken along line I-I shown in Figure 3 and Figure 4A The views of Figure 3 show: an insert 100; semiconductor dies 200A to 200D, which are arranged in a linear array and are laterally surrounded by a sealing body 600; underfill 400; corner pads 500; and conductive terminals 800. In Figure 3 and Figure 4A For clarity of illustration, the surfaces and components that will be covered by the sealing body 600 are shown, but the material of the sealing body 600 is not limited to being transparent. Similarly, for clarity of illustration, Figure 3 and Figure 4A the filler 610 ( Figure 1F shown in Figure 3 and Figure 4A that may be included in the sealing body 600 is omitted. As shown in the views of Figure 3 and Figure 4A the outer semiconductor dies 200A and 200D of the linear array are provided with a rounded corner structure RCS at the outer corner OC. Referring to the semiconductor die 200D, the outer corner OC is a corner formed by a pair of surfaces that share an edge therebetween and share an edge with the backside surface 200b and do not face the adjacent semiconductor die 200C. For example, the outer corner OC is a corner formed by the side surface 200Ds2, the side surface 200Ds3 (which shares the edge 200De3 with the side surface 200Ds2), and the backside surface 200b. As Figure 3As shown, side surface 200Ds2 and dorsal surface 200b share edge 200De1, and side surface 200Ds3 and dorsal surface 200b share edge 200De2. Another external corner OC of semiconductor die 200D is a corner defined by dorsal surface 200b and side surfaces 200Ds1 and 200Ds2. Dorsal surface 200b also shares an edge with side surface 200Ds4. However, side surface 200Ds4 faces semiconductor die 200C and thus side surface 200Ds4 is not considered to form an external corner. For the same reason, since side surfaces 200Cs4 and 200Cs2 of semiconductor die 200C face semiconductor die 200B and semiconductor die 200D respectively, semiconductor die 200C does not form any external corners and is not considered an external semiconductor die. The same reason applies to semiconductor die 200B, while semiconductor die 200A has two external corners OC on which corner pads 500 are provided. However, the present disclosure is not limited thereto. In some alternative embodiments, corner pads 500 may be formed on any corner formed by dorsal surface 200b and any pair of side surfaces. For example, when the distance between adjacent semiconductor dies 200 is greater than 10 micrometers, additional corner pads 500 may be formed on internal corners. In some embodiments, the distance between adjacent semiconductor dies 200 may range from 10 micrometers to 500 micrometers.

[0033] Figure 4B is a schematic top view of semiconductor package 20 according to some embodiments of the present disclosure. Figure 4B of semiconductor package 20 and Figure 4A the difference between semiconductor package 10 is the shape of corner pad 502. That is, in Figure 4B of semiconductor package 20, the corner pad has a shape extending along the direction of the edge between each of surface 200As1 or surface 200As2 and dorsal surface 200b (e.g., Figure 3 as shown). That is, when viewed from a top-down perspective, the contour of corner pad 502 may be different from a circular sector (as shown for pad 500 in the top view of Figure 4A ). However, since corner pad 502 does not present a sharp corner, corner pad 502 can still provide a rounded corner structure RCS at the external corners OC of external semiconductor die 200A and external semiconductor die 200D.

[0034] Figure 4C is a schematic top view of semiconductor package 30 according to some embodiments of the present disclosure. Figure 4C of semiconductor package 30 and Figure 4AThe difference between the semiconductor package 10 and the semiconductor package 30 lies in the number of semiconductor dies 200A to 200H arranged in an array configuration. In the semiconductor package 30, eight semiconductor dies 200A to 200H are arranged in a two-row by four-column array. For example, the semiconductor die 200A faces the semiconductor die 200B in the same row and the semiconductor die 200E in the same column. In the semiconductor die array of the semiconductor package 30, the semiconductor die 200A, the semiconductor die 200E, the semiconductor die 200D, and the semiconductor die 200H are external semiconductor dies because each semiconductor die has a pair of adjacent side surfaces (such as the side surfaces 200Ds1 and 200Ds2 of the semiconductor die 200D), and the pair of adjacent side surfaces do not face other semiconductor dies in the array (for example, for the semiconductor die 200D, they do not face the semiconductor dies 200A to 200C and the semiconductor dies 200E to 200H). Each external semiconductor die 200A, external semiconductor die 200E, external semiconductor die 200D, and external semiconductor die 200H has an external corner OC on which a corner pad 500 is formed. Taking the semiconductor die 200D as an example, the semiconductor die 200D includes a single external corner OC formed by the back surface 200b (as shown in, for example, Figure 3 ). In the semiconductor package 30, the surface 200Ds3 (which also forms an external corner OC in the semiconductor package 10 and has a corner pad 500 formed thereon, see Figure 4A ) faces the semiconductor die 200H and thus does not form an external corner.

[0035] Figure 4D is a schematic top view of a semiconductor package 40 according to some embodiments of the present disclosure. Figure 4D The difference between the semiconductor package 40 and the Figure 4A semiconductor package 10 is that a rounded corner structure RCS is provided at the external corners OC of the external semiconductor dies 200A and 200D, and the corner pad 500 is not formed (as shown in Figure 4A ). In fact, during the manufacture of the semiconductor package 40, for example, via a laser cutting step, the external corners OC are smooth. In some embodiments, by smoothing the external corners OC of the external semiconductor dies 200A and 200D, the mechanical stress at the interface between the back surface 200b (as shown in, for example, Figure 1B ) and the encapsulant 600 can be reduced, thereby reducing or preventing the occurrence of cracks in the encapsulant 600. As shown in Figure 4DAs shown, in some embodiments, the external corner OC is smooth, while other corners formed by the dorsal surface 200b may be sharp. For example, considering the semiconductor die 200A, the dorsal surface 200b may form an external corner OC with the smooth adjacent side surfaces 200As1, side surface 200As2, and the pair of side surfaces 200As3, and may form a corner (sharp corner SC) by combining the non-smooth side surface 200As1 or side surface 200As3 with the side surface 200As4. In some embodiments, before forming the encapsulant 600 and omitting the formation of the corner pad 500, the external corner OC may be smoothed on the Figure 1D structure, for example, via laser cutting. However, the present disclosure is not limited thereto. In some alternative embodiments, the corner pad 500 may also be formed on the external corner OC after the external corner OC has been smoothed.

[0036] According to some embodiments of the present disclosure, a semiconductor package includes an insert, a semiconductor die, and an encapsulant. Each semiconductor die includes an active surface, a dorsal surface, and side surfaces. The dorsal surface is opposite to the active surface. The side surfaces join the active surface to the dorsal surface. The encapsulant includes a first material and laterally wraps the semiconductor die. The semiconductor die is electrically connected to the insert and arranged side by side on the insert, wherein the corresponding dorsal surfaces face away from the insert. At least one of the semiconductor dies includes an external corner. A rounded corner structure is formed at the external corner of at least one semiconductor die. The rounded corner structure includes a second material different from the first material. The external corner is formed by a pair of adjacent side surfaces among the dorsal surface and the side surfaces of at least one semiconductor die. The side surfaces in the pair of adjacent side surfaces have a common first edge. Each side surface in the pair of adjacent side surfaces does not face other semiconductor dies and has a second edge common with the dorsal surface of at least one semiconductor die.

[0037] In some embodiments, a corner pad for forming the rounded corner structure is further included. In some embodiments, an underfill is further included, and the underfill is arranged to contact the pair of adjacent side surfaces of the at least one semiconductor die and the corner pad. In some embodiments, the underfill is at least partially arranged between the corner pad and the pair of adjacent side surfaces of the at least one semiconductor die. In some embodiments, the dorsal surfaces of the plurality of semiconductor dies and the top surface of the corner pad are coplanar with the top surface of the encapsulant. In some embodiments, the at least one semiconductor die includes a semiconductor substrate, and the smooth corner of the semiconductor substrate forms the rounded corner structure. In some embodiments, the dorsal surface of the at least one semiconductor die forms a sharp corner and one or more smooth corners.

[0038] According to some embodiments of the present disclosure, a semiconductor package includes a first semiconductor substrate, semiconductor dies, underfill, corner pads, and a sealant. The first semiconductor substrate has semiconductor vias formed therethrough. The semiconductor dies are arranged side by side on the first semiconductor substrate and electrically connected to the semiconductor vias. The underfill is disposed between the first semiconductor substrate and the semiconductor dies. The corner pad is in physical contact with one of the semiconductor dies. The corner pad is disposed on the underfill corresponding to an outer corner of one of the semiconductor dies. The corner pad includes a first material. The sealant includes a second material different from the first material. The sealant is disposed on the first semiconductor substrate. The sealant laterally encapsulates the semiconductor dies, the corner pads, and the underfill.

[0039] In some embodiments, the underfill includes a third material, and the first material, the second material, and the third material are different from each other. In some embodiments, the first material includes a first polyimide, the second material includes an epoxy resin, and the third material includes a second polyimide. In some embodiments, the underfill includes an inclined surface extending from a side surface of one of the semiconductor dies to the first semiconductor substrate, the side surface of the one semiconductor die sharing an edge with a back surface of the one semiconductor die, and the corner pad is disposed on the inclined surface. In some embodiments, a connector is further included, the connector is disposed on an active surface of the one semiconductor die opposite to the back surface of the one semiconductor die to establish an electrical connection between the one semiconductor die and the semiconductor via, wherein the plurality of semiconductor dies are arranged in an array configuration on the first semiconductor substrate, the one semiconductor die includes a pair of adjacent side surfaces, the side surface in the pair of adjacent side surfaces has a common first edge, each side surface in the pair of adjacent side surfaces connects the back surface of the one semiconductor die to the active surface of the one semiconductor die and does not face other semiconductor dies in the array; and the outer corner of the back surface of the one semiconductor die is formed by the back surface of the one semiconductor die and the pair of adjacent side surfaces of the one semiconductor die. In some embodiments, the back surface of the one semiconductor die forms a second outer corner, and a second corner pad is formed on the second outer corner of the one semiconductor die. In some embodiments, a top surface of the corner pad is substantially coplanar with the back surface of the one semiconductor die.

[0040] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor package includes at least the following steps. A semiconductor die is electrically connected to an insert via a connecting member. The connecting member is disposed at an active surface of the semiconductor die. A filling material is dispensed on the insert around the connecting member and in a gap between adjacent semiconductor dies. The filling material is cured to form an underfill. A rounded corner structure is formed on a backside surface of a first semiconductor die among the semiconductor dies. The backside surface is opposite to the active surface of the first semiconductor die. The rounded corner structure includes a first material. A sealing body is formed to laterally encapsulate the semiconductor die and the underfill. The sealing body includes a second material. The rounded corner structure contacts the sealing body. The first material is different from the second material.

[0041] In some embodiments, the first material includes a semiconductor material; and forming the rounded corner structure includes smoothing an outer corner of the first semiconductor die via laser cutting, the outer corner of the first semiconductor die being formed by the backside surface of the first semiconductor die and a pair of adjacent side surfaces of the first semiconductor die, the side surfaces in the pair of adjacent side surfaces having a common first edge, and each side surface in the pair of adjacent side surfaces not facing other semiconductor dies and having a second edge common with the backside surface of the first semiconductor die. In some embodiments, forming the rounded corner structure includes forming a corner pad on an outer corner of the first semiconductor die, the outer corner of the first semiconductor die being formed by the backside surface of the first semiconductor die and a pair of adjacent side surfaces of the first semiconductor die, the side surfaces in the pair of adjacent side surfaces having a common first edge, and each side surface in the pair of adjacent side surfaces not facing other semiconductor dies and having a second edge common with the backside surface of the first semiconductor die. In some embodiments, forming the corner pad includes: dispensing the first material on the first semiconductor die; and curing the first material, wherein the viscosity of the first material is higher than the viscosity of the filling material. In some embodiments, the filling material is dispensed to at least partially cover the pair of adjacent side surfaces of the first semiconductor die, and the first material is dispensed such that at least a portion of the underfill is inserted between the corner pad and the pair of adjacent side surfaces of the first semiconductor die. In some embodiments, forming the sealing body includes: forming a sealing material on the insert to cover the plurality of semiconductor dies and the cured first material; and removing a portion of the cured first material and a portion of the sealing material.

[0042] The foregoing description of the features of the several embodiments enables those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages as those introduced herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: An insert; A plurality of semiconductor dies, each semiconductor die comprising: An active surface; A back surface, opposite to the active surface; and Side surfaces, joining the active surface to the back surface; and A sealant body, containing a first material and laterally encapsulating the plurality of semiconductor dies, Wherein the plurality of semiconductor dies are electrically connected to the insert and arranged side by side on the insert, with the respective back surfaces facing away from the insert, At least one semiconductor die of the plurality of semiconductor dies includes an external corner, A rounded corner structure is disposed at the external corner of the at least one semiconductor die, the rounded corner structure being in direct contact with the sealant body, and at least one semiconductor die of the plurality of semiconductor dies is spaced apart from the sealant body by the rounded corner structure, The rounded corner structure includes a second material different from the first material; and The external corner is formed by the back surface of the at least one semiconductor die and a pair of adjacent side surfaces of the at least one semiconductor die, the side surfaces in the pair of adjacent side surfaces have a common first edge, and each side surface in the pair of adjacent side surfaces does not face other semiconductor dies and has a second edge common with the back surface of the at least one semiconductor die, and the rounded corner structure partially covers each side surface in the pair of adjacent side surfaces.

2. The semiconductor package according to claim 1, further comprising a corner pad forming the rounded corner structure.

3. The semiconductor package according to claim 2, further comprising an underfill, the underfill being disposed in contact with the pair of adjacent side surfaces of the at least one semiconductor die and the corner pad.

4. The semiconductor package according to claim 3, wherein the underfill is at least partially disposed between the corner pad and the pair of adjacent side surfaces of the at least one semiconductor die.

5. The semiconductor package according to claim 2, wherein the back surfaces of the plurality of semiconductor dies and the top surface of the corner pad are substantially coplanar with the top surface of the sealant body.

6. The semiconductor package according to claim 3, wherein the back surfaces of the plurality of semiconductor dies are spaced apart from the rounded corner structure by the underfill.

7. The semiconductor package according to claim 1, wherein the back surfaces of the plurality of semiconductor dies are spaced apart from the rounded corner structure.

8. A semiconductor package, comprising: A first semiconductor substrate having semiconductor vias formed therethrough; A plurality of semiconductor dies, arranged side by side on the first semiconductor substrate and electrically connected to the semiconductor vias; An underfill, disposed between the first semiconductor substrate and the plurality of semiconductor dies; A corner pad is in physical contact with one of the plurality of semiconductor die. The corner pad is disposed on the underfill corresponding to an outer corner of the backside surface of the one semiconductor die and includes a first material. Wherein a top surface of the corner pad is substantially coplanar with the backside surface of the one semiconductor die, and the top surface of the corner pad and the backside surface of the one semiconductor die face away from the first semiconductor substrate; And A sealant, including a second material different from the first material, is disposed on the first semiconductor substrate and laterally encapsulates the plurality of semiconductor die, the corner pad, and the underfill. Wherein the outer corner of the backside surface of the one semiconductor die is separated from the sealant by the corner pad, Wherein the plurality of semiconductor die are disposed on the first semiconductor substrate in an array configuration, The one semiconductor die includes a pair of adjacent side surfaces, The side surfaces in the pair of adjacent side surfaces have a common first edge, Each side surface in the pair of adjacent side surfaces connects the backside surface of the one semiconductor die to the active surface of the one semiconductor die and does not face other semiconductor die in the array; And The outer corner of the backside surface of the one semiconductor die is formed by the backside surface of the one semiconductor die and the pair of adjacent side surfaces of the one semiconductor die.

9. The semiconductor package according to claim 8, wherein the underfill contains a third material, and the first material, the second material, and the third material are different from each other.

10. The semiconductor package according to claim 9, wherein the first material contains a first polyimide, the second material contains an epoxy resin, and the third material contains a second polyimide.

11. The semiconductor package according to claim 8, wherein the underfill includes an inclined surface extending from a side surface of the one semiconductor die to the first semiconductor substrate. The side surface of the one semiconductor die shares an edge with the backside surface of the one semiconductor die, and the corner pad is disposed on the inclined surface.

12. The semiconductor package according to claim 8, further comprising a connecting member disposed on the active surface of the one semiconductor die opposite to the backside surface of the one semiconductor die to establish an electrical connection between the one semiconductor die and the semiconductor via.

13. The semiconductor package according to claim 8, wherein the backside surface of the one semiconductor die forms a second outer corner, and a second corner pad is formed on the second outer corner of the one semiconductor die.

14. The semiconductor package according to claim 8, wherein the corner pad contacts the sealant.

15. A method of manufacturing a semiconductor package, comprising: The plurality of semiconductor dies are electrically connected to an insert via connectors disposed at active surfaces of the plurality of semiconductor dies, each semiconductor die further including: a backside surface opposite the active surface; and side surfaces that join the active surface to the backside surface, wherein the plurality of semiconductor dies are electrically connected to the insert and are arranged side by side on the insert, with respective backside surfaces facing away from the insert; Dispense a filler material on the insert around the connectors and in gaps between adjacent semiconductor dies; Cure the filler material to form an underfill; Form a rounded corner structure including a first material on a backside surface of a first semiconductor die of the plurality of semiconductor dies, the backside surface of the first semiconductor die being opposite the active surface of the first semiconductor die; and Form a sealant including a second material that laterally encapsulates the plurality of semiconductor dies and the underfill, wherein an outer corner of the first semiconductor die is spaced from the sealant by the rounded corner structure, the rounded corner structure being disposed at the outer corner of at least one semiconductor die, the rounded corner structure being in direct contact with the sealant, the outer corner being formed by the backside surface of the at least one semiconductor die and a pair of adjacent side surfaces of the at least one semiconductor die, the side surfaces in the pair of adjacent side surfaces having a common first edge, and each side surface in the pair of adjacent side surfaces not facing other semiconductor dies and having a second edge common with the backside surface of the at least one semiconductor die, and the rounded corner structure partially covering each side surface in the pair of adjacent side surfaces; and The first material is different from the second material.

16. The method of manufacturing a semiconductor package according to claim 15, wherein the first material comprises a semiconductor material; and Forming the rounded corner structure includes smoothing the outer corner of the first semiconductor die via laser cutting, the outer corner of the first semiconductor die being formed by the backside surface of the first semiconductor die and a pair of adjacent side surfaces of the first semiconductor die, the side surfaces in the pair of adjacent side surfaces having a common first edge, and each side surface in the pair of adjacent side surfaces not facing other semiconductor dies and having a second edge common with the backside surface of the first semiconductor die.

17. The method of manufacturing a semiconductor package according to claim 15, wherein forming the rounded corner structure includes forming a corner pad on the outer corner of the first semiconductor die, the outer corner of the first semiconductor die being formed by the backside surface of the first semiconductor die and a pair of adjacent side surfaces of the first semiconductor die, the side surfaces in the pair of adjacent side surfaces having a common first edge, and each side surface in the pair of adjacent side surfaces not facing other semiconductor dies and having a second edge common with the backside surface of the first semiconductor die.

18. The method of manufacturing a semiconductor package according to claim 17, wherein forming the corner pad includes: Dispense the first material onto the first semiconductor die; and cure the first material, wherein the viscosity of the first material is higher than the viscosity of the encapsulant material.

19. The method of manufacturing a semiconductor package according to claim 18, wherein the encapsulant material is dispensed to at least partially cover the pair of adjacent side surfaces of the first semiconductor die, and the first material is dispensed such that at least a portion of the underfill is inserted between the corner pad and the pair of adjacent side surfaces of the first semiconductor die.

20. The method of manufacturing a semiconductor package according to claim 18, wherein forming the seal body includes: forming a sealing material on the insert to cover the plurality of semiconductor dies and the cured first material; and removing a portion of the cured first material and a portion of the sealing material.

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