Semiconductor device and method for forming the same

Abstract

The present disclosure relates to semiconductor devices and methods for forming the same. One embodiment of the device includes: a first source / drain region located above a semiconductor substrate; and a dummy fin adjacent to the first source / drain region. The dummy fin includes: a first portion including a first film; and a second portion located above the first portion, wherein the second portion includes a second film and a third film. The third film is between the first film and the second film, and the third film is made of a material different from the first film and the second film. The width of the second portion is less than the width of the first portion. The device also includes: a gate stack along a sidewall of the dummy fin.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing layers of insulating or dielectric material, conductive material, and semiconductor material on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first source / drain region located on a semiconductor substrate; a dummy fin adjacent to the first source / drain region, the dummy fin comprising: a first portion comprising a first film; and a second portion located on the first portion, the width of the second portion being smaller than the width of the first portion, wherein the second portion comprises: a second film; and a third film located between the first film and the second film, the third film being made of a material different from the first film and the second film; and a gate stack along the sidewalls of the dummy fin.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first transistor located at the top surface of a semiconductor substrate, the first transistor comprising: a first channel region; and a first gate stack located above the first channel region and along the sidewalls of the first channel region; a second transistor located at the top surface of the semiconductor substrate, the second transistor comprising: a second channel region; and a second gate stack located above the second channel region and along the sidewalls of the second channel region; and a dummy fin physically separating the first gate stack from the second gate stack, wherein the dummy fin comprises: a first film; and a second film located above the first film, wherein a width of the dummy fin measured at the level of the second film is smaller than a width of the dummy fin measured at the level of the first film.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: defining an opening between a first semiconductor fin and a second semiconductor fin; forming a dummy fin between the first semiconductor fin and the second semiconductor fin, wherein forming the dummy fin comprises: depositing a first film in the opening; recessing the first film in the opening; depositing a second film over the first film in the opening; depositing a third film over the second film in the opening, the second film being arranged on the sidewalls and bottom surface of the third film; and etching the second film to at least partially remove the second film from the sidewalls of the third film; and forming a gate structure along the sidewalls and top surfaces of the first semiconductor fin, the second semiconductor fin and the dummy fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 15E 、 Figure 15F 、 Figure 15G 、 Figure 15H 、 Figure 16A 、 Figure 16B 、 Figure 17 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 21A 、 Figure 21B 、 Figure 22A 、 Figure 22B 、 Figure 23A 、 Figure 23B 、 Figure 24A 、 Figure 24B 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 26A 、 Figure 26B 、 Figure 27A 、 Figure 27B 、 Figure 28A and Figure 28B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET, according to some embodiments.

[0010] Figure 29 、 Figure 30 、 Figure 31 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 、 Figure 36A 、 Figure 36B 、 Figure 36C 、 Figure 37A 、 Figure 37B ,and Figure 37C is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some alternative embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] Various embodiments described herein are applicable to fin field-effect transistors (FinFETs). Embodiments may also be applicable to other transistor technologies, including nanosheet FETs (sometimes referred to as gate-all-around field-effect transistors (GAAFETs)).

[0014] In various embodiments, dummy fins can be used to separate the metal gates of adjacent transistors. Dummy fins can also help isolate adjacent source / drain regions by, for example, preventing accidental source / drain merging during the epitaxial growth process. It has been observed that because the dummy fins are close to the channel region of the transistor, the size of the dummy fins (sometimes referred to as the critical dimension (CD)) can affect the yield of the device. Various embodiments include forming a film on the sidewalls of the dummy fins and etching the film. Thus, the profile of the dummy fins can be improved. For example, the middle portion of the dummy fin can be narrower than the bottom of the dummy fin (e.g., having a smaller CD). In this way, the spacing between the dummy fin and the channel region can be increased, and the process window for gate stack gap filling can be increased.

[0015] Figure 1 An example of a device 10 including a FinFET according to some embodiments is shown in a three-dimensional view. A portion of the device 10 is cut away to show the features below (e.g., features outlined with dashed lines). The device 10 includes a fin 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are provided in the substrate 50, and the fins 52 protrude from between adjacent isolation regions 56 and are higher than the isolation regions 56. Although the isolation regions 56 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to only the semiconductor substrate, or a semiconductor substrate including the isolation regions. In addition, although the fin 52 is shown as a single continuous material like the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion extending between adjacent isolation regions 56. The device 10 also includes a dummy fin 52' located between adjacent fins 52.

[0016] A gate dielectric layer 92 is disposed along the sidewalls of the fin 52 and above the top surface of the fin 52, a gate electrode 94 is disposed above the gate dielectric layer 92, and a gate mask layer 96 is disposed above the gate electrode 94. The gate dielectric layer 92, gate electrode 94, and gate mask layer 96 may also be disposed on the sidewalls of the dummy channel region 52′. One or more gate spacers 86 may be located on the sidewalls of the gate dielectric layer 92, gate electrode 94, and gate mask layer 96. Source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92, gate electrode 94, and gate mask layer 96. In some embodiments, gate spacers 86 may also be optionally formed on the sidewalls of the dummy fin 52′. The dummy fin 52′ may be disposed between and physically separate adjacent source / drain regions 82. The source / drain regions 82 may also extend from the recessed portion of the fin 52A.

[0017] The dielectric region 78 extends through the gate mask layer 96 into the gate electrode 94 (see, e.g., Figure 27A ). Dielectric region 78 can extend to dummy fin 52', and the combination of dielectric region 78 and dummy fin 52' can isolate the gate electrode of the adjacent FinFET. Contact etch stop layer (CESL) 87 is disposed over isolation region 56, and dielectric layer 88 is disposed over CESL 87. Dielectric layer 88 can further surround source / drain regions 82, portions of dummy fin 52', gate mask layer 96, gate dielectric layer 92, and gate electrode 94.

[0018] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of gate electrode 94 and is perpendicular to the direction of current flow, for example, between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and is along the longitudinal axis of fin 52 and is perpendicular to the direction of current flow, for example, between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0019] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs).

[0020] Figures 2 to 37C is a cross-sectional view of an intermediate stage in the fabrication of a FinFET, according to some embodiments. Figures 2 to 14 、 Figures 15A to 15H 、 Figure 16A 、 Figure 16B 、 Figure 17 、 Figures 29 to 35 as well as Figures 36A to 36C Shown Figure 1 Reference cross section AA is shown, except for multiple fins / FinFETs. Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23A 、 Figure 24A 、 Figure 25A 、 Figure 26A 、 Figure 27A 、 Figure 28A and Figure 37A Along Figure 1 The reference cross section AA is shown for illustration purposes only, while Figure 18B 、 Figure 19B 、 Figure 20B 、 Figure 21B 、 Figure 22B 、 Figure 23B 、 Figure 24B 、 Figure 25B 、 Figure 25C 、 Figure 26B 、 Figure 27B 、 Figure 28B and Figure 37B Along Figure 1 A similar cross section BB is shown, except with multiple fins / FinFETs. Figure 20C and 37C Along Figure 1 Reference cross section CC is shown for illustration, except for the multiple fins / FinFETs.

[0021] exist Figure 2 In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenic phosphide; or combinations thereof.

[0022] Substrate 50 has a region 50N and a region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type FinFET. Region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type FinFET. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0023] A hard mask 53 is deposited on the substrate 50. The hard mask 53 can be used to define the pattern of the subsequently formed semiconductor fins. In some embodiments, the hard mask is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The hard mask 53 can include silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, or multiple layers thereof. For example, although only one hard mask layer is shown, a multilayer structure (e.g., a silicon oxide layer on a silicon nitride layer) can be formed as the hard mask 53.

[0024] Figures 3 to 28B Various additional steps in fabricating embodiment devices are shown. Figures 3 to 28B Features in either region 50N or region 50P are shown. For example, Figures 3 to 28B The structure shown may apply to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described in the text accompanying each figure.

[0025] Figures 3 to 16B A cross-sectional view (eg, along the line 100) of fabricating a dummy fin according to various embodiments is shown. Figure 1 cross section AA). Figure 3 In the embodiment, fins 52A and 52B are formed in substrate 50. Fins 52A / 52B are semiconductor strips. Fins 52A / 52B include fin 52B located between fins 52A. As will be described in subsequent figures, fin 52B will be removed and replaced by dummy fins 52' (see FIG. Figure 14 ).

[0026] In some embodiments, fins 52A may be formed in substrate 50 by etching trenches in substrate 50. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic.

[0027] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithographic process with a self-aligned process, thereby allowing the creation of patterns having, for example, a spacing smaller than that obtainable using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithographic process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins 52A / 52B.

[0028] exist Figure 4 , an insulating material 54 is formed over the substrate 50 and between adjacent fins 52A / 52B. The insulating material 54 may be an oxide (e.g., silicon oxide, nitride, etc., or a combination thereof) and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable method may be used. In the embodiment shown, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52A / 52B. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a conformal liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52A / 52B. Thereafter, a filler material such as that described above may be formed over the liner.

[0029] After deposition, a removal process is applied to the insulating material 54 to remove excess insulating material 54 located above the fins 52A / 52B. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like. The planarization process exposes the fins 52A / 52B such that the top surfaces of the fins 52A / 52B and the top surface of the insulating material 54 are flush after the planarization process is completed. In embodiments where the mask 53 remains on the fins 52A / 52B, the planarization process may expose the mask 53 or remove the mask 53 such that the top surfaces of the mask or the fins 52A / 52B, respectively, and the top surface of the insulating material 54 are flush after the planarization process is completed.

[0030] exist Figure 5In the embodiment of the present invention, at least a portion of the fins 52B is removed using an acceptable etching process, for example. Thus, openings 100 are formed in the isolation material 54 between the fins 52A. In subsequent processes, dummy channel regions may be formed in the openings 100. The fins 52B may be completely removed, or a portion of the fins 52B may remain below the openings 100.

[0031] exist Figure 6 , an optional spacer layer 102 is deposited over the isolation material 54 and the substrate 50. The spacer layer 102 may be deposited along the sidewalls and bottom surface of the recess 100. In embodiments where a portion of the fin 52B remains, the spacer layer 102 may be deposited over the top surface of the fin 52B. The spacer layer 102 may be deposited using any suitable process, such as CVD, plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), ALD, PVD, etc. The spacer layer 102 may be deposited using a conformal process. The thickness of the spacer layer 102 may be about 1000 mm / s. to about The spacer layer 102 may include a silicon-based dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, etc.), a silicon-based semiconductor material (e.g., silicon germanium), a metal oxide, a metal nitride, etc. In an embodiment, in which the spacer layer 102 includes a metal oxide or a metal nitride, the spacer layer 102 may include a metal, such as hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, etc. The spacer layer 102 is an optional layer and may be omitted in other embodiments.

[0032] exist Figure 7 In the embodiment, the film 104 is deposited over the spacer layer 102 (if present). Alternatively, in embodiments where the spacer layer 102 is omitted, the film 104 can be deposited directly over the isolation material 54 and the substrate 50. The film 104 can be deposited along the sidewalls and bottom surface of the groove 100 until the portion of the film 104 located on the sidewalls of the groove 100 is sufficiently thick and joined together. Thus, the film 104 can fill the remaining portion of the groove 100, and a seam 104' can be formed in the film 104. The film 104 can be deposited using any suitable process, such as CVD, PECVD, PEALD, ALD, PVD, etc. A conformal process can be used to deposit the film 104. The thickness of the film 104 can be about to about The film 104 may include a silicon-based dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, etc.), a silicon-based semiconductor material (e.g., silicon germanium), a metal oxide, a metal nitride, etc. In embodiments where the film 104 includes a metal oxide or a metal nitride, the film 104 may include a metal, such as hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, etc.

[0033] The material of the film 104 can be the same as or different from the spacer layer 102. Furthermore, in embodiments, the spacer 102 can be included to partially fill a portion of the recess 100 so that the film 104 can fill the remainder of the recess 100 with improved gap filling. For example, in embodiments where the recess 100 is relatively wide, multiple layers of material can be deposited in the recess 100 so that the multiple layers together fill the recess 100 without any individual layer being too thick. Furthermore, the material of the spacer 102 can be harder than the film 104. For example, the material of the film 104 can be selected for its gap filling properties, wherein the spacer 102 is a material for the subsequently formed dummy fin 52' (see Figure 14 ) provide strength and structural support.

[0034] exist Figure 8 In the embodiment of the present invention, film 104 may be etched back to a desired height. Etching film 104 may include a selective process that selectively etches film 104 without significantly etching isolation material 54 or fin 52A.

[0035] In some embodiments, the etch-back process may be a plasma process, such as plasma etching, remote plasma processing, free radical etching, or the like. Etching gases used during the plasma process may include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, combinations thereof, or the like. The plasma process may further include flowing a passivation gas through the device 10 to adjust (e.g., increase) the etch selectivity between the film 104 and other features of the device 10. Example passivation gases may include N2, O2, CO2, SO2, CO, SiCl4, combinations thereof, or the like. One or more carrier gases may also be used during the plasma process, such as Ar, He, Ne, combinations thereof, or the like. Furthermore, the plasma process may be performed under the following conditions: a plasma source power in the range of approximately 10 W to approximately 3000 W, a bias power in the range of approximately 0 W to approximately 3000 W, a pressure of approximately 1 mTorr to approximately 800 mTorr, a gas mixture flow rate of approximately 10 sccm to approximately 5000 sccm, or the like.

[0036] In some embodiments, the etch back process is a wet etching process (sometimes referred to as wet cleaning). Example etchants that may be used during the wet etching process may include HF, F2, combinations thereof, and the like. The wet etching process may further include flowing an auxiliary etching chemical through the device 10 to adjust (e.g., increase) the etch selectivity between the film 104 and other features of the device 10. Example auxiliary etching chemicals may include H2SO4, HCl, HBr, NH3, combinations thereof, and the like. Deionized water (DIW), alcohol, acetone, and the like may be used as solvents for mixing the etchant and / or auxiliary etching chemicals during the wet etching process.

[0037] exist Figure 9 In the embodiment of the present invention, the spacer layer 102 is etched back to, for example, the same level as the membrane 104. Etching the spacer layer 102 may include a selective process that selectively etches the spacer layer 102 without significantly etching the isolation material 54 or the fin 52A. The etch back process of the spacer layer 102 may be the same as or different from that of the membrane 104.

[0038] In some embodiments, the etch-back process for the spacer layer 102 can be a plasma process, such as plasma etching, remote plasma processing, free radical etching, and the like. Etching gases used during the plasma process can include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, combinations thereof, and the like. The plasma process can further include flowing a passivation gas through the device 10 to adjust (e.g., increase) the etch selectivity between the spacer layer 102 and other features of the device 10. Example passivation gases can include N2, O2, CO2, SO2, CO, SiCl4, combinations thereof, and the like. One or more carrier gases can also be used during the plasma process, such as Ar, He, Ne, combinations thereof, and the like. In addition, the plasma process may be performed under the following conditions: plasma source power is in the range of about 10 W to about 3000 W, bias power is in the range of about 0 W to about 3000 W, pressure is about 1 mTorr to about 800 mTorr, gas mixture flow rate is about 10 sccm to about 5000 sccm, etc.

[0039] In some embodiments, the etch back process for the spacer layer 102 is a wet etching process (sometimes referred to as wet cleaning). Example etchants that may be used during the wet etching process may include HF, F2, combinations thereof, and the like. The wet etching process may further include flowing an auxiliary etching chemical through the device 10 to adjust (e.g., increase) the etch selectivity between the spacer layer 102 and other features of the device 10. Example auxiliary etching chemicals may include H2SO4, HCl, HBr, NH3, combinations thereof, and the like. Deionized water (DIW), alcohol, acetone, and the like may be used as solvents for mixing the etchant and / or auxiliary etching chemicals during the wet etching process.

[0040] exist Figure 10 In the embodiment, the film 106 is deposited over the fin 52A, the isolation material 54, the film 104, and the spacer layer 102 (if present). The film 106 can be deposited along the sidewalls and bottom surface of the groove 100. The film 106 can be deposited using any suitable process, such as CVD, PECVD, PEALD, ALD, PVD, etc. The film 106 can be deposited using a conformal process. Although a single layer of the film 106 is shown, the film 106 can be a multi-layer structure. For example, in some embodiments, the film 106 can include up to ten layers of different materials. Each layer of the film 106 can be deposited using a similar process as described above. The thickness of each layer in the film 106 can be about to about within the range.

[0041] Each layer of film 106 may include a silicon-based dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, silicon carbide, silicon oxycarbide, silicon oxide, etc.), a silicon-based semiconductor material (e.g., silicon germanium), a metal oxide, a metal nitride, etc. In embodiments where film 106 includes a metal oxide or a metal nitride, film 106 may include a metal, such as hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, etc. The material of each layer of film 106 may be selected to provide etch selectivity in one or more subsequent processes. For example, the material of film 106 may be selected so that it can be etched away to provide a dummy channel region having a thinner top / middle portion.

[0042] exist Figure 11, film 108 is deposited over film 106. Film 108 may be deposited along the sidewalls and bottom surface of groove 100 until the portion of film 108 located on the sidewalls of groove 100 is thick enough and joins together. Thus, film 108 may fill the remaining portion of groove 100, and a seam 108' may be formed in film 108. Film 108 may be deposited using any suitable process, such as CVD, PECVD, PEALD, ALD, PVD, etc. Film 108 may be deposited using a conformal process. The thickness of film 108 may be about to about The film 108 may include a silicon-based dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, etc.), a silicon-based semiconductor material (e.g., silicon germanium), a metal oxide, a metal nitride, etc. In embodiments where the film 108 includes a metal oxide or a metal nitride, the film 108 may include a metal, such as hafnium, tantalum, aluminum, chromium, nickel, iron, yttrium, copper, tin, tungsten, etc.

[0043] The materials of membranes 106 and 108 can be selected so that membrane 106 can be selectively etched in subsequent processes without significantly etching membrane 108. In addition, the material of membrane 108 can also be selected so that membrane 108 is not significantly etched during the source / drain formation steps of the FinFET. As will be described in more detail later, forming the source / drain regions can include etching the gate spacer layer to expose the fin 52A and then etching the fin 52A. Exposing the fin 52A can also expose membrane 108. Therefore, the material of membrane 108 can be selected so that membrane 108 is not significantly etched during the etching of the gate spacer and fin 52'. For example, in an embodiment in which the gate spacer includes a nitride, the nitrogen concentration of membrane 108 can be relatively low to provide etch selectivity during the etching of the gate spacer. In some embodiments, for example, the nitrogen concentration of membrane 108 can be less than 40 at.%, and membrane 108 can be an oxide or an oxynitride. As another example, membrane 108 can be a different material than the fin 52A to provide etch selectivity during the patterning of the fin. For example, the fin 52A may include germanium. In other embodiments, the film 108 may include a high-k material to provide etch selectivity during patterning of the gate spacers and patterning of the fins.

[0044] In some embodiments, the material of film 108 may have a higher chemical bonding energy than the material of film 104 and / or spacer 102. As a result, it may be difficult to directly etch film 108 and reduce the width of film 108. Therefore, a film 106 with a lower bonding energy is formed on film 108, and film 106 is trimmed in a subsequent process step. This trimming advantageously increases the space between fins 52' to improve gap filling in a subsequent process step.

[0045] exist Figure 12 In the embodiment of the present invention, a removal process is applied to films 106 and 108 to remove excess material of films 106 and 108 located above fins 52A / 52B. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes fins 52A and insulating material 54 so that the top surfaces of fins 52A, insulating material 54, films 106, and films 108 are flush after the planarization process is completed.

[0046] Although the film 108 is shown as only a single material, the film 108 can have a multi-layer structure. For example, in other embodiments, the film 108 can include multiple stacked films. In such embodiments, each film layer can be as described above with respect to Figure 11 is deposited as described above and with the same method as described above with respect to recessing the film 104 (see Figure 8 ) is recessed in a similar manner as discussed above. This process can be repeated until the desired number of layers are formed for film 108. In some embodiments, up to ten film layers can be deposited and etched back over film 106 in recess 100. Figure 15G and Figure 15H An example is shown in which the film 108 has multiple layers.

[0047] exist Figure 13 Insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that the upper portion of fin 52A protrudes from between adjacent STI regions 56. In addition, the top surface of STI region 56 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dishing), or a combination thereof. The top surface of STI region 56 can be formed to be flat, convex, and / or concave by appropriate etching. STI region 56 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of insulating material 54 (e.g., etches the material of insulating material 54 at a faster rate than etching the material of fin 52). For example, oxide removal, such as using dilute hydrofluoric acid (dHF), can be used. Insulating material 54 can be recessed using a process that selectively etches insulating material 54 compared to film 106 / 108 and / or spacer layer 102.

[0048] refer to Figures 2 to 13The process described is only one example of how fin 52A may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52A. For example, Figure 13 The fin 52A in the substrate 50 may be recessed, and a material different from the fin 52A may be epitaxially grown over the recessed fin 52A. In such embodiments, the fin 52A includes the recessed material and the epitaxially grown material disposed over the recessed material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 50, and trenches may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52A. In some embodiments in which a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implantations, but in situ doping and implantation doping may be used together.

[0049] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (e.g., an NMOS region) than in region 50P (e.g., a PMOS region). It may also be advantageous to epitaxially grow a different material in a first circuit region (e.g., an SRAM) of device 10 than in a second circuit region of device 10 (regardless of the device type (e.g., NMOS or PMOS) in the first or second circuit region). In various embodiments, the upper portion of fin 52A may be made of silicon germanium (SiGe). x Ge 1-x , where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0050] Further in Figure 13 In the embodiment of the present invention, appropriate wells (not shown) may be formed in fin 52A and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, either a P-well or an N-well may be formed in both region 50N and region 50P.

[0051] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52A and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N (e.g., an NMOS region). The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0052] After implanting region 50P, a photoresist is formed over fin 52A and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed by using a spin coating technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant is performed in region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P (e.g., a PMOS region). The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0053] After implanting regions 50N and 50P, an anneal may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fins may be in-situ doped during growth, which may avoid implantation, but in-situ and implantation doping may be used together.

[0054] exist Figure 14In the embodiment of the present invention, film 106 is etched and at least partially removed from the sidewalls of film 108. Etching film 106 may include a selective process that selectively etches film 106 without significantly etching film 108, spacer layer 102, or film 104.

[0055] In some embodiments, etching film 106 may include a plasma process, such as plasma etching, remote plasma processing, free radical etching, and the like. Etching gases used during the plasma process may include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, combinations thereof, and the like. The plasma process may further include flowing a passivation gas through device 10 to adjust (e.g., increase) the etch selectivity between film 106 and other features of device 10. Example passivation gases may include N2, O2, CO2, SO2, CO, SiCl4, combinations thereof, and the like. One or more carrier gases may also be used during the plasma process, such as Ar, He, Ne, combinations thereof, and the like. Furthermore, the plasma process may be performed under the following conditions: a plasma source power in the range of approximately 10 W to approximately 3000 W, a bias power in the range of approximately 0 W to approximately 3000 W, a pressure of approximately 1 mTorr to approximately 800 mTorr, a gas mixture flow rate of approximately 10 sccm to approximately 5000 sccm, and the like.

[0056] In some embodiments, etching the film 106 may include a wet etching process (sometimes referred to as a wet clean). Example etchants that may be used during the wet etching process may include HF, F2, combinations thereof, and the like. The wet etching process may further include flowing an auxiliary etching chemical through the device 10 to adjust (e.g., increase) the etch selectivity between the film 106 and other features of the device 10. Example auxiliary etching chemicals may include H2SO4, HCl, HBr, NH3, combinations thereof, and the like. Deionized water (DIW), alcohol, acetone, and the like may be used as solvents for mixing the etchant and / or auxiliary etching chemicals during the wet etching process.

[0057] Film 106 can mask film 104 during etching so that film 104 is not accidentally etched. Etching film 104 can have detrimental consequences. For example, significantly reducing the width of film 104 can affect the structural stability of dummy fin 52'. Therefore, in some embodiments, film 106 is trimmed while masking film 104 so that the stability of dummy fin 52' is not significantly affected.

[0058] Thus, a dummy fin 52' is formed. The dummy fin 52' includes the spacer layer 102, the membrane 104, the remaining portion of the membrane 106, and the membrane 108. As a result of etching the membrane 106, the middle portion of the dummy fin 52' (e.g., including the membranes 106 and 108) has a width D2. The width D2 may be less than the width D1 of the lower portion of the dummy fin 52' (e.g., including the spacer layer 102 and the membrane 104). The width D1 may be measured at the level of the membrane 104, and the width D2 may be measured at the level of the membrane 108. For example, the width D1 may be in the range of about 2 nm to about 1000 nm, and the width D2 may be in the range of about 2 nm to about 1000 nm. The widths D1 and D2 may depend on the location of the particular dummy fin 52'. For example, in the first region, the width D1 may be in the range of about 8 nm to about 14 nm, and the width D2 may be in the range of about 4 nm to about 10 nm. In the second region, widths D1 and D2 may be approximately 100 nm or greater. By providing a width D2 that is smaller than width D1 (e.g., within the above range), the distance D3 of the space between the fin 52A and the dummy fin 52' may be increased. For example, the space between the fin 52A and the dummy fin 52' may be enlarged, which improves the process window for filling the space between the fin 52A and the dummy fin 52' in subsequent steps (e.g., dummy gate fill or metal gate fill). In addition, the base of the dummy fin 52' is not reduced, which improves the structural stability of the dummy fin 52', particularly in subsequent process steps in which the region of the dummy fin 52' may be exposed to one or more etchants. Thus, manufacturing defects (e.g., voids) may be reduced in subsequent deposition processes.

[0059] Figure 14 An embodiment configuration of the dummy fin 52' is shown. In other embodiments, the dummy fin 52' may have a different configuration. For example, Figure 15A Shown as Figure 14 A detailed view of dummy fin 52' is shown. Figures 15B to 15H Alternative embodiments of fins 52' are shown, each of which may be deployed in Figure 14 in the structure.

[0060] exist Figure 15A In other embodiments, the width of the top surface of the membrane 106 (e.g., the surface adjacent to the membrane 108) is less than the width of the bottom surface of the membrane 106 (e.g., the surface adjacent to the membrane 104). Figure 15B As shown, the width of the top surface of the membrane 106 can be greater than the width of the bottom surface of the membrane 106. In other embodiments, such as Figure 15CAs shown, the width of the middle portion of the membrane 106 can be less than the width of the top and bottom surfaces of the membrane 106, and the membrane 106 has concave sidewalls. In such embodiments, the widths of the top and bottom surfaces of the membrane 106 can be the same or different.

[0061] In addition, Figure 15A , the film 106 is shown as being completely removed from the sidewalls of the film 108. In other embodiments, a portion of the film 106 may remain on the sidewalls of the film 108. For example, Figure 15D As shown, the film 106 remains on the sidewalls of the film 108 and extends to the top surface of the film 108. As another example, Figure 15E As shown, membrane 106 may extend partially upwardly onto the sidewalls of membrane 108 such that membrane 108 extends higher than membrane 106. Figure 15D and Figure 15E In some embodiments, the maximum thickness T1 of the film 106 on the sidewalls of the film 108 may be less than the thickness T2 of the film 106 on the bottom surface of the film 108. In some embodiments, the thickness T2 of the film 106 on the bottom surface of the film 108 may be about to about In addition, the total height T3 of the membrane 106 can be about to about The height T3 can be measured from the bottommost surface of the membrane 106 to the topmost point of the membrane 106.

[0062] Figure 15F An embodiment is shown in which the optional spacer layer is omitted. In such an embodiment, the membrane 104 can be in direct contact with the STI region 56 and the rest of the substrate 50 / fin 52A (see Figure 14 ).Although Figure 15F The film 106 is shown to have Figure 15A The same configuration, but it should be understood that any configuration of membrane 106 (e.g., Figures 15B-15E shown).

[0063] Figure 15G and Figure 15H An embodiment in which the film 108 is a multi-layer structure is shown. Figure 15G In FIG, the film 108 includes a film layer 108A and a film layer 108B located on the top surface of the film layer 108A. Figure 15H, film 108 includes film layer 108A, film layer 108B located on the top surface of film layer 108A, and film layer 108C located on the top surface of film layer 108B. As described above, each film layer 108A, 108B, and 108C can be deposited and optionally recessed. Each film layer 108A, 108B, and 108C can have a different material composition than adjacent film layers. Furthermore, in some embodiments, as a result of (one or more) etch-back processes to recess one or more film layers (e.g., film layers 108A / 108B), the top surfaces of these etched film layers can have a V-shape. Although Figure 15G and Figure 15H The film 106 is shown to have Figure 15A The same configuration, but it should be understood that any configuration of membrane 106 (e.g., Figures 15B-15E In addition, Figure 15G and Figure 15H In the embodiment, the spacer layer 102 is optional and can be excluded, as described above with respect to Figure 15F As stated.

[0064] exist Figure 14 In the embodiment of FIG. 5 , STI regions 56 are shown as having a top surface that is lower than films 106 / 108. For example, spacer layer 102, film 104, film 106, and film 108 each extend higher than STI regions 56. In other embodiments, STI regions 56 may be disposed at different levels. For example, Figure 16A An embodiment is shown in which the top surface of the STI regions 56 is substantially flush with the bottom surface of the membrane 106 (eg, within manufacturing tolerances), and substantially flush with the top surfaces of the spacer layer 102 and the membrane 104 . Figure 16B An embodiment is shown in which the top surface of STI regions 56 is higher than the bottom surface of film 106, the top surface of spacer layer 102, and the top surface of film 104. Other configurations are possible.

[0065] exist Figure 17 In FIG. 5 , dummy dielectric layer 60 is formed over fin 52A and dummy fin 52′. Dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques.

[0066] A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 can be made of other materials having high etch selectivity relative to the etching of the isolation region.

[0067] By removing portions of film 106 from the sidewalls of dummy fins 52', the space between fins 52A and dummy fins 52' can be increased. As a result, dummy gate layer 62 can be deposited with fewer defects (eg, fewer voids) in the space around and between fins 52A / dummy fins 52'.

[0068] Mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. Note that dummy dielectric layer 60 is shown covering only fin 52A for illustrative purposes only. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 56, extending between dummy gate layer 62 and STI region 56.

[0069] exist Figure 18A and Figure 18B In the embodiment, the mask layer 64 (see Figure 17 ) is patterned to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers each channel region 58 of the fin 52A. The dummy gate 72 also covers the top surface and sidewalls of the dummy fin 52'. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from the adjacent dummy gate. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52A.

[0070] Further in Figure 18A and Figure 18BIn the embodiment of the present invention, a gate sealing spacer 80 may be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52A / dummy fin 52'. Thermal oxidation or deposition and subsequent anisotropic etching may form the gate sealing spacer 80. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0071] After forming the gate sealing spacer 80, an implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. Figure 13 , a mask (e.g., photoresist) may be formed over region 50N while exposing region 50P, and impurities of an appropriate type (e.g., p-type) may be implanted into the exposed fins 52A in region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over region 50P while exposing region 50N, and impurities of an appropriate type (e.g., n-type) may be implanted into the exposed fins 52A in region 50N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities, and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have a density of approximately 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implantation damage and activate the implanted impurities.

[0072] exist Figure 19A and Figure 19B , a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like.

[0073] Note that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be utilized, a different order of steps may be utilized (e.g., the gate sealing spacer 80 may not be etched before forming the gate spacer 86, thereby producing an "L-shaped" gate sealing spacer), spacers may be formed and removed, etc. Furthermore, different structures and steps may be used to form n-type and p-type devices. For example, the LDD region for an n-type device may be formed before forming the gate sealing spacer 80, and the LDD region for a p-type device may be formed after forming the gate sealing spacer 80.

[0074] exist Figure 20A and Figure 20B In the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fin 52A. The source / drain regions 82 can exert stress in the corresponding channel region 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fin 52A so that each dummy gate 72 is disposed between adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 can extend into the fin 52A and can also penetrate the fin 52A. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gate 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the gate of a subsequently formed FinFET.

[0075] Epitaxial source / drain regions 82 in region 50N (e.g., an NMOS region) can be formed by masking region 50P (e.g., a PMOS region) and etching the source / drain regions of fin 52A in region 50N to form recesses in fin 52A. Epitaxial source / drain regions 82 in region 50N are then epitaxially grown in the recesses. Epitaxial source / drain regions 82 can include any acceptable material, such as a material suitable for n-type FinFETs. For example, if fin 52A is silicon, epitaxial source / drain regions 82 in region 50N can include a material that imposes tensile strain in channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. Epitaxial source / drain regions 82 in region 50N can have surfaces that protrude from corresponding surfaces of fin 52A and can be faceted.

[0076] Epitaxial source / drain regions 82 in region 50P (e.g., a PMOS region) can be formed by masking region 50N (e.g., an NMOS region) and etching the source / drain regions of fin 52A in region 50P to form recesses in fin 52A. Epitaxial source / drain regions 82 in region 50P are then epitaxially grown in the recesses. Epitaxial source / drain regions 82 can include any acceptable material, such as a material suitable for p-type FinFETs. For example, if fin 52A is silicon, epitaxial source / drain regions 82 in region 50P can include a material that imposes compressive strain in channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, etc. The epitaxial source / drain regions 82 in region 50P can also have surfaces that protrude from corresponding surfaces of fin 52A and can be faceted.

[0077] The epitaxial source / drain regions 82 and / or fins 52A may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The impurity concentration of the source / drain regions may be approximately 10 19 cm-3 With about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities previously discussed. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0078] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fins 52A. Gate spacers 86 are formed to cover the portions of the sidewalls of fins 52A that extend over STI regions 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of STI regions 56.

[0079] In various embodiments, as Figure 20C As shown, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated. For example, source / drain regions 82 can be grown to physically contact dummy fins 52', which physically separate adjacent source / drain regions 82 from each other. Thus, adjacent epitaxial source / drain regions 82 can be prevented from merging and accidentally shorting. As described above, the material of film 108 can be selected so that film 108 is not significantly etched during the formation of the source / drain regions.

[0080] For example, the source / drain region 82 may contact the film 108 of the dummy fin 52'. In some embodiments, the middle portion of the dummy fin 52' having a width D2 is the portion of the dummy fin 52' that contacts the epitaxial source / drain region 82. The width D2 may be less than the width D1 of the lower portion of the dummy fin 52'. The width D1 may be measured at the level of the film 104, and the width D2 may be measured at the level of the film 108.

[0081] exist Figure 21A and Figure 21B In the first interlayer dielectric (ILD) 88 is deposited on Figure 20A and Figure 20B. The first ILD 88 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable method may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The CESL 87 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having a different etch rate than the material of the first ILD 88 above.

[0082] exist Figure 22A and Figure 22B During the planarization process, a planarization process such as CMP may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process also removes the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0083] exist Figure 23A and Figure 23B , dielectric region 78 is formed to extend through dummy gate 72 to dummy fin 52'. Dielectric region 78 can be formed, for example, by etching dummy gate 72 using (one or more) wet and / or dry etching processes. The etching process can expose dummy fin 52'. Subsequently, dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, etc., can be deposited in the groove. A planarization process can be performed to remove excess dielectric material from above dummy gate 72. Dielectric region 78 and dummy fin 52', in combination, separate dummy gate 72 into different regions (e.g., regions 72A and 72B). For example, different regions can correspond to the positions of different transistor devices. Therefore, dielectric region 78 and dummy fin 52' can provide isolation between adjacent FinFETs.

[0084] exist Figure 24A and Figure 24BIn the embodiment of the present invention, the remaining dummy gate 72 (and mask 74, if present) are removed in one or more etching steps, forming recesses 90. The portion of dummy dielectric layer 60 within recesses 90 may also be removed. In some embodiments, only dummy gate 72 is removed, and dummy dielectric layer 60 remains and is exposed by recesses 90. In some embodiments, dummy dielectric layer 60 is removed from recesses 90 in a first die region (e.g., a core logic region) and remains within recesses 90 in a second die region (e.g., an input / output region). In some embodiments, dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etches dummy gate 72 without etching first ILD 88 or gate spacers 86. Each recess 90 exposes and / or covers a channel region 58 of a corresponding fin 52A. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be optionally removed after the dummy gate 72 is removed.

[0085] exist Figure 25A and Figure 25B In the embodiment, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 25C Shown Figure 25B Detailed view of region 89 of FIG. A gate dielectric layer 92 is conformally deposited in recess 90 , for example, on the top surface and sidewalls of fin 52A, on the sidewalls of dummy fin 52′, on the sidewalls of dielectric region 78 , and on the sidewalls of gate seal spacer 80 / gate spacer 86 . Gate dielectric layer 92 may also be formed on the top surface of first ILD 88 . According to some embodiments, gate dielectric layer 92 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a k value greater than approximately 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods of forming gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy gate dielectric 60 remain in the recess 90 , the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (eg, SiO 2 ).

[0086] Gate electrodes 94 are separately deposited over gate dielectric layer 92 and fill the remaining portions of recesses 90. By removing portions of film 106 from the sidewalls of dummy fins 52', the space between fins 52A and dummy fins 52' can be increased. As a result, gate electrodes 94 can be deposited in the space around and between fins 52A / dummy fins 52' with fewer defects (e.g., fewer voids).

[0087] The gate electrode 94 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Figure 25B A single-layer gate electrode 94 is shown in FIG, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler materials 94C, such as Figure 25C As shown. After filling the recess 90, a planarization process (e.g., CMP) can be performed to remove excess portions of the gate dielectric layer 92 and the gate electrode 94 material that are above the top surface of the ILD 88. The material of the gate electrode 94 and the remaining portion of the gate dielectric layer 92 thus form a replacement gate for the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as a "gate stack." The gate and the gate stack can extend along the sidewalls of the channel region 58 of the fin 52A. When adjacent gate stacks correspond to different FinFETs, the dielectric region 78 and the dummy fin 52' isolate the adjacent gate stacks (e.g., gate stack 92A / 94A and gate stack 92B / 94B).

[0088] The formation of gate dielectric layer 92 in region 50N and region 50P can occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 can occur simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region can be formed by a different process, such that gate dielectric layer 92 can be a different material, and / or gate electrode 94 in each region can be formed by a different process, such that gate electrode 94 can be a different material. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0089] exist Figure 26A and Figure 26BIn the embodiment of the present invention, the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94 above) is recessed to form a groove directly above the gate stack and between the opposing portions of the gate spacers 86. The etching process can be selective so that the dielectric region 78 is not significantly etched. The groove is filled with a gate mask 96 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), and then a planarization process is performed to remove excess portions of the dielectric material extending above the first ILD 88. The gate contact 110 ( Figure 27A and Figure 27B ) passes through gate mask 96 to contact the top surface of recessed gate electrode 94. Dielectric region 78 may extend through gate mask 96.

[0090] exist Figure 27A and Figure 27B , the second ILD 114 is deposited over the first ILD 88. In some embodiments, the second ILD 114 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 114 is formed of a dielectric material (e.g., PSG, BSG, BPSG, USG, etc.) and can be deposited by any suitable method (e.g., CVD and PECVD).

[0091] Also in Figure 27A and Figure 27B, in accordance with some embodiments, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 114 and the first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 114, and an opening for the gate contact 110 is formed through the second ILD 114 and the gate mask 96. Acceptable photolithography and etching techniques can be used to form the opening. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., CMP) can be performed to remove excess material from the surface of the ILD 114. The remaining liner and conductive material form the source / drain contacts 112 and the gate contact 110 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contacts 112 and the gate contact 110 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 112 and the gate contact 110 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0092] The above embodiments describe forming the dielectric region 78 before the gate stack 92 / 94. In other embodiments, the gate stack (e.g., including the gate dielectric 92 and the gate electrode 94) may be formed before forming the dielectric region 78. Subsequently, the gate stack 92 / 94 may be etched to expose the dummy fin 52', and a dielectric material may be deposited to form the dielectric region 78. Figure 28A and Figure 28B The resulting structure is shown in .

[0093] Figures 29 to 37C 1 shows a cross-sectional view of an intermediate step in fabricating a device 20 having dummy fins 52' according to an alternative embodiment. Figures 29 to 37C In the drawings, the same reference numerals are used as in Figures 2 to 28B The same components are formed by the same process as described in the previous section. Figure 29 In FIG. 5 , fins 52 are formed to extend from substrate 50 . A hard mask 53 is used to pattern the fins 52 and may remain on the fins 52 .

[0094] exist Figure 30, insulating material 54 is deposited over fins 52 and along the sidewalls of fins 52. Insulating material 54 may be deposited using a conformal process that only partially fills the spaces between fins 52. As a result of the deposition process, openings 100 are defined between fins 52 and over insulating material 54. Material may then be filled in openings 100 to form dummy fins 52'.

[0095] exist Figure 31 In the embodiment, an optional spacer layer 102 and a membrane 104 are deposited in the openings. Figure 6 and Figure 7 Similar processes as described are performed to deposit the spacer layer 102 and the membrane 104 .

[0096] exist Figure 32 In the embodiment, the optional spacer layer 102 and the membrane 104 are recessed in sequence. Figure 8 and Figure 9 A similar process is described for recessing the spacer layer 102 and the membrane 104 .

[0097] exist Figure 33 In the embodiment, films 106 and 108 are deposited in opening 100. Films 106 and 108 can be deposited over spacer layer 102 and film 104. Figure 10 and Figure 11 A similar process is described for depositing films 106 and 108. Film 108 may be a single layer structure or a multilayer structure.

[0098] exist Figure 34 In the process, a removal process is applied to film 106, film 108, insulating material 54, and hard mask 53 (if present) to remove excess material located above fin 52. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes fin 52 so that the top surfaces of fin 52, insulating material 54, film 106, and film 108 are flush after the planarization process is completed.

[0099] exist Figure 35 In the embodiment of the present invention, the insulating material 54 is etched back to expose the sidewalls of the fin 52 and define the STI region 56. The insulating material 54 can be etched back using the method described above. Figure 13 As a result of the etch back, the top surface of STI region 56 may be below the top surface of film 104, above the top surface of film 104 (e.g., see Figure 36B ), or is substantially flush with the top surface of the membrane 104 (e.g., see Figure 36C ).

[0100] exist Figure 36A-Figure 36BIn this embodiment, film 106 is etched and at least partially removed from the sidewalls of film 108 . Figure 36A An embodiment is shown in which the top surface of STI region 56 is lower than the top surface of film 104; Figure 36B An embodiment is shown in which the top surface of STI regions 56 is higher than the top surface of film 104; and Figure 36C An embodiment is shown in which the top surface of STI region 56 is substantially flush with the top surface of membrane 104. Figure 14 A similar process as described is used to etch membrane 106. Thus, fin 52' is formed. Dummy fin 52' may be embedded in STI region 56. For example, STI region 56 may extend below and cover the bottom surface of dummy fin 52'.

[0101] The middle portion of the dummy fin 52' has a width D2, which may be smaller than the width D1 of the bottom of the dummy fin 52'. By reducing the width D2 of the dummy fin 52', the space between the dummy fin 52' and the fin 52 can be increased. Therefore, the gate material can be formed around the fin 52 and the dummy fin 52' with an increased process window, and manufacturing defects can be reduced.

[0102] Although Figures 36A-36C The dummy fin 52' is shown as having a particular configuration, but other embodiments contemplate different configurations of the dummy fin 52' in the device 20. For example, as described above with respect to Figures 15A to 15H Any of the configurations described may be incorporated into device 20 .

[0103] Subsequent processes may be performed on the device to form a FinFET. For example, the process described above with respect to Figures 16A to 28B Similar processes are performed to form source / drain regions 82 in fin 52 and gate stacks are formed over and along the sidewalls of fin 52 and dummy fin 52'. Dummy fin 52' can physically separate adjacent source / drain regions 82, and dielectric region 78 can extend through gate stack to dummy fin 52'. The resulting structure is Figures 37A-37C Shown in.

[0104] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are formed by patterning a stack of alternating layers of channel layers and sacrificial layers. A dummy gate stack and source / drain are formed in a similar manner as described above. After removing the dummy gate stack, the sacrificial layer can be partially or completely removed in the channel region. A replacement gate structure is formed in a similar manner as described above and will partially or completely surround the channel layer in the channel region of the NSFET device. An ILD and contacts to the gate structure and source / drain are formed in a similar manner as described above. The nanostructured device can be formed as disclosed in U.S. Patent Application Publication 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0105] In various embodiments, dummy fins can be used to separate the metal gates of adjacent transistors. Dummy fins can also help isolate adjacent source / drain regions by, for example, preventing accidental source / drain merging during the epitaxial growth process. Various embodiments include forming a first film on the sidewalls and bottom surface of a second film. The first film is then etched and at least partially removed from the sidewalls of the second film to reduce the width of the resulting dummy fin. Thus, the profile of the dummy fin can be improved. For example, the middle portion of the dummy fin can be narrower than the bottom of the dummy fin (e.g., having a smaller CD). In this way, the spacing between the dummy fin and the channel region can be increased, and the process window for gate stack gap filling can be increased.

[0106] In some embodiments, a device includes: a first source / drain region located above a semiconductor substrate; a dummy fin adjacent to the first source / drain region, the dummy fin including: a first portion including a first film; a second portion located above the first portion, the second portion having a width smaller than the first portion, wherein the second portion includes: a second film; and a third film located between the first and second films, the third film being made of a different material than the first and second films; and a gate stack located along sidewalls of the dummy fin. In some embodiments, the third film extends along the sidewalls of the second film. In some embodiments, the third film extends to the uppermost surface of the second film. In some embodiments, the chemical bonding energy of the material of the third film is smaller than the chemical bonding energy of the material of the second film. In some embodiments, the first source / drain region contacts the second film. In some embodiments, the device further includes: a second source / drain region located on a side of the dummy fin opposite the first source / drain region, wherein the second source / drain region contacts the second film. In some embodiments, the second portion further includes: a fourth film located above the second film, the fourth film being made of a different material than the second film. In some embodiments, the device further comprises: a dielectric region located above and in contact with the dummy fin, wherein the gate stack extends along sidewalls of the dielectric region. In some embodiments, a first surface of the third film adjacent to the first film has a width smaller than a second surface of the third film adjacent to the second film. In some embodiments, a first surface of the third film adjacent to the first film has a width larger than a second surface of the third film adjacent to the second film. In some embodiments, the third film has concave sidewalls.

[0107] In some embodiments, a device includes: a first transistor located at a top surface of a semiconductor substrate, the first transistor including: a first channel region; and a first gate stack located above and along sidewalls of the first channel region; a second transistor located at the top surface of the semiconductor substrate, the second transistor including: a second channel region; and a second gate stack located above and along sidewalls of the second channel region; and a dummy fin physically separating the first gate stack from the second gate stack, wherein the dummy fin includes: a first film; and a second film located above the first film, wherein a width of the dummy fin measured at the level of the second film is less than a width of the dummy fin measured at the level of the first film. In some embodiments, the device further includes: a spacer layer along the sidewalls and bottom surface of the first film. In some embodiments, the device further includes: a third film located between the first film and the second film. In some embodiments, the dummy fin is embedded in an isolation region. In some embodiments, the dummy fin is in contact with the semiconductor substrate.

[0108] In some embodiments, a method includes: defining an opening between a first semiconductor fin and a second semiconductor fin; forming a dummy fin between the first semiconductor fin and the second semiconductor fin, wherein forming the dummy fin includes: depositing a first film in the opening; recessing the first film in the opening; depositing a second film in the opening over the first film; depositing a third film in the opening over the second film, the second film disposed on sidewalls and a bottom surface of the third film; and etching the second film to at least partially remove the second film from sidewalls of the third film; and forming a gate structure along the sidewalls and top surfaces of the first semiconductor fin, the second semiconductor fin, and the dummy fin. In some embodiments, the method further includes: depositing a spacer layer along the sidewalls and bottom surfaces of the opening before depositing the first film, wherein depositing the first film includes depositing the first film over the spacer layer. In some embodiments, forming the dummy fin further includes: recessing the third film below a topmost surface of the second film; and depositing a fourth film in the opening over the third film, the second film disposed on sidewalls of the fourth film. In some embodiments, etching the second film includes a selective etching process that etches the second film at a faster rate than etching the third film.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments or examples introduced herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0110] Example 1. A semiconductor device, comprising: a first source / drain region located on a semiconductor substrate; a dummy fin adjacent to the first source / drain region, the dummy fin comprising: a first portion comprising a first film; and a second portion located on the first portion, the width of the second portion being smaller than the width of the first portion, wherein the second portion comprises: a second film; and a third film located between the first film and the second film, the third film being made of a material different from the first film and the second film; and a gate stack along the sidewalls of the dummy fin.

[0111] Example 2. The semiconductor device of Example 1, wherein the third film extends along a sidewall of the second film.

[0112] Example 3. The semiconductor device of Example 1, wherein the third film extends to an uppermost surface of the second film.

[0113] Example 4. The semiconductor device of Example 1, wherein a chemical bonding energy of a material of the third film is smaller than a chemical bonding energy of a material of the second film.

[0114] Example 5. The semiconductor device of Example 1, wherein the first source / drain region is in contact with the second film.

[0115] Example 6. The semiconductor device of Example 1, further comprising: a second source / drain region located on a side of the dummy fin opposite to the first source / drain region, wherein the second source / drain region is in contact with the second film.

[0116] Example 7. The semiconductor device of Example 1, wherein the second portion further comprises: a fourth film located on the second film, and the fourth film is made of a material different from that of the second film.

[0117] Example 8. The semiconductor device of Example 1, further comprising: a dielectric region over and in contact with the dummy fin, wherein the gate stack extends along a sidewall of the dielectric region.

[0118] Example 9. The semiconductor device of Example 1, wherein a width of a first surface of the third film adjacent to the first film is smaller than a width of a second surface of the third film adjacent to the second film.

[0119] Example 10. The semiconductor device of Example 1, wherein a width of a first surface of the third film adjacent to the first film is greater than a width of a second surface of the third film adjacent to the second film.

[0120] Example 11. The semiconductor device of Example 1, wherein the third film has a concave sidewall.

[0121] Example 12. A semiconductor device comprising: a first transistor located at the top surface of a semiconductor substrate, the first transistor comprising: a first channel region; and a first gate stack located above and along the sidewalls of the first channel region; a second transistor located at the top surface of the semiconductor substrate, the second transistor comprising: a second channel region; and a second gate stack located above and along the sidewalls of the second channel region; and a dummy fin physically separating the first gate stack from the second gate stack, wherein the dummy fin comprises: a first film; and a second film located above the first film, wherein a width of the dummy fin measured at the level of the second film is smaller than a width of the dummy fin measured at the level of the first film.

[0122] Example 13. The semiconductor device of Example 12, further comprising: a spacer layer along the sidewalls and bottom surface of the first film.

[0123] Example 14. The semiconductor device according to Example 12, further comprising: a third film located between the first film and the second film.

[0124] Example 15. The semiconductor device of Example 12, wherein the dummy fin is embedded in an isolation region.

[0125] Example 16. The semiconductor device of Example 12, wherein the dummy fin is in contact with the semiconductor substrate.

[0126] Example 17. A method for manufacturing a semiconductor device, comprising: defining an opening between a first semiconductor fin and a second semiconductor fin; forming a dummy fin between the first semiconductor fin and the second semiconductor fin, wherein forming the dummy fin comprises: depositing a first film in the opening; recessing the first film in the opening; depositing a second film over the first film in the opening; depositing a third film over the second film in the opening, the second film being disposed on the sidewalls and bottom surface of the third film; and etching the second film to at least partially remove the second film from the sidewalls of the third film; and forming a gate structure along the sidewalls and top surfaces of the first semiconductor fin, the second semiconductor fin, and the dummy fin.

[0127] Example 18. The method of Example 17, further comprising: depositing a spacer layer along sidewalls and a bottom surface of the opening before depositing the first film, wherein depositing the first film comprises depositing the first film over the spacer layer.

[0128] Example 19. The method of Example 17, wherein forming the dummy fin further comprises: recessing the third film below a topmost surface of the second film; and depositing a fourth film over the third film in the opening, the second film disposed on sidewalls of the fourth film.

[0129] Example 20. The method of Example 17, wherein etching the second film comprises a selective etching process that etches the second film at a faster rate than etching the third film.

Claims

1. A semiconductor device comprising: a first source / drain region located on the semiconductor substrate; a dummy fin, adjacent to the first source / drain region, the dummy fin comprising: a first portion comprising a first film; and a second portion, located above the first portion, wherein the width of the second portion is smaller than the width of the first portion, wherein the second portion includes: a second film; and a third film located between the first film and the second film, the third film being made of a material different from that of the first film and the second film; and The gate stack, along the sidewalls of the dummy fin, The bottom of the second film is above the top of the first film.

2. The semiconductor device according to claim 1, wherein The third film extends along a sidewall of the second film.

3. The semiconductor device according to claim 1, wherein The third film extends to the uppermost surface of the second film.

4. The semiconductor device according to claim 1, wherein The chemical bonding energy of the material of the third film is smaller than the chemical bonding energy of the material of the second film. The semiconductor device according to claim 1 , wherein The first source / drain region is in contact with the second film.

6. The semiconductor device according to claim 1, further comprising: A second source / drain region is located on a side of the dummy fin opposite to the first source / drain region, wherein the second source / drain region is in contact with the second film.

7. The semiconductor device according to claim 1, wherein The second portion further includes a fourth film located on the second film, and the fourth film is made of a material different from that of the second film.

8. The semiconductor device according to claim 1, further comprising: A dielectric region is located above and in contact with the dummy fin, wherein the gate stack extends along a sidewall of the dielectric region.

9. The semiconductor device according to claim 1, wherein A width of a first surface of the third film adjacent to the first film is smaller than a width of a second surface of the third film adjacent to the second film.

10. The semiconductor device according to claim 1, wherein A width of a first surface of the third film adjacent to the first film is greater than a width of a second surface of the third film adjacent to the second film.

11. The semiconductor device according to claim 1, wherein The third film has a concave sidewall.

12. A semiconductor device comprising: a first transistor located at a top surface of the semiconductor substrate, the first transistor comprising: a first channel region; and a first gate stack located above the first channel region and along a sidewall of the first channel region; a second transistor located at a top surface of the semiconductor substrate, the second transistor comprising: a second channel region; and a second gate stack located above the second channel region and along a sidewall of the second channel region; and A dummy fin physically separates the first gate stack from the second gate stack, wherein the dummy fin comprises: First membrane; a second film overlying the first film, wherein a width of the dummy fin measured at a level of the second film is smaller than a width of the dummy fin measured at a level of the first film, and wherein a bottommost portion of the second film is above a topmost portion of the first film; and The third film is located between the first film and the second film.

13. The semiconductor device according to claim 12, further comprising: A spacer layer is provided along the sidewalls and bottom surface of the first film.

14. The semiconductor device according to claim 12, wherein The dummy fin is embedded in the isolation region.

15. The semiconductor device according to claim 12, wherein The dummy fin contacts the semiconductor substrate.

16. A method for manufacturing a semiconductor device, comprising: defining an opening between the first semiconductor fin and the second semiconductor fin; A dummy fin is formed between the first semiconductor fin and the second semiconductor fin, where the forming of the dummy fin comprises: depositing a first film in the opening; recessing the first film in the opening; depositing a second film over the first film in the opening; depositing a third film over the second film in the opening, the second film being disposed on sidewalls and a bottom surface of the third film; and etching the second film to at least partially remove the second film from sidewalls of the third film; and A gate structure is formed along sidewalls and top surfaces of the first semiconductor fin, the second semiconductor fin, and the dummy fin.

17. The method according to claim 16, further comprising: Prior to depositing the first film, a spacer layer is deposited along sidewalls and a bottom surface of the opening, wherein depositing the first film includes depositing the first film over the spacer layer.

18. The method according to claim 16, wherein Forming the dummy fin further includes: recessing the third film below the topmost surface of the second film; and A fourth film is deposited over the third film in the opening, and the second film is disposed on a sidewall of the fourth film.

19. The method according to claim 16, wherein Etching the second film includes a selective etching process that etches the second film at a faster rate than etching the third film.

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