Vertical conduction electron power device with reduced on-resistance and manufacturing process

Abstract

Embodiments of the present disclosure relate to vertical conduction electronic power devices with reduced on-resistance and manufacturing processes. A vertical conduction electronic power device includes a body defined by a first surface and a second surface and having an epitaxial layer of a semiconductor material, and a substrate. The epitaxial layer is defined by the first surface of the body and the substrate is defined by the second surface of the body. The epitaxial layer includes at least a first conduction region and a second conduction region, has a first doping type, and a plurality of insulated gate regions extending within the epitaxial layer. The substrate has at least one silicide region extending from the second surface of the body toward the epitaxial layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a vertical conduction electronic power device with reduced on-resistance and a manufacturing process thereof. In particular, reference will be made hereinafter to MOSFET devices. BACKGROUND

[0002] It is known that power MOSFETs, in particular vertical conduction MOSFETs, are electronic devices characterized, for example, by high switching speed, high energy efficiency, and ease of manufacturing and integration rate. For this reason, they are currently widely used in various electronic systems.

[0003] In particular, depending on the value of the reference voltage level, such electronic systems can be divided into two categories (low voltage or high voltage).

[0004] For low voltage applications, for example for reference voltage levels lower than 200 V, typically used in electrical power supply systems, DC-DC converters and engine control units, it is required that, during operation, the current path between the source terminal and the drain terminal of the electronic device has a drain-to-source on-resistance R DSon (also referred to below as on-resistance R DSon ) as low as possible, in order to limit the energy consumption.

[0005] As shown in the cross-sectional view of Fig. 1, one of the possible implementations of a vertical conduction power MOSFET device comprises providing a trench-gate terminal. Figure 1

[0006] The vertical conduction power MOSFET device 1 with trench-gate terminal is generally formed by a plurality of structures identical to each other, arranged in parallel in the same chip, and only one of them is shown in Fig. 1. Figure 1

[0007] The MOSFET device 1 is formed in a body 20 of semiconductor material having a first surface 20A and a second surface 20B, and comprises a substrate 2 and an epitaxial layer 4 which overlap each other.

[0008] The substrate 2 has a first doping type, for example made of N-doped silicon, typically having a thickness of 250 pm, and forms the second surface 20B of the body 20.

[0009] A bottom metallization region, typically formed by a stack of layers of conductive material such as titanium, nickel and gold, extends below the second surface 20B of the body 20, is in electrical contact with the second surface 20B and forms a drain terminal 3 which constitutes a conduction terminal of the MOSFET device 1.

[0010] ​​Furthermore, the epitaxial layer 4 has a first doping type (eg, N-doped silicon), and the epitaxial layer 4 has a doping level lower than the doping level of the substrate 2 .

[0011] The epitaxial layer 4 includes a plurality of active regions 5 , a plurality of source regions 6 , a plurality of first enriched regions 7 and second enriched regions 8 , a plurality of insulated gate regions 9 and a drift region 10 .

[0012] In detail, the insulated gate region 9 extends from the first surface 20A of the body 20 through the epitaxial layer 4 along the first axis Z of the Cartesian reference system XYZ, and includes a portion 9A of a conductive material (e.g., polysilicon) and an insulating layer 9B (e.g., of silicon oxide). The insulating layer 9B surrounds the portion 9A to electrically insulate it from the epitaxial layer 4. Furthermore, the insulated gate regions 9 are spaced apart from one another along the second axis X of the reference system XYZ.

[0013] Each source region 6 extends from the first surface 20A in the epitaxial layer 4 to a depth that is less than the depth of the insulating gate regions 9 (along the first axis Z) and covers a distance that separates two adjacent insulating gate regions 9 along the second axis X. In addition, each source region 6 has a first doping type (here, N-type doping) with a doping level that is much higher than the doping level of the epitaxial layer 4, for example, greater than 10 19 atoms / cm 3 .

[0014] Each active region 5 extends below the source region 6 along the first axis Z, to a depth that is less than the depth of the insulating gate region 9. Each active region 5 covers the distance separating two adjacent insulating gate regions 9 along the second axis X, and each active region 5 has the second doping type (here, P-type doping).

[0015] Each first enriched region 7 is arranged inside the corresponding active region 5 and has a second doping type (here, P-type doping). The doping level of the first enriched region 7 is higher than the doping level of the active region 5, for example, higher than 5·10 17 atoms / cm 3 .

[0016] Each second enriched region 8 is arranged approximately inside the corresponding active region 5 and contacts the corresponding source region 6 at the top and contacts the corresponding first enriched region 7 at the bottom. In addition, each second enriched region 8 has a second doping type (here, P-type doping), and the second enriched region 8 has a doping level higher than the doping level of the first enriched region 7.

[0017] The portion of the epitaxial layer 4 arranged between the substrate 2 and the active region 5 (and the insulated gate region 9 ) forms a drift region 10 .

[0018] The device also has a top metallization region of a conductive material (for example, aluminum) which forms the source terminal 12 and constitutes a further conductive terminal of the MOSFET device 1 ; a dielectric insulation region 11, for example constituted by silicon oxide or borophosphosilicate glass (BPSG), and a plurality of metal contact regions 13, for example constituted by a conductive material (for example, tungsten).

[0019] The dielectric insulation region 11 is arranged on the first surface 20A of the body 20 and the source terminal 12 is arranged above the dielectric insulation region 11. In this way, the dielectric insulation region 11 electrically insulates the source terminal 12 from the epitaxial layer 4.

[0020] Each metal contact region 13 extends along the first axis Z, between and in direct electrical contact with the source terminal 12 and the respective second enrichment region 8, passing through the dielectric insulation region 11 and the respective source region 6.

[0021] The source terminal 12, the metal contact regions 13, and the first and second enrichment regions 7, 8 form an input region 14 of the MOSFET device 1 characterized by an input resistance Rin.

[0022] The source regions 6, together with the respective portions of the active regions 5, form a channel region 15 having a channel resistance Rc. Furthermore, the drain terminal 3 has an output resistance Ro, the drift region 10 has a drift resistance Rd, and the substrate 2 has a substrate resistance Rs.

[0023] In use, the MOSFET device 1 switches between a first phase (off phase) and a second phase (on phase) depending on the way in which a bias voltage is applied to the insulated gate region 9.

[0024] In the on phase, a vertical conduction channel is formed in each active region 5 along the first axis Z, an electrical closure exists in the current path between the source terminal 12 and the drain terminal 3, and the current path is formed by the input region 14, the channel region 15, the drift region 10, the substrate 2 and the drain terminal 3, which are connected together in series from an electrical point of view. As mentioned above, associated with said current path is, in the on phase, an on resistance RDSon which should be as low as possible in low reference voltage applications.

[0025] In this phase, in general, the resistances mentioned above (input resistance Rin, channel resistance Rc, output resistance Ro, drift resistance Rd and substrate resistance Rs) constitute the main resistance components of the current path. Nonetheless, other resistance components can be included in the current path depending on the design of the MOSFET device 1.

[0026] Typically, the input resistance Rin and the output resistance Ro are very low, since they are mainly formed by metallic connection elements.

[0027] The channel resistance Rc is determined at the design stage by the physical dimensions and the density of the charge carriers of the channel region 15.

[0028] The drift resistance Rd determines the breakdown voltage of the MOSFET device 1 and is therefore accurately selected at the design stage by setting the thickness and the doping level of the drift region 10, according to the required breakdown voltage and the application of the device in which the integrated MOSFET device 1 is to be used.

[0029] The substrate resistance Rs constitutes an unwanted resistance in the current path, especially in the need to switch on the resistance R DSon as low as possible in the above-mentioned low-voltage applications.

[0030] In practice, in fact, the substrate 2 has substantially only the function of mechanical support, without which the MOSFET device 1 would be mechanically fragile during both the manufacturing steps and the assembly steps in the electronic apparatus.

[0031] Obviously, the substrate resistance Rs depends on the thickness and the doping level of the substrate 2.

[0032] The current state of the art therefore includes thinning the substrate 2 or increasing its doping level, in order to reduce the value of the substrate resistance Rs to a minimum.

[0033] However, the thinning of the substrate 2 (for example, via grinding) has limitations. As mentioned above, in fact, in order not to compromise the mechanical strength of the MOSFET device, the thickness of the substrate cannot be reduced to zero, and therefore the resistance value cannot be reduced below a certain threshold.

[0034] On the other hand, increasing the doping level requires the introduction of additional manufacturing steps and therefore increases the manufacturing complexity and the related costs of the power MOSFET device.

[0035] A different solution is described in the US patent US 2002 / 0197832 Al, which includes digging a trench at the bottom of the substrate of the power MOSFET device and filling it with a conductive material, such as copper or polysilicon. The trench can be obtained, for example, via selective electrochemical removal.

[0036] In this way, the substrate of the device is formed by an alternation of regions of conductive material and regions of semiconductor, electrically connected in parallel. The presence of the metal regions allows the substrate resistance to be reduced; at the same time, the mechanical stability of the substrate is guaranteed.

[0037] However, the above-mentioned solution does not allow sufficiently low resistance values to be obtained for certain applications. SUMMARY

[0038] In various embodiments, the present disclosure provides a vertically conducting electronic power device that will enable reduced turn-on resistance.

[0039] According to the present disclosure, a vertically conducting electronic power device and a manufacturing process thereof are provided.

[0040] In at least one embodiment, a vertically conducting electronic power device is provided, comprising: a body having a first surface and a second surface, and comprising an epitaxial layer of semiconductor material and a substrate. The epitaxial layer is bounded by the first surface of the body, and the substrate is bounded by the second surface of the body. The epitaxial layer contains at least a first and a second conductive region, having a first doping type. A plurality of insulated gate regions extends on the first surface of the body or within the epitaxial layer. The substrate has at least one silicide region extending from the second surface of the body towards the epitaxial layer.

[0041] In at least one embodiment, a method for manufacturing a vertically conducting electronic power device is provided, the method comprising: forming a plurality of insulated gate regions on a wafer of semiconductor material, the wafer comprising an epitaxial layer and a substrate, and having a first surface and a second surface, the plurality of insulated gate regions being formed on the first surface of the wafer or within the epitaxial layer; forming a first and a second conductive region within the epitaxial layer; and, forming at least one silicide region in the substrate, the silicide region extending from the second surface of the body towards the epitaxial layer.

[0042] In at least one embodiment, a device comprising a substrate is provided, the substrate comprising a silicide layer. An epitaxial layer of semiconductor material is disposed on the silicide layer, and the epitaxial layer comprises: a drift region having a first doping type, on and in contact with the silicide layer; an active region having a second doping type, on the drift region; and, a source region on the active region. The source region has the first doping type and has a higher concentration than the first doping type of the drift region. A first and a second insulated gate region extend from a surface of the epitaxial layer into the drift region, and the active region and the source region are disposed between and contiguous to the first and the second insulated gate regions. BRIEF DESCRIPTION OF DRAWINGS

[0043] For a better understanding of the present disclosure, some embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings in which:

[0044] Figure 1 is a cross-sectional view of a known vertically conducting power MOSFET device;

[0045] Figures 2 to 7is a cross-sectional view of the present MOSFET device in a continuous manufacturing step;

[0046] Figure 8 a vertically conducting power MOSFET device is shown, in accordance with at least one embodiment; and

[0047] Figure 9 another embodiment of the present vertically conducting power MOSFET device is shown. DETAILED DESCRIPTION

[0048] Described below are steps for manufacturing a vertically conducting power MOSFET device, which can be used in electronic devices, in particular devices operating at low reference voltages.

[0049] In particular, the manufacturing steps described below lead to the production of a MOSFET device having a general structure similar to the one shown in Figure 1 Fig. 1. Therefore, the same elements as the ones described with reference to Figure 1 Fig. 1 are denoted by the same reference numerals raised by 50.

[0050] In detail, Figure 2 is a cross-sectional view of the wafer 50 processed in a manner known to the person skilled in the art, for example in a manner similar to the one described in European Patent Application No. 3396718. In particular, in the wafer 50, a substrate 52 and an epitaxial layer 54 (forming a body 70 having a first surface 70A and a second surface 70B coinciding with the surfaces delimiting the wafer 50), an active region 55, a source region 56, a first and a second enrichment region 57, 58, an insulating gate region 59, a drift region 60 and a dielectric insulating region 61 have been provided. Furthermore, a metal contact layer 48 has been deposited on the dielectric insulating region 61, which fills the contact trenches 49 dug in the dielectric insulating region 61 (in which the metal contact regions 63 are formed) and has a surface portion 48’ extending on the dielectric insulating region 61 itself.

[0051] Furthermore, a patterned layer 82, for example made of a photosensitive material such as a resist, has been deposited on the second surface 70B of the body 70 and has been patterned via a photolithography process to form a plurality of cavities 83 having a circular cross-section, for example with a diameter in the range of 0.5 pm to 3 pm, in some embodiments in the range of 1 pm to 2 pm.

[0052] Figure 3The wafer 50 is shown after a chemical etching is performed on the second surface 70B of the body 70. The chemical etching enables a selective removal of portions of the substrate 52 at the cavities 83, thus forming a plurality of trenches 84 extending for a high depth along the first axis Z. For example, for a substrate having a depth of 250 pm, the depth of the trenches 84 can be in the range of 150 pm to 250 pm; however, these values are not limiting and the trenches 84 can extend through the entire thickness of the substrate, up to reaching a minimum distance from the epitaxial layer 54, typically not less than 1 pm. Likewise, in the case of a thinner or thicker substrate, the trenches 84 can extend only through a portion of the substrate 52, or up to reaching a minimum distance from the epitaxial layer 54 not less than 1 pm. In practice, the substrate 52 is now formed by the trenches 84 alternating with the semiconductor pillars 81.

[0053] The formation of the trenches 84 can be performed by means of processes known to the person skilled in the art, such as, for example, color etching, metal-assisted chemical etching, and reactive ion etching.

[0054] Next, as shown in Figure 4 , the patterned layer 82 is removed and a metal layer 85 of conductive material is deposited, for example, a transition metal such as titanium or tungsten if the substrate 52 has an N-type doping, or cobalt or chromium if the substrate 52 has a P-type doping.

[0055] The metal layer 85 is deposited to completely fill the trenches 84 and forms a surface portion 85’ covering the second surface 70B of the body 70.

[0056] In Figure 5 , the wafer 50 is annealed at a temperature in the range of 700 °C to 900 °C for a period of time in the range of 1 minute to 2 minutes, the time depending on the temperature.

[0057] The above thermal budget is low enough not to affect the previously formed structures (active region 55, source region 56, first enrichment region 57 and second enrichment region 58), but enables the portion of the substrate 52 in contact with the metal layer 85 to chemically react with the metal layer 85 itself, to form a highly conductive silicide. For example, in the case where the metal layer 85 is titanium, titanium silicide (TiSi2) is obtained. At the end of the annealing process, the entire substrate 52 has undergone a silicidation reaction. In this way, all the silicon of the substrate 52 has been transformed into silicide, while in the present embodiment only the portion of the metal layer 85 in the trench 84, which has also been transformed into silicide, has been consumed. Therefore, the wafer 50 has, under the epitaxial layer 54, a metal drain layer 90 formed by silicide pillars 91 (resulting from the silicidation of the semiconductor pillars 81 with the portion of metal of the trench 84), which surrounds pillars of metal material 92 (the remaining portion of the metal layer 85, not reacted into silicide). Alternatively, depending on the metal used, the dimensions and the process parameters, all the metal present in the trench 84 can completely undergo a silicidation reaction, as shown below in Figure 8

[0058] The metal drain layer 90 thus formed has a higher conductivity than that of the doped semiconductor material (for example, N-doped silicon) from which the substrate 52 is made; considering that now the entire area of the metal drain layer 90 has a very high conductivity, this is also higher than the case of a substrate with a trench filled with metal material surrounded by a pillar of semiconductor material. In practice, the present solution enables a significant reduction of the electrical resistance Rs associated with the substrate 52, which now includes a greater surface with a very low resistivity, usable for the flow of current.

[0059] Next, in Figure 6 the wafer 50 is chemically etched (for example, anisotropic dry chemical etching) according to processes known to those skilled in the art, to remove the surface portion 48' of the metal contact layer 48. A first metallization layer 86 (for example, aluminum) is then deposited on the dielectric insulating region 61 and on the metal contact region 63, thus forming the source terminal 62.

[0060] Finally, in Figure 7 a second metallization layer 87 and a third metallization layer 88 are deposited in succession on the metal drain layer 90, to form the drain terminal 53. For example, the second metallization layer 87, consisting of a compound of nickel and palladium or nickel and vanadium, facilitates an ohmic contact with the underlying metal layer 85. For example, the third metallization layer 88, made of gold, silver or palladium, prevents oxidation of the first metallization layer 87.

[0061] The wafer 50 is then diced, and after the usual steps of electrical connection and packaging, each chip thus produced forms a MOSFET device 51.

[0062] ​Due to the fact that the substrate 52 corresponding to the metal drain layer 90 is now completely composed of metal, as described above, the present MOSFET device 51 has a very low substrate resistance Rs while maintaining mechanical stability and low manufacturing costs. In fact, the above-mentioned manufacturing steps can be easily integrated into the process for manufacturing current power MOSFET devices and do not require complex or expensive manufacturing processes.

[0063] Figure 8 MOSFET device 101 according to another embodiment is shown. MOSFET device 101 undergoes similar manufacturing steps as MOSFET device 51 and therefore has a similar structure; therefore, like elements are denoted by like reference numerals. Here, at the end of the annealing, all of the metal present in trench 84 has been completely reacted, and the area where the trench is present is also occupied by silicide. In practice, the silicide region 141 extends over the entire substrate 52 to form a metal drain layer 140, which is composed entirely of silicide and is arranged between the epitaxial layer 54 and the drain terminal 53. Obviously, in this case, the metal drain layer 140 also has a particularly low substrate resistance Rs, because it is made entirely of a material with an extremely low resistivity.

[0064] Alternatively, Figure 9 As shown in FIG, a MOSFET device 151 may be provided. Also here, the same elements as those of the MOSFET device 51 are denoted by the same reference numerals. In this embodiment, Figure 4 The semiconductor pillar 81 has completely reacted with the metal layer 85 to form a silicide pillar 91, while only a portion of the trench 84 has reacted to form a metal material pillar 92 to react with the metal layer 85. Figure 5 . Unlike the MOSFET device 51, an insulated gate region 109 is obtained on top of the epitaxial layer 54 and within the dielectric insulating region 61 in a manner known to those skilled in the art. Finally, it is obvious that modifications and variations can be made to the MOSFET devices 51, 101, 151 and the manufacturing processes described and illustrated herein without thereby departing from the scope of the present disclosure. For example, the various embodiments described can be combined to provide further solutions.

[0065] Furthermore, the described fabrication process can be used to reduce the substrate resistance of other vertically conducting power devices, for example devices with different designs of insulated gate regions, where it is necessary or beneficial for the resistance of the current path between the two conducting terminals to be as low as possible.

[0066] Finally, the doping types of the substrate, the epitaxial layer, the active region, the source region, and the first and second enriched regions may be opposite.

[0067] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the detailed description. In general, the selected terms used in the following claims are not to be construed as limiting the claims to the specific embodiments disclosed in the specification and the claims. Rather, the claims should be construed in accordance with the full extent permitted by the patent laws. Accordingly, it is appropriate that the claims be construed broadly.

Claims

1. A vertical conduction electronic power device comprising: a body having a first surface and a second surface and comprising a substrate and an epitaxial layer of a semiconductor material, the epitaxial layer being located between the first surface of the body and the substrate, the epitaxial layer comprising at least a first conductive region and a second conductive region having a first doping type; a plurality of insulated gate regions extending above the first surface of the body or within the epitaxial layer; a plurality of silicide pillars at the second surface, including a bottom distal from the epitaxial layer; as well as A metal layer on the bottom of the plurality of silicide pillars, the metal layer including a plurality of metal pillars extending partially through the substrate toward the epitaxial layer between the plurality of silicide pillars, wherein the lateral space between each pair of adjacent metal pillars is completely filled with a corresponding silicide pillar from the plurality of silicide pillars. 2 . The device of claim 1 , wherein the substrate is entirely formed of the plurality of silicide pillars.

3. The device of claim 1 , wherein the plurality of silicide pillars collectively form the substrate, the plurality of silicide pillars extending from the second surface of the body toward the epitaxial layer and at least partially surrounding corresponding metal pillars among a plurality of metal pillars and separating adjacent corresponding metal pillars among the plurality of metal pillars from each other. The device of claim 1 , wherein the plurality of silicide pillars extend to the epitaxial layer. The device of claim 1 , wherein the device comprises a vertically conducting power transistor.

6. The device according to claim 1, further comprising: a first conductive terminal on the first surface of the body and in electrical contact with the first conductive region; as well as A second conductive terminal is on the second surface of the body and is in direct electrical contact with the plurality of silicide pillars.

7. A method for manufacturing a vertical conduction electronic power device, comprising: forming a plurality of insulated gate regions on a wafer of semiconductor material, the wafer having a first surface and a second surface and comprising a substrate and an epitaxial layer located between the first surface and the substrate, the plurality of insulated gate regions being formed on the first surface of the wafer or within the epitaxial layer; forming a first conductive region and a second conductive region in the epitaxial layer; forming a plurality of trenches extending partially through the substrate from the second surface toward the first surface, the plurality of trenches having respective ends closer to the epitaxial layer than the second surface, respective adjacent trenches of the plurality of trenches being separated from one another by pillars of semiconductor material of the substrate; forming a plurality of metal pillars in the corresponding trenches by depositing a metal material in the plurality of trenches; as well as A plurality of silicide pillars are formed in the substrate, the plurality of silicide pillars extending from the second surface toward the epitaxial layer, wherein a lateral space between each pair of adjacent metal pillars is completely filled with a corresponding silicide pillar from the plurality of silicide pillars.

8. The method according to claim 7, wherein forming the plurality of silicide pillars comprises: The wafer is annealed and the pillars of semiconductor material are reacted with the metallic material in the plurality of trenches.

9. The method of claim 8, wherein the annealing is continued until all of the pillars of semiconductor material are converted to suicide.

10. The method of claim 8, wherein the annealing occurs at a temperature in the range of 700°C to 900°C for a time in the range of 1 minute to 2 minutes.

11. The method of claim 8, wherein the trench extends into the substrate to within 1 μm of the epitaxial layer.

12. The method of claim 11, wherein the trench extends to a depth in the range of 150 µm to 250 µm into the substrate, and the trench has a width in the range of 1 µm to 3 µm.

13. The method according to claim 7, further comprising: forming a first metallized region on the first surface; as well as A second metallization region is formed on the second surface, wherein forming the plurality of silicide pillars is performed after forming the first conductive region and the second conductive region and before forming the first metallization region and forming the second metallization region.

14. The method of claim 8, wherein the substrate has N-type doping, and the metal material is one of titanium or tungsten.

15. The method of claim 8, wherein the substrate has a P-type doping, and the metal material is one of cobalt or chromium.

16. A semiconductor device comprising: a substrate, including a top surface and a bottom surface; a plurality of silicide pillars extending from the bottom surface toward the top surface; an epitaxial layer of semiconductor material, on the top surface, the epitaxial layer comprising: a drift region on and in contact with the plurality of silicide pillars, the drift region having a first doping type; an active region on the drift region, the active region having a second doping type different from the first doping type; and a source region, on the active region, the source region having the first doping type and having a higher concentration of the first doping type than the drift region; and a first insulating gate region and a second insulating gate region extending from a surface of the epitaxial layer into the drift region, the surface of the epitaxial layer being opposite to the top surface, the active region and the source region being arranged between the first insulating gate region and the second insulating gate region and being adjacent to the first insulating gate region and the second insulating gate region; and A metal layer on the bottom of the plurality of silicide pillars includes a plurality of metal pillars, the plurality of metal pillars extending partially through the substrate toward the epitaxial layer between the plurality of silicide pillars, wherein the lateral space between each pair of adjacent metal pillars is completely filled by a corresponding silicide pillar from the plurality of silicide pillars. The semiconductor device according to claim 16 , further comprising a dielectric layer on the epitaxial layer. 18 . The semiconductor device of claim 17 , further comprising a conductive terminal extending through the dielectric layer and into the source region, the conductive terminal being electrically coupled to the source region.

19. The device of claim 16, wherein the plurality of metal pillars are within 1 μm of the epitaxial layer.

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