Electrical converter system and method of manufacturing thereof

Abstract

An electrical converter system and a method of manufacturing the same are disclosed, which relate to parallel power switching devices for power conversion. An electrical converter system is provided, which includes a printed circuit board including at least a first layer and a second layer; a switching node disposed on the second layer; a first transistor, a second transistor, a third transistor, and a fourth transistor disposed on the first layer; a first conduction path from a source of the first transistor through the switching node to a drain of the fourth transistor, the first conduction path having a first length; and a second conduction path from a source of the first transistor through the switching node to a drain of the second transistor, the second conduction path having a second length, wherein the first length of the first conduction path is greater than the second length of the second conduction path.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Indian Patent Application No. 202011004303, filed on January 31, 2020, pursuant to 35 U.SC §119, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The embodiments of the present invention generally relate to power conversion, and more specifically, to a variety of parallel power switching devices for power conversion. Background Technology

[0004] As is well known, power supply devices such as uninterruptible power supplies (UPS) are used to provide regulated, uninterrupted power to sensitive and / or critical loads such as computer systems and other data processing systems. UPS typically includes various types of power converters for converting alternating current (AC) to direct current (DC), vice versa, and from one voltage level to another. These various power converters can include power switching circuits utilizing various types of switching devices, such as field-effect transistors (FETs), high electron mobility transistors (HEMTs), bipolar junction transistors (BJTs), and insulated-gate bipolar transistors (IGBTs). Summary of the Invention

[0005] At least one aspect of the present invention relates to an electrical converter system, comprising: a printed circuit board including at least a first layer and a second layer; a switching node disposed on the second layer; a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor being disposed on the first layer, the first transistor and the third transistor each having a source coupled to the switching node, and the second transistor and the fourth transistor each having a drain coupled to the switching node; a first conductive path from the source of the first transistor through the switching node to the drain of the fourth transistor, the first conductive path having a first length; and a second conductive path from the source of the first transistor through the switching node to the drain of the second transistor, the second conductive path having a second length, wherein the first length of the first conductive path is greater than the second length of the second conductive path.

[0006] In one embodiment, the converter system includes a third conduction path from the source of the third transistor through the switching node to the drain of the second transistor, the third conduction path having a third length; and a fourth conduction path from the source of the third transistor through the switching node to the drain of the fourth transistor, the fourth conduction path having a fourth length, wherein the third length of the third conduction path is greater than the fourth length of the fourth conduction path.

[0007] In some embodiments, a plurality of transistors are symmetrically arranged on the first layer such that a first distance between the first transistor and the second transistor is substantially the same as a second distance between the third transistor and the fourth transistor, and a third distance between the first transistor and the third transistor is substantially the same as a fourth distance between the second transistor and the fourth transistor. In some embodiments, the first length of the first conduction path is substantially the same as the third length of the third conduction path, and the second length of the second conduction path is substantially the same as the fourth length of the fourth conduction path.

[0008] In various embodiments, the electro-converter system includes a plurality of gate drive outputs and a plurality of gate drive conduction paths located between the plurality of gate drive outputs and the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor, wherein each of the plurality of gate drive conduction paths has substantially the same length.

[0009] In one embodiment, the power converter system includes a positive bus and a negative bus disposed on the first layer, wherein a drain of a first transistor and a drain of a third transistor are coupled to the positive bus, and a source of a second transistor and a source of a fourth transistor are coupled to the negative bus. In some embodiments, the power converter system includes a plurality of decoupling capacitors coupled between the positive bus and the negative bus, and disposed between the plurality of transistors and on the first layer above the switching node.

[0010] In some embodiments, each of the transistors is a gallium nitride (GaN) power transistor. In some embodiments, the gallium nitride power transistor is disposed in one of a through-hole device package and a surface mount device package.

[0011] Another aspect of the present invention relates to an electrical converter system, comprising: a printed circuit board including at least a first layer and a second layer; a switching node disposed on the second layer; a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor being disposed on the first layer, the first transistor and the third transistor each having a source coupled to the switching node, and the second transistor and the fourth transistor each having a drain coupled to the switching node; a first conductive path from the source of the first transistor through the switching node to the drain of the fourth transistor, the first conductive path having a first inductance; and a second conductive path from the source of the first transistor through the switching node to the drain of the second transistor, the second conductive path having a second inductance, wherein the first inductance of the first conductive path is greater than the second inductance of the second conductive path.

[0012] In one embodiment, the converter system includes a third conduction path from the source of the third transistor through the switching node to the drain of the second transistor, the third conduction path having a third inductance; and a fourth conduction path from the source of the third transistor through the switching node to the drain of the fourth transistor, the fourth conduction path having a fourth inductance, wherein the third inductance of the third conduction path is greater than the fourth inductance of the fourth conduction path.

[0013] In some embodiments, a plurality of transistors are symmetrically arranged on the first layer such that a first distance between the first transistor and the second transistor is substantially the same as a second distance between the third transistor and the fourth transistor, and a third distance between the first transistor and the third transistor is substantially the same as a fourth distance between the second transistor and the fourth transistor. In some embodiments, the first inductance of the first conduction path is substantially the same as the third inductance of the third conduction path, and the second inductance of the second conduction path is substantially the same as the fourth inductance of the fourth conduction path.

[0014] In various embodiments, the electro-converter system includes a plurality of gate drive outputs and a plurality of gate drive conduction paths located between the plurality of gate drive outputs and the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor, wherein each of the plurality of gate drive conduction paths has substantially the same length.

[0015] In one embodiment, the power converter system includes a positive bus and a negative bus disposed on the first layer, wherein a drain of a first transistor and a drain of a third transistor are coupled to the positive bus, and a source of a second transistor and a source of a fourth transistor are coupled to the negative bus. In some embodiments, the power converter system includes a plurality of decoupling capacitors coupled between the positive bus and the negative bus, and disposed between the plurality of transistors and on the first layer above the switching node.

[0016] In some embodiments, each of the transistors is a gallium nitride (GaN) power transistor. In some embodiments, the gallium nitride power transistor is disposed in one of a through-hole device package and a surface mount device package.

[0017] Another aspect of the present invention relates to a method for manufacturing an electrical converter system, the method comprising: providing a printed circuit board having at least a first layer and a second layer, a switching node disposed on the second layer; arranging a first transistor, a second transistor, a third transistor, and a fourth transistor on the first layer of the printed circuit board adjacent to the switching node; and coupling a source of the first transistor, a drain of the second transistor, a source of the third transistor, and a drain of the fourth transistor to the switching node such that a first length of a first conductive path from the source of the first transistor through the switching node to the drain of the fourth transistor is greater than a second length of a second conductive path from the source of the first transistor through the switching node to the drain of the second transistor.

[0018] In one embodiment, the method includes arranging a plurality of decoupling capacitors on a first layer between the plurality of transistors and above the switching node. In some embodiments, the method includes coupling the plurality of decoupling capacitors between a positive bus and a negative bus disposed on the first layer.

[0019] In some embodiments, arranging the plurality of transistors on the first layer further includes symmetrically arranging the plurality of transistors such that a first distance between the first transistor and the second transistor is substantially the same as a second distance between the third transistor and the fourth transistor, and a third distance between the first transistor and the third transistor is substantially the same as a fourth distance between the second transistor and the fourth transistor.

[0020] In some embodiments, the method includes coupling the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor to a plurality of gate driver outputs such that the length of each conduction path between the plurality of gate driver outputs and the gates of the plurality of transistors is substantially the same. Attached Figure Description

[0021] At least one embodiment will now be discussed with reference to the accompanying drawings, which are not intended to be drawn to scale. The drawings are included to provide illustration and further understanding of the aspects and embodiments, and are incorporated in and form part of this specification, but are not intended to be a limitation of the invention. In the drawings, each identical or substantially identical component shown in the various figures is represented by similar numbers. For clarity, not every component may be labeled in every figure. In the figures:

[0022] Figure 1This is a functional block diagram of an uninterruptible power supply (UPS) according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of a power switching circuit according to an embodiment of the present invention;

[0024] Figure 3A This is a diagram of a power switching component according to an embodiment of the present invention;

[0025] Figure 3B This is a diagram of a power switching component according to an embodiment of the present invention;

[0026] Figure 4A This is a diagram of a power switching application according to an embodiment of the present invention;

[0027] Figure 4B This is a diagram of a power switching application according to an embodiment of the present invention;

[0028] Figure 5A A diagram of a power switching assembly according to an embodiment of the present invention; and

[0029] Figure 5B This is a diagram of a power switching component according to an embodiment of the present invention. Detailed Implementation

[0030] The examples of methods and systems discussed herein are not limited to the details of construction and the arrangement of components set forth in the following description or shown in the accompanying drawings. The methods and systems can be implemented in other embodiments and can be practiced or performed in various ways. The examples of specific implementations provided herein are for illustrative purposes only and are not intended to be limiting. In particular, actions, components, elements, and features discussed in conjunction with any one or more examples are not intended to exclude similar roles in any other examples.

[0031] Similarly, the wording and terminology used herein are for descriptive purposes and should not be considered restrictive. Any reference to examples, embodiments, components, elements, or actions of systems and methods mentioned herein in the singular may include multiple forms, and any reference herein in the plural may include only the singular embodiments. References in the singular or plural form are not intended to limit the systems or methods, their components, actions, or elements currently disclosed. The use of “including,” “comprising,” “having,” “containing,” “involving,” and variations thereof herein is intended to cover the items listed thereafter and their equivalents, as well as other items. References to “or” may be interpreted as inclusive, such that any term described using “or” may refer to a single, more than one, and any one of all the described terms. Furthermore, if there is any inconsistency in the use of terminology between this document and a document incorporated herein by reference, the terminology used in the incorporated reference shall supplement the terminology used in this document; in the case of irreconcilable inconsistencies, the terminology used in this document shall prevail.

[0032] As described above, power supply devices such as uninterruptible power supplies (UPS) can be used to provide regulated, uninterrupted power to sensitive and / or critical loads. An online UPS uses a power factor correction converter (PFC) circuit to rectify the input alternating current (AC) supplied by the power company to provide DC power to at least one direct current (DC) bus. When mains power is available, the rectified DC power on the DC bus can be used to charge the battery. In the absence of mains power, the battery discharges and provides DC power to the DC bus. An inverter generates an AC output voltage from the DC power on the DC bus, which is provided to a load. Because power is supplied to the DC bus from mains power or a battery, the UPS output power will not be interrupted if the mains power fails and the battery is fully charged. Online UPSs can also operate in bypass mode, in which unconditioned power with basic protection functions can be supplied directly to the load from the AC power supply via a bypass line.

[0033] Figure 1This is a block diagram of one embodiment of a UPS 100, which provides regulated power from input AC power received at an input 102 and backup power from a battery 112 to an output 110. The UPS 100 includes a converter 104, a DC bus 106, an inverter 108, and a controller 114 for controlling the converter and the inverter. The converter 104 is coupled to the input 102, the inverter 108 is coupled to the output 110, and the DC bus 106 is coupled between the converter 104 and the inverter 108.

[0034] The input 102 is configured to receive an input AC power having an input voltage level from an AC power source. The controller 114 monitors the input AC power received by the input 102 and is configured to operate the UPS 100 in different operating modes based on the state of the input AC power received by the input 102. When the AC power supplied to the input 102 is acceptable (i.e., above an input power threshold), the controller 114 operates the UPS 100 in an online operating mode.

[0035] In online operation mode, AC power from input 102 can be supplied to converter 104. According to one embodiment, converter 104 is a power factor correction (PFC) converter; however, in other embodiments, other types of converters may be used. Controller 114 operates converter 104 to convert AC power to DC power and supplies the DC power to DC bus 106. DC power from DC bus 106 is supplied to inverter 108. Furthermore, DC power from DC bus 106 can be supplied directly from converter 104 or via a DC / DC converter to battery 112 for charging. Controller 114 operates inverter 108 to convert the DC power to regulated AC power and supplies the regulated AC power to a load coupled to output 110.

[0036] When the AC power supplied to input 102 is unacceptable (i.e., below an input power threshold), the controller 114 operates the UPS 100 in a standby operating mode. In this standby operating mode, DC power from the battery 112 is supplied to the DC bus 106 directly or via a DC / DC converter. The inverter 108 receives DC power from the DC bus 106, and the controller 114 operates the inverter 108 to convert the DC power from the DC bus 106 into regulated AC power and supply the regulated AC power to the output 110.

[0037] As mentioned above, a UPS can include various types of power converters for converting AC to DC, DC to AC, and DC from one DC voltage level to another. These various power converters are known to include power switching circuits utilizing switching devices, such as field-effect transistors (FETs), high-electron-mobility transistors (HEMTs), bipolar junction transistors (BJTs), and insulated-gate bipolar transistors (IGBTs). Gallium nitrate (GaN) is a common wide-bandgap material used to fabricate such switching devices for power switching applications. In some examples, GaN FETs can provide high switching speeds to reduce switching losses, enabling high-frequency power converter designs. Furthermore, GaN FETs exhibit low on-resistance even at high temperatures and high voltages.

[0038] In power switching applications, voltage and current can be switched at a high rate through GaN devices to reduce switching losses. In some examples, this high rate of change, combined with the parasitic capacitance and inductance associated with the GaN device and / or printed circuit boards (PCBs), can generate current oscillations and / or voltage overshoots. These current oscillations and voltage overshoots can damage or destroy GaN devices, and in some cases, ultimately lead to GaN device failure.

[0039] The aforementioned limitations can increase significantly when two or more GaN devices are configured in parallel to increase the power rating of a power converter. In some examples, power switching circuits that include parallel GaN devices may be affected by increased parasitic capacitance and inductance, which can lead to severe electromagnetic interference, current oscillations, voltage overshoot, and uneven dynamic current sharing among multiple GaN devices.

[0040] Some methods to mitigate issues associated with parallel GaN devices include adding passive components, such as ferrite beads and resistive-capacitive (RC) buffers, to suppress oscillations and overshoot. However, ferrite beads connected in series with GaN devices introduce additional inductance into the signal path, while RC buffers result in additional losses, degrading performance in high-speed applications. Furthermore, such components often cause manufacturing problems and can reduce the reliability of power converters. For example, such components (e.g., toroidal ferrite beads) may be susceptible to damage during manufacturing due to drops and / or vibrations.

[0041] This paper provides a more efficient and reliable PCB structure for parallel GaN devices. In at least one embodiment, the parallel GaN devices are arranged such that each switching leg of a power switching circuit maintains an independent conduction path. In some examples, maintaining an independent conduction path for each switching leg of the power switching circuit can achieve maximum dynamic current sharing among the parallel GaN devices, while reducing voltage overshoot and current oscillations, and improving the efficiency of the power switching circuit.

[0042] Figure 2 This is a schematic diagram of an example of a power switching circuit 200 according to the aspects described herein. In one example, the power switching circuit 200 may be configured as a half-bridge inverter. The power switching circuit 200 may be used, for example, as an inverter in a UPS (e.g., Figure 1 The inverter 108 of the UPS 100 shown. In other examples, the power switching circuit 200 may be configured as a half-bridge converter and may be used in a converter within a UPS (e.g., Figure 1 The converter 104 of the UPS 100 shown.

[0043] like Figure 2As shown, the power switching circuit 200 includes a positive bus 202, a switching node 204, a negative bus 206, a first switching branch 208, and a second switching branch 210 connected in parallel with the first switching branch 208. However, in other examples, the power switching circuit 200 may include three or more parallel switching branches. The first switching branch 208 includes a first GaN device 212 and a second GaN device 222. The first GaN device 212 has a drain 216 and a source 218. The drain 216 is coupled to the positive bus 202, and the source 218 is coupled to the switching node 204. The second GaN device 222 has a drain 226 and a source 228. The drain 226 is coupled to the switching node 204, and the source 228 is coupled to the negative bus 206. The second switching branch 210 includes a third GaN device 232 and a fourth GaN device 242. The third GaN device 232 has a drain 236 and a source 238. The drain 236 is coupled to the positive bus 202, and the source 238 is coupled to the switching node 204. The fourth GaN device 242 has a drain 246 and a source 248. The drain 246 is coupled to the switching node 204, and the source 248 is coupled to the negative bus 206. In this document, "drain" can refer to any device terminal into which current enters the device. Similarly, "source" can refer to any device terminal from which current flows out of the device. Figure 2 As shown, the first GaN device 212 and the third GaN device 232 are coupled in parallel between the positive bus 202 and the switching node 204. Similarly, the second GaN device 222 and the fourth GaN device 242 are coupled in parallel between the negative bus 206 and the switching node 204.

[0044] As described above, the power switching circuit can be used in high-power applications by sharing current among parallel GaN devices. In one example, the current on the positive bus 202 and the negative bus 206 can be shared between the first switching branch 208 and the second switching branch 210, and multiple switching branches can operate uniformly. For example, in a first state of the power switching circuit 200, the first GaN device 212 and the third GaN device 232 can be turned on to couple the positive bus 202 to the switching node 204, and in a second state of the power switching circuit 200, the second GaN device 222 and the fourth GaN device 242 can be turned on to couple the negative bus 206 to the switching node 204.

[0045] In some examples, the first switching branch 208 may include a first decoupling capacitor 252a and a second decoupling capacitor 252b coupled between the positive bus 202 and the negative bus 206 to provide a locally stable DC voltage to the first GaN device 212 and the second GaN device 222. Similarly, the second switching branch 210 may include a third decoupling capacitor 254a and a fourth decoupling capacitor 254b coupled between the positive bus 202 and the negative bus 206 to provide a locally stable DC voltage to the third GaN device 232 and the fourth GaN device 242. In other examples, a different number of decoupling capacitors may be used.

[0046] In some examples, each GaN device 212, 222, 232, and 242 can be subjected to various parasitic inductances. For example, each GaN device 212, 222, 232, and 242 can be packaged in a device package such as a through-hole package, a surface mount package, etc. Thus, each device terminal (i.e., gate, drain, source) can have an associated package parasitic inductance. In some examples, the package parasitic inductance associated with each device terminal can correspond to the connection from a device substrate or die to the package pins and / or leads (e.g., wire bonding). Figure 2 As shown. The first GaN device 212 may have a packaged parasitic gate inductor 215a, a packaged parasitic drain inductor 217a, and a packaged parasitic source inductor 219a. Similarly, the second GaN device 222 may have multiple packaged parasitic inductors 225a, 227a, and 229a, the third GaN device 232 may have multiple packaged parasitic inductors 235a, 237a, and 239a, and the fourth GaN device 242 may have multiple packaged parasitic inductors 245a, 247a, and 249a.

[0047] In one example, the GaN devices 212, 222, 232, and 242 can be arranged on a printed circuit board (PCB) and connected via electrical traces and / or planar connections included on or within the PCB. Thus, each device terminal of the GaN device can have an associated PCB parasitic inductance, in addition to the package parasitic inductance. In some examples, the PCB parasitic inductance associated with each GaN device terminal can correspond to the inductance of one or more traces coupled to each device terminal. In some examples, the PCB parasitic inductance associated with each device terminal can also include an inductance electrically and physically coupled to a terminal pin, lead, or pad on the PCB.

[0048] like Figure 2 As shown, the first GaN device 212 may have a PCB parasitic gate inductance 215b, a PCB parasitic drain inductance 217b, and a PCB parasitic source inductance 219b. Similarly, the second GaN device 222 may have a PCB parasitic gate inductance 225b, a PCB parasitic drain inductance 227b, and a PCB parasitic source inductance 239b; the third GaN device 232 may have a PCB parasitic gate inductance 235b, a PCB parasitic drain inductance 237b, and a PCB parasitic source inductance 239b; and the fourth GaN device 242 may have a PCB parasitic gate inductance 245b, a PCB parasitic drain inductance 247b, and a PCB parasitic source inductance 249b.

[0049] In one example, the PCB parasitic source inductance 219b of the first GaN device 212 and the PCB parasitic drain inductance 227b of the second GaN device 222 may correspond to the inductance of a conduction path between the first GaN device 222 and the second GaN device 222 through the switching node 204. Similarly, the PCB parasitic source inductance 239b of the third GaN device 232 and the PCB parasitic drain inductance 247b of the fourth GaN device 242 may correspond to a conduction path between the third GaN device 232 and the fourth GaN device 242. In some examples, the PCB parasitic inductances of multiple GaN devices and the parasitic midpoint inductance 205 may correspond to the inductance of the switching path between the GaN devices in the first switching branch 208 and the GaN devices in the second switching branch 210. For example, the inductance of a conduction path from the first GaN device 212 through the switching node 204 to the fourth GaN device 242 may include the PCB parasitic source inductance 219b of the first GaN device 212, the PCB parasitic midpoint inductance 205, and the PCB parasitic drain inductance 247b of the fourth GaN device 242.

[0050] Figure 3AThis is a diagram illustrating an example of a power switching assembly 300 including the power switching circuit 200 arranged on a PCB 302. In one example, the PCB 302 may be a multilayer PCB. In some examples, the GaN devices and the switching node 204 may be disposed on different layers of the PCB 302. For example, the GaN devices 212, 222, 232, and 242 may be disposed on a first layer, and the switching node 204 may be disposed on a second layer or any other layer. In one example, the GaN devices may be located on a first layer above the switching node 204. In other examples, the GaN devices may be located on the first layer such that each GaN device at least partially overlaps with the switching node 204. In one example, the switching node 204 may have the following characteristics: Figure 3A The rectangular shape shown is used. However, in other examples, the switching node 204 can have a different shape.

[0051] like Figure 3A As shown, a first distance D1 corresponds to the distance between the source 218 of the first GaN device 212 and the drain 226 of the second GaN device 222, and a second distance D2 corresponds to the distance between the source 238 of the third GaN device 232 and the drain 246 of the fourth GaN device 242. Similarly, a third distance D3 corresponds to the distance between the source 218 of the first GaN device 212 and the source 238 of the third GaN device 232, and a fourth distance D4 corresponds to the distance between the drain 226 of the second GaN device 222 and the drain 246 of the fourth GaN device 242.

[0052] As described above, the GaN devices (i.e., 212, 222) of the first switching branch 208 and the GaN devices (i.e., 232, 242) of the second inverter branch 210 can be operated concurrently. This allows for maximum dynamic current sharing by maintaining an independent conduction path for each switching branch, thereby improving the efficiency of the power switching circuit 200. For example, maximum dynamic current sharing can be achieved by preventing current commutation between GaN devices in different inverter branches; that is, allowing current from the first GaN device 212 to be commutated only through the second GaN device 222, and allowing current from the third GaN device 232 to be commutated only through the fourth GaN device 242, and vice versa.

[0053] In some examples, an independent conduction path for each switching branch can be established by adjusting the distances D1 to D4 between the plurality of GaN devices 212, 222, 232, and 242. For example, the plurality of GaN devices can be arranged such that a first distance D1 between the first GaN device 212 and the second GaN device 222 in the first switching branch 208 is smaller than the distance between the first switching branch 208 and the second switching branch 210 (i.e., D3 and D4). Additionally, the plurality of GaN devices can be arranged such that a second distance D2 between the third GaN device 232 and the fourth GaN device 242 is also smaller than the distance between the first switching branch 208 and the second switching branch 210 (i.e., D3 and D4). In one example, the plurality of GaN devices can be arranged such that the distance between GaN devices in the same switching branch is smaller than the distance between GaN devices in different switching branches coupled diagonally across the switching node 204. For example, distances D1 to D4 can be adjusted such that distances D1 and D2 are smaller than the distance between the first GaN device 212 and the fourth GaN device 242, and the distance between the second GaN device 222 and the third GaN device 232. In one example, the plurality of GaN devices can be arranged symmetrically such that D1 and D2 are substantially the same, and D3 and D4 are substantially the same. For example, in some examples, the plurality of GaN devices can be arranged such that D1 and D2 have a mismatch of less than 10%. In some examples, the plurality of GaN devices can be arranged such that distances D3 and D4 are at least 20 to 30% larger than distances D1 and D2.

[0054] Since each GaN device 212, 222, 232, and 242 has at least one device terminal coupled to the switching node 204, distances D1 to D4 can correspond to the lengths of the conduction paths between the multiple GaN devices. For example, by minimizing D1 relative to D3 and D4, the length of the conduction path from the source 218 of the first GaN device 212 through the switching node 204 to the drain 226 of the second GaN device 222 can be shorter than the length of the conduction path from any of the GaN devices 212 and 222 to the GaN devices (i.e., 232 and 242) of the second switching branch 210. Similarly, by minimizing D2 relative to D3 and D4, the length of the conduction path from the source 238 of the third GaN device 232 through the switching node 204 to the drain 246 of the fourth GaN device 242 can be shorter than the length of the conduction path from any of the GaN devices 232 and 242 to the GaN devices (i.e., 212 and 222) of the first switching branch 208. In other words, the conduction path between GaN devices in the same switching branch (e.g., 208 or 210) can be shorter than the conduction path between the GaN devices in the first switching branch 208 and the GaN devices in the second switching branch 210.

[0055] In one example, the length of each conduction path can affect the inductance of each conduction path; that is, a shorter conduction path can have a lower inductance, while a longer conduction path can have a higher inductance. Thus, the inductance of the conduction path between the source 218 of the first GaN device 212 and the drain 226 of the second GaN device 222 can be lower than the inductance of the conduction path from either GaN device 212 or 222 to the GaN devices (i.e., 232, 242) of the second switching branch 210. Similarly, the inductance of the conduction path between the source 238 of the third GaN device 232 and the drain 246 of the fourth GaN device 242 can be lower than the inductance of the conduction path from either GaN device 232 or 242 to the GaN devices (i.e., 212, 222) of the first switching branch 208.

[0056] In some examples, because the conduction path between GaN devices with the same switching branch has a lower inductance than the conduction path between GaN devices with different switching branches, the first switching branch 208 and the second switching branch 210 can each maintain an independent conduction path. For example, the current carried by the first switching branch 208 can be commutated between the first GaN device 212 and the second GaN device 222, and the current carried by the second switching branch 210 can be commutated between the third GaN device 232 and the fourth GaN device 242.

[0057] Figure 3B A side view of the power switching assembly 300 is shown (only the first switching branch 208 is shown). As described above, the first GaN device 212 and the second GaN device 222 can be arranged on a first (i.e., top) layer 304 of the PCB 302, and the switching node 204 can be arranged on a second layer 306 of the PCB 302. Furthermore, a plurality of decoupling capacitors 252a, 252a of the first switching branch 208 and a plurality of decoupling capacitors 254a, 254b of the second switching branch 210 can be disposed between the plurality of GaN devices and on the first layer 304 above the switching node 204.

[0058] An example of a first conduction path between the first GaN device 212 and the second GaN device 222 is generally shown at 308. As shown, the length of the first conduction path 308 corresponds to the distance D1 between the source 218 of the first GaN device 212 and the drain 226 of the second GaN device 222. As described above, by minimizing the distance D1, the length of the first conduction path 308 can be minimized, and the first conduction path 308 can have a lower inductance than the conduction path between the plurality of GaN devices 212, 222 of the first switching branch 208 and the plurality of GaN devices 232, 242 of the second switching branch 210. In this way, current from the first GaN device 212 can be commutated to the second GaN device 222 via the first conduction path 308, and vice versa. Similarly, by minimizing distance D2, the inductance of a second conduction path (not shown) between the GaN devices 232 and 242 of the second switching branch 210 can be minimized, such that the current from the third GaN device 232 is commutated to the fourth GaN device 242 via the second conduction path, and vice versa.

[0059] Figure 4A and Figure 4B A power switching application 400 including the power switching circuit 200 is illustrated. In one example, the power switching application 400 may correspond to an AC-to-DC converter of a UPS (e.g., Figure 1 The operation of the power switching circuit used in the converter 104 of the UPS 100 shown. In other examples, the power switching application 400 may correspond to a DC-to-AC inverter in a UPS (e.g., Figure 1 The operation of the power switching circuit used in the inverter 108 of the UPS 100 shown. In some examples, the power switching application 400 may correspond to the operation of the power switching circuit used in a DC-DC converter of a UPS.

[0060] In one example, such as Figure 3A and Figure 3B As shown, the power switching circuit 200 is arranged in the power switching assembly 300. For example... Figure 4A and Figure 4B As shown, the switching node 204 is coupled to a load 402 having a load current 404. In one example, the switching node 204 is coupled to the load 402 between a plurality of GaN devices in the first switching branch 208 and the second switching branch 210. In some examples, the load 402 may be coupled to a device terminal of each GaN device coupled to the switching node 204. For example, the source 218 of the first GaN device 212 and the drain 226 of the second GaN device 222 may each be coupled to the switching node 204 and the load 402. Similarly, the source 238 of the third GaN device 232 and the drain 246 of the fourth GaN device 242 may each be coupled to the switching node 204 and the load 402.

[0061] Figure 4A and Figure 4B A power switching circuit 200 in a power switching application 400 is illustrated when transitioning from a first state to a second state. As described above, the first state of the power switching circuit 200 may include turning on the first GaN device 212 of the first switching branch 208 and the third GaN device 232 of the second switching branch 210 to couple the positive bus 202 to the switching node 204. Similarly, the second state of the power switching circuit 200 may include turning on the second GaN device 222 of the first switching branch 208 and the fourth GaN device 242 of the second switching branch 210. In some examples, the first switching branch 208 may carry a first portion of the load current 404, such as a first load current 406, and the second switching branch 210 may carry a second portion of the load current 404, such as a second load current 408.

[0062] To transition from the first state to the second state, the first GaN device 212 and the third GaN device 232 are turned off, and the second GaN device 222 and the fourth GaN device 242 are turned on. Figure 4AIn this configuration, the first GaN device 212 and the third GaN device 232 have been switched off, and the load current 402 is transferred to a positive bus capacitor 406 in opposite directions (i.e., from source to drain). In one example, each GaN device may have a similar positive temperature coefficient, and therefore the on-resistance is substantially similar. This allows the quiescent current to be shared evenly between the first switching branch 208 and the second switching branch 210 (e.g., ...). Figure 4A The load current 402 shown is shown; that is, the first load current 406 and the second load current 408 can be substantially equal parts of the load current 402.

[0063] Figure 4B The diagram illustrates a power switching circuit 200 after the second GaN device 222 and the fourth GaN device 242 have been turned on. As described above, the conduction path between the first GaN device 212 and the second GaN device 222 can have a lower inductance than the conduction path including the PCB parasitic midpoint inductance 205 (e.g., the conduction path from the first switching branch 208 to the second switching branch 210). Thus, when the power switching circuit 200 is switched from a first state to a second state, the first load current 406 can be commutated from the first GaN device 212 to the second GaN device 222, and the second GaN device 222 can begin to carry the first load current 406 in a positive direction (i.e., drain to source). Similarly, the conduction path between the third GaN device 232 and the fourth GaN device 242 can have a lower inductance than the conduction path including the PCB parasitic midpoint inductance 205 (e.g., the conduction path from the second switching branch 210 to the first switching branch 208). When the power switching circuit 200 transitions from the first state to the second state, the second load current 408 can be commutated from the third GaN device 232 to the fourth GaN device 242, and the fourth GaN device 242 can begin to carry the second load current 408 in the positive direction. Thus, during the transition of the power switching circuit 200, the dynamic current can be shared equally between the first switching branch 208 and the second switching branch 210; that is, the first load current 406 and the second load current 408 can maintain a substantially equal portion of the load current 402. Similarly, when the power switching circuit 200 transitions back from the second state to the first state, the first load current 406 can be commutated from the second GaN device 222 to the first GaN device 212, and the load current 408 can be commutated from the fourth GaN device 242 to the third GaN device 232.

[0064] By establishing an independent conduction path for each switching branch, current commutation between switching branches can be prevented, thus achieving average dynamic current sharing. In some examples, the efficiency of the power switching circuit 200 can be improved by maximizing dynamic current sharing between switching branches. Furthermore, sharing equal dynamic current between switching branches 208 and 210 can reduce or eliminate ringing, oscillation, and overshoot during operation of the power switching circuit 200.

[0065] It should be understood that the embodiments described herein are not limited to specific methods for establishing conductive path lengths and / or inductances to achieve independent conductive paths for each switching branch (e.g., 208 and 210). As described above, multiple GaN devices 212, 222, 232, and 242 can be physically arranged on a PCB (e.g., 302) to establish different conductive path lengths and corresponding conductive path inductances. However, in other examples, different methods for establishing various conductive path lengths and inductances can be employed. For example, the characteristics of the conductive paths can be controlled by modifying the properties of the traces and / or vias included on the PCB 302.

[0066] Furthermore, the embodiments discussed herein are not limited to specific types of GaN devices or device packages. For example, Figure 5A An example of a power switching component layout 500 including a power switching circuit 200 disposed on the PCB 302 is shown. In one example, the power switching component layout 500 may be similar to Figure 3A and Figure 3B The power switching assembly 300 includes a plurality of GaN devices 212, 222, 232, and 242 disposed in a through-hole package. As described above, the plurality of GaN devices can be arranged on the top (i.e., first) layer 304 of the PCB 302 such that GaN devices of the same switching branch (e.g., 208 or 210) are closer to each other than GaN devices of another switching branch. Thus, the conduction path between GaN devices of the same switching branch can have a lower inductance than the conduction path between GaN devices of different switching branches.

[0067] As described above, this arrangement allows multiple GaN devices to be symmetrically placed on the PCB 302. For example, GaN devices 212 and 222 of the first inverter branch 208 can be arranged symmetrically with GaN devices 232 and 242 of the second inverter branch 210. (Refer to...) Figure 5ABy symmetrically arranging the GaN devices on the PCB 302, the lengths of the gate drive conduction paths 504a, 504b, 504c, and 504d between the gate(s) output(s) 506 and the gates of each GaN device can be substantially the same (e.g., within 10%). In one example, since each gate drive conduction path can have substantially the same length, each gate drive conduction path can have substantially the same inductance. In some examples, the inductance of each gate drive conduction path can correspond to... Figure 2 The parasitic gate inductances 215b, 225b, 235b, and 245b of the PCB are shown. Since the inductances of the gate drive conduction paths are substantially the same, the gate drive delay between the multiple GaN devices can be minimized, thereby improving the efficiency of the power switching circuit 200. In some examples, the gate drive conduction paths 504a to 504d may be included on the first layer 304 or the second layer 306; however, in other examples, the gate drive conduction paths may be included on different layers of the PCB 302, such as a third layer, a fourth layer, or any other layer.

[0068] Additionally, as described above, the first switching branch 208 may include a first decoupling capacitor 252a and a second decoupling capacitor 252b coupled between the positive bus 202 and the negative bus 206. Similarly, the second switching branch 212 may include a third decoupling capacitor 254a and a fourth decoupling capacitor 254b coupled between the positive bus 202 and the negative bus 206. Figure 5AAs shown, multiple decoupling capacitors 252a, 252b, 254a, and 254b can be arranged between the multiple GaN devices and on the first layer 304 of the PCB 302 above the switching node 204. In some examples, this arrangement of the multiple decoupling capacitors can provide a locally stable DC voltage to each GaN device, thereby effectively eliminating PCB parasitic inductance between the multiple GaN devices, the positive bus 202, and the negative bus 206. For example, decoupling capacitor 252b can be located near the source 228 of the second GaN device 222 to disable the PCB parasitic source inductance 229b of the second GaN device 222, and decoupling capacitor 252a can be located near the drain 216 of the first GaN device 212 to disable the PCB parasitic drain inductance 217b of the first GaN device 212. Similarly, the decoupling capacitor 254a can be located near the source 248 of the fourth GaN device 242 to disable the PCB parasitic source inductance 249b of the fourth GaN device 242, and the decoupling capacitor 254b can be located near the drain 236 of the third GaN device 232 to disable the PCB drain parasitic inductance 237b of the third GaN device 232. In some examples, the positive bus 202 and the negative bus 206 can also be disposed on the first layer 304; however, in other examples, the positive bus 202 and the negative bus 206 can be disposed on different layers of the PCB 302.

[0069] like Figure 5A As shown, a first via 508a can be used to couple the source 218 of the first GaN device 212 to the switching node 204, and a second via 508b can be used to couple the drain 226 of the second GaN device 222 to the switching node 204. Similarly, a third via 508c can be used to couple the source 238 of the third GaN device 232 to the switching node 204, and a fourth via 508d can be used to couple the drain 246 of the fourth GaN device 242 to the switching node 204. By placing the switching node 204 between the plurality of GaN devices and below the plurality of decoupling capacitors, the inductance of the conduction path between the plurality of GaN devices in the same switching branch can be further minimized. In some examples, minimizing the inductance between the plurality of GaN devices in the same switching branch can improve the performance of the power switching circuit 200 in high-speed power switching applications.

[0070] Figure 5BAn example of a power switching component layout 525 including the power switching circuit 200 disposed on the PCB 302 is shown. In one example, the power switching component layout 525 may be similar to Figure 3A and Figure 3B The power switching assembly 300, wherein the plurality of GaN devices 212, 222, 232, and 242 are provided in surface mount device (SMD) packages. In some examples, the plurality of GaN devices may be provided in various types of SMD packages, including but not limited to flat packages, small outline packages, and grid arrays (e.g., ball grids and column grids). Similar to the power switching assembly layout 500 of FIG. 5, the plurality of GaN devices are arranged on the first layer 304 of the PCB 302 such that the conduction path between GaN devices in the same switching branch (e.g., 208 or 210) is shorter than the conduction path between GaN devices in different switching branches. Thus, the conduction path between GaN devices in the same switching branch can have a lower inductance than the conduction path between GaN devices in different switching branches.

[0071] Similar to the power switching component layout 500, the switching node 204 of the power switching component layout 525 may be disposed on the second layer 306 of the PCB 302. The power switching component layout 525 also includes a plurality of decoupling capacitors 252a, 252b, 254a, and 254b coupled between the positive bus 202 and the negative bus 206, and arranged on the first layer 304 of the PCB 302 between the plurality of GaN devices, and above the switching node 204. Furthermore, the plurality of GaN devices are symmetrically arranged on the PCB 302 and oriented such that the gate drive conduction paths 504a to 504d can have substantially the same length, thereby minimizing the gate drive delay between the plurality of GaN devices. In some examples, the gate drive conduction paths 504a to 504d may be included on the first layer 304 or the second layer 306; however, in other examples, the gate drive conduction paths may be included on different layers of the PCB 302, such as a third layer, a fourth layer, or any other layer.

[0072] As described above, the examples provided herein can be implemented using GaN field-effect transistors, each having gate, drain, and source terminals; however, in other examples, different types of GaN devices with different device terminals can be used. For example, the examples provided herein can be implemented using GaN bipolar junction transistors, each having base, collector, and emitter terminals. In other examples, different types of GaN devices can be used, such as GaN high electron mobility transistors and insulated-gate bipolar transistors. In some examples, devices made of semiconductor materials other than GaN can be used, such as silicon (Si) devices, gallium arsenide (GaAs) devices, etc.

[0073] Furthermore, the embodiments discussed herein are not limited to a specific type of power switching circuit and can be advantageously used in various power switching circuits with parallel GaN devices. As described above, the power switching circuit 200 can be configured as a half-bridge inverter having a first switching branch 208 and a second switching branch 210. However, in other examples, the power switching circuit 200 can be configured differently. For example, the power switching circuit 200 can be configured as a half-bridge converter, a full-bridge inverter, or any other type of power conversion circuit including parallel GaN devices. As described above, similar to Figure 1 The power switching circuit 200 may be included in the power conversion circuit of a UPS 100. Additionally, the power switching circuit 200 may be configured to have two or more switching branches.

[0074] As described above, this paper provides a more efficient and reliable PCB structure for parallel GaN devices. In at least one embodiment, the parallel GaN devices are arranged such that each switching branch of a power switching circuit maintains an independent conduction path. By maintaining an independent conduction path for each switching branch of the power switching circuit, maximum dynamic current sharing can be achieved among the parallel GaN devices, thereby reducing voltage overshoots and current oscillations, and improving the efficiency of the power switching circuit, especially in high-power applications.

[0075] Therefore, having described several aspects of at least one embodiment of the invention, various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the invention. Therefore, the foregoing description and drawings are merely illustrative.

Claims

1. An electrical converter system, characterized by The electrical converter system includes: a printed circuit board including at least a first layer and a second layer; a switching node disposed on the second layer; a first transistor, a second transistor, a third transistor, and a fourth transistor disposed on the first layer, the first transistor and the third transistor each having a source coupled to the switching node, and the second transistor and the fourth transistor each having a drain coupled to the switching node; a first conduction path from the source of the first transistor through the switching node to the drain of the fourth transistor, the first conduction path having a first length; and a second conduction path from the source of the first transistor through the switching node to the drain of the second transistor, the second conduction path having a second length, wherein the first length of the first conduction path is greater than the second length of the second conduction path.

2. The electrical converter system of claim 1, wherein: The electrical converter system further includes: a third conduction path from the source of the third transistor through the switching node to the drain of the second transistor, the third conduction path having a third length; and a fourth conduction path from the source of the third transistor through the switching node to the drain of the fourth transistor, the fourth conduction path having a fourth length, wherein the third length of the third conduction path is greater than the fourth length of the fourth conduction path.

3. The electrical converter system of claim 2, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are symmetrically placed on the first layer such that a first distance between the first transistor and the second transistor is substantially the same as a second distance between the third transistor and the fourth transistor, and a third distance between the first transistor and the third transistor is substantially the same as a fourth distance between the second transistor and the fourth transistor.

4. The electrical converter system of claim 3, wherein: The first length of the first conduction path is substantially the same as the third length of the third conduction path, and the second length of the second conduction path is substantially the same as the fourth length of the fourth conduction path.

5. The electrical converter system of claim 4, wherein: The electrical converter system further includes: a plurality of gate drive outputs and a plurality of gate drive conduction paths between the plurality of gate drive outputs and gates of the first transistor, the second transistor, the third transistor, and the fourth transistor, wherein each of the plurality of gate drive conduction paths has substantially the same length.

6. The electrical converter system of claim 1, wherein: The electrical converter system further includes: a positive bus and a negative bus disposed on the first layer, wherein a drain of the first transistor and a drain of the third transistor are coupled to the positive bus, and a source of the second transistor and a source of the fourth transistor are coupled to the negative bus.

7. The electrical converter system of claim 6, wherein: The electrical converter system further includes a plurality of decoupling capacitors coupled between the positive bus and the negative bus and disposed on the first layer above the first transistor, the second transistor, the third transistor, the fourth transistor, and the switching node.

8. The electrical converter system of claim 1, wherein: Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a gallium nitride power transistor.

9. The electrical converter system of claim 8, wherein: The gallium nitride power transistor is disposed in one of a through-hole device package and a surface mount device package.

10. An electrical converter system characterized by The electrical converter system includes: a printed circuit board including at least a first layer and a second layer; a switching node disposed on the second layer; a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor disposed on the first layer, the first transistor and the third transistor each having a source coupled to the switching node, and the second transistor and the fourth transistor each having a drain coupled to the switching node; a first conduction path from the source of the first transistor through the switching node to the drain of the fourth transistor, the first conduction path having a first inductance; and a second conduction path from the source of the first transistor through the switching node to the drain of the second transistor, the second conduction path having a second inductance, wherein the first inductance of the first conduction path is greater than the second inductance of the second conduction path.

11. The electrical converter system of claim 10, wherein: The electrical conversion system further includes a third conduction path from the source of the third transistor through the switching node to the drain of the second transistor, the third conduction path having a third inductance; and a fourth conduction path from the source of the third transistor through the switching node to the drain of the fourth transistor, the fourth conduction path having a fourth inductance, wherein the third inductance of the third conduction path is greater than the fourth inductance of the fourth conduction path.

12. The electrical converter system of claim 11, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are symmetrically placed on the first layer such that a first distance between the first transistor and the second transistor is substantially the same as a second distance between the third transistor and the fourth transistor, and a third distance between the first transistor and the third transistor is substantially the same as a fourth distance between the second transistor and the fourth transistor.

13. The electrical converter system of claim 12, wherein: The first inductance of the first conduction path is substantially the same as the third inductance of the third conduction path, and the second inductance of the second conduction path is substantially the same as the fourth inductance of the fourth conduction path.

14. The electrical converter system of claim 13, wherein: The electric converter system also includes a plurality of gate drive outputs and a plurality of gate drive conduction paths between the plurality of gate drive outputs and gates of the first, second, third, and fourth transistors, wherein each of the plurality of gate drive conduction paths has substantially the same length.

15. The electrical converter system of claim 10, wherein: The electric converter system also includes a positive bus and a negative bus disposed on the first layer, wherein a drain of the first transistor and a drain of the third transistor are coupled to the positive bus, and a source of the second transistor and a source of the fourth transistor are coupled to the negative bus.

16. The electrical converter system of claim 15, wherein: The electric converter system also includes a plurality of decoupling capacitors coupled between the positive bus and the negative bus and disposed on the first layer above the first, second, third, and fourth transistors and the switching node.

17. The electrical converter system of claim 10, wherein: Each of the first, second, third, and fourth transistors is a gallium nitride power transistor.

18. The electrical converter system of claim 17, wherein: The gallium nitride power transistor is disposed in one of a through-hole device package and a surface mount device package.

19. A method for manufacturing an electrical converter system, characterized by The method includes: providing a printed circuit board having at least a first layer and a second layer, a switching node disposed on the second layer; disposing a first transistor, a second transistor, a third transistor, and a fourth transistor on the first layer of the printed circuit board proximate the switching node; and coupling a source of the first transistor, a drain of the second transistor, a source of the third transistor, and a drain of the fourth transistor to the switching node such that a first length of a first conduction path from the source of the first transistor through the switching node to the drain of the fourth transistor is greater than a second length of a second conduction path from the source of the first transistor through the switching node to the drain of the second transistor.

20. The method of claim 19, wherein: The method also includes disposing a plurality of decoupling capacitors on the first layer between the first, second, third, and fourth transistors and above the switching node.

21. The method of claim 20, wherein: The method also includes coupling the plurality of decoupling capacitors between a positive bus and a negative bus disposed on the first layer.

22. The method of claim 19, wherein: Arranging the first transistor, the second transistor, the third transistor, and the fourth transistor on the first layer also includes placing the first transistor, the second transistor, the third transistor, and the fourth transistor symmetrically such that a first distance between the first transistor and the second transistor is substantially the same as a second distance between the third transistor and the fourth transistor, and a third distance between the first transistor and the third transistor is substantially the same as a fourth distance between the second transistor and the fourth transistor.

23. The method of claim 22, wherein: The method also includes coupling gates of the first transistor, the second transistor, the third transistor, and the fourth transistor to a plurality of gate driver outputs such that lengths of each of the first conduction path and the second conduction path between the plurality of gate driver outputs and the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor are substantially the same.

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