Circuit, system, and method for error correction code management of write-once memory codes

Abstract

Circuits, systems, and methods for error correction code management of write-once memory codes are disclosed. In described examples, a system for error correction code (ECC) management of write-once memory (WOM) codes includes a host processor arranged to send a data word to be stored into a WOM (write-once memory) device. A host interface is arranged to receive (710) a first data word for processing by a WOM controller and an ECC controller. The WOM controller is to generate (720) a first WOM encoded word in response to original symbols of the first data word, and the ECC controller is to generate (730) a first set of ECC bits in response to the original symbols of the first data word. A memory device interface is to write (740) the first WOM encoded word and the first set of ECC bits to the WOM device according to a memory address associated with the first data word.

Description

[0001] This application is a divisional application of Chinese Patent Application 201680035012.5 (PCT / US2016 / 030822), entitled "Circuit, System and Method for Error Correction Code Management of Write-once Memory Codes", filed on May 4, 2016, and entered the national phase on December 15, 2017. Background Technology

[0002] Computer systems include processors that operate to retrieve, process, and store data in memory devices. Memory devices used in computer systems encompass different types, each typically exhibiting different performance and operational characteristics. The type of memory device used in a particular system is usually selected based on the specific application requirements of the computer system. For example, some system designs require the ability to write and read data from non-volatile memory locations. However, some memory device solutions (such as electrically erasable read-only memory) are unsuitable for certain applications because they increase cost and degrade performance characteristics. Summary of the Invention

[0003] The aforementioned issues can be addressed in a system for managing error correction codes (ECC) for Write-once Memory (WOM) codes, comprising, for example, a host processor configured to transmit data words to be stored in a WOM (Write-once Memory) device. A host interface is configured to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller generates a first WOM-encoded word in response to the original symbol of the first data word, while the ECC controller generates a first set of ECC bits in response to the original symbol of the first data word. A memory device interface writes the first WOM-encoded word and the first set of ECC bits into the WOM device according to a memory address associated with the first data word. Attached Figure Description

[0004] Figure 1 An illustrative computing system according to an example embodiment is shown.

[0005] Figure 2 This is a block diagram of a processing system including an ECC-managed WOM according to an example embodiment.

[0006] Figure 3 This section describes symbol-level WOM encoding in an example memory system.

[0007] Figure 4 This is an encoding diagram of an example two-stage / two-level Reed-Solomon and WOM encoding scheme according to an example embodiment.

[0008] Figure 5 This is an encoding diagram of an example two-stage BCH (Bose-Chaudhuri-Hocaquenghem) and WOM encoding scheme according to an example embodiment.

[0009] Figure 6 This is an encoding diagram of an example two-stage WOM encoding and ECC encoding scheme according to an example embodiment.

[0010] Figure 7 This is an example flowchart based on an example embodiment. Detailed Implementation

[0011] Various names may refer to components or systems. A system may be a subsystem of another system. If a first device is coupled to a second device, the connection may be made by a direct electrical connection or by an indirect electrical connection via other devices and connections.

[0012] Figure 1 An illustrative computing system 100 according to an example embodiment is shown. For example, computing system 100 is or is incorporated into electronic system 129, such as a computer, electronic control “box” or display, communication device (including transmitter), or any other type of electronic system arranged to generate radio frequency signals.

[0013] In some embodiments, the computing system 100 includes a megacell or system-on-a-chip (SoC) comprising control logic such as a CPU 112 (Central Processing Unit), storage device 114 (such as random access memory (RAM)), and power supply 110. For example, the CPU 112 may be a CISC (Complex Instruction Set Computer) CPU, a RISC (Reduced Instruction Set Computer) CPU, an MCU (Microcontroller Unit), or a digital signal processor (DSP). Storage device 114 (which may be memory such as on-processor cache, off-processor cache, RAM, flash memory, or disk storage) stores one or more software applications 130 (such as embedded applications) that, when executed by the CPU 112, perform any suitable functions related to the computing system 100.

[0014] CPU 112 includes memory and logic for storing information frequently accessed from storage device 114. The computing system 100 is frequently controlled by a user interface (UI) 116, which provides output to and receives input from the user during the execution of software application 130. Output is provided using a display 118, indicator lights, speakers, vibration, etc. Input is received using audio and / or video input (using, for example, voice or image recognition) and electrical and / or mechanical devices (such as keyboards, switches, proximity detectors, gyroscopes, accelerometers, etc.). CPU 112 is coupled to I / O (input-output) port 128, which provides an interface configured to receive input from (and / or provide output to) network device 131. Network device 131 may include any device capable of point-to-point and / or network communication with computing system 100. Computing system 100 may also be coupled to peripherals and / or computing devices, including tangible, non-transitory media (such as flash memory) and / or cable or wireless media. These and other input / output devices are selectively coupled to the computing system 100 via external devices connected wirelessly or by cable. For example, storage device 114 can be accessed via network device 131.

[0015] CPU 112 is coupled to I / O (input-output) port 128, which provides an interface configured to receive input (and / or provide output to) peripherals and / or computing devices 131 (including tangible (e.g., "non-transitory") media (such as flash memory) and / or cable or wireless media) (such as a Joint Test Action Group (JTAG) interface). These and other input and output devices are selectively coupled to computing system 100 via external devices connected wirelessly or by cable. CPU 112, storage device 114, and power supply 110 may be coupled to an external power source (not shown) or to a local power source (such as a battery, solar cell, alternator, induction field, fuel cell, capacitor, etc.).

[0016] The computing system 100 includes a memory 138 suitable for relatively fast memory access and is typically formed using a solid-state memory device. Such a solid-state memory device includes a write-once memory (WOM) 140 with ECC (Electronic Correction Code) management. The WOM 140 is memory that is typically written to once (or a relatively small number of times) (e.g., before being discarded or erased). The use of WOM encoding enables a particular system to write data to and read data from non-volatile memory. However, the use of ECC in WOM applications is problematic (e.g., regarding...). Figure 3 (As discussed).

[0017] ECC-managed WOM 140 write accesses are typically faster than ECC-managed WOM 140 erase cycles (if any), and in one embodiment, a write access can change a bit position in the ECC-managed WOM 140 from an erase state to a write state (e.g., from "0" to "1"). The erase state typically depends on the chosen technology and can therefore be either "0" or "1," while the write state is typically the opposite of the erase state. Some memory devices can store multiple bits of information in a single memory cell, in which case the write bit includes one or more bits of information with a state opposite to the erase state.

[0018] The ECC-managed WOM 140 is written using WOM codes to efficiently write the WOM, allowing it to be written multiple times without erasure. The ECC-managed WOM 140 is intended to provide cost-effective non-volatile memory (NVM) with limited reprogramming capabilities and / or an increased number of write / erase cycles (compared to traditional NVM solutions).

[0019] Figure 2 This is a block diagram of a processing system including an ECC-managed WOM according to an example embodiment. Generally, the processing system 200 includes an MCU 204 and a memory controller 210. The MCU 204 and the memory controller 210 are typically arranged on a common substrate 202. The memory controller 210 is communicatively coupled to the MCU 204 and is operable to manage memory access to memory devices, memory access to (at least) an ECC-managed WOM 140, and memory access to memory devices such as RAM 292, PROM (Programmable Read-Only Memory) 294, and optional EEPROM (Electrically Erasable Read-Only Memory) 296 (which may optionally be formed using a substrate different from the substrate 202)).

[0020] During operation, memory access served by memory controller 210 includes write operations and read operations. Generally, data written in memory is stored in a memory such as... Figure 2 The data transmitted from top to bottom, as described, is read in the following manner: Figure 2 The transmission is shown in a bottom-up direction. Accordingly, the host interface 220 is configured to select (e.g., in response to a system address provided with a memory access command) a memory device to write data to or read data from it.

[0021] Memory controller 210 includes an ECC controller such as ECC manager 250. During a write operation, ECC manager 250 is operable to apply error correction codes to data for writing to the ECC-managed WOM 140. During a read operation, ECC manager 250 is operable to evaluate the retrieved data, and, if necessary, the ECC controller is operable to perform a correction action in response to the evaluation. For example, the correction action is operable to correct the retrieved data using ECC-encoded data read from the ECC-managed WOM 140 via WOM manager 260.

[0022] Memory controller 210 includes a WOM manager 260. During a write operation, the WOM manager 260 is operable to encode data using WOM codes (such as data encoded using ECC codes by ECC manager 260) for writing WOM (and ECC) encoded data to an ECC-managed WOM 140. During a read operation, the WOM manager 260 is operable to decode WOM-encoded data from the ECC-managed WOM 140. After the WOM-encoded data is decoded, the decoded data is sent to the ECC manager 250 for further decoding based on the ECC codes used to originally encode the data written to the ECC-managed WOM 140.

[0023] Memory controller 210 includes memory device interface 270. During a write operation, memory device interface 270 is operable to write encoded data (such as data encoded using ECC codes via ECC manager 260 and WOM codes via WOM manager 260) to ECC-managed WOM 140. During a read operation, memory device interface 270 is operable to read encoded data from ECC-managed WOM 140. Memory device interface 270 is also operable to execute block initialization routines on ECC-managed WOM 140 (such as performing block erasure on ECC-managed WOM 140 so that the addressed memory locations are erased to logic zero). Typically, the block initialization routine requires more execution time than the execution time required for a normal read or write cycle on ECC-managed WOM 140.

[0024] In other embodiments (as referred to below) Figure 6 As discussed, WOM manager 260 is operable to encode payload data as WOM-encoded data, causing ECC manager 250 to encode the WOM-encoded data. Similarly, ECC manager 250 is operable to decode ECC-encoded data retrieved from memory, causing WOM manager 260 to decode the WOM-encoded data to retrieve the originally encoded payload data.

[0025] WOM encoding can be implemented using an n-bit symbol (such as any integer number of bits greater than or equal to 2), which is written to the WOM memory a finite number of times. For example, Table 1 below illustrates WOM encoding for a 2-bit symbol, which can be written to the WOM twice at a given memory location (e.g., before a memory erase is required).

[0026] Table 1

[0027] 2-digit sign 3-digit WOM code (first write) 3-digit WOM code (second write) 00 000 111 01 100 011 10 010 101 11 001 110

[0028] Each row in Table 1 describes a 2-bit sign (making m...) WOM =2, where m WOM (This refers to the number of bits per symbol), which is encoded as a 3-bit field by WOM. As mentioned above, m WOM The value can be any integer greater than or equal to 2. When WOM-encoded data is written to the WOM memory for the first time, 1 bit (at most) is set in the encoded data. When WOM-encoded data is written to the WOM memory a second time, the WOM memory is updated normally only if the new data is different from the previously stored data.

[0029] For example, if the WOM memory is "000" after the first write and the new data written a second time is "00", then the WOM memory will still be "000" after the second write. If the WOM memory is written a second time (e.g., with a value changed from the value written during the first write), at least 2 bits (out of 3) are set in the encoded data. Therefore, the WOM manager 260 can determine the number of writes to that location (used to store the symbol for the WOM encoding) by reading the data stored in the WOM location (and without relying on, for example, a separate counter for each memory location).

[0030] Figure 3 This illustrates symbol-level WOM encoding in an example memory system. Generally, memory system 300 includes a symbol space 302 and a WOM-encoded memory 304. Symbol space 302 includes 2-bit symbols 310 with values ​​such as "00".

[0031] In operation 312, the encoded symbol 310 is generated according to Table 1 to produce the encoded symbol 320. It should be understood that the principles and techniques described herein can be used for n-bit symbols and are not limited to 2-bit symbols. The WOM code-encoded memory 304 includes a 3-bit value (“000”) 320 for storing the encoded symbol 320 (e.g., for simplicity, a default erase bit value “0” is used for the WOM code-encoded memory 304). The WOM code-encoded memory 304 is susceptible to bit errors, which can lead to data loss.

[0032] In operation 322, an error occurs in the least significant bit of memory location 320. Regardless of the use (or absence) of error correction codes in the encoded data, single or multiple bit errors are possible in the encoded data: the strength of the error correction code determines the extent to which an error in the encoded data appears in the decoded data. Therefore, the 3-bit value 320 is incorrectly changed to a 3-bit value ("001") 330, which represents (e.g., in WOM code-encoded memory 304) a 1-bit error.

[0033] In operation 332, the 3-bit value ("001") 330 is read and decoded according to Table 1, resulting in a 2-bit symbol 340 (representing the decoded 3-bit value 330) with the value "11". In this example, the value "1" represents a 2-bit error in the symbol, although only one bit error occurs in the WOM-encoded memory 304. In some example cases, a 1-bit error in the WOM-encoded symbol could lead to errors in all bits of the WOM symbol.

[0034] For example, this disclosure includes a two-stage concatenated coding scheme that provides symbol-level protection for data stored in WOM-coded memory devices, offering low processing latency and / or reduced layout requirements. See below for reference. Figure 4 and Figure 5 The two-stage cascaded coding scheme discussed includes: a first stage in which payload data is encoded using Electronic Correction Code (ECC) to generate payload data for ECC protection; and a second stage in which WOM coding is used to encode the payload data for ECC protection.

[0035] Figure 4 This is an example encoding diagram of a two-stage Reed-Solomon and WOM encoding scheme according to an embodiment of the present disclosure. Generally, the data flow diagram 400 includes word 410, ECC-encoded word 420, and WOM-encoded word 430 (with ECC encoding). The ECC encoding 480 of the ECC-encoded word 420 is stored in the WOM encoding 490 of the WOM-encoded word 430.

[0036] Word 410 includes "k" symbols, where each symbol is stored in a symbol field (such as symbol fields 412 and 414). Each such symbol field is "n" bits (e.g., 2 bits) long. When n = 2, k = 2 (e.g., 4 / 2 = 2). Accordingly, word 410 includes 2 symbols, where each symbol is stored in symbol fields 412 and 414 respectively. For example, word 410 includes 4 bits of data representing the payload data of the two symbols to be encoded (e.g., according to k = 2). In various embodiments, the symbol field includes several groups of one or more bits, and each group represents one symbol being encoded. Accordingly, word 410 includes symbol field 412 (for encoding the first symbol) and symbol field 414 (for encoding the second symbol), where each symbol field will be encoded in encoding operation 402. As shown, symbol field 412 includes the value "10" and symbol field 414 includes the value "11".

[0037] Encoding operation 402 is a first-stage operation operable to encode (e.g., unencoded) symbol fields of word 410 using a symbol-based error-correcting coding scheme (such as Reed-Solomon codes). In the Reed-Solomon coding scheme, parity symbols are used to detect and optionally correct errors in the encoded word (wherein the number of errors that can be corrected depends on how many parity symbols are used). The number of parity symbols used in each RS code is given by 2*T (which has a total of 2*m). RS *T bits), where m RS M is the bit width of each symbol to be encoded, and T is the number of correctable errors in the encoded symbol. To ensure that the bits of each WOM code are in the same RS symbol, m RS Selected as m WOM Integer multiples of.

[0038] In the example described in this article, for ease of explanation, m is selected. RS =m WOM The error correction code scheme described herein can correct a single bit error in a retrieved WOM-encoded word (e.g., where the single error correction capability ECC is encapsulated within the WOM code). Other embodiments are possible, where the encapsulated error correction code can correct multiple bit errors (e.g., where each WOM-stored word can correct two or more errors in the WOM-stored word).

[0039] For example, when an RS code with a T=1 correctable error is used to encode k=2 symbols, encoding operation 402 generates k=2 separate RS codes 420. The ECC-encoded word 420 includes a symbol field 422 for the first RS code (e.g., symbol field 422 is a direct copy of symbol field 412) and a symbol field 426 for the second RS code (e.g., symbol field 426 is a direct copy of symbol field 414). The parity bit (e.g., check bit) field 424 has a 2*m value according to the above. RS *T = 4, a length determined by the given value. Accordingly, the parity field 424 is a 4-bit group of bits used to protect the sign field 422. Similarly, the parity field 428 is 4 bits long and used to protect the sign field 426. As shown, the sign field 422 includes the value "10", the parity field 424 includes the value "1010" (this value is an example RS encoding of the sign field 422), the sign field 426 includes the value "11", and the parity field 428 includes the value "1011" (this value is an example RS encoding of the sign field 426).

[0040] The 404 encoding operation is a WOM encoding operation in the second stage of the operation (as mentioned above). Figure 3 (As discussed), and operable to encode the output of the first-stage operation 402 (e.g., an ECC-encoded word) into a WOM-encoded word. For example, encoding operation 404 encodes the ECC-encoded word 420 into a WOM-encoded word 430 (e.g., which retains the information of the original ECC-encoded word 420). The WOM-encoded word 430 includes WOM fields 432, 434, 436, and 438, where WOM field 432 is the WOM code for symbol field 422, WOM field 434 is the WOM code for symbol field 424, WOM field 436 is the WOM code for symbol field 426, and WOM field 438 is the WOM code for symbol field 428. As shown, WOM field 432 includes the value "010", WOM field 434 includes the value "010001", WOM field 436 includes the value "100", and WOM field 438 includes the value "000100".

[0041] As mentioned above Figure 3Each WOM-encoded word comprises a 3-bit (e.g., NWOM = 3 width) encoding scheme for each 2-bit symbol to be encoded. As discussed above, WOM encoding allows WOM-encoded words (e.g., stored in WOM memory) to be rewritten multiple times, thereby reducing (if not all at once) the execution of relatively slow (and finite-lifetime) block initialization routines. Block initialization routines include routines such as block erase operations (writing all "0"s to a block of non-volatile memory) or block preset operations (writing all "1"s to a block of non-volatile memory)). The type of block operation is typically determined by the technology of the memory cells used.

[0042] Decoding operation 406 is a WOM decoding operation (as mentioned above). Figure 3 (As discussed), and operable to decode a WOM-encoded word of an ECC-encoded word into (e.g., ideally) the original ECC-encoded word. For example, operation 406 is a "second-stage" operation of the encoding of "reverse" "second-stage" operation 404. Decoding operation 406 decodes the WOM-encoded word 430 to (e.g., ideally) retrieve the ECC-encoded word 420 encoded in the WOM-encoded word 430. Parity fields 424 and 428 are used to enable (e.g., restore) the sign fields 422 and 426, respectively.

[0043] Decoding operation 408 is an ECC decoding operation operable to decode ECC-encoded data into valid data. For example, operation 408 is a "first-stage" operation that "reverses" the encoding of "first-stage" operation 402. In operation 408, parity fields 424 and 428 are used to make sign fields 422 and 426 valid (e.g., recoverable). In the event of a 1-bit error, the strength of the ECC encoding (as determined by the type of ECC and the number of correction bits used) is sufficient to correct the error, making the data of word 410 recoverable. Therefore, after retrieving a stored WOM-encoded word from memory, bit errors (e.g., single-bit errors) in the WOM-encoded fields are correctable. In contrast, in WOM-encoded words (as mentioned above...)... Figure 3 Example 1 error in the above example can lead to 2-bit error in the symbol.

[0044] Figure 5 This is an encoding diagram of an example two-stage BCH encoding and WOM encoding scheme according to an example embodiment. Generally, the data flow diagram 500 includes word 510, ECC-encoded word 520, and WOM-encoded word 530 (with ECC encoding). The ECC encoding 580 of the ECC-encoded word 520 is stored in the WOM encoding 590 of the WOM-encoded word 530.

[0045] Word 510 comprises "k" symbols, each stored in a symbol field (such as symbol fields 512 and 514). Therefore, word 510 comprises two symbols, each stored in symbol fields 512 and 514 respectively. The symbol fields will be encoded in encoding operation 502. For illustration, symbol field 512 includes the value "10" and symbol field 514 includes the value "11".

[0046] Encoding operation 502 is a first-stage operation operable to encode the symbol field of word 510 (e.g., unencoded) using a non-binary cyclic error correction (BCH) scheme (e.g., BCH code). In the BCH encoding scheme, parity symbols are used to detect and optionally correct errors in the encoded word. Because each bit error in a WOM-encoded word can lead to errors in the decoded word by up to m... WOM Bit errors, each BCH code can fully correct T=m WOM Bit error. Therefore, the number of parity symbols used is determined by m. WOM (which includes m) BCH *m WOM (bits) are given, where m BCH It is the bit width of each symbol to be BCH encoded, and m WOM It equals the width of the symbol field 522 (which is 2 bits wide). When m BCH = 2 symbols and m WOM = Two correctable errors are used during the encoding operation, and four parity bits are used to protect each symbol.

[0047] Encoding operation 502 generates an ECC-encoded word 520. The ECC-encoded word 520 includes a symbol field 522 for the first BCH code (e.g., a direct copy of symbol field 512) and a symbol field 524 for the second BCH code (e.g., a direct copy of symbol field 514). The parity bit field 526 has a parity value based on m. BCH *m WOM A defined length, where m BCH =2 and m WOM = 2. Therefore, parity field 526 is 4 bits long and is used to protect (and, for example, correct) the symbol of symbol field 522. Similarly, parity field 528 is 4 bits long and is used to protect the symbol of symbol field 524. For illustration, symbol field 522 includes the value "10", parity field 526 includes the value "0110" (which is the BCH code of symbol field 522), symbol field 524 includes the value "11", and parity field 528 includes the value "0010" (which is the BCH code of symbol field 524).

[0048] Encoding operation 504 is a second-stage operation, a WOM encoding operation (for example, the above regarding...). Figure 3 The discussed operation is operable to encode the output of the first-stage operation 502 (e.g., an ECC-encoded word) into a WOM-encoded word. For example, encoding operation 504 encodes the ECC-encoded word 520 into a WOM-encoded word 530 (e.g., which retains the information of the original ECC-encoded word 520). The WOM-encoded word 530 includes WOM fields 532, 536, 534, and 538, wherein WOM field 532 is the WOM code of symbol field 522, WOM field 536 is the WOM code of symbol field 526, WOM field 534 is the WOM code of symbol field 524, and WOM field 538 is the WOM code of symbol field 528. For illustration, WOM field 532 includes the value "010", WOM field 536 includes the value "100010", WOM field 534 includes the value "100", and WOM field 538 includes the value "000010".

[0049] As mentioned above Figure 3 Each WOM-encoded word includes a 3-bit (e.g., NWOM = 3 width) encoding scheme for each 2-bit symbol to be encoded. Parity fields 526 and 528 are both 4 bits wide, such that 6-bit fields (e.g., WOM fields 536 and 538) are used to store each of the WOM-encoded values ​​of parity fields 526 and 528.

[0050] Decoding operation 506 is a WOM decoding operation (as mentioned above). Figure 3 The discussed method is operable to decode a WOM-encoded word of an ECC-encoded word into (e.g., ideally) the original ECC-encoded word. For example, decoding operation 506 decodes the WOM-encoded word 530 to (e.g., ideally) retrieve the ECC-encoded word 520 encoded in the WOM-encoded word 530.

[0051] Decoding operation 508 is an ECC decoding operation operable to decode ECC-encoded data into valid data. For example, parity fields 526 and 528 are used to make sign fields 522 and 524 valid (e.g., recoverable), respectively. In the event of a 1-bit error, the strength of the ECC encoding (as determined by the type of ECC and the number of correction bits used) is sufficient to correct the error, making the data in word 510 recoverable.

[0052] Figure 6 This is an example encoding diagram of a two-stage WOM encoding and ECC encoding scheme according to an embodiment of the present disclosure. Generally, the data flow diagram 600 includes a word 610, a WOM-encoded word 620, and an ECC-encoded word 630 (with ECC encoding). The WOM encoding 690 of the WOM-encoded word 620 is stored within the ECC encoding 680 of the ECC-encoded word 630.

[0053] Word 610 includes "k" WOM symbols, each stored in a symbol field (such as symbol fields 612 and 614). Accordingly, word 610 includes 2 symbols, each stored in symbol fields 612 and 614 respectively. Therefore, word 610 includes symbol field 612 (for encoding the first symbol) and symbol field 614 (for encoding the second symbol), each of which will be encoded in encoding operation 602. For illustration, symbol field 612 includes the value "10" and symbol field 614 includes the value "11".

[0054] Encoding operation 602 is the first-stage operation, which can be used with WOM encoding operations (as mentioned above). Figure 3 The symbol field of the coded word 610 (e.g., uncoded) discussed is operable for outputting the encoded symbol as a WOM-encoded word. As mentioned above... Figure 3 The WOM-encoded word includes a 3-bit (NWOM = 3 width) encoding scheme for each 2-bit symbol to be encoded (various embodiments include other ratios, such as 4-bit NWOM encoding for each n = 2 width symbol).

[0055] For example, encoding operation 602 encodes word 610 into a WOM-encoded word 620 (e.g., which retains the information of word 610). The WOM-encoded word 620 includes WOM fields 622 and 624, where WOM field 622 is the WOM code for symbol field 612, and WOM field 624 is the WOM code for symbol field 614. For illustration, WOM field 622 includes the value "010" and WOM field 624 includes the value "100".

[0056] Encoding operation 604 is a second-stage operation operable for fields encoded with WOM (Write-Operated Markov Code) using a linear error-correcting code scheme (such as Hamming code or SECDED code). Example encoding operation 604 operates according to an extended Hamming code. For 6 WOM-encoded data bits, an extended Hamming code (16, 11) is indicated, and therefore 5 parity bits are used for each write operation. Given the 2-write capability of the WOM code, two sets of 5-bit parity bits are provided, with different sets of 5 parity bits used for each write operation.

[0057] Encoding operation 604 generates an ECC-encoded word 630. The ECC-encoded word 630 includes a WOM field 632 (e.g., a direct copy of WOM field 622) and a WOM field 634 (e.g., a direct copy of WOM field 624). A parity field 636 is 5 bits long and is used in a first write operation to a specific location on the WOM device to protect (and, for example, correct) the symbols of WOM fields 632 and 634. Similarly, a parity field 638 is 5 bits long and is used to protect the symbols of WOM fields 632 and 634 for a second write operation. As illustrated, WOM field 632 includes the value "010" and WOM field 634 includes the value "100". For the first write operation to a specific memory location, parity field 636 includes the value "XXXXX" (which is a first SECDED encoding of the first set of contents of WOM fields 632 and 634). For a second write operation to a specific location on the WOM device, parity field 638 may include (for example, in this case) an undetermined value “YYYYY”, which is a second SECDED encoding of (for example, arbitrarily) new values ​​of sign fields 632 and 634. For example, parity fields 636 and 638 may be written using an encoding (such as “plain” binary) that differs from the WOM encoding used to encode WOM fields 632 and 634.

[0058] Decoding operation 606 is an ECC decoding operation operable to decode ECC-encoded data into valid data. For example, parity field 636 is used to validate (e.g., restore) WOM fields 632 and 634 after a first write operation, while parity field 638 is used to validate (e.g., restore) WOM fields 632 and 634 after a second write operation. Therefore, the choice of which parity field to use is made based on logical analysis of the retrieved content of WOM fields 632 and 634 (e.g., as discussed above with respect to Table 1), for example, to determine whether a particular memory location is written once or twice. In the event of a 1-bit error, the strength of the ECC encoding in either WOM field 632 or parity field 636 is sufficient to correct the error, making the correct data in WOM field 632 recoverable.

[0059] Decoding operation 608 is a WOM decoding operation (as mentioned above). Figure 3 The discussed method is operable to decode WOM-encoded words of ECC-encoded words to retrieve (e.g., ideally) the original ECC-encoded words. For example, decoding operation 608 decodes WOM-encoded word 620 to (e.g., ideally) retrieve the original data encoded within WOM-encoded word 620 in encoding operation 602.

[0060] Figure 7This is an example flowchart according to an example embodiment. The process begins at endpoint 702, where the process proceeds to operation 710. In operation 710, a data word for storage in the WOM device is received. For example, the first data word includes at least one primitive symbol encoded as at least 2 bits and associated with a memory address to be written to and read from it. The process proceeds to step 720.

[0061] In operation 720, the first stage of encoding is applied to the received data word. This first stage is an encoding operation, which is either ECC encoding or WOM encoding. The process then proceeds to step 730.

[0062] In operation 730, the second stage of encoding is applied to the received data word. The second stage of encoding is an encoding operation that differs from either ECC encoding or WOM encoding, which is selected separately. For example, when the first stage operation is WOM encoding, the second stage is ECC encoding. When the first stage operation is ECC encoding, the second stage operation is WOM encoding. The process proceeds to step 740.

[0063] In operation 740, the word encoded twice (e.g., encoded in stage 1 and stage 2 such that the stage 1 encoding is encapsulated by the stage 2 encoding) is stored in the WOM device. Typically, the WOM device is block initialized (where each WOM bit is set or cleared to the same logic state) and written by changing the bits from the block initialized state to the programmed state (which is the opposite of the block initialized state). As discussed above, through the use of WOM encoding, a specific WOM memory location can be rewritten at least once. The process proceeds to step 750.

[0064] In operation 750, the word stored in the WOM is retrieved, decoded, and evaluated. For example, if the symbol and ECC bit indication of the WOM decoded read from the WOM device are incorrect, the ECC controller can be operated to perform corrective actions in response to the evaluation (such as correcting bit errors, generating a system interrupt, or replacing the defective position of the WOM device with a free storage location). The process proceeds to endpoint 799, where it ends.

[0065] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An electronic device comprising: a write-once memory (WOM) device; and a memory controller comprising: - a host interface to receive a data word comprising a first symbol and a second symbol, each of the first and second symbols having at least two bits; - a WOM controller to encode the first and second symbols and output a WOM-encoded word comprising a first WOM code corresponding to the first symbol and a second WOM code corresponding to the second symbol, wherein each of the first and second WOM codes comprises at least three bits, wherein at least two of the at least three bits have the same logical value; - an error-correcting code (ECC) controller to encode the WOM-encoded word and output an ECC-encoded word comprising the first and second WOM codes and a first set of ECC bits corresponding to a first write operation; and - a storage device interface to write the ECC-encoded word to a first address of the WOM device as part of the first write operation.

2. The electronic device of claim 1, wherein the ECC controller encodes the WOM-encoded word using a Hamming code.

3. The electronic device of claim 1, wherein the ECC controller encodes the WOM-encoded word using a single error correction double error detection (SECDED) code.

4. The electronic device of claim 1, wherein the ECC-encoded word further comprises a second set of ECC bits corresponding to a second write operation, the second set of ECC bits having an undetermined value prior to completion of the first write operation.

5. The electronic device of claim 4, wherein the second set of ECC bits is determined based on updated values of the first and second WOM codes after the first write operation, and the second set of ECC bits corresponds to a second write operation.

6. The electronic device of claim 5, wherein: the first set of ECC bits protects the first and second WOM codes during the first write operation; and the second set of ECC bits protects the updated first and second WOM codes during the second write operation.

7. The electronic device of claim 1, wherein each of the first and second symbols comprises 2 bits, each of the first and second WOM codes comprises 3 bits, and the first set of ECC bits comprises 5 bits.

8. The electronic device of claim 1, wherein the WOM controller encodes every two bits of the data word as a WOM code having three bits.

9. A method for error-correcting code management comprising: performing a first write operation to a write-once memory (WOM) device by: - receiving a data word having a first symbol and a second symbol, each of the first and second symbols comprising at least two bits; ​ - encoding the first symbol and the second symbol using WOM encoding and generating a WOM-encoded word, the WOM-encoded word comprising a first WOM code corresponding to the first symbol and a second WOM code corresponding to the second symbol, each of the first and second WOM codes comprising at least three bits, wherein at least two of the at least three bits have the same logical value; - encoding the WOM-encoded word using error-correcting code encoding, ECC encoding, and generating an ECC-encoded word comprising the first and second WOM codes, a first set of ECC bits and a second set of ECC bits, wherein the first set of ECC bits is generated by ECC encoding the first and second WOM codes and corresponds to the first write operation, and wherein the second set of ECC bits has an undetermined value prior to completion of the first write operation; and - writing the ECC-encoded word to the WOM device.

10. The method of claim 9, comprising: performing a second write operation after the first write operation by: - generating an updated ECC-encoded word using error-correcting code encoding, ECC encoding, the updated ECC-encoded word comprising an updated first WOM code and an updated second WOM code, the first set of ECC bits and the second set of ECC bits, wherein the second set of ECC bits is updated by ECC encoding the updated first and second WOM codes and corresponds to the second write operation; and - writing the updated ECC-encoded word to the WOM device.

11. The method of claim 10, wherein the first set of ECC bits protects the first and second WOM codes during the first write operation and the second set of ECC bits protects the updated first and second WOM codes during the second write operation.

12. The method of claim 9, wherein each of the first and second symbols comprises 2 bits, each of the first and second WOM codes comprises 3 bits, and each of the first and second sets of ECC bits comprises 5 bits.

13. The method of claim 12, wherein the ECC encoding is performed using a (16, 11) extended Hamming code.

14. The method of claim 9, wherein the WOM encoding produces a three-bit WOM code for every two bits of the data word being encoded.

15. The method of claim 9, wherein writing the ECC-encoded word to the WOM device comprises changing a block initialization state of selected bits of the WOM device corresponding to a first address.

16. The method of claim 15, wherein the block initialization state is a block erase state.

17. The method of claim 9, comprising: ​ in response to a request to read the data word from the WOM device after the first write operation but before a second write operation: - decode the first and second WOM codes from the ECC encoded word using ECC decoding; - evaluate whether the decoded first and second WOM codes match the first and second WOM codes and, when the decoded first and second WOM codes do not match the first and second WOM codes, correct the decoded first and second WOM codes using the first set of ECC bits; and - WOM decode the decoded first and second WOM codes to retrieve the first and second symbols.

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