Low voltage anti-fuse element

Abstract

The present invention discloses a low-voltage anti-fuse element, which sequentially has a first gate dielectric layer and a first gate on a substrate, and a first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a pointed corner portion extending and tapering from one side of the body portion, and both the body portion and the pointed corner portion are adjacent to the first gate dielectric layer. During operation, based on the principle that the charge density is higher at the pointed corner, when a write voltage is applied between the first gate and the first ion-doped region, a part of the first gate dielectric layer under the pointed corner portion is prone to breakdown, thereby reducing the breakdown voltage, achieving the purpose of reducing current consumption. At the same time, the gate area can be reduced, the element size can be shrunk, and thus the production cost can be lowered.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory, and more particularly to a low voltage anti-fuse element which utilizes an improved gate structure to reduce a breakdown voltage. Background Art

[0002] In today's advanced computer information products, non-volatile memories with the function of electrically writing and erasing data, such as EEPROM and flash, are widely used in electronic products because the stored data will not disappear after the power is turned off. However, the structure of these read-only memories or caches is relatively complex, the reliability is relatively low, and the manufacturing cost is high. Therefore, many places can use one-time programmable memory (OTP) with high reliability and low manufacturing cost. OTP using fuse or anti-fuse as components is more flexible in use.

[0003] Traditional fuses mainly include metal fuses and polysilicon fuses. The writing method is mainly to burn out the fuse with high-energy laser or high current. After writing, the resistance value of the fuse will increase, consuming more power. Anti-fuse mainly adds a dielectric layer between two conductors in a capacitor manner. When writing, a bias is applied to each of the two ends of the conductor to cause the dielectric layer to collapse and break down. After writing, the resistance value of the anti-fuse will decrease. With the rapid development of integrated circuits, the size of components is shrinking. In recent years, the use of MOS components to make anti-fuse components has been developed, and its writing method is mainly based on the gate dielectric layer collapse mechanism.

[0004] Since the anti-fuse element is based on the rupture of the gate dielectric layer to form a permanent conductive path, its limitation is that a high voltage must be applied to cause the gate dielectric layer to collapse, and a relatively high current is required to achieve the purpose of breaking through the gate dielectric layer. On the other hand, the production of non-volatile memory using advanced process technology often requires the addition of many processes, which not only increases the difficulty of manufacturing, but also increases production costs, especially in embedded products; therefore, the current advanced process technology is all developing towards low voltage. Summary of the invention

[0005] In view of the above problems, the main purpose of the present invention is to provide a low voltage anti-fuse element, in which the gate on the gate dielectric layer is formed with an extended and tapered sharp corner portion. During operation, the density of charges at the sharp corner is higher to reduce the breakdown voltage, which can greatly reduce the current requirement of the programmed anti-fuse element.

[0006] Therefore, to achieve the above object, the present invention provides a low-voltage antifuse element, comprising a substrate, a first gate dielectric layer, a first gate, and a first ion-doped region. The first gate dielectric layer is disposed on the substrate. The first gate includes a body portion and a sharp-corner portion that extends and tapers from one side of the body portion, and the body portion and the sharp-corner portion are adjacent to the first gate dielectric layer. The first ion-doped region is disposed in the substrate on one side of the first gate dielectric layer. Wherein, when a write voltage is applied between the first gate and the first ion-doped region, an electric field is generated, and this electric field will concentrate on the sharp-corner portion, making a part of the first gate dielectric layer below the sharp-corner portion prone to breakdown, so as to reduce the breakdown voltage.

[0007] In an embodiment of the present invention, the substrate is a P-type semiconductor substrate or an N-type semiconductor substrate; when the substrate is a P-type semiconductor substrate, the first ion-doped region is an N-type doped region, and when the substrate is an N-type semiconductor substrate, the first ion-doped region is a P-type doped region.

[0008] In an embodiment of the present invention, it further includes an access transistor adjacent to the first ion-doped region. The access transistor includes a second dielectric layer, a second gate, and a second ion-doped region. The second dielectric layer is disposed on the substrate, the second gate is stacked on the second gate dielectric layer, the second ion-doped region is located in the substrate on the side of the second gate dielectric layer away from the first ion-doped region, and the first ion-doped region and the second ion-doped region are doped with ions of the same type.

[0009] In an embodiment of the present invention, it further includes a well region. The well region is disposed in the substrate and below the first ion-doped region, and the well region and the first ion-doped region are doped with ions of different types.

[0010] Since the gate structure is designed to have a sharp-corner portion, based on the principle that the charge density at the sharp corner is relatively high, the first gate dielectric layer below the sharp corner will be more prone to breakdown. A low operating voltage and low operating current can be used, and at the same time, the gate area can be reduced, achieving the effect of reducing the element size, thereby reducing the production cost of the antifuse element.

[0011] The following is described in detail through specific embodiments in conjunction with the accompanying drawings, and it will be easier to understand the object, technical content, features and achieved effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a plan view of the low-voltage antifuse element according to the first embodiment of the present invention.

[0013] Figure 2 is Figure 1 a cross-sectional view of the low-voltage antifuse element along line A-A.

[0014] Figure 3 is a plan view of the low-voltage antifuse element according to the second embodiment of the present invention.

[0015] Figure 4 For Figure 3 Cross-sectional view of the low-voltage antifuse element along line B-B.

[0016] Explanation of reference numerals: 100 - low-voltage antifuse element; 102 - substrate; 104 - first gate; 105 - body portion; 106 - sharp corner portion; 108 - first gate dielectric layer; 110 - sidewall spacer; 112 - first ion-doped region; 114 - channel region; 116 - bit line contact; 118 - LDD region; 120 - active region; 200 - low-voltage antifuse element; 202 - access transistor; 204 - well region; 206 - second gate; 207 - sidewall spacer; 208 - second gate dielectric layer; 210 - second ion-doped region; 212 - bit line contact; 214 - active region; 216 - LDD region; 218 - channel region; WL - word line; BL - bit line; Vcp - cell screen voltage. Detailed implementation manners

[0017] Please refer to Figure 1 , which shows a plan view of the low-voltage antifuse element provided by the first embodiment of the present invention; at the same time, please refer to Figure 2 , which shows Figure 1 Cross-sectional view of the low-voltage antifuse element.

[0018] In this embodiment, the low-voltage anti-fuse element 100 includes a substrate 102, a first gate 104, a first gate dielectric layer 108, sidewall spacers 110, a first ion-doped region 112, a channel region 114, and a bit-line contact 116. Among them, the first gate dielectric layer 108 is formed on the substrate 102, the first gate 104 is stacked on the first gate dielectric layer 108, the sidewall spacers 110 are disposed on both sides of the first gate 104, the first ion-doped region 112 is formed in the substrate 102 on one side of the first gate dielectric layer 108, and may have a lightly doped drain (LDD) region 118 adjacent to the vertical edge of the first gate dielectric layer 108, and the first ion-doped region 112, the LDD region 118, and the channel region 114 are located in the active region 120. Further, the first gate 104 has a body portion 105 and a pointed corner portion 106 that tapers and extends from a part of one side of the body 105. The body portion 105 and the pointed corner portion 106 are formed above the first gate dielectric layer 108 to contact the first gate dielectric layer 108. More specifically, the shape of the pointed corner portion 106 of the first gate 104 is generally triangular, which extends from one side of the body portion 105. It can use the same or different materials as the body portion 105. The body portion 105 and the pointed corner portion 106 are formed to overlap the active region 120 on the substrate 102, and the number and size of the pointed corner portions 106 are not limited. The preferably number in actual implementation is one, and it can be appropriately selected according to the preset write voltage and the thickness of the first gate dielectric layer 108.

[0019] In this embodiment, the substrate 102 can be a P-type semiconductor substrate or an N-type semiconductor substrate; when the substrate 102 is a P-type semiconductor substrate, the first ion-doped region 112 is an N-type doped region, and when the substrate 102 is an N-type semiconductor substrate, the first ion-doped region 112 is a P-type doped region. The first gate dielectric layer 108 is located under the first gate 104. The first gate dielectric layer 108 is generally uniform in thickness and the material is a relatively thin gate oxide. Its material can be selected from an oxide layer, a nitride layer, an oxynitride layer, a metal oxide layer, or a combination of at least two of an oxide layer, a nitride layer, an oxynitride layer, and a metal oxide layer.

[0020] In this embodiment, the first gate 104 is connected to the word line WL. The first ion-doped region 112 is connected to the bit line BL via the bit line contact 116 or other lines for sensing the current from the first gate 104, and can be doped to adapt to the programmed voltage or current. During the write operation, a write voltage is applied to the first gate 104 through the word line WL, and a bit line voltage is applied to the first ion-doped region 112, thereby generating an electric field between the first gate 104 and the first ion-doped region 112. Using the principle of tip discharge, due to the large concentration of charges at the sharp corner portion 106 of the first gate 104 and the stronger electric field, the write voltage required for a part of the first gate dielectric layer 108 corresponding to the lower part of the sharp corner portion 106 to break down is reduced, making it easier to be broken down and shortening the write time.

[0021] Next, through Figure 3 and Figure 4 describe the second embodiment of the present invention. The low-voltage anti-fuse element 200 can be serially connected to the access transistor 202. Please refer to Figure 3 which shows the plan view of the low-voltage anti-fuse element provided by the second embodiment of the present invention; at the same time, please refer to Figure 4 which shows Figure 3 the cross-sectional view of the low-voltage anti-fuse element 200.

[0022] In this embodiment, the low-voltage anti-fuse element 200 includes an access transistor 202 adjacent to the first ion-doped region 112. The anti-fuse structure of the low-voltage anti-fuse element 200 can be similar to that shown in Figure 1 and Figure 2 so the same previously described components are labeled with the same numbers. More specifically, the structure of the first gate 104 is the same as that shown in Figure 2 and also has a body portion 105 and a sharp corner portion 106, except that the first ion-doped region 112 does not have a bit line contact formed thereon.

[0023] The low-voltage antifuse element 200 and the access transistor 202 have a well region 204 disposed on the substrate 102. A second gate dielectric layer 208 is disposed on the well region 204. The second gate 206 covers the second gate dielectric layer 208 and has sidewall spacers 207 on both sides thereof. A first ion-doped region 112 is formed on one side of the second gate dielectric layer 208. A second ion-doped region 210 is formed on the other side of the second gate dielectric layer 208 and has a bit-line contact 212 formed thereon for making electrical contact with a bit line (not shown in the figure). The second ion-doped region 210 may have a lightly doped (LDD) region 216 adjacent to the vertical edge of the second gate dielectric layer 208. The well region 204 includes an active region 214, and the first ion-doped region 112, the second ion-doped region 210, the LDD region 118, the LDD region 216, the channel region 114, and the channel region 218 are located in the active region 214. The first ion-doped region 112 and the second ion-doped region 210 may be doped with ions of the same type. The first ion-doped region 112 and the well region 204 are doped with ions of different types and may have different doping concentrations, depending on the desired operating voltage.

[0024] In this embodiment, the substrate 102 may be a P-type semiconductor substrate or an N-type semiconductor substrate. When the substrate 102 is a P-type semiconductor substrate, the first ion-doped region 112 and the second ion-doped region 210 are N-type doped regions, and the well region 204 is a P-type doped region. When the substrate 102 is an N-type semiconductor substrate, the first ion-doped region 112 and the second ion-doped region 210 are P-type doped regions, and the well region 204 is an N-type doped region. The first gate dielectric layer 108 is located under the first gate 104. The first gate dielectric layer 108 is relatively thin and substantially uniform in thickness, and its material is a gate oxide. Its material may be selected from an oxide layer, a nitride layer, an oxynitride layer, a metal oxide layer, or a combination of at least two of an oxide layer, a nitride layer, an oxynitride layer, and a metal oxide layer. The low-voltage antifuse elements 100 and 200 of the above embodiments can be fabricated by any standard CMOS process, such as the formation of sidewall spacers, lightly doped (LDD), and gate silicidation. The second gate dielectric layer 208 of the access transistor 202 is formed at the same time as the first gate dielectric layer 108. Therefore, the second gate dielectric layer 208 and the first gate dielectric layer 108 have substantially the same composition and may have the same or different thicknesses.

[0025] The operation of the low-voltage anti-fuse element 200 in this embodiment is similar to that of the low-voltage anti-fuse element 100 in the first embodiment. The second ion-doped region 210 of the access transistor 202 is coupled to the bit line BL through the bit line contact 212 to the first ion-doped region 112, the word line WL is coupled to the second gate 206 of the access transistor 202, and the cell screen voltage Vcp is coupled to the first gate 104. During the write operation, a write voltage is applied to the Vcp polysilicon line, while the bit line BL is grounded, turning on the access transistor 202 to couple the first ion-doped region 112 to ground through the bit line, so as to generate an electric field between the first gate 104 and the first ion-doped region 112. Using the principle of point discharge, due to the large concentration of charges at the sharp corner portion 106 of the first gate 104, the electric field is stronger, so that the write voltage required for the partial breakdown of the first gate dielectric layer 108 corresponding to the lower part of the sharp corner portion 106 is reduced, it is easier to be broken down, and the write time can be shortened.

[0026] In summary, according to the low-voltage anti-fuse element provided by the present invention, this anti-fuse element uses voltage to break down the gate dielectric layer to conduct the circuit. Compared with the shape of the gate of the traditional anti-fuse element above the gate dielectric layer, which is mostly a square with vertical sides and has an average charge density, a high voltage is required, and relatively a higher current is also required. The low-voltage anti-fuse element of the present invention designs the gate structure to have a sharp corner portion. During operation, the charge density at the sharp corner is higher, so that the part of the gate dielectric layer below the sharp corner portion is easy to break down, thereby reducing the breakdown voltage and achieving the purpose of reducing current consumption. At the same time, the present invention can also reduce the gate area, achieve the effect of reducing the element size, and can reduce the production cost.

[0027] The above uses embodiments to illustrate the features of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, rather than limiting the patent scope of the present invention. Therefore, any equivalent modifications or modifications completed without departing from the spirit disclosed by the present invention should still be included in the protection scope of this case.

Claims

1. A low-voltage anti-fuse element, characterized in that Comprising: A substrate; A first gate dielectric layer disposed on the substrate; A first gate including a body portion and a pointed corner portion extending and tapering from one side of the body portion, the body portion and the pointed corner portion being adjacent to the first gate dielectric layer, and the first gate being connected to a word line; And A first ion-doped region disposed in the substrate on one side of the first gate dielectric layer, the first ion-doped region being connected to a bit line; Wherein, the pointed corner portion is only formed on the side of the body portion facing the first ion-doped region; Wherein, the substrate, the first gate dielectric layer, the first gate and the first ion-doped region form a capacitive structure. When the capacitor is in a write operation, a write voltage is applied to the first gate through the word line, and a bit line voltage is applied to the first ion-doped region through the bit line, and an electric field is generated between the first gate and the first ion-doped region. The electric field is concentrated at the pointed corner portion, making a part of the first gate dielectric layer under the pointed corner portion liable to breakdown.

2. The low-voltage antifuse element according to claim 1, characterized in that, The substrate is a P-type semiconductor substrate or an N-type semiconductor substrate.

3. The low-voltage anti-fuse element according to claim 1, wherein The substrate is a P-type semiconductor substrate, and the first ion-doped region is an N-type doped region.

4. The low-voltage anti-fuse element according to claim 1, characterized in that, The substrate is an N-type semiconductor substrate, and the first ion-doped region is a P-type doped region.

5. The low-voltage anti-fuse element according to claim 1, characterized in that, Further comprising a access transistor adjacent to the first ion-doped region, the access transistor comprising: A second gate dielectric layer disposed on the substrate; A second gate stacked on the second gate dielectric layer; and A second ion-doped region located in the substrate on the side of the second gate dielectric layer away from the first ion-doped region, and the first ion-doped region and the second ion-doped region are doped with ions of the same type.

6. The low-voltage anti-fuse element according to claim 5, characterized in that, The second gate dielectric layer and the first gate dielectric layer have the same composition and the same thickness.

7. The low-voltage anti-fuse element according to claim 5, characterized in that, The second gate dielectric layer and the first gate dielectric layer have the same composition and different thicknesses.

8. The low-voltage anti-fuse element according to claim 5, characterized in that, The second ion-doped region is connected to the bit line.

9. The low-voltage antifuse element according to claim 1, characterized in that, The first gate dielectric layer is located under the first gate and has a uniform thickness.

10. The low-voltage anti-fuse element according to claim 1, characterized in that, The first gate dielectric layer is an oxide layer, a nitride layer, an oxynitride layer or a combination of at least two of an oxide layer, a nitride layer, and an oxynitride layer.

11. The low-voltage anti-fuse element according to claim 1, wherein, Further comprising a well region disposed in the substrate and under the first ion-doped region, and the well region is doped with ions of a different type from the first ion-doped region.

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