Three-dimensional memory element and preparation method thereof

Abstract

The present invention discloses a three-dimensional memory device comprising a substrate, multiple horizontal conductive layers, multiple vertical memory structures, and a vertical conductive plate. The multiple horizontal conductive layers are located on the substrate, with a first air gap formed between adjacent two of these conductive layers. The memory structure is connected to the substrate through these conductive layers. The conductive plate is located between adjacent two of these memory structures and is connected to the substrate through these conductive layers. A second air gap is formed between the conductive plate and the edges of the adjacent horizontal conductive layers.

Description

Technical Field

[0001] The present invention relates to a memory device and a manufacturing method thereof, and more particularly to a three-dimensional memory device with high storage density and a manufacturing method thereof. Background Art

[0002] Memory devices are crucial data storage components in portable electronic devices such as MP3 players, digital cameras, laptops, and smartphones. With the proliferation of applications and enhanced functionality, the demand for memory devices is trending towards smaller size and larger storage capacity. To meet this demand, designers are currently developing 3D memory devices, such as vertical channel 3D NAND flash memory devices, which consist of multiple layers of memory cells.

[0003] However, as the critical dimensions of components shrink to the limits of conventional memory cell technology, achieving higher storage capacity within the limitations of existing equipment has become a critical challenge in this field. For example, in high-density three-dimensional memory devices, reducing the capacitance between metal lines and increasing the breakdown voltage are crucial issues. Therefore, there is a need to provide an advanced three-dimensional memory device and its fabrication method to address the challenges faced by conventional technologies. Summary of the Invention

[0004] One embodiment of this specification discloses a three-dimensional memory device comprising a substrate, multiple horizontal conductive layers, multiple vertical memory structures, and a vertical conductive plate. The multiple horizontal conductive layers are disposed on the substrate, with a first air gap formed between adjacent two of these conductive layers. A memory structure is connected to the substrate through these conductive layers. A conductive plate is disposed between adjacent two of these memory structures and is connected to the substrate through these conductive layers. A second air gap is formed between the conductive plate and the edges of the adjacent horizontal conductive layers.

[0005] In other embodiments of the present specification, the first air gap is connected to the second air gap.

[0006] In other embodiments of the present disclosure, the three-dimensional memory device further includes a conformal oxide layer formed on the conductive layers, the memory structures, and the surfaces of the conductive plates exposed on the first and second air gaps.

[0007] In other embodiments of the present disclosure, each memory structure includes a storage layer contacting the conductive layers and a channel layer contacting the storage layer.

[0008] In other embodiments of the present disclosure, a width of the first air gap is about 10 nanometers to about 50 nanometers, and a width of the second air gap is about 10 nanometers to about 100 nanometers.

[0009] In other embodiments of the present disclosure, the three-dimensional memory device further includes a non-conformal layer covering the conductive layers, the memory structures, and the top of the conductive plate.

[0010] In other embodiments of the present disclosure, the non-conformal layer includes a third air gap between the conductive plate and one of the memory structures adjacent thereto, and the third air gap is not connected to the first and second air gaps.

[0011] In other embodiments of the present specification, the three-dimensional memory device further includes a non-conformal layer covering the memory structures and the top of the conductive plate. A third air gap is formed below the non-conformal layer and is located between the conductive plate and one of the memory structures adjacent thereto. The third air gap is connected to the first and second air gaps.

[0012] Another embodiment of the present specification discloses a method for preparing a three-dimensional memory element, which includes the following steps: alternately depositing multiple first insulating layers and second insulating layers on a substrate; etching multiple first through-holes through these first and second insulating layers; forming a vertical memory structure in these first through-holes; etching a channel between two adjacent ones of these memory structures; etching these first insulating layers through the channel to form a gap between these second insulating layers; depositing conductive material into the gap through the channel to form multiple horizontal conductive layers between these second insulating layers; depositing a third insulating layer to cover the sidewalls of the channel; depositing a vertical conductive plate in the channel and located within the third insulating layer; and removing these second and third insulating layers to form a first air gap between two adjacent ones of these horizontal conductive layers and a second air gap between the conductive plate and the edge of the adjacent ones of these horizontal conductive layers.

[0013] In other embodiments of the present disclosure, the method for fabricating a three-dimensional memory device further includes forming a conformal oxide layer on the conductive layers, the memory structures, and the surfaces of the conductive plates exposed on the first and second air gaps.

[0014] According to the aforementioned embodiments, the three-dimensional memory element of the present invention includes air gaps between adjacent word lines and between the source line and the adjacent word line, effectively reducing the capacitance between them and increasing the breakdown voltage between them. Consequently, the sacrificial insulating layer can be made thinner, making it easier to stack more layers. Furthermore, the gap between the source line and the adjacent word line can be reduced, thereby increasing the storage density of the three-dimensional memory element.

[0015] The above description will be described in detail below with reference to implementation examples, and a further explanation of the technical solution of the present invention will be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To make the above and other objects, features, advantages and embodiments of the present invention more apparent, the accompanying drawings are described as follows:

[0017] Figures 1 to 10D The invention shows cross-sectional views of a method for manufacturing a semiconductor memory device in multiple steps according to an embodiment of the present invention.

[0018] To make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying symbols are explained as follows:

[0019] 102...Substrate

[0020] 104...Insulation layer

[0021] 104a...air gap

[0022] 106...Insulation layer

[0023] 106a...Gap

[0024] 108...conductive layer

[0025] 110...Hard mask layer

[0026] 113...cover oxide layer

[0027] 114...Memory Structure

[0028] 114a...Storage Layer

[0029] 114b...Channel layer

[0030] 115a...Epitaxial silicon

[0031] 115b...bonding pad

[0032] 116...Through hole

[0033] 126...channel

[0034] 130...conductive plate

[0035] 132...Insulation layer

[0036] 132a...air gap

[0037] 136...Oxide layer

[0038] 140...Non-conformal layer

[0039] 150...Non-conformal layer

[0040] 152...air gap

[0041] 160...Non-conformal layer

[0042] 162...air gap

[0043] 170...Non-conformal layer

[0044] 172...air gap

[0045] W1...width

[0046] W2...width DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0048] This specification provides a method for fabricating a three-dimensional memory device, which can achieve higher storage capacity within a smaller device size while maintaining device operational stability. To facilitate understanding of the aforementioned embodiments and other objectives, features, and advantages of this specification, a memory device and its fabrication method are described below as a preferred embodiment, along with accompanying drawings.

[0049] However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention may still be implemented using other features, components, methods, and parameters. The preferred embodiments are merely intended to illustrate the technical features of the present invention and are not intended to limit the claims of the present invention. Those skilled in the art will be able to make equivalent modifications and changes based on the description below without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0050] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section.

[0051] The terms used herein are intended only to describe specific embodiments of the present invention and are not intended to limit the present invention. For example, the terms "a", "an" and "the" used herein do not limit the elements to be in the singular or in the plural. "Or" as used herein means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" or "comprise" specify the presence and / or parts of the features, regions, wholes, steps, operations, elements, parts and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or combinations thereof.

[0052] Please refer to Figures 1 to 10D , which depicts a cross-sectional view of a semiconductor memory device fabrication method in multiple steps according to an embodiment of the present specification.

[0053] Reference Figure 1 A plurality of insulating layers 104 and 106 are alternately deposited on a semiconductor substrate 102 or on an oxide layer above the semiconductor substrate to form a multilayer stacked structure. In some embodiments of the present specification, the insulating layer 104 may be made of a dielectric material including an oxide material such as silicon oxide, and the insulating layer 106 may be made of a dielectric material such as a nitride material such as silicon nitride. A hard mask layer 110 is further deposited on the multilayer stacked structure, and the hard mask layer 110 may be made of a dielectric material different from that of the insulating layer 104. In this embodiment, the hard mask layer 110 may be deposited on the topmost insulating layer 104.

[0054] Reference Figure 2 , an etching step is performed to form a plurality of through holes 116 on the multilayer stack structure, thereby forming an array of through holes (i.e., a plurality of rows of through holes). Each through hole 116 passes through the multilayer stack structure (104, 106) and the hard mask layer 110 to expose the substrate 102. In some embodiments of the present specification, the plurality of through holes 116 may have an O-shaped, circular, elliptical, or rectangular shape, but is not limited thereto. In some embodiments of the present specification, an anisotropic etching process, such as a reactive ion etching (RIE) process, is performed using the hard mask layer 110 as an etching mask to pattern the plurality of through holes 116 through the multilayer stack structure.

[0055] Reference Figure 3, a memory layer 114a and a channel layer 114b are then formed on the bottom and sidewalls of each through-hole 116 through a deposition process to form a vertical memory structure 114. In some embodiments of the present disclosure, the memory layer 114a may be a composite layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer (i.e., an ONO composite layer), but the structure of the memory layer is not limited thereto. In other embodiments of the present specification, the composite layer of the memory layer may also be selected from the group consisting of an oxide-nitride-oxide-nitride-oxide (ONONO) structure, a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, a tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon (TANOS) structure, and a metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structure. In this embodiment, the memory layer 114a comprises an ONO composite layer. The channel layer 114b can be made of a doped or undoped semiconductor material, and in this embodiment, can be made of polysilicon. In some other embodiments, epitaxial silicon (self-epitaxial-growth silicon) 115a can be deposited at the bottom of each via 116, and a bonding pad 115b can be deposited at the top of each via 116. A cap oxide layer 113 can also be deposited over the hard mask layer 110 and vias 116 to protect the memory structure 114 within the vias 116.

[0056] Reference Figure 4 An etching step is performed to form a trench 126 between two adjacent memory structures 114 to penetrate the insulating layer 104 and the insulating layer 106 of the multi-layer stack structure, thereby exposing the substrate 102 .

[0057] Reference Figure 5A wet etching process is then performed to remove the insulating layer 106 from the multi-layer stack until the sidewalls of the memory structure 114 are exposed in each trench 126. The etching is performed by filling the insulating layer 106 with an etchant that etches at a much faster rate than the insulating layer 104 and the memory layer 114a. This etching process etches all of the insulating layer 106 between the insulating layers 104, thereby forming gaps 106a between the remaining (unetched) insulating layers 104. Consequently, the sidewalls of the memory structure 114 (i.e., the sidewalls of the memory layer 114a) are exposed in each trench 126. The memory structure 114 serves as a support pillar to prevent the remaining insulating layer 104 from collapsing due to the gaps 106a therebetween.

[0058] Reference Figure 6 Conductive material is deposited into each trench 126 to form a conductive layer 108 filling the gap. Each conductive layer 108 should extend or touch the exposed sidewalls of memory structure 114. The conductive material may include a metal such as copper, aluminum, tungsten, or a metal alloy thereof. An additional etching process is performed to remove excess conductive material in trenches 126, separating adjacent conductive layers 108 from each other to prevent bridging between adjacent conductive layers 108. Conductive layer 108 may also serve as a "word line" in the three-dimensional memory element.

[0059] refer to Figure 7 An oxide insulating layer 132 may be deposited on the sidewalls of each trench 126, and a vertical conductive wall or plate 130 may be deposited within the oxide insulating layer 132 and in contact with the oxide insulating layer 132. The conductive plate 130 is separated from the edges of the conductive layer 108 and the insulating layer 104 by the oxide insulating layer 132. The vertical conductive plate 130 includes a metal such as copper, aluminum, tungsten, or a metal alloy thereof, and may also serve as a "source line" in the three-dimensional memory element.

[0060] Reference Figure 8 Another wet etching process is then performed to remove all oxide layers (including the insulating layer 104, the oxide insulating layer 132, the hard mask layer 110, and the cap oxide layer 113). The wet etching process is performed by filling the oxide material with an etchant that etches the oxide material much faster than the conductive layer 108, the conductive plate 130, and the memory layer 114a. This etches all oxide layers, thereby forming a gap between the remaining (unetched) conductive layer 108 and the conductive plate 130. The memory structure 114 still serves as a support pillar, thereby supporting the remaining conductive layer 108, for example, so that the conductive layer 108 does not collapse due to the gap therebetween.

[0061] In some embodiments of the present specification, air gap 104a is formed between two adjacent conductive layers 108 and has a width (W1) ranging from approximately 10 nanometers to approximately 50 nanometers. In some embodiments of the present specification, air gap 104a may have a width (W1) less than approximately 20 nanometers. In some embodiments of the present specification, air gap 132a is formed between conductive plate 130 and an edge adjacent to conductive layer 108 and has a width (W2) ranging from approximately 10 nanometers to approximately 100 nanometers. In some embodiments of the present specification, air gap 132a may have a width (W2) less than approximately 50 nanometers. In some embodiments of the present specification, air gap 104a is connected to air gap 132a.

[0062] Reference Figure 9 A conformal oxide layer 136 may be formed on the surfaces of the conductive layer 108, memory structure 114, and conductive plate 130 exposed to the air gaps (104a, 132a), but is not limited thereto. In some embodiments of the present disclosure, the oxide layer 136 may have a uniform thickness ranging from approximately 1 nanometer to approximately 5 nanometers. The conformal oxide layer 136 serves to firmly secure the conductive layer 108 to the memory structure 114, making it less likely that the conductive layer 108 will collapse due to the voids or air gaps therebetween. Therefore, the air gaps (104a, 132a) are enclosed between the oxide layer 136.

[0063] Reference Figure 10A , the non-conformal layer 140 is deposited over the top of the conductive layer 108, the memory structure 114, and the conductive plate 130, and does not fill in the air gaps (104a, 132a).

[0064] Reference Figure 10B , non-conformal layer 150 is deposited over the top of conductive layer 108, memory structure 114, and conductive plate 130, and does not fill the air gaps (104a, 132a). Air gap 152 is formed within non-conformal layer 150 and is located between conductive plate 130 and the adjacent memory structure 114. Air gap 152 does not connect to air gaps (104a, 132a).

[0065] Reference Figure 10C , non-conformal layer 160 is deposited over the top of conductive layer 108, memory structure 114, and conductive plate 130, and does not fill the air gaps (104a, 132a). Air gap 162 is formed within non-conformal layer 160 and is located between conductive plate 130 and the adjacent memory structure 114. Air gap 162 has a different shape than air gap 152. Air gap 162 does not connect to air gaps (104a, 132a).

[0066] Reference Figure 10D , non-conformal layer 170 is deposited on top of memory structure 114 and conductive plate 130 and does not fill air gaps (104a, 132a). Therefore, air gap 172 is formed below non-conformal layer 170 and between conductive plate 130 and the immediately adjacent memory structure 114. Air gap 172 communicates with air gaps (104a, 132a).

[0067] In some embodiments of the present disclosure, the aforementioned non-conformal layers ( 140 , 150 , 160 , 170 ) are made of a dielectric material, such as oxide or nitride.

[0068] According to the aforementioned embodiments, the 3D memory device of the present invention has an air gap between adjacent word lines (i.e., conductive layer 108), and an air gap between the source line (i.e., conductive plate 130) and the adjacent word line, effectively reducing the capacitance between them and increasing the breakdown voltage between them. Consequently, the sacrificial insulating layer (i.e., insulating layers 104 and 106) can be made thinner, making it easier to stack more layers. Furthermore, the gap between the source line and the adjacent word line can be reduced, thereby increasing the storage density of the 3D memory device.

[0069] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A three-dimensional memory device, comprising: a substrate; A plurality of horizontal conductive layers are located on the substrate, wherein a first air gap is formed between two adjacent conductive layers; a plurality of vertical memory structures connected to the substrate through the conductive layers; as well as a vertical conductive plate located between two adjacent ones of the memory structures and extending through the conductive layers to connect to the substrate, wherein a second air gap is formed in the horizontal direction between the conductive plate and the edges of the adjacent ones of the horizontal conductive layers, the second air gap filling the entire area between the vertical conductive plate and the corresponding vertical memory structure; a conformal oxide layer having a first portion formed between the first air gap and the vertical memory structures, and a second portion formed between the first air gap and the conductive layers, wherein the first portion and the second portion have uniform thickness; and A non-conformal layer covers the conductive layers, the memory structures and the top of the conductive plate. The non-conformal layer includes a third air gap between the conductive plate and one of the memory structures adjacent thereto. The third air gap is not connected to the first and second air gaps.

2. The three-dimensional memory element according to claim 1, wherein: The first air gap communicates with the second air gap.

3. The three-dimensional memory element according to claim 1, wherein The conformal oxide layer is also formed on the surface of the conductive plate exposed at the two air gaps.

4. The three-dimensional memory element according to claim 1, wherein: Each of the memory structures includes a storage layer contacting the conductive layers and a channel layer contacting the storage layer.

5. The three-dimensional memory element according to claim 1, wherein The first air gap has a width of about 10 nanometers to about 50 nanometers, and the second air gap has a width of about 10 nanometers to about 100 nanometers.

6. A method for preparing a three-dimensional memory element, wherein: Include: Alternatingly depositing a plurality of first insulating layers and second insulating layers on a substrate; Etching a plurality of first through holes through the first and second insulating layers; forming a vertical memory structure in the first through holes; Etching a trench between two adjacent ones of the memory structures; etching the first insulating layers through the trench to form gaps between the second insulating layers; depositing a conductive material through the trench into the gap to form a plurality of horizontal conductive layers between the second insulating layers; depositing a third insulating layer to cover the sidewalls of the trench; Depositing a vertical conductive plate in the trench and within the third insulating layer; as well as removing the second insulating layer and the third insulating layer to form a first air gap between two adjacent horizontal conductive layers and a second air gap in the horizontal direction between the conductive plate and the edge of the adjacent horizontal conductive layers; wherein the second air gap fills the entire area between the vertical conductive plate and the corresponding vertical memory structure; forming a conformal oxide layer on surfaces of the conductive layers and the memory structures exposed in the first air gap, wherein the conformal oxide layer has a uniform thickness in a first portion formed between the first air gap and the vertical memory structures and in a second portion formed between the first air gap and the conductive layers; forming a non-conformal layer covering the conductive layers, the memory structures, and the top of the conductive plate; A third air gap is formed in the non-conformal layer and is located between the conductive plate and one of the memory structures adjacent thereto. The third air gap is not connected to the first and second air gaps.

7. The preparation method according to claim 6, wherein The method further comprises forming the conformal oxide layer on the surface of the conductive plate exposed in the two air gaps.

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