Image sensing device

Abstract

The present invention discloses an image sensing device. The image sensing device includes a first unit pixel provided with a first photoelectric conversion element and a first floating diffusion area, a second unit pixel provided with a second photoelectric conversion element and a second floating diffusion area, a third unit pixel provided with a third photoelectric conversion element and a third floating diffusion area, and a fourth unit pixel provided with a fourth photoelectric conversion element and a fourth floating diffusion area. The first unit pixel to the fourth unit pixel are isolated from each other by a first device isolation structure. The first floating diffusion area to the fourth floating diffusion area are connected to a common floating diffusion node by a wire. At least one unit pixel of the first unit pixel to the fourth unit pixel includes a conversion gain transistor connected to the common floating diffusion node, and the conversion gain transistor is configured to adjust the capacitance of the common floating diffusion node in response to a gain control signal provided to the conversion gain transistor.

Description

Technical Field

[0001] The technologies and implementations disclosed in this patent document generally relate to image sensing devices. Background Art

[0002] Image sensors are semiconductor devices used to convert optical images into electrical signals. In recent years, with the continuous development of the computer industry and the communications industry, the demand for high-quality, high-performance image sensors has increased rapidly in various fields such as digital cameras, camcorders, personal communication systems (PCS), game consoles, surveillance cameras, medical micro cameras, robots, etc.

[0003] Image sensing devices can be roughly divided into image sensors based on CCD (charge coupled device) and image sensors based on CMOS (complementary metal oxide semiconductor). CMOS image sensors have a simpler and more convenient driving scheme, and therefore may be preferred in certain applications. In addition, CMOS image sensors can integrate signal processing circuits into a single chip, making CMOS image sensors easy to miniaturize for implementation in products, and an additional benefit is that they consume very low power. CMOS image sensors can be manufactured using CMOS processes to obtain low manufacturing costs. CMOS image sensors have been intensively studied, and CMOS image sensors have been widely used and designed to achieve high-resolution images.

[0004] Furthermore, as the image resolution of CMOS image sensors gradually increases, the size of each pixel gradually decreases so that the number of pixels can be increased without increasing the size of the chip. Summary of the invention

[0005] Various embodiments of the disclosed technology are directed to an image sensing device with a high dynamic range, which can obtain low illumination and high illumination characteristics by adjusting conversion gain.

[0006] Various embodiments of the disclosed technology are directed to an image sensing device having a new layout structure capable of adjusting a conversion gain in a shared pixel structure configured to share a floating diffusion (FD) region.

[0007] According to one embodiment of the disclosed technology, an image sensing device may include: a first unit pixel, the first unit pixel including a first photoelectric conversion element and a first floating diffusion area, the first photoelectric conversion element being configured to generate photocharges in response to incident light, and the first floating diffusion area being configured to receive the photocharges generated by the first photoelectric conversion element; a second unit pixel, the second unit pixel including a second photoelectric conversion element and a second floating diffusion area, the second photoelectric conversion element being configured to generate photocharges in response to incident light, and the second floating diffusion area being configured to receive the photocharges generated by the second photoelectric conversion element; a third unit pixel, the third unit pixel including a third photoelectric conversion element and a third floating diffusion area, the third photoelectric conversion element being configured to generate photocharges in response to incident light, and the third floating diffusion area being configured to receive the photocharges generated by the third photoelectric conversion element; and a fourth unit pixel, the fourth unit pixel including a fourth photoelectric conversion element and a fourth floating diffusion area, the fourth photoelectric conversion element being configured to generate photocharges in response to incident light, and the fourth floating diffusion area being configured to receive the photocharges generated by the fourth photoelectric conversion element. The first to fourth unit pixels may be isolated from each other by a first device isolation structure. The first to fourth floating diffusion regions may be connected to a common floating diffusion node by a wire. At least one unit pixel of the first to fourth unit pixels may include a conversion gain transistor connected to the common floating diffusion node, and the conversion gain transistor is configured to adjust the capacitance of the common floating diffusion node in response to a gain control signal provided to the conversion gain transistor.

[0008] According to another embodiment of the disclosed technology, an image sensing device may include a plurality of pixel groups arranged along a first direction and a second direction perpendicular to the first direction. Each pixel group may include unit pixels isolated from each other by a first device isolation structure. Each unit pixel may include: a photoelectric conversion element configured to generate photocharges by performing photoelectric conversion of incident light; a floating diffusion area configured to receive photocharges; and a transfer transistor configured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion area. The floating diffusion area of ​​the unit pixel may be connected to a common floating diffusion node by a wire. At least one of the unit pixels may include a conversion gain transistor configured to adjust the capacitance of the common floating diffusion node in response to a gain control signal provided to the conversion gain transistor.

[0009] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are illustrative and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above-described and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0011] Figure 1 is an example of a block diagram illustrating an image sensing device based on some implementations of the disclosed technology.

[0012] Figure 2 Some implementations based on the disclosed technology are shown Figure 1 An example of a schematic diagram of a layout structure of a pixel group (PXG) is shown.

[0013] Figure 3 is a diagram showing some implementations based on the disclosed technology. Figure 1 An example of an equivalent circuit diagram of an equivalent circuit corresponding to the pixel group (PXG) shown.

[0014] Figure 4A Some implementations based on the disclosed technology are shown Figure 2 An example of a schematic diagram of a layout structure of a unit pixel (PX1) included in a pixel group (PXG) is shown.

[0015] Figure 4B Some implementations based on the disclosed technology are shown Figure 2 An example of a schematic diagram of a layout structure of a unit pixel (PX2) included in a pixel group (PXG) is shown.

[0016] Figure 4C Some implementations based on the disclosed technology are shown Figure 2 An example of a schematic diagram of a layout structure of a unit pixel (PX3) included in a pixel group (PXG) is shown.

[0017] Figure 4D Some implementations based on the disclosed technology are shown Figure 2 An example of a schematic diagram of a layout structure of a unit pixel (PX4) included in a pixel group (PXG) is shown.

[0018] Figure 5 is a diagram showing some implementations based on the disclosed technology. Figure 4C A cross-sectional view of an example of a unit pixel taken along line AA′ is shown. DETAILED DESCRIPTION

[0019] This patent document provides implementations and examples of image sensing devices, and the disclosed features can be implemented to substantially solve one or more problems caused by limitations and shortcomings of various image sensing devices. Some implementations of the disclosed technology can propose a design of an image sensing device with a high dynamic range, which can obtain low illumination (illuminance) and high illumination characteristics by adjusting the conversion gain. Some implementations of the disclosed technology can be used to provide a design of an image sensing device with a new layout structure capable of adjusting the conversion gain in a shared pixel structure of a shared floating diffusion (FD) area. For example, the disclosed technology provides various implementations of an image sensing device capable of improving its operating characteristics, and also provides various implementations of an image sensing device capable of adjusting the conversion gain in a shared structure in which multiple pixels share a floating diffusion (FD) area without increasing the size of the pixel.

[0020] Reference will now be made in detail to certain embodiments, examples of which are shown in the accompanying drawings. The same reference numerals will be used throughout the drawings to refer to the same or similar components as much as possible. In the following description, detailed descriptions of related known configurations or functions included herein will be omitted to avoid confusing the subject matter.

[0021] Figure 1 is a block diagram illustrating an example of an image sensing device 100 based on some implementations of the disclosed technology.

[0022] Reference Figure 1 , the image sensing device 100 may include a pixel array 110, a row decoder 120, a correlated double sampler (CDS) circuit 130, an analog-to-digital converter (ADC) circuit 140, an output buffer 150, a column decoder 160, and a timing controller 170. In this case, the above-mentioned constituent elements of the image sensing device 100 are disclosed only for the purpose of explanation, and at least some elements may be added to or omitted from the image sensing device 100 as needed.

[0023] The pixel array 110 may include a plurality of pixel groups (PXG) arranged continuously and repeatedly in a matrix shape. Each pixel group (PXG) may include a plurality of unit pixels to convert incident light received from the outside into an electrical signal. Each unit pixel may include a photosensitive pixel that generates a photocharge by converting the incident light into an electrical signal. The unit pixels included in each pixel group (PXG) may be shared pixels, wherein the floating diffusion (FD) regions respectively formed in the unit pixels are connected to each other by wires. Each unit pixel may receive a drive signal including a selection signal, a reset signal, a transfer signal, a gain control signal, etc. from a row decoder 120 through a row line, and may be driven by the drive signal.

[0024] The row decoder 120 may drive the pixel array 110 upon receiving a control signal from the timing controller 170. Specifically, the row decoder 120 may select at least one row line from a plurality of row lines of the pixel array 110. In order to select at least one row line from a plurality of row lines, the row decoder 120 may generate a row selection signal. The row decoder 120 may sequentially enable a pixel reset signal and a transmission signal for pixels corresponding to at least one selected row line. Therefore, an analog reference signal and an analog image signal may be generated by each pixel included in the selected row line, so that the analog reference signal and the analog image signal generated by each pixel included in the selected row line may be sequentially transmitted to the correlated double sampler (CDS) circuit 130. In this case, the reference signal and the image signal generated by each pixel may be collectively referred to as a pixel signal as needed.

[0025] The correlated double sampler (CDS) circuit 130 may sequentially sample and hold reference signals and image signals transmitted to a plurality of column lines from the pixel array 110. That is, the correlated double sampler (CDS) circuit 130 may sample and hold the levels of the reference signal and the image signal corresponding to each column of the pixel array 110.

[0026] The correlated double sampler (CDS) circuit 130 may transmit a correlated double sampling (CDS) signal corresponding to the reference signal and the image signal of each column to the ADC circuit 140 upon receiving a control signal from the timing controller 170 .

[0027] The ADC circuit 140 may receive the CDS signal of each column from the CDS circuit 130, may convert the received CDS signal into a digital signal, and may output the digital signal therefrom. The ADC circuit 140 may perform counting and calculation operations based on the CDS signal of each column and the ramp signal received from the timing controller 170, so that the ADC circuit 140 may generate digital image data from which noise corresponding to each column (e.g., unique reset noise for each pixel) is removed.

[0028] The ADC circuit 140 may include a plurality of column counters corresponding to the respective columns of the pixel array 110, and may convert the CDS signal of each column into a digital signal using the column counters. According to another embodiment, the ADC circuit 140 may include a single global counter, and may convert the CDS signal corresponding to each column into a digital signal using a global code received from the global counter.

[0029] The output buffer 150 may receive the image data of each column output from the ADC circuit 140, may capture the received image data, and may output the captured image data. The output buffer 150 may temporarily store the image data output from the ADC circuit 140 upon receiving a control signal from the timing controller 170. The output buffer 150 may serve as an interface configured to compensate for a transmission speed difference (or a processing speed difference) between the image sensor 100 and another device coupled to the image sensor 100.

[0030] The column decoder 160 may select a column of the output buffer 150 upon receiving a control signal from the timing controller 170, and the image data temporarily stored in the selected column of the output buffer 150 may be sequentially output. In more detail, the column decoder 160 may receive an address signal from the timing controller 170, may generate a column selection signal based on the received address signal, and may select a column of the output buffer 150, so that the column decoder 160 may control the image data of the selected column from the output buffer 150 to be output as the output signal SO.

[0031] The timing controller 170 may control the row decoder 120 , the ADC circuit 140 , the output buffer 150 , and the column decoder 160 .

[0032] The timing controller 170 may transmit clock signals required for constituent elements of the image sensor 100, control signals required for timing control, and address signals required for selecting a row or column to the row decoder 120, the column decoder 160, the ADC circuit 140, and the output buffer 150. According to an embodiment, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0033] Figure 2 Some implementations based on the disclosed technology are shown Figure 1 An example of a schematic diagram of a layout structure of a pixel group (PXG) is shown.

[0034] Reference Figure 2 , each pixel group (PXG) may include 4 unit pixels PX1 to PX4. The unit pixels PX1 to PX4 may be arranged to be contiguous or adjacent to each other in a first direction (X-axis direction) and a second direction (Y-axis direction) perpendicular to the first direction. For example, the unit pixels PX1 to PX4 may be arranged in the shape of a (2×2) matrix.

[0035] Each of the unit pixels PX1 to PX4 may be an isolated pixel physically isolated from a continuous or adjacent unit pixel by a device isolation structure ISO1. For example, each of the unit pixels PX1 to PX4 includes its own photoelectric conversion element PD1 to PD4, a single floating diffusion (FD) region FD1 to FD4, or a transistor. Therefore, any two unit pixels do not share the photoelectric conversion element PD1 to PD4, the floating diffusion (FD) region FD1 to FD4, and the transistor (TX1 to TX4, DX1 to DX3, SX1 to SX3, RX, CGX).

[0036] In some embodiments, the device isolation structure ISO1 may include a trench isolation structure in which the substrate is etched to a predetermined depth and an insulating material fills the etched area. For example, the device isolation structure ISO1 may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a combination thereof.

[0037] Electrical connection between elements included in different unit pixels may be achieved through conductive lines (eg, metal lines) formed on a substrate.

[0038] Each of the unit pixels PX1 to PX4 may include a backside illuminated (BSI) structure or a frontside illuminated (FSI) structure.

[0039] Each of the unit pixels PX1 to PX4 may include a single photoelectric conversion element (any one of PD1 to PD4), a single floating diffusion (FD) region (any one of FD1 to FD4), and three transistors. Figure 2 In the example shown, the type of transistors included in some unit pixels included in the pixel group (PXG) may be different from the type of transistors included in other unit pixels. Figure 2 , the three unit pixels PX1, PX2, and PX4 included in the pixel group (PXG) may include three transistors, including a transfer transistor (any one of TX1, TX2, and TX4), a source follower transistor (any one of DX1, DX2, and DX4), and a selection transistor (any one of SX1, SX2, and SX4). The unit pixel PX3 included in the pixel group (PXG) may include a transfer transistor TX3, a reset transistor RX, and a conversion gain transistor CGX.

[0040] In the above implementation, the four unit pixels PX1 to PX4 include a total of 12 transistors, including 4 transfer transistors, 3 source follower transistors, 3 selection transistors, a single reset transistor and a single conversion gain transistor, and each of the unit pixels PX1 to PX4 may include 3 transistors.

[0041] As an example, four transfer transistors may be formed in the unit pixels PX1 to PX4, respectively. Three source follower transistors may be formed in the three unit pixels PX1, PX2, and PX4, respectively. Three selection transistors may be formed in the three unit pixels PX1, PX2, and PX4, respectively. In the remaining unit pixel PX3 where the source follower transistor and the selection transistor are not formed, a single reset transistor and a single conversion gain transistor may be formed.

[0042] The photoelectric conversion elements PD1 to PD4 may be formed in the corresponding unit pixels PX1 to PX4 on a one-to-one basis. The photoelectric conversion elements PD1 to PD4 may generate photocharges by performing photoelectric conversion of incident light. Each unit pixel includes a photoelectric conversion element including, for example, a photodiode, a photogate, a phototransistor, a photoconductor, or some other photosensitive structure capable of generating photocharges.

[0043] The floating diffusion (FD) regions FD1 to FD4 may receive photocharges generated by the photoelectric conversion elements PD1 to PD4 through the transfer transistors TX1 to TX4, and may temporarily store the received photocharges. The floating diffusion (FD) regions FD1 to FD4 may be electrically connected to each other through wires. Therefore, the unit pixels PX1 to PX4 included in the pixel group (PXG) may be configured to share the floating diffusion (FD) regions FD1 to FD4 and have a 4-shared pixel structure.

[0044] The length of the wire that electrically connects the floating diffusion (FD) regions to each other depends on the arrangement of the floating diffusion (FD) regions connected by the wire. In order to minimize the length of the wire that connects the floating diffusion (FD) regions FD1 to FD4 to each other, the floating diffusion (FD) regions can be placed as close as possible in the pixel group (PXG). For example, the floating diffusion (FD) regions FD1 to FD4 can be located closest to each other within the pixel group (PXG). For example, the floating diffusion (FD) regions FD1 to FD4 can be arranged near the corner regions of the corresponding unit pixels PX1 to PX4, so that the floating diffusion regions FD1 to FD4 can meet near the center portion of the pixel group (PXG).

[0045] In the unit pixels (PX1 to PX4), the transfer transistors TX1 to TX4 may be arranged to be continuous or adjacent to the floating diffusion (FD) regions FD1 to FD4 in the first direction. In the unit pixels PX1, PX2, and PX4, the source follower transistors DX1 to DX3 may be arranged to be continuous or adjacent to the floating diffusion (FD) regions FD1, FD2, and FD4 in the second direction, and the selection transistors SX1 to SX3 may be arranged to be continuous or adjacent to the source follower transistors DX1 to DX3 in the first direction. In the unit pixel PX3, the conversion gain transistor CGX may be arranged to be continuous or adjacent to the floating diffusion (FD) region FD3 in the second direction, and the reset transistor RX may be arranged to be continuous or adjacent to the conversion gain transistor CGX in the first direction.

[0046] The unit pixels PX1 to PX4 may include tap regions T1 to T4, respectively. The tap regions T1 to T4 may be located on one side of the transfer transistors TX1 to TX4 in the first direction. Therefore, the tap regions T1 to T4 may be located opposite to the floating diffusion (FD) regions FD1 to FD4, respectively. Here, each of the tap regions T1 to T4 may apply a bias voltage to the well region of the substrate.

[0047] As described above, the unit pixels PX1, PX2, and PX4 may include the same constituent elements. In this case, the constituent elements included in the unit pixel PX1 and the constituent elements included in the unit pixel PX2 may be arranged to be symmetrical to each other with respect to the boundary area between the unit pixel PX1 and the unit pixel PX2. In addition, the constituent elements included in the unit pixel PX2 and the constituent elements included in the unit pixel PX4 may be arranged to be symmetrical to each other with respect to the boundary area between the unit pixel PX2 and the unit pixel PX4.

[0048] Although for ease of description, Figure 2 An exemplary case in which the reset transistor RX and the conversion gain transistor CGX are formed in the unit pixel PX3 is shown, but this implementation is provided only as an example, and other implementations are possible. For example, the reset transistor RX and the conversion gain transistor CGX may be formed in any one of the unit pixels PX1, PX2, and PX4, and the selection transistor and the source follower transistor may be formed in the unit pixel PX3.

[0049] Figure 3 is a diagram showing some implementations based on the disclosed technology. Figure 1 An example of an equivalent circuit diagram of an equivalent circuit corresponding to the pixel group (PXG) shown.

[0050] Reference Figure 3, the pixel group (PXG) may include photoelectric conversion elements PD1 to PD4, floating diffusion regions FD1 to FD4, transfer transistors TX1 to TX4, source follower transistors DX1 to DX3, selection transistors SX1 to SX3, reset transistor RX, conversion gain transistor CGX and conversion gain capacitor C.

[0051] Each of the photoelectric conversion elements PD1 to PD4 may perform photoelectric conversion on incident light and may thereby generate photocharges corresponding to the amount of incident light. Each of the photoelectric conversion elements PD1 to PD4 may be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0052] The transfer transistors TX1 to TX4 may be coupled to the photoelectric conversion elements PD1 to PD4 and the floating diffusion areas FD1 to FD4. In some embodiments, the transfer transistor TX1 may be coupled to the photoelectric conversion element PD1 and the floating diffusion area FD1, the transfer transistor TX2 may be coupled to the photoelectric conversion element PD2 and the floating diffusion area FD2, the transfer transistor TX3 may be coupled to the photoelectric conversion element PD3 and the floating diffusion area FD3, and the transfer transistor TX4 may be coupled to the photoelectric conversion element PD4 and the floating diffusion area FD4. Therefore, one terminal of each of the transfer transistors TX1 to TX4 may be coupled to the photoelectric conversion element PD1 to PD4 in the same unit pixel, and the other terminal of each of the transfer transistors TX1 to TX4 may be coupled to the floating diffusion areas FD1 to FD4 in the same unit pixel. The transfer transistors TX1 to TX4 may be turned on or off in response to the transfer signals TS1 to TS4 applied to the gate terminals thereof, so that the transfer transistors TX1 to TX4 may transfer the photocharges generated by the photoelectric conversion elements PD1 to PD4 to the corresponding floating diffusion areas FD1 to FD4.

[0053] The floating diffusion regions FD1 to FD4 may be electrically and commonly connected to each other through a wire, thereby forming a common floating diffusion (CFD) node. The common floating diffusion (CFD) node may be modeled as a single junction capacitor connected in parallel with the floating diffusion regions FD1 to FD4. The capacitance of the common floating diffusion (CFD) node may be represented by the sum of the capacitances of the floating diffusion regions FD1 to FD4. The common floating diffusion (CFD) node may receive photoelectric charges of the photoelectric conversion elements PD1 to PD4 through transfer transistors TX1 to TX4, and may temporarily store the received photoelectric charges.

[0054] The source follower transistors DX1 to DX3 may be connected to the selection transistors SX1 to SX3 corresponding thereto and a power supply voltage (VDD) node. In some implementations, one terminal of the source follower transistor DX1 may be connected to the power supply voltage (VDD) node, and the other terminal of the source follower transistor DX1 may be connected to the selection transistor SX1 belonging to the same unit pixel; one terminal of the source follower transistor DX2 may be connected to the power supply voltage (VDD) node, and the other terminal of the source follower transistor DX2 may be connected to the selection transistor SX2 belonging to the same unit pixel; one terminal of the source follower transistor DX3 may be connected to the power supply voltage (VDD) node, and the other terminal of the source follower transistor DX3 may be connected to the selection transistor SX3 belonging to the same unit pixel. The source follower transistors DX1 to DX3 may be connected to a common floating diffusion (CFD) node through their gate terminals, may generate a signal corresponding to the potential magnitude of the common floating diffusion (CFD) node, and may output the generated signal to the corresponding selection transistors SX1 to SX3. Therefore, each of the source follower transistors DX1 to DX3 may amplify a potential change of the common floating diffusion (CFD) node and may output the amplified potential to the selection transistors SX1 to SX3 .

[0055] The selection transistors SX1 to SX3 may be respectively connected to the source follower transistors DX1 to DX3 corresponding thereto, and each of the selection transistors SX1 to SX3 may be connected to an output node (OUT). The selection transistors SX1 to SX3 may be turned on or off in response to a row selection signal (RSS) applied to their gate terminals, so that the selection transistors SX1 to SX3 may transmit the output signals of the source follower transistors DX1 to DX3 to the output node (OUT). The output node (OUT) may be connected to a column line. The selection transistors SX1 to SX3 according to the present embodiment may be commonly connected to a single output node (OUT), and may receive the same row selection signal (RSS) through their gate terminals, so that the selection transistors SX1 to SX3 may operate as a single transistor having a relatively large channel width.

[0056] The reset transistor RX and the conversion gain transistor CGX can be connected in series between the power supply voltage (VDD) node and the common floating diffusion (CFD) node. The conversion gain capacitor (C) for adjusting the capacitance of the common floating diffusion (CFD) node can be connected to the common node of the reset transistor RX and the conversion gain transistor CGX. The reset transistor RX can be turned on or off in response to the reset signal (RS) applied to its gate terminal, so that the reset transistor RX can reset the common floating diffusion (CFD) node to the power supply voltage (VDD) level. The conversion gain transistor CGX can selectively connect the conversion gain capacitor (C) to the common floating diffusion (CFD) node in parallel in response to the gain control signal GCS applied to its gate terminal, so that the conversion gain transistor CGX can adjust the capacitance of the common floating diffusion (CFD) node. The gain control signal GCS can be received from the row decoder 120.

[0057] FIG. 4A to FIG. 4D Some implementations based on the disclosed technology are shown Figure 2 Schematic diagram of a layout structure of unit pixels PX1 to PX4 included in a pixel group (PXG) shown in FIG.

[0058] In the substrate, the area where the unit pixel is formed may be defined by the device isolation structure ISO1. The device isolation structure ISO1 may be formed in the boundary area of ​​continuous or adjacent unit pixels so that the device isolation structure ISO1 may physically isolate continuous or adjacent unit pixels from each other. The device isolation structure ISO1 may include a DTI structure and / or a combination structure of a DTI structure and an STI structure. For example, a substrate in which a photoelectric conversion element of a unit pixel is formed may include a first surface to which light is incident and a second surface opposite to the first surface and including pixel transistors TX1, DX1, and SX1. The device isolation structure ISO1 may include a front deep trench isolation (FDTI) structure in which a groove formed by etching the substrate to a predetermined depth in a direction from the second surface to the first surface is filled with an insulating material.

[0059] The unit pixel PX1 may include active areas ACT11 and ACT12 defined by a device isolation structure ISO21. The active area ACT11 may include a selection transistor SX1, a source follower transistor DX1, and a transfer transistor TX1. For example, the selection transistor SX1, the source follower transistor DX1, and the transfer transistor TX1 may be formed to share the same active area ACT11. The tap area T1 may be formed in the active area ACT12. The device isolation structure ISO21 may be formed to have a shallow trench isolation (STI) structure in which a trench formed by etching a substrate to a predetermined depth is filled with an insulating material.

[0060] The selection transistor SX1 may include a selection gate SG1 formed on an active region ACT11. In the active region ACT11, an active region on one side of the selection gate SG1 may be connected to the output node OUT through a conductive line, and an active region on the other side of the selection gate SG1 may be connected to the source follower transistor DX1. The selection gate SG1 may receive a row selection signal RSS through a conductive line.

[0061] The source follower transistor DX1 may include a drive gate DG1 formed on an active area ACT11. In the active area ACT11, the active area on one side of the drive gate DG1 may be connected to a power supply voltage (VDD) node through a wire, and the active area on the other side of the drive gate DG1 may be connected to the selection transistor SX1. In this case, the selection transistor SX1 and the source follower transistor DX1 may not be electrically connected to each other through a wire, but may be electrically connected to each other through a shared active area ACT11. The drive gate DG1 may be connected to a common floating diffusion (CFD) node through a wire.

[0062] The transfer transistor TX1 may include a transfer gate TG1 formed on the active region ACT11. The transfer transistor TX1 may be a transistor in which the photoelectric conversion element PD1 and the floating diffusion (FD) region FD1 are used as source / drain regions. In this case, the transfer gate TG1 may be buried to a predetermined depth in the substrate, and may be formed in a recessed gate shape that forms a vertical channel region between the photoelectric conversion element PD1 and the floating diffusion (FD) region FD1 in response to the transfer signal TS1.

[0063] The transfer gate TG1 may be formed in the active area ACT11. Therefore, in the active area ACT11, a floating diffusion (FD) region FD1 may be formed on one side of the transfer gate TG1, and the selection transistor SX1 and the source follower transistor DX1 may be connected to the other side of the transfer gate TG1. For example, the active area ACT11 may form a T-shaped structure in which three branches are connected to each other and each of the three branches is bent. Each of the selection gate SG1, the drive gate DG1, and the transfer gate TG1 may be formed in the central portion of each branch. In this case, in the active area ACT11, although a specific area in which the transfer transistor TX1 is formed is physically connected to another area in which the selection transistor SX1 and the source follower transistor SX1 are formed through the active area ACT11, it should be noted that the specific area is not electrically connected to the above-mentioned other area. For example, impurities used to form the source / drain region of the transistor may not be injected into the central portion of the unit pixel PX1 in the active area ACT11. As a result, although the transfer gate TG1 is turned on, the floating diffusion (FD) region FD1 may not be electrically coupled to the selection transistor SX1 or the source follower transistor DX1 .

[0064] The transmission gate TG1 may receive a transmission signal TS1 through a conductive line. The floating diffusion (FD) region FD1 may be coupled to a common floating diffusion (CFD) node through a conductive line.

[0065] The tap region T1 may be used to apply a bias voltage to a well region of a substrate, and may be formed in an active region ACT12 isolated from an active region ACT11 by a device isolation structure ISO21. The active region ACT12 may be formed in an island shape at a corner region of the unit pixel PX1. The tap region T1 may be connected to a bias voltage (BV) node by a wire.

[0066] The unit pixel PX2 may be arranged to be continuous or adjacent to the unit pixel PX1 in the first direction. The unit pixel PX2 may include active areas ACT21 and ACT22 defined by the device isolation structure ISO22. The active area ACT21 may include a selection transistor SX2, a source follower transistor DX2, and a transfer transistor TX2. For example, the selection transistor SX2, the source follower transistor DX2, and the transfer transistor TX2 may be formed to share the same active area ACT21. The active area ACT22 may include a tap area T2.

[0067] The unit pixel PX2 may include a layout structure symmetrical to the unit pixel PX1 in the first direction with respect to a boundary area between the unit pixel PX2 and the unit pixel PX1. For example, the active areas ACT21 and ACT22 of the unit pixel PX2 may be arranged to be symmetrical to the active areas ACT11 and ACT12 of the unit pixel PX1 in the first direction, respectively. The gates SG2, DG2, and TG2 of the unit pixel PX2 may be formed on the active area ACT21 so that the gates SG2, DG2, and TG2 of the unit pixel PX2 are arranged to be symmetrical to the gates SG1, DG1, and TG1 of the unit pixel PX1 in the first direction. The transistors SX2, DX2, and TX2 of the unit pixel PX2 may be structurally identical to the transistors SX1, DX1, and TX1 of the unit pixel PX1, and may also be functionally identical to the transistors SX1, DX1, and TX1 of the unit pixel PX2.

[0068] The tap region T2 of the unit pixel PX2 may be arranged symmetrically with the tap region T1 of the unit pixel PX1 in the first direction. The tap region T2 may be formed in an active region ACT22 isolated from the active region ACT21 by a device isolation structure ISO22. The active region ACT22 may be formed in an island shape at a corner region of the unit pixel PX2. The tap region T2 may be coupled to a bias voltage (BV) node by a wire.

[0069] The unit pixel PX3 may be arranged to be continuous or adjacent to the unit pixel PX1 in the second direction. The unit pixel PX3 may include active areas ACT31 and ACT32 defined by the device isolation structure ISO23. The active area ACT31 may include a transfer transistor TX3, a reset transistor RX, and a conversion gain transistor CGX. For example, the transfer transistor TX3, the reset transistor RX, and the conversion gain transistor CGX may be formed to share the same active area ACT31. The active area ACT32 may include a tap area T3.

[0070] The transfer transistor TX3 may include a transfer gate TG3 formed in the active region ACT31. The transfer gate TG3 may include a recessed gate that forms a vertical channel region between the photoelectric conversion element PD3 and a floating diffusion (FD) region FD3 in response to a transfer signal TS3.

[0071] In the active area ACT31, a floating diffusion (FD) area FD3 may be formed on one side of the transmission gate TG3, and the other side of the transmission gate TG3 may be connected to the reset transistor RX and the conversion gain transistor CGX. The transmission gate TG3 may receive a transmission signal TS3 through a wire. The floating diffusion (FD) area FD3 may be connected to a common floating diffusion (CFD) node through a wire.

[0072] The reset transistor RX may include a reset gate RG formed on an active area ACT31. In the active area ACT31, an active area on one side of the reset gate RG may be connected to a power supply voltage (VDD) node through a wire, and an active area on the other side of the reset gate RG may be connected to the conversion gain transistor CGX and the conversion gain capacitor (C). In this case, the reset transistor RX may be connected to the conversion gain transistor CGX by sharing the active area ACT31 with the conversion gain transistor CGX, and may be connected to the conversion gain capacitor (C) through a wire. The reset gate RG may receive a reset signal (RS) through a wire.

[0073] The conversion gain transistor CGX may include a conversion gate CG formed on an active area ACT31. In the active area ACT31, a floating diffusion (FD) area FD3 may be formed on one side of the conversion gate CG, and the other side of the conversion gate CG may be connected to the reset transistor RX and the conversion gate capacitor (C). In this case, the conversion gain transistor CGX may be connected to the reset transistor RX by sharing the active area ACT31 with the reset transistor RX, and may be connected to the conversion gain capacitor (C) through a wire. The conversion gate CG may receive a gain control signal (GCS) through a wire.

[0074] The impurity region VSS coupled to the conversion gain capacitor (C) may be locally formed at a central portion of the unit pixel PX3 among the active region ACT31. For example, the impurity region VSS may be used to ground one terminal of the conversion gain capacitor (C).

[0075] The tap region T3 may be arranged to be symmetrical with the tap region T1 of the unit pixel PX1 in the second direction. The tap region T3 may be formed in an active region ACT32 isolated from the active region ACT31 by a device isolation structure ISO23. The active region ACT32 may be formed in an island shape at a corner region of the unit pixel PX3. The tap region T3 may be connected to a bias voltage (BV) node by a wire.

[0076] The unit pixel PX4 may be arranged to be continuous or adjacent to the unit pixel PX3 in the first direction, and may also be continuous or adjacent to the unit pixel PX2 in the second direction. The unit pixel PX4 may include active areas ACT41 and ACT42 defined by the device isolation structure ISO24. The active area ACT41 may include a selection transistor SX3, a source follower transistor DX3, and a transfer transistor TX4. For example, the selection transistor SX3, the source follower transistor DX3, and the transfer transistor TX4 may be formed to share the same active area ACT41. The active area ACT42 may include a tap area T4.

[0077] The unit pixel PX4 may include a layout structure that is symmetrical with the unit pixel PX2 in the second direction relative to the boundary area between the unit pixel PX4 and the unit pixel PX2. For example, the active areas ACT41 and ACT42 may be arranged to be symmetrical with the active areas ACT21 and ACT22 of the unit pixel PX2 in the second direction. The gates SG3, DG3, and TG4 of the unit pixel PX4 may be formed on the active area ACT41 so that the gates SG3, DG3, and TG4 of the unit pixel PX4 are arranged to be symmetrical with the gates SG2, DG2, and TG2 of the unit pixel PX2 in the second direction. That is, the transistors SX3, DX3, and TX4 of the unit pixel PX4 may be arranged to be symmetrical with the transistors SX2, DX2, and TX2 of the unit pixel PX2 in the second direction. The transistors SX3, DX3, and TX4 of the unit pixel PX4 may be structurally identical to the structures of the transistors SX2, DX2, and TX2 of the unit pixel PX2, and may also be functionally identical to the transistors SX2, DX2, and TX2 of the unit pixel PX2.

[0078] The tap region T4 may be arranged to be symmetrical with the tap region T2 of the unit pixel PX2 in the second direction. The tap region T4 may be formed in an active region ACT42 isolated from the active region ACT41 by a device isolation structure ISO24. The active region ACT42 may be formed in an island shape at a corner region of the unit pixel PX4. The tap region T4 may be connected to a bias voltage (BV) node by a wire.

[0079] Figure 5 is shown along Figure 4C AA′ is a cross-sectional view of an example of a unit pixel. In more detail, Figure 5 A method for forming a conversion gain capacitor is illustrated.

[0080] Reference Figure 5 , a conversion gain capacitor (C) may be formed over the active region ACT31 in the unit pixel PX3. For example, the conversion gain capacitor (C) may include a metal-insulator-metal (MIM) capacitor in which an insulating material is formed between two metal plates MP0 and MP1 over the active region ACT31.

[0081] In this case, the metal plate MP0 may correspond to the lower electrode of the conversion gain capacitor (C) and may be formed at the same time as the conductive line of the metal layer M0 is formed. The metal plate MP1 may correspond to the upper electrode of the conversion gain capacitor (C) and may be formed at the same time as the conductive line of the metal layer M1 is formed. The metal plate MP0 may be coupled to the impurity region VSS, and the metal plate MP1 may be coupled to the impurity region CAP formed between the conversion gate CG and the reset gate RG.

[0082] Although for ease of description, Figure 5 An exemplary case of forming a conversion gain capacitor (C) in the unit pixel PX3 for minimizing the length of the conductive line connecting the conversion gain capacitor (C) to the conversion gate transistor CGX is shown, but other implementations are also possible. For example, the conversion gain capacitor (C) can be formed anywhere in a redundant space in which no conductive line is formed within the pixel group (PXG).

[0083] Although for ease of description, Figure 5 Only one conversion gain capacitor (C) is exemplarily shown, but the number of conversion gain capacitors is not limited to 1. In some implementations, several conversion gain capacitors may also be connected in parallel with each other.

[0084] It is apparent from the above description that an image sensing device based on some implementations of the disclosed technology can improve its operating characteristics.

[0085] An image sensing device based on some implementations of the disclosed technology can adjust conversion gain in a shared structure in which a plurality of pixels share a floating diffusion (FD) region without increasing the size of the pixel.

[0086] Those skilled in the art will appreciate that the embodiments may be performed in other specific ways than those described herein. Therefore, the above embodiments should be interpreted in all aspects as illustrative rather than restrictive. In addition, those skilled in the art will appreciate that claims that are not explicitly referenced to each other in the appended claims may be presented as a combination of embodiments, or may be included as new claims through subsequent amendments after the application is filed.

[0087] Although a number of illustrative embodiments have been described, it should be understood that modifications to the disclosed embodiments and other embodiments may be made based on the disclosure of this patent document.

[0088] CROSS-REFERENCE TO RELATED APPLICATIONS

[0089] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0013094, filed on Feb. 4, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. An image sensing device, the image sensing device include: a first unit pixel, the first unit pixel comprising a first photoelectric conversion element and a first floating diffusion region, the first photoelectric conversion element being configured to generate photocharges in response to incident light, the first floating diffusion region being configured to receive the photocharges generated by the first photoelectric conversion element; a second unit pixel, the second unit pixel comprising a second photoelectric conversion element configured to generate photocharges in response to incident light and a second floating diffusion region configured to receive the photocharges generated by the second photoelectric conversion element; a third unit pixel, the third unit pixel comprising a third photoelectric conversion element and a third floating diffusion area, the third photoelectric conversion element being configured to generate photocharges in response to incident light, the third floating diffusion area being configured to receive the photocharges generated by the third photoelectric conversion element; as well as a fourth unit pixel, the fourth unit pixel comprising a fourth photoelectric conversion element and a fourth floating diffusion area, the fourth photoelectric conversion element being configured to generate photocharges in response to incident light, the fourth floating diffusion area being configured to receive the photocharges generated by the fourth photoelectric conversion element, The first to fourth unit pixels are isolated from each other by a first device isolation structure. The first floating diffusion region to the fourth floating diffusion region are connected to a common floating diffusion node through a wire, and At least one of the first to fourth unit pixels includes a conversion gain transistor coupled to the common floating diffusion node, the conversion gain transistor being configured to adjust a capacitance of the common floating diffusion node in response to a gain control signal provided to the conversion gain transistor, Wherein, each of the remaining unit pixels of the first to fourth unit pixels except the at least one unit pixel includes: a source follower transistor coupled to the common floating diffusion node via a gate terminal; and a select transistor coupled to the source follower transistor and an output node, wherein each of the remaining unit pixels comprises a first active area; and The transfer transistor, the source follower transistor, and the selection transistor of each of the remaining unit pixels are formed to share the first active region.

2. The image sensing device according to claim 1, in, The first device isolation structure includes a deep trench isolation (DTI) structure.

3. The image sensing device according to claim 1, in, The at least one unit pixel further includes: A conversion gain capacitor is coupled to the conversion gain transistor.

4. The image sensing device according to claim 3, in, The conversion gain capacitor comprises a Metal Insulator Metal MIM capacitor.

5. The image sensing device according to claim 1, in, Each of the first to fourth unit pixels further includes: A transfer transistor configured to transfer photocharges generated by a corresponding photoelectric conversion element to a corresponding floating diffusion region.

6. The image sensing device according to claim 5, in, The at least one unit pixel further includes: A reset transistor is configured to reset the common floating diffusion node in response to a reset signal provided to the reset transistor.

7. The image sensing device according to claim 6, in: The at least one unit pixel includes a first active region and a second active region defined by a second device isolation structure, The conversion gain transistor, the transfer transistor, and the reset transistor are formed to share the first active area of ​​the at least one unit pixel.

8. The image sensing device according to claim 7, in, The second active region comprises: A tap region is configured to receive a bias voltage as an input.

9. The image sensing device according to claim 5, in, The source follower transistor generates a signal corresponding to the magnitude of the potential of the common floating diffusion node and outputs the generated signal; and The selection transistor transmits an output signal of the source follower transistor to the output node in response to a selection signal.

10. The image sensing device according to claim 9, in: Each of the remaining unit pixels includes the first active region and the second active region defined by a second device isolation structure.

11. The image sensing device according to claim 10, in, The second active region comprises: A tap region is configured to receive a bias voltage as an input.

12. An image sensing device, the image sensing device include: a plurality of pixel groups, the plurality of pixel groups being arranged along a first direction and a second direction perpendicular to the first direction, Each of the pixel groups includes unit pixels isolated from each other by a first device isolation structure, Wherein, each of the unit pixels comprises: a photoelectric conversion element configured to generate photocharges by performing photoelectric conversion on incident light; a floating diffusion region configured to receive the photo charges; and a transfer transistor configured to transfer the photocharge generated by the photoelectric conversion element to the floating diffusion region, in, The floating diffusion area of ​​the unit pixel is connected to a common floating diffusion node through a conductive line; and At least one of the unit pixels includes a conversion gain transistor configured to adjust a capacitance of the common floating diffusion node in response to a gain control signal provided to the conversion gain transistor, Wherein, each of the remaining unit pixels except the at least one unit pixel further includes: a source follower transistor coupled to the common floating diffusion node via a gate terminal; and a select transistor coupled to the source follower transistor and an output node, Wherein, each of the remaining unit pixels includes the transfer transistor, the source follower transistor, and the selection transistor configured to share a first active region.

13. The image sensing device according to claim 12, in, Each of the unit pixels includes: A first active region and a second active region, wherein the first active region and the second active region are defined by a second device isolation structure.

14. The image sensing device according to claim 12, in, The at least one unit pixel further includes: A reset transistor is configured to reset the common floating diffusion node in response to a reset signal.

15. The image sensing device according to claim 14, in, The at least one unit pixel includes the transfer transistor, the conversion gain transistor, and the reset transistor configured to share a first active region of the at least one unit pixel.

16. The image sensing device according to claim 12, in, The source follower transistor generates a signal corresponding to the magnitude of the potential of the common floating diffusion node and outputs the generated signal; and The selection transistor transmits an output signal of the source follower transistor to the output node in response to a selection signal.

17. An image sensing device according to claim 16, wherein the remaining unit pixels include two adjacent unit pixels, and the two adjacent unit pixels are arranged so that the transfer transistors, the source follower transistors and the selection transistors of the two adjacent unit pixels are symmetrical to each other relative to a boundary area between the two adjacent unit pixels.

18. The image sensing device according to claim 13, in, The second active region comprises: A tap region is configured to receive a bias voltage as an input.

19. The image sensing device according to claim 13, in, The at least one unit pixel further includes: A conversion gain capacitor in which a lower electrode is coupled to the first active region of the at least one unit pixel and an upper electrode is coupled to the conversion gain transistor.

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