Semiconductor device and method of manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate having a first conductivity type; a first well region disposed in the substrate and having a second conductivity type; a second well region disposed in the substrate and having the first conductivity type; source and drain regions having the second conductivity type, respectively disposed in the second well region and the first well region; an isolation structure disposed between the source region and the drain region; a gate structure disposed on the substrate between the source region and the drain region, wherein the gate structure covers a part of the isolation structure; a first top doped region disposed in the second well region below the source region and having the first conductivity type; and a second top doped region disposed in the first well region below the isolation structure and having the first conductivity type.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an ultra-high voltage semiconductor device and a manufacturing method thereof. Background Art

[0002] When an ultra-high voltage semiconductor device operates, it must have a relatively high breakdown voltage and a relatively low on-state resistance. Currently, due to the relatively high resistance value of the substrate, the breakdown voltage of the ultra-high voltage semiconductor device cannot be effectively increased. Summary of the Invention

[0003] The present invention provides a semiconductor device and a manufacturing method thereof, which can reduce the resistance value of the current path and increase the breakdown voltage of the semiconductor device.

[0004] The semiconductor device of the present invention includes: a substrate having a first conductivity type; a first well region disposed in the substrate and having a second conductivity type; a second well region disposed in the substrate and having the first conductivity type; a source region and a drain region disposed in the substrate and having the second conductivity type, the drain region being located in the first well region, and the source region being located in the second well region; an isolation structure disposed between the source region and the drain region; a gate structure disposed on the substrate between the source region and the drain region, wherein the gate structure covers a part of the isolation structure; a first top doped region disposed in the second well region under the source region and having the first conductivity type; and a second top doped region disposed in the first well region under the isolation structure and having the first conductivity type.

[0005] The manufacturing method of the semiconductor device of the present invention includes the following steps. Forming a first well region having a second conductivity type in a substrate having a first conductivity type; forming a second well region having the first conductivity type in the substrate; forming a first top doped region in the second well region and forming a second top doped region in the first well region, the first top doped region and the second top doped region having the first conductivity type; forming an isolation structure on the substrate, wherein the second top doped region is located under the isolation structure; forming a gate structure on the substrate, wherein the gate structure covers a part of the isolation structure; and forming a source region and a drain region having the second conductivity type in the substrate on one side of the gate structure and on one side of the isolation structure respectively, wherein the source region is located on the first top doped region and adjacent to the gate structure, and the drain region is adjacent to the isolation structure.

[0006] Based on the above, since adding a top doping region below the source region of the semiconductor device of the present invention can reduce the resistance value of the current path and improve the breakdown voltage of the semiconductor device.

[0007] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0008] Figure 1A A top view schematic diagram of the semiconductor device according to an embodiment of the present invention.

[0009] Figure 1B A top view schematic diagram of the top doping region and other components of the semiconductor device according to an embodiment of the present invention.

[0010] Figures 2A to 2H A cross-sectional schematic diagram of the manufacturing method of the semiconductor device according to an embodiment of the present invention, wherein Figure 2H is a cross-sectional schematic diagram taken along the cutting line A-A' of the semiconductor device according to Figure 1A of.

[0011] Figure 3 is the doping profile of the top doping region.

[0012] Figure 4 An electrical property diagram of the ultra-high voltage semiconductor according to an embodiment of the present invention.

[0013] [Symbol Description]

[0014] 10: Semiconductor device

[0015] 100: Substrate

[0016] 102, 106, 114: Patterning mask layer

[0017] 104, 108, 116, 118: Ion implantation process

[0018] 110: First well region

[0019] 112: Second well region

[0020] 120, 120a, 120b: Top doping region

[0021] 122, 122a, 122b: Ladder region

[0022] 130: Source region

[0023] 132, 134: Doping region

[0024] 140: Drain region

[0025] 200: Isolation structure

[0026] 200a: First isolation structure

[0027] 200b: Second isolation structure

[0028] 200c: Third isolation structure

[0029] 200d: Fourth isolation structure

[0030] 300: Gate structure

[0031] 302: Gate oxide layer

[0032] 304: Gate

[0033] 306: Spacer

[0034] A - A', B - B', C - C': Section lines

[0035] D1, D2: Distances

[0036] IR: Inner peripheral region

[0037] L: Linear region

[0038] MF: Multiple finger regions

[0039] R: Turning region

[0040] OR: Outer peripheral region

[0041] S10, S20, S100, S200: Curves Detailed implementation manners

[0042] To make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0043] In the following embodiments, the first conductivity type is P-type, and the second conductivity type is N-type; however, the present invention is not limited thereto. In other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type. P-type doping is, for example, boron, and N-type doping is, for example, phosphorus or arsenic.

[0044] The schematic diagrams herein are only used to illustrate some embodiments of the present invention. Therefore, the shapes, quantities, and proportional sizes of the various elements shown in the schematic diagrams should not be used to limit the present invention.

[0045] Figure 1A Is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1B Is a top view schematic diagram of the top doping region and other components of a semiconductor device according to an embodiment of the present invention. Figure 2H Is based on Figure 1A A cross-sectional schematic diagram of a semiconductor device. It should be noted here thatFigure 2H is a schematic cross-sectional view corresponding to the section line A-A' of Figure 1A .

[0046] Please also refer to Figure 1A , Figure 1B and Figure 2H , the semiconductor element 10 of this embodiment is, for example, an ultra-high voltage element, and its operating voltage is, for example, 300V to 1000V. In one embodiment, the semiconductor element 10 includes a substrate 100, a first well region 110, a top doped region 120, an isolation structure 200, a gate structure 300, a source region 130, and a drain region 140. In this embodiment, a plurality of finger regions MF are formed between the source region 130 and the drain region 140. Therefore, the semiconductor element 10 of this embodiment can also be referred to as a finger-type ultra-high voltage element. Specifically, between the source region 130 and the drain region 140, for example, a plurality of straight regions L and a plurality of turning regions R are included. Two parallel straight regions L and one turning region R connecting the two straight regions L can form a finger region. Therefore, the plurality of straight regions L and the plurality of turning regions R are connected to each other to form a plurality of finger regions MF. Each turning region R is, for example, a C-shaped, U-shaped, or racetrack-shaped turning region.

[0047] The substrate 100 is, for example, a semiconductor substrate having a first conductivity type. For example, in this embodiment, the substrate 100 is a P-type substrate, and the material of the substrate 100 can be, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In another embodiment, the substrate 100 can also be a silicon-on-insulator (SOI) substrate. In yet another embodiment, the substrate 100 can be a P-type epitaxial (P-epi) wafer.

[0048] The first well region 110 is disposed in the substrate 100 and has a second conductivity type. The first well region 110 is, for example, an N-type well region, and is, for example, a high-voltage N-type well region (HVNW).

[0049] In this embodiment, the semiconductor element 10 may further include a second well region 112. The second well region 112 has a first conductivity type. The second well region 112 is, for example, a P-type well region. In this embodiment, the second well region 112 is formed in the substrate 100, and its sidewalls extend into the first well region 110. The second well region 112 serves as, for example, the source well region of the semiconductor element 10.

[0050] The source region 130 and the drain region 140 are, for example, disposed in the substrate 100 and have a second conductivity type. The source region 130 and the drain region 140 are, for example, N-type doped regions. In this embodiment, the source region 130 is located in the second well region 112, while the drain region 140 is located in the first well region 110. In Figure 1AIn [the figure], the source region 130 is located in the outer peripheral region OR of the plurality of finger regions MF, and the drain region 140 is located in the inner peripheral region IR surrounded by the plurality of finger regions MF.

[0051] In this embodiment, the semiconductor element 10 may further include doped regions 132 and 134. The doped regions 132 and 134 have a first conductivity type, for example, a P-type doped region. The doped region 132 is also called a bulk doped region, which is located in the second well region 112 and adjacent to the source region 130. The doped region 134 is located in the substrate 100.

[0052] The isolation structure 200 is located on the substrate 100 and between the source region 130 and the drain region 140. In this embodiment, the isolation structure 200 includes a first isolation structure 200a, a second isolation structure 200b, a third isolation structure 200c, and a fourth isolation structure 200d. The first isolation structure 200a is located on the substrate 100 and adjacent to the doped region 134. The second isolation structure 200b is located between the doped region 134 and the doped region 132 and covers a part of the second well region 112. The third isolation structure 200c is located on the first well region 110 and between the source region 130 and the drain region 140. In Figure 1A [the figure], the third isolation structure 200c is disposed on the plurality of finger regions MF between the source region 130 and the drain region 140. The fourth isolation structure 200d is located on the first well region 110 and adjacent to the drain region 140. In other words, the source region 130 is located between the second isolation structure 200b and the third isolation structure 200c, and the drain region 140 is located between the third isolation structure 200c and the fourth isolation structure 200d. In this embodiment, the isolation structure 200 is, for example, a field oxide layer. That is, the material of the isolation structure 200 is, for example, an insulating material, and for example, undoped silicon oxide, silicon nitride, or a combination thereof.

[0053] The gate structure 300 is, for example, disposed on the substrate 100 and the third isolation structure 200c between the source region 130 and the drain region 140. From another perspective, the gate structure 300 covers a part of the first well region 110 and the second well region 112, is adjacent to the source region 130, and covers a part of the third isolation structure 200c. In this embodiment, the gate structure 300 includes a gate oxide layer 302, a gate 304, and a spacer 306. The gate oxide layer 302 is, for example, disposed on the substrate 100 and between the source region 130 and the third isolation structure 200c. The gate 304 is, for example, disposed on the gate oxide layer 302 and the third isolation structure 200c. The spacer 306 is, for example, disposed on the sidewalls of the gate 304. The materials of the gate oxide layer 302 and the spacer 306 are, for example, silicon oxide, silicon nitride, or a combination thereof. The material of the gate 304 is, for example, a metal or its alloy, polysilicon, or a combination thereof.

[0054] In an embodiment of the present invention, the top doped region 120 includes a top doped region 120a and a top doped region 120b. The top doped region 120 has a first conductivity type, for example, P-type. The top doped region 120a is disposed below the source region 130 and the doped region 134. In some embodiments, the top doped region 120a is within the second well region 112 and extends downward into the substrate 100 such that the distance D1 between the bottom surface of the top doped region 120a and the top surface of the substrate 100 is greater than the distance D2 between the bottom surface of the second well region 112 and the top surface of the substrate 100. The top doped region 120b is disposed in the first well region 110 below the third isolation structure 200c (as Figure 2H described). In other embodiments, the top doped region 120a is within the second well region 112 and the distance D1 between the bottom surface of the top doped region 120a and the top surface of the substrate 100 is less than the distance D2 between the bottom surface of the second well region 112 and the top surface of the substrate 100 (not shown).

[0055] In Figure 1A , the source region 130 is located in the outer region OR outside the plurality of finger regions MF, and the top doped region 120a is located below the source region 130. The top doped region 120b is disposed below the third isolation structure 200c among the plurality of finger regions MF. For clarity, in Figure 1B , the source region 130 and the third isolation structure 200c are not shown to clearly show the positions of the top doped regions 120a and 120b. In Figure 1B , the top doped region 120a is located in the outer region OR outside the plurality of finger regions MF, while the top doped region 120b is disposed among the plurality of finger regions MF.

[0056] Figure 3 The curves S100 and S200 of Figure 2H are the doping profiles of the top doped regions 120a and 120b of the cross-sectional lines B-B' and C-C' in Figure 1B , Figure 2H and Figure 3 . Referring to

[0057] , in some embodiments, the peak of the curve S200 of the doping profile of the top doped region 120a is closer to the surface of the substrate 100 than the peak of the curve S100 of the doping profile of the top doped region 120b. That is, the peak of the top doped region 120b is deeper than the peak of the top doped region 120a.

[0057] Please refer to Figure 1A , Figure 2H, in this embodiment, the semiconductor element 10 may further include a stepped region 122. The stepped region 122 includes stepped regions 122a and 122b. The stepped region 122 has a second conductivity type, for example, N-type. The stepped region 122a is disposed in the second well region 112, between the source region 130, the doped region 134, and the top doped region 120a. The stepped region 122b is located between the third isolation structure 200c and the top doped region 120b. The stepped region 122 and the top doped region 120 may have the same or similar shapes.

[0058] In the semiconductor element 10 of this embodiment, the stepped region 122a and the top doped region 120a are added under the source region 130 and the doped region 132, which can reduce the resistance of the current path between the drain region 140 and the doped region 132, allowing a larger current to pass through the current path and then flow out through the doped regions 130 and 132. Therefore, the breakdown voltage of the element can be increased through the stepped region 122a and the top doped region 120a, improving the performance of the element.

[0059] Figures 2A to 2H It is a cross-sectional schematic view of a manufacturing method of a semiconductor element according to an embodiment of the present invention. It must be noted here that in this embodiment, the description of some of the above-mentioned same technical contents is omitted. For the description of the omitted part, reference can be made to the description and effects of the above-mentioned embodiment, and the following embodiments will not be repeated.

[0060] Please refer to Figure 2A , a substrate 100 having a first conductivity type is provided. Then, a first well region 110 having a second conductivity type is formed in the substrate 100. In this embodiment, the substrate 100 is a P-type substrate, and the first well region 110 is an N-type high-voltage well region. The method of forming the first well region 110 in the substrate 100, for example, includes the following steps. First, a patterned mask layer 102 is formed on the substrate 100. Then, through an ion implantation process 104, doping is implanted into the substrate 100. The doping implanted by the above ion implantation process 104 is, for example, phosphorus or arsenic, and the doping dose is, for example, 2×E 12 cm -2 to 5×E 12 cm -2 . After removing the above-mentioned patterned mask layer 102, a heat treatment process can be performed to form the first well region 110.

[0061] Please refer to Figure 2B, a second well region 112 of a first conductivity type is formed in the first well region 110. In this embodiment, the second well region 112 is a P-type well region. The method of forming the second well region 112, for example, includes the following steps. First, a patterned mask layer 106 is formed on the substrate 100. Then, an ion implantation process 108 is performed through the patterned mask layer 106. The doping implanted by the above ion implantation process 108 is, for example, boron, and the doping dose is, for example, 8×E 12 cm -2 to 1.2×E 13 cm -2 . After that, the above patterned mask layer 106 is removed and a heat treatment process is performed to form the second well region 112 in the first well region 110.

[0062] Please refer to Figure 2C , a top doped region 120a is formed in the second well region 112, and a top doped region 120b is formed in the first well region 110. In this embodiment, the conductivity type of the top doped region 120 is P-type. The top doped regions 120a and 120b can be formed simultaneously in the same step. In some embodiments, the method of forming the top doped regions 120a and 120b, for example, includes the following steps. First, a patterned mask layer 114 is formed on the substrate 100. Then, using the patterned mask layer 114 as a mask, an ion implantation process 116 is performed to form the top doped region 120a in the second well region 112 and the top doped region 120b in the first well region 110. The doping implanted by the above ion implantation process 116 is, for example, boron, and the doping dose is, for example, 5×E 12 cm -2 to 1×E 13 cm -2 . After that, the above patterned mask layer 114 is removed. The formed top doped region 120a extends downward from the top surface of the second well region 112. The formed top doped region 120b extends downward from the top surface of the first well region 110.

[0063] Please refer to Figure 2D , a ladder region 122a of a second conductivity type is formed in the second well region 112, and a ladder region 122b of a second conductivity type is formed in the first well region 110. In this embodiment, the conductivity types of the ladder regions 122a and 122b are N-type. The ladder regions 122a and 122b can be formed simultaneously in the same step. In some embodiments, forming the ladder regions 122a and 122b in the first well region 110, for example, includes the following steps. Using the patterned mask layer 114 as a mask, an ion implantation process 118 is performed. The doping implanted by the above ion implantation process 118 is, for example, phosphorus or arsenic, and the doping dose is, for example, 1×E 12 cm -2 to 5×E 12 cm-2 After that, the above-mentioned patterned mask layer 114 is removed. After removing the above-mentioned patterned mask layer 114, a heat treatment process is performed to diffuse the doping in the top doping regions 120a, 120b and the ladder regions 122a, 122b to a predetermined width and depth, so that the top doping regions 120a, 120b and the ladder regions 122a, 122b have the desired profiles. The temperature of the above heat treatment process is, for example, 1000 °C.

[0064] The formed ladder region 122a extends downward from the top surface of the second well region 112. The formed ladder region 122b extends downward from the top surface of the first well region 110. The depth of the ladder region 122 in the substrate 100 is less than the depth of the top doping region 120 in the substrate 100. In other words, the ladder region 122a is located above the top doping region 120a, and the ladder region 122b is located above the top doping region 120b.

[0065] Please refer to Figure 2E , an isolation structure 200 is formed on the substrate 100. The formation method of the isolation structure 200 can be, for example, local oxidation isolation method or shallow trench isolation method. In this embodiment, the formation method of the isolation structure 200 is local area oxidation method. The isolation structure 200 includes a first isolation structure 200a, a second isolation structure 200b, a third isolation structure 200c and a fourth isolation structure 200d.

[0066] Please refer to Figure 2F , a gate structure 300 is formed on the substrate 100, and the formed gate structure 300 covers a part of the third isolation structure 200c. In this embodiment, the gate structure 300 includes a gate oxide layer 302, a gate 304 and a spacer 306. The method of forming the gate structure 300 on the substrate 100 includes, for example, the following steps. First, a gate oxide material layer and a gate material layer are formed on the substrate 100 by thermal oxidation (or chemical vapor deposition). After that, the gate material layer and the gate oxide material layer are patterned by photolithography and etching processes to form the gate 304 and the gate oxide layer 302. After that, a spacer material layer is formed by thermal oxidation or chemical vapor deposition, and then an anisotropic etching process is performed on the spacer material layer to form the spacer 306 on the sidewalls of the gate 304. The formed gate oxide layer 302 is, for example, adjacent to the third isolation structure 200c and located between the second isolation structure 200b and the third isolation structure 200c. The formed gate 304 is, for example, located on the gate oxide layer 302 and the third isolation structure 200c.

[0067] Please refer to Figure 2G, a source region 130 and a drain region 140 are respectively formed in the substrate 100 on one side of the gate structure 300 and on one side of the third isolation structure 200c. In this embodiment, the source region 130 and the drain region 140 have a second conductivity type, for example, N-type. Forming the source region 130 and the drain region 140, for example, includes the following steps. First, a patterned mask layer (not shown) is formed on the substrate 100. Then, an ion implantation process is performed through the patterned mask layer. The doping implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 1×E 15 cm -2 to 5×E 15 cm -2 . After that, the above-mentioned patterned mask layer is removed, and a heat treatment process is performed to respectively form the source region 130 and the drain region 140 in the substrate 100. The formed source region 130 is, for example, located in the second well region 112 and adjacent to the gate structure 300, and is located between the second isolation structure 200b and the third isolation structure 200c. The formed drain region 140 is, for example, located in the first well region 110 and between the third isolation structure 200c and the fourth isolation structure 200d.

[0068] Please refer to Figure 2H , doping regions 132 and 134 are respectively formed in the substrate 100 and the second well region 112. In this embodiment, the doping regions 132 and 134 have a first conductivity type, for example, P-type. The method of forming the doping regions 132 and 134 in the substrate 100 and the second well region 112, for example, includes the following steps. First, a patterned mask layer (not shown) is formed on the substrate 100. Then, an ion implantation process is performed through the patterned mask layer. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1×E 15 cm -2 to 5×E 15 cm -2 . After that, the above-mentioned patterned mask layer is removed and a heat treatment process is performed to respectively form the doping regions 132 and 134 in the substrate 100 and the second well region 112. The formed doping region 134 is between the first isolation structure 200a and the second isolation structure 200b. The formed doping region 132 is located between the second isolation structure 200b and the source region 130.

[0069] Please also refer to Figure 1A , Figure 1B and Figure 2H , in the embodiments of the present invention, the patterned mask layers required for the ladder regions 122a, 122b and the top doping regions 120a, 120b can be formed through the same mask process. Therefore, the process cost can be not increased, the current path resistance can be reduced, and the device performance can be improved.

[0070] Please refer to Figure 4 , in some embodiments, the semiconductor element is an ultra-high voltage element, and its breakdown voltage in the off state is 500 volts. By adding a graded region and a top doping region under the source region, the breakdown voltage in its on state (when the gate voltage is applied at 7.5 volts) can be increased from 375 volts (as shown by curve S10) to 398 volts (as shown by curve S20). Therefore, adding a graded region and a top doping region under the source region and the doping region in the present invention can improve the performance of the ultra-high voltage element.

[0071] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A semiconductor device, comprising: a substrate having a first conductivity type; a first well region disposed in the substrate and having a second conductivity type; a second well region disposed in the substrate and having the first conductivity type; a source region and a drain region disposed in the substrate and having the second conductivity type, the drain region being located in the first well region, and the source region being located in the second well region; an isolation structure disposed between the source region and the drain region; a gate structure disposed on the substrate between the source region and the drain region, wherein the gate structure covers a part of the isolation structure; a first top doped region disposed in the second well region below the source region and having the first conductivity type; and a second top doped region disposed in the first well region below the isolation structure and having the first conductivity type.

2. The semiconductor device according to claim 1, further comprising a doped region having the first conductivity type, located in the second well region, above the first top doped region, and adjacent to the source region.

3. The semiconductor device according to claim 2, further comprising a first step region and a second step region having the first conductivity type, the first step region being located between the first top doped region and the source region, and the second step region being located between the isolation structure and the second top doped region.

4. The semiconductor device according to claim 3, wherein between the source region and the drain region includes a plurality of finger regions formed by a plurality of straight regions and a plurality of turning regions, and the isolation structure is formed on the plurality of finger regions.

5. The semiconductor device according to claim 4, wherein the first top doped region and the first step region are located in an outer peripheral region outside the plurality of finger regions; the first top doped region and the first step region are located in the plurality of finger regions.

6. A method of manufacturing a semiconductor device, comprising: forming a first well region having a second conductivity type in a substrate having a first conductivity type; forming a second well region having a first conductivity type in the substrate; forming a first top doped region in the second well region and forming a second top doped region in the first well region, the first top doped region and the second top doped region having the first conductivity type; forming an isolation structure on the substrate, wherein the second top doped region is located below the isolation structure; forming a gate structure on the substrate, wherein the gate structure covers a part of the isolation structure; and forming a source region and a drain region having the second conductivity type in the substrate on one side of the gate structure and on one side of the isolation structure, respectively, wherein the source region is located on the first top doped region and adjacent to the gate structure, and the drain region is adjacent to the isolation structure.

7. The method of manufacturing a semiconductor device according to claim 6, further comprising forming a doped region having the first conductivity type, located in the second well region, above the first top doped region, and adjacent to the source region.

8. The method for manufacturing a semiconductor device according to claim 7 further includes forming a first stepped region and a second stepped region having a first conductivity type, the first stepped region being located between the first top doped region and the source region, and the second stepped region being located between the isolation structure and the second top doped region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein a plurality of finger-shaped regions formed by a plurality of straight regions and a plurality of turning regions are included between the source region and the drain region, and the isolation structure is formed on the plurality of finger-shaped regions.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the first top doped region and the first stepped region are formed in a peripheral region outside the plurality of finger-shaped regions; the first top doped region and the first stepped region are formed in the plurality of finger-shaped regions.

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