Printed circuit board and wiring layout method thereof

Abstract

The present invention provides a printed circuit board and a wiring layout method thereof, wherein the packaging area of ​​the printed circuit board is formed with left and right wiring areas and upper and lower wiring areas; in the left and right wiring areas: first grounding vias are respectively arranged in the vertical direction corresponding to two vias of the high-speed differential line on the pad device, and a second grounding via is arranged between the two vias of the high-speed differential line on the pad device; in the upper and lower wiring areas: a fifth grounding via is arranged between the two vias of the high-speed differential line on the pad device; a sixth grounding via is arranged between the two high-speed differential lines of the two vias on the pad device and in the outer area of ​​the pad device; wherein the connection line of the fifth grounding via and the sixth grounding via is perpendicular to the connection line of the two vias of the high-speed differential line on the pad device. The present invention enables the BGA area to fan out the most optimized high-speed differential line, thereby reducing the crosstalk of the wiring fan-out.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, in particular to the technical field of printed circuit boards. Background Art

[0002] With the development of electronic technology, printed circuit boards are more and more widely used in the electronic field, and integrated circuit chips in ball grid array packages (BGA) have become the mainstream chip packages today. The chip pins of ball grid array packages (BGA) are on the back of the chip package, so the optimization of the circuit board layout is taken into consideration during the design of printed circuit boards.

[0003] Since the BGA package has a high density of wires, the wire pattern will affect the impedance of the via and the crosstalk of the fan-out, and impedance and crosstalk are crucial factors affecting signal quality. How to optimize the wire pattern so that the wires in the BGA area can achieve the most optimized high-speed differential line fan-out has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a printed circuit board and a wiring layout method thereof, which are used to optimize the high-speed differential line fan-out mode of the printed circuit board.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a printed circuit board, wherein a packaging area is arranged on the front side of the printed circuit board; a via array corresponding to the packaging area is arranged on the back side of the printed circuit board; the packaging area of ​​the printed circuit board is formed with left and right lead-out areas and upper and lower lead-out areas; in the left and right lead-out areas: first ground vias are respectively arranged in the vertical direction corresponding to two vias of the high-speed differential line on the pad device, so that the two vias of the high-speed differential line on the pad device lead out in the vertical direction; a second ground via is arranged between the two vias of the high-speed differential line on the pad device; the outer two side areas of the pad device are divided into At least one third ground via is separately provided, and the outlet direction of the third ground via has an angle with the horizontal direction; in the upper and lower outlet areas: fourth ground vias corresponding to the two vias are respectively arranged in a direction perpendicular to the connection direction of the two vias of the high-speed differential line on the pad device; a fifth ground via is arranged between the two vias of the high-speed differential line on the pad device; a sixth ground via is provided between the two high-speed differential lines of the two vias on the pad device and located in the outer area of ​​the pad device; wherein the connection line between the fifth ground via and the sixth ground via is perpendicular to the connection line between the two vias of the high-speed differential line on the pad device.

[0006] In one embodiment of the present invention, in the left and right outgoing line areas and the upper and lower outgoing line areas, the receiving signal routing lines and the transmitting signal routing lines are arranged in different layers of the printed circuit board.

[0007] In one embodiment of the present invention, in the left and right lead-out areas, the offset angle of the pad device in the horizontal direction or relative to the horizontal direction does not exceed ±15°; in the upper and lower lead-out areas, the offset angle of the pad device relative to the horizontal direction does not exceed 60°±15°.

[0008] In one embodiment of the present invention, in the left and right lead-out areas, the second ground via is located on the pad device and away from the middle of the side of the first ground via.

[0009] In one embodiment of the present invention, in the left and right outlet areas, the diameter range of the anti-pad of the via is 24mils to 26mils; the center distance between the two vias of the high-speed differential line on the pad device is 38.37mils to 40.37mils; the diameter range of the anti-pad of the two vias of the high-speed differential line on the pad device is 27mils to 29mils; the distance between the center of the via of the high-speed differential line on the pad device and the center of the second ground via is 23mils to 25mils; the minimum distance between the routing of the high-speed differential line and the edge of the anti-pad of the via of the high-speed differential line is 3mils to 5mils; the minimum distance between the routing of the high-speed differential line and the first ground via is 2mils±2mils; the minimum distance between the routing of the high-speed differential line and the power via is 2mils±2mils.

[0010] In one embodiment of the present invention, in the upper and lower lead-out areas, the center distance between the two vias of the high-speed differential line on the pad device is 38.37mils to 40.37mils; the diameter range of the anti-pads of the two vias of the high-speed differential line on the pad device is 27mils to 29mils; the distance between the center of the via of the high-speed differential line on the pad device and the center of the fifth ground via is 23mils to 25mils; the minimum distance between the routing of the high-speed differential line and the edge of the via anti-pad of the high-speed differential line is 3mils to 5mils; the minimum distance between the routing of the high-speed differential line and the ground via in the upper and lower lead-out areas is 2mils±2mils; the minimum distance between the routing of the high-speed differential line and the power via is 2mils±2mils.

[0011] In one embodiment of the present invention, in the left and right lead-out areas and the upper and lower lead-out areas, two interconnected first elliptical accommodating cavities and second elliptical accommodating cavities are formed on the second layer or the second and third layers, or the second to fourth layers of the printed circuit board; the first elliptical accommodating cavity corresponds to a pad device having two vias of a high-speed differential line, and the second elliptical accommodating cavity corresponds to an anti-pad of the two vias of the high-speed differential line.

[0012] In one embodiment of the present invention, the printed circuit board includes a solder resist layer, a protective layer, a power layer, a receiving signal routing layer, a power layer, a transmitting signal routing layer, a power layer, a protective layer, a solder resist layer, and multiple insulating layers, multiple core boards, and multiple ground layers located between or within each layer, which are arranged in sequence from top to bottom.

[0013] In one embodiment of the present invention, the number of layers of the printed circuit board ranges from 20 to 40 layers; the thickness of the printed circuit board ranges from 4 mm ± 1 mm.

[0014] The embodiment of the present invention further provides a wiring layout method for a printed circuit board, comprising: dividing a packaging area of ​​the printed circuit board into left and right wiring areas and upper and lower wiring areas; in the left and right wiring areas: first grounding vias are respectively arranged in the vertical direction corresponding to two vias of the high-speed differential line on the pad device, so that the two vias of the high-speed differential line on the pad device are wired out in the vertical direction; a second grounding via is arranged between the two vias of the high-speed differential line on the pad device; at least one third grounding via is respectively arranged on the outer two side areas of the pad device, and the third grounding via is ... The outlet direction of the hole has an angle with the horizontal direction; in the upper and lower outlet areas: fourth ground vias corresponding to the two vias are respectively arranged in a direction perpendicular to the connection direction of the two vias of the high-speed differential line on the pad device; a fifth ground via is arranged between the two vias of the high-speed differential line on the pad device; a sixth ground via is arranged between the two high-speed differential lines of the two vias on the pad device and in the outer area of ​​the pad device; wherein the connection line between the fifth ground via and the sixth ground via is perpendicular to the connection line between the two vias of the high-speed differential line on the pad device.

[0015] As described above, a printed circuit board and a wiring layout method thereof of the present invention have the following beneficial effects:

[0016] The present invention optimizes the outlet direction of the via holes of each high-speed differential line in the left and right outlet areas and the upper and lower outlet areas of the packaging area of ​​the printed circuit board and the layout position and outlet direction of the grounding holes, so that the BGA area has an optimized high-speed differential line fan-out mode, thereby reducing the crosstalk of the outlet fan-out, and further reducing the crosstalk of the outlet fan-out by arranging the receiving signal routing and the sending signal routing in different layers of the printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Shown is a schematic diagram of the overall structure of the printed circuit board in the present invention;

[0018] Figure 2 and Figure 3 Shown is a schematic diagram of the left and right lead-out areas in the printed circuit board of the present invention;

[0019] Figure 4 and Figure 5 Shown is a schematic diagram of the wiring of the upper and lower wiring areas in the printed circuit board of the present invention;

[0020] Figure 6 Shown is a schematic diagram of the principle of the printed circuit board layout method in the present invention.

[0021] Figure 7 Shown is a schematic diagram of the internal structure of the printed circuit board in the present invention.

[0022] Figure 8 The figure shows a specific structural example of the interior of the printed circuit board in the present invention.

[0023] Component number description

[0024] 100 Printed Circuit Board

[0025] 110 Left exit area

[0026] 111, 116 First ground via

[0027] 112, 115 Second ground via

[0028] 113, 114 Third ground via

[0029] 120 Right exit area

[0030] 130 Upper outlet area

[0031] 131 Fourth ground via

[0032] 132 Fifth ground via

[0033] 133 Sixth ground via

[0034] 140 Lower outlet area

[0035] 150 First elliptical receiving cavity

[0036] 160 Second elliptical receiving cavity

[0037] 101 Solder Mask

[0038] 102 Top Floor

[0039] 103 Power Layer

[0040] 104 Receive signal routing layer

[0041] 105 Send signal routing layer DETAILED DESCRIPTION

[0042] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0043] See also Figures 1 to 8 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0044] The purpose of this embodiment is to provide a printed circuit board and a wiring layout method thereof, which are used to optimize the high-speed differential line fan-out mode of the printed circuit board.

[0045] The following will describe in detail the principles and implementation methods of a printed circuit board and a wiring layout method of the present embodiment, so that those skilled in the art can understand the printed circuit board and a wiring layout method of the present embodiment without creative work.

[0046] like Figure 1 As shown, this embodiment provides a printed circuit board 100, wherein a packaging area is arranged on the front side of the printed circuit board 100; wherein the packaging area adopts but is not limited to a ball grid array package (BGA). A via array corresponding to the packaging area is arranged on the back side of the printed circuit board 100.

[0047] The vias include VIPPO (Via-In-Pad Plated Over, vias drilled on pads) vias and non-VIPPO vias (conventional through holes). In this embodiment, the back side of the printed circuit board 100 is provided with VIPPO vias.

[0048] In this embodiment, if Figure 1As shown, the package area of ​​the printed circuit board 100 is formed with left and right lead-out areas and upper and lower lead-out areas. The lead-out method of the left and right lead-out areas and upper and lower lead-out areas in the package area of ​​the printed circuit board 100 will affect the impedance of the via and the crosstalk of the fan-out, thereby affecting the signal quality. Figure 1 As shown, the left and right wire outlet areas include a left wire outlet area 110 and a right wire outlet area 120 , and the upper and lower wire outlet areas include an upper wire outlet area 130 and a lower wire outlet area 140 .

[0049] In this embodiment, in the left and right outgoing line areas and the upper and lower outgoing line areas, the receiving signal routing lines and the transmitting signal routing lines are arranged in different layers of the printed circuit board 100, which can reduce the crosstalk of the outgoing line fan-out.

[0050] Among them, in this embodiment, in the left and right outlet areas: first ground vias 111 are respectively arranged in the vertical direction corresponding to the two vias of the high-speed differential line on the pad device, so that the two vias of the high-speed differential line on the pad device are outlet in the vertical direction. That is to say, in the two vias of the high-speed differential line on each pad device, each via corresponds to a first ground via 111, wherein the vertical direction is a direction perpendicular to the center line of the two vias, that is, the line between the center of the first ground via 111 and the center of the corresponding via is perpendicular to the line between the two vias.

[0051] In this embodiment, the offset angle of the pad device in the left and right lead-out areas in the horizontal direction or relative to the horizontal direction does not exceed ±15°.

[0052] Preferably, at the level of the pad device in the left and right lead-out areas, a line connecting the center of the first ground via 111 and the center of the corresponding via is a vertical line.

[0053] In addition, the pad device may also be slightly inclined relative to the horizontal direction, for example, the pad device is inclined counterclockwise relative to the horizontal direction, or the pad device is inclined clockwise relative to the horizontal direction, for example, the inclination angle is about 15°.

[0054] In this embodiment, a second ground via 112 is disposed between two vias of the high-speed differential line on the pad device; the second ground via 112 is located at the center of one side edge of the pad device.

[0055] Specifically, in the left and right outlet areas, the second ground via 112 is located on the pad device and away from the middle of the side of the first ground via 111. That is, the second ground via 112 is arranged relative to the first ground via 111, and an isosceles triangle or a congruent triangle is formed between the two first ground vias 111 and the second ground via 112.

[0056] Among them, Figure 2 As shown, the positional relationship between the second ground via 112 and the first ground via 111 includes: the second ground via 112 is located in the middle of the lower side of the pad device, and the two first ground vias 111 are located in the upper side direction of the pad device; or the second ground via 115 is located in the middle of the upper side of the pad device, and the two first ground vias 116 are located in the lower side direction of the pad device.

[0057] In this embodiment, at least one third ground via 113 is respectively disposed on two side regions outside the pad device, and an exit direction of the third ground via 113 forms an angle with a horizontal direction.

[0058] That is, a plurality of third ground vias 113 with inclined extensions are provided on both sides of the outer area of ​​the pad device. For example, two third ground vias 113 are provided on the left side of the pad device and are inclined at a certain angle clockwise relative to the horizontal direction, and two third ground vias 114 are provided on the right side of the pad device and are inclined at a certain angle counterclockwise relative to the horizontal direction. The third ground vias 113 or the third ground vias 114 are shared between adjacent pad devices.

[0059] In this embodiment, the angle between the outlet direction of the third ground via 113 and the offset relative to the horizontal direction is 30° to 60°, and a certain angle fluctuation is allowed. Those skilled in the art can configure the number of the third ground via 113 or the third ground via 114 outside the pad device and the angle with the horizontal direction based on actual needs.

[0060] Since the outlet directions of the left and right outlet areas are different from those of the upper and lower outlet areas, in this embodiment, the specific wiring layout of the left and right outlet areas is different from the specific wiring layout of the upper and lower outlet areas during optimization. The specific wiring layout of the left and right outlet areas and the wiring layout of the upper and lower outlet areas are described below.

[0061] For the left and right outlet areas, the receiving signal routing and the transmitting signal routing are arranged in different layers of the printed circuit board 100: in this embodiment, preferably, the receiving signal routing is arranged in several layers of the upper half of the printed circuit board 100, and the transmitting signal routing is arranged in several layers of the lower half of the printed circuit board 100, so as to reduce the crosstalk of the outlet fan-out.

[0062] Among them, the left outlet area 110 and the right outlet area 120 can use the same number of layers to lay out the receiving signal routing, or use different numbers of layers to lay out the receiving signal routing. Correspondingly, the left outlet area 110 and the right outlet area 120 can use the same number of layers to lay out the sending signal routing, or use different numbers of layers to lay out the sending signal routing.

[0063] In this embodiment, the diameter of the via drill is selected to be 9 mils, the diameter of the formed via is 7 mils, and the diameter of the via pad is 17 mils.

[0064] like Figure 3 As shown, in the left and right lead-out areas, the diameter of the anti-pad of the via hole ranges from 24 mils to 26 mils; preferably, the diameter of the anti-pad of the via hole is 25 mils.

[0065] like Figure 3 As shown, in the left and right lead-out areas, the center distance between the two vias of the high-speed differential line on the pad device ( Figure 3 The D1 shown in FIG is 38.37 mils to 40.37 mils. Preferably, the center distance between two via holes of each high-speed differential line in the left and right line-out regions is 39.37 mils.

[0066] like Figure 3 As shown, in the left and right lead-out areas, the diameter of the anti-pads of the two vias of the high-speed differential line on the pad device ( Figure 3 The diameter of D2) shown in the figure is 27 mils to 29 mils. Preferably, the diameter of the anti-pads of the two via holes of the high-speed differential line on the pad device is 28 mils.

[0067] like Figure 3 As shown, in the left and right lead-out areas, the distance between the center of the via hole of the high-speed differential line on the pad device and the center of the second ground via hole 112 ( Figure 3 The distance D3 shown in FIG. 1 is 23 mils to 25 mils. Preferably, the distance between the center of the via hole of the high-speed differential line on the pad device and the center of the second ground via hole 112 is 24 mils.

[0068] like Figure 3 As shown, in the left and right outgoing line areas, the minimum distance between the routing of the high-speed differential line and the edge of the via anti-pad of the high-speed differential line ( Figure 3 The D4 shown in FIG is 3 mils to 5 mils. Preferably, the minimum distance between the high-speed differential line and the edge of the via anti-pad of the high-speed differential line is 4 mils.

[0069] like Figure 3As shown, in the left and right outgoing line areas, the minimum distance between the routing of the high-speed differential line and the first ground via 111 is ( Figure 3 D5) shown in is 2mils±2mils. Preferably, the minimum distance between the high-speed differential line and the first ground via 111 is 4mils.

[0070] like Figure 3 As shown, in the left and right outlet areas, the minimum distance between the high-speed differential line and the power via is 2 mils±2 mils. Preferably, the minimum distance between the high-speed differential line and the power via is 4 mils.

[0071] By optimizing the outlet direction of the vias of each high-speed differential line in the left and right outlet areas and the layout position and outlet direction of the grounding holes, the left and right outlet areas of the BGA can achieve the most optimized high-speed differential line fan-out mode, thereby minimizing the crosstalk of the outlet fan-out.

[0072] In this embodiment, if Figure 4 As shown, in the upper and lower outlet areas: fourth ground vias 131 corresponding to the two vias are respectively arranged in a direction perpendicular to the connection direction of the two vias of the high-speed differential line on the pad device, so that the two vias of the high-speed differential line on the pad device are outlet in a direction perpendicular to the connection direction of the two vias. In other words, in the two vias of the high-speed differential line on each pad device, each via corresponds to a fourth ground via 131, and the connection line between the center of the fourth ground via 131 and the center of the corresponding via is perpendicular to the connection line between the two vias.

[0073] In this embodiment, in the upper and lower wiring areas, the pad device has an offset angle of no more than 60°±15° relative to the horizontal direction. For example, the pad device is tilted about 60° counterclockwise relative to the horizontal direction, or the pad device is tilted about 60° clockwise relative to the horizontal direction.

[0074] In this embodiment, a fifth ground via 132 is disposed between two vias of the high-speed differential line on the pad device. The fifth ground via 132 is located at the center of one side edge of the pad device.

[0075] Specifically, in the upper and lower lead-out areas, the fifth ground via 132 is located on the pad device and away from the middle of the side of the fourth ground via 131. That is, the fifth ground via 132 is arranged relative to the fourth ground via 131, and an isosceles triangle or a congruent triangle is formed between the two fourth ground vias 131 and the fifth ground via 132.

[0076] Among them, the positional relationship between the fifth ground via 132 and the fourth ground via 131 includes: the fifth ground via 132 is located in the middle of the left side of the pad device, and the two fourth ground vias 131 are located in the right side direction of the pad device; or the fifth ground via 132 is located in the middle of the right side of the pad device, and the two fourth ground vias 131 are located in the left side direction of the pad device.

[0077] In this embodiment, a sixth ground via 133 is provided between two high-speed differential lines of two vias on the pad device and in the external area of ​​the pad device; wherein the connection line between the fifth ground via 132 and the sixth ground via 133 is perpendicular to the connection line between the two vias of the high-speed differential line on the pad device.

[0078] In the upper and lower outgoing line areas of this embodiment, the receiving signal routing and the sending signal routing are arranged in different layers of the printed circuit board 100. In this embodiment, preferably, the receiving signal routing is arranged in several layers of the upper half of the printed circuit board 100, and the sending signal routing is arranged in several layers of the lower half of the printed circuit board 100, so as to reduce the crosstalk of the outgoing line fan-out.

[0079] Among them, the upper outlet area 130 and the lower outlet area 140 can use the same number of layers to lay out the receiving signal routing, or use different numbers of layers to lay out the receiving signal routing. Correspondingly, the upper outlet area 130 and the lower outlet area 140 can use the same number of layers to lay out the transmitting signal routing, or use different numbers of layers to lay out the transmitting signal routing.

[0080] In this embodiment, the diameter of the via drill is selected to be 9 mils, the diameter of the formed via is 7 mils, and the diameter of the via pad is 17 mils.

[0081] In this embodiment, if Figure 5 As shown, in the upper and lower lead-out areas, the center distance between the two vias of the high-speed differential line on the pad device ( Figure 5 The D6 shown in FIG is 38.37 mils to 40.37 mils. Preferably, the center distance between two via holes of the high-speed differential line on the pad device is 39.37 mils.

[0082] In this embodiment, if Figure 5 As shown, the diameter of the anti-pad of the two vias of the high-speed differential line on the pad device ( Figure 5 The diameter of D7) shown in FIG is 27 mils to 29 mils. Preferably, the diameter of the anti-pads of the two via holes of the high-speed differential line on the pad device is 28 mils.

[0083] In this embodiment, if Figure 5As shown, the distance between the center of the via hole of the high-speed differential line on the pad device and the center of the fifth ground via hole 132 ( Figure 5 The distance D8 shown in FIG. 1 is 23 mils to 25 mils. Preferably, the distance between the center of the via hole of the high-speed differential line on the pad device and the center of the fifth ground via hole 132 is 24 mils.

[0084] In this embodiment, if Figure 5 As shown, the minimum distance between the high-speed differential line and the edge of the via anti-pad of the high-speed differential line ( Figure 5 The D9 shown in FIG is 3 mils to 5 mils. Preferably, the minimum distance between the high-speed differential line and the edge of the via anti-pad of the high-speed differential line is 4 mils.

[0085] In this embodiment, if Figure 5 As shown, the minimum distance between the high-speed differential line and the ground vias in the upper and lower lead-out areas ( Figure 5 D10 shown in is 2mils±2mils. Preferably, the minimum distance between the high-speed differential line and the ground vias in the upper and lower lead-out areas is 4mils.

[0086] In this embodiment, if Figure 5 As shown, the minimum distance between the high-speed differential line and the power via is 2 mils±2 mils. Preferably, the minimum distance between the high-speed differential line and the power via is 4 mils.

[0087] By optimizing the outlet direction of the vias of each high-speed differential line in the upper and lower outlet areas and the layout position and outlet direction of the grounding holes, the upper and lower outlet areas of the BGA can achieve the most optimized high-speed differential line fan-out mode, thereby minimizing the crosstalk of the outlet fan-out.

[0088] In this embodiment, if Figure 6 As shown, in the left and right lead-out areas and the upper and lower lead-out areas, two interconnected first elliptical accommodating cavities 150 and second elliptical accommodating cavities 160 are formed on the second layer or the second and third layers, or the second to fourth layers of the printed circuit board 100; the first elliptical accommodating cavity 150 corresponds to a pad device having two vias of a high-speed differential line, and the second elliptical accommodating cavity 160 corresponds to the anti-pad of the two vias of the high-speed differential line.

[0089] Figure 7 The internal structure diagram of the printed circuit board 100 of the present invention is shown. Figure 7As shown, the printed circuit board 100 includes a solder resist layer, a protective layer, a power layer, a receiving signal routing layer, a power layer, a transmitting signal routing layer, a power layer, a protective layer, a solder resist layer, and multiple insulating layers, multiple core boards, and multiple grounding layers located between or within each layer, which are sequentially arranged from top to bottom.

[0090] Among them, the power supply layer may include multiple layers of sub-power supply layers, the receiving signal routing layer includes multiple receiving signal routing sub-layers, and the transmitting signal routing layer includes multiple transmitting signal routing sub-layers.

[0091] In this embodiment, by laying out the layers of the printed circuit board 100 and the routing of the layers, the printed circuit board 100 reduces the crosstalk of the fan-out lines.

[0092] In this embodiment, the number of layers of the printed circuit board 100 is in the range of, but not limited to, 20 to 40 layers; the thickness of the printed circuit board 100 is in the range of, but not limited to, 4 mm±1 mm.

[0093] In this embodiment, preferably, the thickness of the printed circuit board 100 is 4.4 mm, and the diameter of the anti-pad corresponding to the via hole is 25 mils.

[0094] like Figure 8 As shown, this embodiment takes the printed circuit board 100 having 28 layers as an example to illustrate the internal structure of the printed circuit board 100 in this embodiment.

[0095] like Figure 8 As shown, the top of the printed circuit board 100 is a solder mask layer 101 (SM), followed by the first protective layer 102 (Top), and the second layer is configured as a ground layer (GND), and an insulating layer (PREPREG) is provided between the ground layer (GND) and the protective layer 102 (Top). The third layer (VCC), the fifth layer (VCC1) and the sixth layer (VCC2) are power layers 103, and the fourth layer is a ground layer (GND), wherein an insulating layer (PREPREG) is provided between VCC and GND, a core board (CORE) is provided between the third layer (VCC) and the GND of the second layer, and a core board (CORE) is provided between the fourth layer (GND) and the GND of the fifth layer (VCC1). An insulating layer (PREPREG) is provided between the fifth layer (VCC1) and the sixth layer (VCC2). The 7th layer is the ground layer (GND), and a core board (CORE) is provided between the 6th layer (VCC2) and the 7th layer ground layer (GND). The 3rd layer, the 8th layer, the 10th layer and the 12th layer are the receiving signal routing layer 104, including multiple receiving signal routing sub-layers SIG1 to SIG4. A core board (CORE), a ground layer (GND) and an insulation layer (PREPREG) are provided between the multiple receiving signal routing sub-layers SIG1 to SIG4.

[0096] The 13th layer is the ground layer (GND), and the 14th layer (VCC3) and the 15th layer (VCC4) constitute the power layer 103. The 16th layer is the ground layer (GND), and the 17th, 19th, 21st and 26th layers are the transmission signal routing layer 105, including multiple receiving signal routing sub-layers SIG5 to SIG8. An insulating layer (PREPREG), a ground layer (GND) and a core board (CORE) are respectively provided between the multiple receiving signal routing sub-layers SIG5 to SIG8. The 22nd layer is the ground layer (GND), and the 23rd layer (VCC5), the 24th layer (VCC6) and the 26th layer (VCC) are the power layer 103, and the 28th layer is the protective layer 102 (Bottom). The solder resist layer 101 (SM, Sloder mask) is also configured outside the protective layer 102.

[0097] In this embodiment, the thickness of the flame retardant layer is but not limited to 0.5±0.1mils, and the thickness of the flame retardant layer 102 is but not limited to 3.1±0.5mils. The material of the core board between the power layer and the ground layer is MC24M double-sided etched embedded capacitance material with a thickness of 1mil. The thickness of the core board (CORE) in the receiving signal routing layer 104 and the transmitting signal routing layer 105 is 3.9±0.5mils, and the material of the core board is DVN material.

[0098] In addition, this embodiment also provides a wiring layout method for a printed circuit board 100, including:

[0099] 1) Divide the packaging area of ​​the printed circuit board into left and right lead-out areas and upper and lower lead-out areas;

[0100] 2) In the left and right lead-out areas: first ground vias are respectively arranged in the vertical direction corresponding to the two vias of the high-speed differential line on the pad device, so that the two vias of the high-speed differential line on the pad device lead out in the vertical direction; a second ground via is arranged between the two vias of the high-speed differential line on the pad device; at least one third ground via is respectively arranged on the two side areas outside the pad device, and the lead-out direction of the third ground via has an angle with the horizontal direction;

[0101] 3) In the upper and lower line-out areas: fourth ground vias corresponding to the two vias on the pad device are respectively arranged in a direction perpendicular to the connection direction of the two vias of the high-speed differential line on the pad device; a fifth ground via is arranged between the two vias of the high-speed differential line on the pad device; a sixth ground via is arranged between the two high-speed differential lines of the two vias on the pad device and in the external area of ​​the pad device; wherein the connection line between the fifth ground via and the sixth ground via is perpendicular to the connection line between the two vias of the high-speed differential line on the pad device.

[0102] The technical principle of the printed circuit board routing method is similar to the above-mentioned Figures 1 to 8 The technical principle of the wiring layout of the printed circuit board 100 described in the above is the same as that described above and will not be repeated here.

[0103] In summary, the present invention optimizes the outlet direction of the via holes of each high-speed differential line in the left and right outlet areas and the upper and lower outlet areas of the packaging area of ​​the printed circuit board and the layout position and outlet direction of the grounding holes, so that the BGA area has an optimized high-speed differential line fan-out mode, thereby reducing the crosstalk of the outlet fan-out, and further reducing the crosstalk of the outlet fan-out by arranging the receiving signal routing and the transmitting signal routing in different layers of the printed circuit board. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A printed circuit board, wherein a packaging area is arranged on the front side of the printed circuit board; and a via array corresponding to the packaging area is arranged on the back side of the printed circuit board; characterized in that: The packaging area of ​​the printed circuit board is formed with left and right lead-out areas and upper and lower lead-out areas; In the left and right lead-out areas: first ground vias are respectively arranged in the vertical direction corresponding to the two vias of the high-speed differential line on the pad device, so that the two vias of the high-speed differential line on the pad device lead out in the vertical direction; a second ground via is arranged between the two vias of the high-speed differential line on the pad device; at least one third ground via is respectively arranged on the two side areas outside the pad device, and the lead-out direction of the third ground via has an angle with the horizontal direction, and the angle is 30° to 60°; In the upper and lower line-out areas: fourth ground vias corresponding to the two vias on the pad device are respectively arranged in a direction perpendicular to the connection direction of the two vias of the high-speed differential line; a fifth ground via is arranged between the two vias of the high-speed differential line on the pad device; a sixth ground via is arranged between the two high-speed differential lines of the two vias on the pad device and in the outer area of ​​the pad device; wherein the connection line between the fifth ground via and the sixth ground via is perpendicular to the connection line between the two vias of the high-speed differential line on the pad device.

2. The printed circuit board according to claim 1, characterized in that: In the left and right outgoing wire areas and the upper and lower outgoing wire areas, receiving signal routing lines and sending signal routing lines are arranged in different layers of the printed circuit board.

3. The printed circuit board according to claim 1, characterized in that: In the left and right lead-out areas, the pad device has a horizontal or relative horizontal offset angle of ±15°; in the upper and lower lead-out areas, the pad device has a relative horizontal offset angle of 60°±15°.

4. The printed circuit board according to claim 1, characterized in that: In the left and right lead-out areas, the second ground via is located on the pad device and away from the middle of the side of the first ground via.

5. The printed circuit board according to claim 1, characterized in that: In the left and right outlet areas, the diameter range of the anti-pad of the via is 24mils to 26mils; the center distance between the two vias of the high-speed differential line on the pad device is 38.37mils to 40.37mils; the diameter range of the anti-pad of the two vias of the high-speed differential line on the pad device is 27mils to 29mils; the distance between the center of the via of the high-speed differential line on the pad device and the center of the second ground via is 23mils to 25mils; the minimum distance between the routing of the high-speed differential line and the edge of the anti-pad of the via of the high-speed differential line is 3mils to 5mils; the minimum distance between the routing of the high-speed differential line and the first ground via is 2mils±2mils; the minimum distance between the routing of the high-speed differential line and the power via is 2mils±2mils.

6. The printed circuit board according to claim 1, characterized in that: In the upper and lower lead-out areas, the center distance between the two vias of the high-speed differential line on the pad device is 38.37mils to 40.37mils; the diameter range of the anti-pads of the two vias of the high-speed differential line on the pad device is 27mils to 29mils; the distance between the center of the via of the high-speed differential line on the pad device and the center of the fifth ground via is 23mils to 25mils; the minimum distance between the routing of the high-speed differential line and the edge of the anti-pad of the via of the high-speed differential line is 3mils to 5mils; the minimum distance between the routing of the high-speed differential line and the ground via in the upper and lower lead-out areas is 2mils±2mils; the minimum distance between the routing of the high-speed differential line and the power via is 2mils±2mils.

7. The printed circuit board according to claim 1, characterized in that: In the left and right lead-out areas and the upper and lower lead-out areas, two interconnected first elliptical accommodating cavities and second elliptical accommodating cavities are formed on the second layer or the second and third layers, or the second to fourth layers of the printed circuit board; the first elliptical accommodating cavity corresponds to a pad device having two vias of a high-speed differential line, and the second elliptical accommodating cavity corresponds to an anti-pad of the two vias of the high-speed differential line.

8. The printed circuit board according to claim 1, characterized in that: The printed circuit board includes a solder resist layer, a protective layer, a power layer, a receiving signal routing layer, a power layer, a sending signal routing layer, a power layer, a protective layer, a solder resist layer, and multiple insulating layers, multiple core boards, and multiple grounding layers located between or within each layer, which are sequentially arranged from top to bottom.

9. The printed circuit board according to claim 1 or 8, characterized in that: The number of layers of the printed circuit board ranges from 20 to 40 layers; the thickness of the printed circuit board ranges from 4 mm ± 1 mm.

10. A method for routing a printed circuit board, characterized in that: include: Divide the packaging area of ​​the printed circuit board into left and right lead-out areas and upper and lower lead-out areas; In the left and right lead-out areas: first ground vias are respectively arranged in the vertical direction corresponding to the two vias of the high-speed differential line on the pad device, so that the two vias of the high-speed differential line on the pad device lead out in the vertical direction; a second ground via is arranged between the two vias of the high-speed differential line on the pad device; at least one third ground via is respectively arranged on the two side areas outside the pad device, and the lead-out direction of the third ground via has an angle with the horizontal direction, and the angle is 30° to 60°; In the upper and lower line-out areas: fourth ground vias corresponding to the two vias on the pad device are respectively arranged in a direction perpendicular to the connection direction of the two vias of the high-speed differential line; a fifth ground via is arranged between the two vias of the high-speed differential line on the pad device; a sixth ground via is arranged between the two high-speed differential lines of the two vias on the pad device and in the outer area of ​​the pad device; wherein the connection line between the fifth ground via and the sixth ground via is perpendicular to the connection line between the two vias of the high-speed differential line on the pad device.

Images