Three-dimensional device having a bonding structure including a support die and a method for making the same

Abstract

A memory die including a three-dimensional array of memory elements and a logic die including peripheral circuits supporting the operation of the three-dimensional array of memory elements can be joined by die-to-die bonding to provide a joined assembly. External bonding pads for the joined assembly can be provided by forming a recessed area through the memory die or through the logic die to physically expose the metal interconnect structures within the interconnect level dielectric layer. These external bonding pads may include a physically exposed subset of these metal interconnect structures, or may be formed on a physically exposed subset of these metal interconnect structures. Alternatively or in addition, a lateral insulating external connection via structure may be formed through the joined assembly to multiple levels of these metal interconnect structures. In addition, a through dielectric external connection via structure extending through a stepped dielectric material portion of the memory die may be physically exposed, and external bonding pads may be formed thereon.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent applications Serial Nos. 16 / 291,457, 16 / 291,504, and 16 / 291,577, filed on March 4, 2019, and the entire contents of these applications are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to a three-dimensional memory device having a bonding structure including a support die and a method of manufacturing the same. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a bonding assembly is provided, the bonding assembly comprising: a first semiconductor die, the first semiconductor die comprising: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer comprising a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bonding pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; and a second semiconductor die, the second semiconductor die comprising: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located on or above the second proximal planar surface of the second substrate, a second die comprising a second proximal planar surface electrically connected to the second semiconductor device a second interconnect level dielectric layer of a metal interconnect structure, and a second die-to-die bonding pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure, wherein: the second die-to-die bonding pad is bonded to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; an external bonding pad, the external bonding pad is located on or in one of the first interconnect level dielectric layer and the second interconnect level dielectric layer, the external bonding pad has a physically exposed horizontal surface; and the external bonding pad is completely located within a first horizontal plane and a second horizontal plane, the first horizontal plane includes the first proximal flat surface of the first substrate, and the second horizontal plane includes the second proximal flat surface of the second substrate.

[0006] According to another aspect of the present disclosure, a method for forming a bonded assembly is provided, the method comprising: providing a first semiconductor die, wherein the first semiconductor die comprises: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer comprising a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bonding pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; providing a second semiconductor die, wherein the second semiconductor die comprises: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located on or above the second proximal planar surface of the second substrate, a first interconnect level dielectric layer comprising a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bonding pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure. The invention relates to a method of manufacturing a second semiconductor device comprising: forming a second interconnect level dielectric layer of a second metal interconnect structure of the second semiconductor device, and a second die-to-die bonding pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure; bonding the second die-to-die bonding pad to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; forming a recessed area by removing a portion of material extending vertically from the second distal planar surface through the second substrate and extending into the volume of the second proximal planar surface to provide a physically exposed horizontal surface of one of the first interconnect level dielectric layer and the second interconnect level dielectric layer; and providing an external bonding pad located on or in one of the first interconnect level dielectric layer and the second interconnect level dielectric layer.

[0007] According to another aspect of the present disclosure, a bonding assembly is provided, the bonding assembly comprising: a first semiconductor die, the first semiconductor die comprising: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer comprising a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bonding pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; and a second semiconductor die, the second semiconductor die comprising: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located on or above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer comprising a second metal interconnect structure electrically connected to the second semiconductor device, and a second die-to-die bonding pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure, wherein: the second die-to-die bonding pad is bonded to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; a first external bonding pad is located on or above the second distal planar surface of the second substrate; and a first lateral insulating external connection via structure, the first lateral insulating external connection via structure extending vertically from at least the second distal planar surface of the second substrate through the second substrate, the second interconnect level dielectric layer, a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and a subset of layers within the first interconnect level dielectric layer, and extending to one of the first metal interconnect structures and contacting the first bonding pad.

[0008] According to another aspect of the present invention, a method for forming a bonded assembly is provided, the method comprising: providing a first semiconductor die, wherein the first semiconductor die comprises: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer comprising a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bond pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; providing a second semiconductor die, wherein the second semiconductor die comprises: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located on or above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer comprising a second metal interconnect structure electrically connected to the second semiconductor device, and a second die-to-die bond pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure. layer, and a second die-to-die bonding pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure; bonding the second die-to-die bonding pad to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; forming a first connecting via cavity through the second substrate, the second interconnect level dielectric layer, a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and a subset of layers within the first interconnect level dielectric layer, wherein one of the first metal interconnect structures is physically exposed at the bottom of the first connecting via cavity; forming a first lateral insulating external connecting via structure in the first connecting via cavity on the one of the first metal interconnect structures; and forming a first external bonding pad on the first lateral insulating external connecting via structure.

[0009] According to another aspect of the present disclosure, a bonding assembly is provided, the bonding assembly comprising: a memory die, the memory die comprising an alternating stack of insulating layers and conductive layers having a stepped surface, a memory stack structure extending vertically through the alternating stack, a stepped dielectric material portion contacting the stepped surface of the alternating stack, a through dielectric external connection via structure extending vertically through the stepped dielectric material portion; a memory side metal interconnect structure, the memory side metal interconnect structure included in a memory side interconnect level dielectric layer, and a memory side bonding pad; a logic A logic die, the logic die comprising: a semiconductor substrate, a semiconductor device located on the semiconductor substrate and including a peripheral circuit configured to control the operation of the memory stack structure within the memory die, a logic side metal interconnect structure included in a logic side interconnect level dielectric layer, and a logic side bonding pad bonded to the memory side bonding pad of the memory die at a die-to-die bonding interface; and an external bonding pad, the external bonding pad being located on a surface of the stepped dielectric material portion and contacting a distal flat surface of the through-dielectric external connection via structure.

[0010] According to another aspect of the present disclosure, a method for forming a bonding assembly is provided, the method comprising: providing a memory die, the memory die comprising a memory side substrate, an alternating stack of insulating layers and conductive layers having a stepped surface and located on the memory side substrate, a memory stack structure extending vertically through the alternating stack, a stepped dielectric material portion contacting the stepped surface of the alternating stack, a through-dielectric external connection via structure extending vertically through the stepped dielectric material portion, a memory side metal interconnect structure included in a memory side interconnect level dielectric layer, and a memory side bonding pad; providing a logic die, the logic die The memory die includes: a semiconductor substrate, a semiconductor device located on the semiconductor substrate and including a peripheral circuit configured to control the operation of the memory stack structure within the memory die, a logic side metal interconnect structure included in a logic side interconnect level dielectric layer, and a logic side bonding pad; bonding the memory side bonding pad to the logic side bonding pad to form a die-to-die bonding interface; physically exposing the distal flat surface of the through-dielectric external connection via structure by removing at least a portion of the memory side substrate; and forming an external bonding pad on the distal flat surface of the through-dielectric external connection via structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a vertical cross-sectional view of a first exemplary structure after forming a first alternating stack of first insulating layers and first spacer material layers according to an embodiment of the present disclosure.

[0012] Figure 2 is a vertical cross-sectional view of a first exemplary structure after forming a first level staircase region, a first stepped dielectric material portion, and an interlayer dielectric layer according to an embodiment of the present disclosure.

[0013] Figure 3A is a vertical cross-sectional view of a first exemplary structure after forming a first layer memory opening and a first layer support opening according to an embodiment of the present disclosure.

[0014] Figure 3B yes Figure 3A A horizontal cross-sectional view of the first exemplary structure. The articulated vertical plane AA' corresponds to Figure 3A A plane of a vertical section.

[0015] Figure 4 is a vertical cross-sectional view of the first exemplary structure after forming various sacrificial fill structures according to an embodiment of the present disclosure.

[0016] Figure 5 is a vertical cross-sectional view of the first exemplary structure after forming a second alternating stack of second insulating layers and second spacer material layers, a second stepped surface, and a second stepped dielectric material portion according to an embodiment of the present disclosure.

[0017] Fig. 6A is a vertical cross-sectional view of the first exemplary structure after forming a second layer memory opening and a second layer support opening according to an embodiment of the present disclosure.

[0018] Figure 6B is along Fig. 6A A horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane BB' of FIG. The hinged vertical plane AA' corresponds to Fig. 6A A plane of a vertical section.

[0019] Figure 7 is a vertical cross-sectional view of the first exemplary structure after forming an inter-layer memory opening and an inter-layer support opening according to an embodiment of the present disclosure.

[0020] FIG. 8A to FIG. 8H Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure according to an embodiment of the present disclosure are shown.

[0021] Fig.9A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure and a support pillar structure according to an embodiment of the present disclosure.

[0022] Fig. 9B is along Fig.9A A horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane BB'. The hinged vertical plane AA" corresponds to Fig.9A A plane of a vertical section.

[0023] Fig. 10A is a vertical cross-sectional view of the first exemplary structure after forming a first contact level dielectric layer and backside trenches according to an embodiment of the present disclosure.

[0024] Fig. 10B is along Fig. 10A A horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane BB' of FIG. The hinged vertical plane AA' corresponds to Fig. 10A A plane of a vertical section.

[0025] Fig.11 is a vertical cross-sectional view of the first exemplary structure after forming backside trenches according to an embodiment of the present disclosure.

[0026] FIG. 12A to FIG. 12E Sequential vertical cross-sectional views of a memory opening filling structure and a backside trench during formation of a conductive layer in a backside recess according to an embodiment of the present disclosure are shown.

[0027] Fig.13 is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0028] Fig.14A is a vertical cross-sectional view of the first exemplary structure after forming a dielectric wall structure in the backside trench according to an embodiment of the present disclosure.

[0029] Fig. 14B is along Fig.14A A horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane BB' of FIG. The hinged vertical plane AA' corresponds to Fig.14A A plane of a vertical section.

[0030] Fig. 14C is along Fig. 14B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0031] Fig.15A is a vertical cross-sectional view of the first exemplary structure after forming a second contact level dielectric layer and various contact via structures according to an embodiment of the present disclosure.

[0032] Fig. 15B is along Fig.15A A horizontal cross-sectional view of the first exemplary structure taken along the vertical plane BB' of FIG. The hinged vertical plane AA' corresponds to Fig.15A A plane of a vertical section.

[0033] Fig.16is a vertical cross-sectional view of a first exemplary structure after forming a memory die including an interconnect level dielectric layer and a metal interconnect structure according to an embodiment of the present disclosure.

[0034] Fig.17 is a vertical cross-sectional view of a logic die subsequently incorporated into a first exemplary structure according to an embodiment of the present disclosure.

[0035] 18A to 18D are sequential vertical cross-sectional views of a first configuration of a first exemplary structure during formation of a bonded assembly including a recessed region containing an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0036] Fig.18E yes Fig.18D A vertical cross-sectional view of a first configuration of a first exemplary structure.

[0037] Fig.18F yes Fig.18D A vertical cross-sectional view of a first alternative configuration of a first exemplary structure at a processing step of .

[0038] Figure 18G yes Fig.18D A vertical cross-sectional view of a second alternative embodiment of the first configuration of the first exemplary structure.

[0039] FIG. 19A to FIG. 19C are sequential vertical cross-sectional views of a second configuration of a first exemplary structure during formation of a bonded assembly including a recessed region containing an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0040] Fig. 20A is a vertical cross-sectional view of a configuration of a first exemplary structure after forming a memory die including an interconnect level dielectric layer and a metal interconnect structure according to an embodiment of the present disclosure.

[0041] Fig. 20B is subsequently incorporated into the embodiment according to the present disclosure Fig. 20A A vertical cross-sectional view of the configuration of a logic die in a first exemplary structure.

[0042] FIG. 20C to FIG. 20F are sequential vertical cross-sectional views of a third configuration of a first exemplary structure during formation of a bonded assembly including a recessed region containing an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0043] Figure 20G is another vertical cross-sectional view of the third configuration of the first exemplary structure.

[0044] Fig. 20His a vertical cross-sectional view of a fourth configuration of the first exemplary structure according to an embodiment of the present disclosure.

[0045] Fig.21A is a vertical cross-sectional view of a configuration of a first exemplary structure after forming a memory die including an interconnect level dielectric layer and a metal interconnect structure according to an embodiment of the present disclosure.

[0046] Fig. 21B is subsequently incorporated into the embodiment according to the present disclosure Fig.21A A vertical cross-sectional view of the configuration of a logic die in a first exemplary structure.

[0047] FIG. 21C to FIG. 21F are sequential vertical cross-sectional views of a fifth configuration of a first exemplary structure during formation of a bonded assembly including a recessed region containing an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0048] Figure 21G is a vertical cross-sectional view of an alternative embodiment of a fifth configuration of the first exemplary structure.

[0049] Fig.21H is a vertical cross-sectional view of a sixth configuration of the first exemplary structure.

[0050] Fig.22A is a vertical cross-sectional view of a configuration of a first exemplary structure after forming a memory die including an interconnect level dielectric layer and a metal interconnect structure according to an embodiment of the present disclosure.

[0051] Fig. 22B is subsequently incorporated into the embodiment according to the present disclosure Fig.22A A vertical cross-sectional view of the configuration of a logic die in a first exemplary structure.

[0052] FIG. 22C to FIG. 22F are sequential vertical cross-sectional views of a seventh configuration of a first exemplary structure during formation of a bonded assembly including a recessed region containing an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0053] Figure 22G is a vertical cross-sectional view of an eighth configuration of the first exemplary structure according to an embodiment of the present disclosure.

[0054] Fig.23A is a vertical cross-sectional view of a configuration of a memory die including interconnect level dielectric layers and metal interconnect structures according to an embodiment of the present disclosure.

[0055] Fig. 23B is subsequently incorporated into the embodiment according to the present disclosure Fig.21A A vertical cross-sectional view of the configuration of a logic die in a first exemplary structure.

[0056] FIG. 23C to FIG. 23E are sequential vertical cross-sectional views of a first configuration of a second exemplary structure during formation of a bonded assembly including a lateral insulated external connecting via structure, an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0057] Fig.23F is a vertical cross-sectional view of a second configuration of a second exemplary structure according to an embodiment of the present disclosure.

[0058] Figure 23G is a vertical cross-sectional view of an alternative second configuration of a second exemplary structure according to an embodiment of the present disclosure.

[0059] Fig.24A is a vertical cross-sectional view of a configuration of a memory die including interconnect level dielectric layers and metal interconnect structures according to an embodiment of the present disclosure.

[0060] Fig. 24B is subsequently incorporated into the embodiment according to the present disclosure Fig.24A A vertical cross-sectional view of the configuration of a logic die in a first exemplary structure.

[0061] FIG. 24C to FIG. 24E are sequential vertical cross-sectional views of a third configuration of a second exemplary structure during formation of a bonded assembly including a lateral insulated external connecting via structure, an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0062] Fig.24F is a vertical cross-sectional view of a fourth configuration of the second exemplary structure according to an embodiment of the present disclosure.

[0063] Fig.25A is a vertical cross-sectional view of a memory die in an exemplary process after forming a through-dielectric external connection via structure according to an embodiment of the present disclosure.

[0064] Fig.25B is a vertical cross-sectional view of a first exemplary memory die according to an embodiment of the present disclosure.

[0065] FIG. 25C to FIG. 25F are sequential vertical cross-sectional views of a first configuration of a third exemplary structure during formation of a bonded assembly including a through-dielectric external connection via structure, an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure.

[0066] Figure 25G is an alternative embodiment of the first configuration of the third exemplary structure according to the embodiment of the present disclosure.

[0067] Fig.26Ais a vertical cross-sectional view of a memory die in a second exemplary process after forming a first alternating stack of first insulating layers and first spacer material layers according to an embodiment of the present disclosure.

[0068] Fig.26B yes Fig.26A FIG. 5 is an enlarged vertical cross-sectional view of a region of a memory die during a second exemplary process.

[0069] FIG. 27A to FIG. 27D are sequential vertical cross-sectional views of a memory opening of a memory die in a second exemplary process during formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0070] Fig.28 is a vertical cross-sectional view of a memory die in a second exemplary process after forming backside trenches according to an embodiment of the present disclosure.

[0071] FIG. 29A to FIG. 29E are sequential vertical cross-sectional views of a region of a memory die in a second exemplary process including two memory opening fill structures and a backside trench during replacement of a source level material layer with a source level material layer in accordance with an embodiment of the present disclosure.

[0072] Fig.30 is a vertical cross-sectional view of a memory die in a second exemplary process after forming a dielectric wall structure according to an embodiment of the present disclosure.

[0073] Fig.31 is a vertical cross-sectional view of a memory die in a second exemplary process after forming a through-dielectric external connection via structure according to an embodiment of the present disclosure.

[0074] Fig.32 is a vertical cross-sectional view of a second exemplary memory die according to an embodiment of the present disclosure.

[0075] FIG. 33A to FIG. 33D are sequential vertical cross-sectional views of a second configuration of a third exemplary structure during formation of a bonded assembly including a through-dielectric external connection via structure, an external bond pad, a solder ball, and a bond wire according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0076] As described above, various embodiments of the present disclosure are all related to three-dimensional memory devices. Support (i.e., driver) circuits are provided to perform write, read, and erase operations of memory cells in vertical NAND strings. Typically, complementary metal oxide semiconductor (CMOS) devices are formed on the same substrate as the three-dimensional memory device. However, degradation of CMOS devices due to incidental thermal cycles and hydrogen diffusion during the manufacture of the three-dimensional memory device may severely constrain the performance of support circuits including CMOS devices. Various embodiments provide a bonding structure that combines high-performance support circuits on a substrate different from the three-dimensional memory array, and then the substrates are bonded to each other. Embodiments of the present disclosure can be used to form various structures, including multi-level memory structures, non-limiting examples of which include semiconductor devices, such as three-dimensional monomer memory array devices including multiple NAND memory strings.

[0077] The accompanying drawings are not drawn to scale. Multiple instances of an element may be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first", "second" and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components. As used herein, if there is a conductive path between a first electronic component and a second electronic component, the first electronic component is electrically connected to the second electronic component.

[0078] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0079] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolith" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. Three-dimensional memory devices according to various embodiments of the present disclosure include monolithic three-dimensional NAND string memory devices and may be manufactured using various embodiments described herein.

[0080] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded therein, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block includes a plurality of pages, which are minimum units that can be selected for programming, ie, minimum units on which a program operation can be performed.

[0081] refer to Figure 1 , shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate, which is referred to herein as a memory side substrate 310. The memory side substrate 310 may be a semiconductor substrate, an insulating substrate, or a conductive substrate. In one embodiment, a commercially available silicon wafer may be used for the memory side substrate 310.

[0082] An alternating stack of first and second material layers is subsequently formed. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least another alternating stack of material layers is subsequently formed above the alternating stack of first and second material layers, the alternating stack is referred to herein as a first alternating stack. A level of the first alternating stack is referred to herein as a first level, and a level of the alternating stack to be subsequently formed immediately above the first level is referred to herein as a second level, etc.

[0083] The first alternating stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced with a conductive layer, in other embodiments the spacer material layer is formed as a conductive layer (thereby avoiding the need to perform a replacement process).

[0084] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating multiple first insulating layers 132 and first sacrificial material layers 142 are formed over the memory side substrate 310. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0085] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0086] The first alternating stack (132, 142) may include a first insulating layer 132 composed of a first material, and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0087] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0088] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0089] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0090] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the first alternating stack (132, 142) can have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0091] A first insulating capping layer 170 is then formed over the stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating capping layer 170 can be in the range of 20 nm to 300 nm, although lesser and greater thicknesses can also be used.

[0092] refer to Figure 2 , the first insulating cap layer 170 and the first alternating stack (132, 142) can be patterned to form a first stepped surface in the staircase area 200. The staircase area 200 may include a corresponding first stepped area and a second stepped area, in which a first stepped surface is formed, and in the second stepped area, an additional stepped surface is subsequently formed in a second layer structure (which is subsequently formed above the first layer structure) and / or an additional layer structure. The first stepped surface can be formed, for example, by forming a mask layer having an opening therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively extending the etching area, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etching cavity positioned in the etching area. In one embodiment, the top surface of the first sacrificial material layer 142 can be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as the first stepped cavity.

[0093] A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the area overlying the first stepped surface constitutes a first stepped dielectric material portion 165. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first alternating stack (132, 142) and the first stepped dielectric material portion 165 together constitute a first layer structure, which is a process structure that is subsequently modified.

[0094] An interlayer dielectric layer 180 may be optionally deposited over the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 comprises a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may comprise doped silicate glass, which has a greater etching rate than the material of the first insulating layer 132 (which may comprise undoped silicate glass). For example, the interlayer dielectric layer 180 may comprise phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0095] refer to Figure 3A and Figure 3B , various first layer openings (149, 129) may be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the memory side substrate 310. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the memory side substrate 310 by a first anisotropic etching process to form various first layer openings (149, 129) simultaneously (i.e., during the first isotropic etching process). The various first layer openings (149, 129) may include a first layer memory opening 149 and a first layer support opening 129. In Figure 3B The location of the step S in the first alternating stack (132, 142) is shown by dashed lines.

[0096] The first layer memory openings 149 are openings formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. The first layer memory openings 149 may be formed as clusters of first layer memory openings 149 that are laterally spaced apart along the second horizontal direction hd2. Each cluster of first layer memory openings 149 may be formed as a two-dimensional array of first layer memory openings 149.

[0097] In one embodiment, the first anisotropic etching process may include an initial step in which the material of the first alternating stack (132, 142) is etched during the material of the first stepped dielectric material portion 165. The chemistry of the initial etching step may be alternating to optimize the etching of the first material and the second material in the first alternating stack (132, 142) while providing an average etching rate comparable to the material of the first stepped dielectric material portion 165. The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings (149, 129) may be substantially vertical, or may be tapered. The photoresist layer may then be removed, for example, by ashing.

[0098] Optionally, the portion of the first layer memory opening 149 and the first layer support opening 129 at the level of the interlayer dielectric layer 180 can be expanded laterally by isotropic etching. In this case, the interlayer dielectric layer 180 can include a dielectric material (such as borosilicate glass) having a greater etching rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). Isotropic etching (such as wet etching using HF) can be used to expand the lateral size of the first layer memory opening 149 at the level of the interlayer dielectric layer 180. The portion of the first layer memory opening 149 located at the level of the interlayer dielectric layer 180 can be optionally widened to provide a larger landing pad for the second layer memory opening that will be subsequently formed through the second alternating stack (subsequently formed before forming the second layer memory opening).

[0099] refer to Figure 4 , a sacrificial first layer opening filling portion (148, 128) can be formed in various first layer openings (149, 129). For example, a sacrificial first layer filling material is deposited simultaneously in each of the first layer openings (149, 129). The sacrificial first layer filling material includes a material that can be selectively removed from the material of the first insulating layer 132 and the first sacrificial material layer 142.

[0100] In one embodiment, the sacrificial first layer fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0101] In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the materials of the first insulating layer 132, the first insulating capping layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0102] In another embodiment, the sacrificial first layer fill material may include amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently selectively removed for the material of the first alternating stack (132, 142).

[0103] Portions of the deposited sacrificial material may be removed from above the topmost layer of the first alternating stack (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial first layer of fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

[0104] The remaining portions of the sacrificial first layer filling material include sacrificial first layer opening filling portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening filling portion 128. The various sacrificial first layer opening filling portions (148, 128) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits the sacrificial first layer filling material and a planarization process that removes the first layer deposition process from above the first alternating stack (132, 142), such as from above the top surface of the interlayer dielectric layer 180. The top surface of the sacrificial first layer opening filling portion (148, 128) may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening filling portions (148, 128) may or may not include a cavity therein.

[0105] refer to Figure 5 , a second layer structure may be formed above the first layer structure (132, 142, 170, 148). The second layer structure may include additional alternating stacks of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers may be subsequently formed on the top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes alternating multiple third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0106] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed for the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0107] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second alternating stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0108] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0109] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) can have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

[0110] The second stepped surface in the second stepped region can be formed in the staircase region 200 using the same set of processing steps as the processing steps used to form the first stepped surface in the first stepped region, wherein the pattern of at least one mask layer is appropriately adjusted. A second stepped dielectric material portion 265 can be formed over the second stepped surface in the staircase region 200.

[0111] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242). The second insulating capping layer 270 comprises a dielectric material different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may comprise silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) may comprise silicon nitride.

[0112] Generally speaking, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the memory side substrate 310, and at least one stepped dielectric material portion (165, 265) can be formed above the staircase area on at least one alternating stack (132, 142, 232, 242).

[0113] Optionally, the drain select level isolation structure 72 may be formed as a subset of the layers in the upper portion of the second alternating stack (232, 242). The second sacrificial material layer 242 cut by the drain select level isolation structure 72 corresponds to the level at which the drain select level conductive layer is subsequently formed. The drain select level isolation structure 72 includes a dielectric material, such as silicon oxide. The drain select level isolation structure 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The combination of the second layer alternating stack (232, 242), the second stepped dielectric material portion 265, the second insulating cap layer 270, and the optional drain select level isolation structure 72 together constitute the second layer structure (232, 242, 265, 270, 72).

[0114] refer to Fig. 6A and Figure 6B , various second layer openings (249, 229) may be formed through the second layer structure (232, 242, 265, 270, 72). A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be photolithographically patterned to form various openings therethrough. The pattern of the openings may be the same as the pattern of the various first layer openings (149, 129), which are the same as the sacrificial first layer opening filling portions (148, 128). Thus, the photoresist layer may be patterned using a photolithographic mask used to pattern the first layer openings (149, 129).

[0115] The pattern of openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270, 72) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form various second layer openings (249, 229). The various second layer openings (249, 229) can include second layer memory openings 249 and second layer support openings 229.

[0116] The second layer memory opening 249 is formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening filling portions 148. The second layer support opening 229 is formed directly on the top surface of a corresponding one of the sacrificial first layer support opening filling portions 128. In addition, each second layer support opening 229 may be formed to pass through a horizontal surface within the second stepped surfaces, which include the inter-face surfaces between the second alternating stacks (232, 242) and the second stepped dielectric material portion 265. Figure 6B The positions of the steps S in the first alternating stack (132, 142) and the second alternating stack (232, 242) are shown by dashed lines.

[0117] The second anisotropic etching process may include an etching step in which the material of the second alternating stack (232, 242) is etched during the material of the second stepped dielectric material portion 265. The chemistry of the etching steps may be alternating to optimize the etching of the material in the second alternating stack (232, 242) while providing an average etching rate comparable to the material of the second stepped dielectric material portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various second layer openings (249, 229) may be substantially vertical, or may be tapered. The bottom perimeter of each second layer opening (249, 229) may be laterally offset, and / or may be completely positioned within the perimeter of the top surface of the sacrificial first layer opening filling portion (148, 128) below. The photoresist layer may then be removed, for example, by ashing.

[0118] refer to Figure 7 , the sacrificial first layer filling material of the sacrificial first layer opening filling portion (148, 128) can be removed using an etching process that etches the sacrificial first layer filling material selective to the materials of the first insulating layer 132 and the second insulating layer 232, the first sacrificial material layer 142 and the second sacrificial material layer 242, the first insulating capping layer 170 and the second insulating capping layer 270, and the interlayer dielectric layer 180. Memory openings 49 (also referred to as interlayer memory openings 49) are formed in each combination of the second layer memory openings 249 and the volume from which the sacrificial first layer memory opening filling portion 148 is removed. Support openings 19 (also referred to as interlayer support openings 19) are formed in each combination of the second layer support openings 229 and the volume from which the sacrificial first layer support opening filling portion 128 is removed.

[0119] FIG. 8A to FIG. 8D Sequential cross-sectional views of the memory opening 49 during the formation of the memory opening filling structure are provided. The same structural changes occur in each of the memory opening 49 and the support opening 19.

[0120] refer to Fig. 8A , showing Figure 7 Memory opening 49 in the first exemplary device structure. Memory opening 49 extends through the first layer structure and the second layer structure, and into the upper portion of the memory side substrate 310. At this processing step, each support opening 19 can extend through the second stepped dielectric material portion 265 and optionally through the first stepped dielectric material portion 165, through a subset of the layers in the alternating stack {(132, 142), (232, 242)}, and extend downward to the memory side substrate 310. The bottom surface of each memory opening can be recessed to a depth in the range of 0nm to 30nm relative to the top surface of the memory side substrate 310, but larger recessed depths can also be used. Optionally, the sacrificial material layer (142, 242) can be partially recessed laterally to form a lateral recess (not shown), for example by isotropic etching.

[0121] refer to Figure 8B , an optional pedestal channel portion (e.g., epitaxial pedestal) 11 may be formed, for example, by selective epitaxy, at the bottom portion of each memory opening 49 and each support opening 19. The pedestal channel portion 11 may be a portion of a transistor channel that extends between a source region that will be subsequently formed in the memory-side substrate 310 and a drain region that will be subsequently formed in the upper portion of the memory opening 49. A memory cavity 49' exists in an unfilled portion of the memory opening 49 above the pedestal channel portion 11. In one embodiment, the pedestal channel portion 11 may include single crystal silicon. In one embodiment, the pedestal channel portion 11 may have a doping of a first conductivity type that is the same conductivity type as the memory-side substrate 310 that the pedestal channel portion contacts.

[0122] refer to Figure 8C A layer stack including a blocking dielectric layer 52 , a charge storage layer 54 , a tunneling dielectric layer 56 and an optional first semiconductor channel layer 601 may be sequentially deposited in the memory opening 49 .

[0123] The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is essentially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may be essentially composed of at least one metal element and oxygen, or may be essentially composed of at least one metal element, oxygen and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride).

[0124] Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source atomized chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in the range of 1nm to 20nm, but smaller and larger thicknesses can also be used. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 can include a plurality of dielectric metal oxide layers having different material compositions.

[0125] Alternatively or in addition, the blocking dielectric layer 52 may include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 may be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Alternatively, the blocking dielectric layer 52 may be omitted, and a backside blocking dielectric layer may be formed after a backside recess is formed on the surface of the memory film to be subsequently formed.

[0126] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer.

[0127] In another embodiment, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. Although the present disclosure is described using an embodiment in which the charge storage layer 54 is a single continuous layer, in other embodiments the charge storage layer 54 is replaced with a plurality of vertically spaced memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions).

[0128] The charge storage layer 54 may be formed as a single charge storage layer of uniform composition, or may include a stack of multiple charge storage layers. Multiple charge storage layers (if used) may include multiple spaced-apart floating gate material layers containing conductive materials (e.g., metals such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or semiconductor materials (e.g., polycrystalline or amorphous semiconductor materials including at least one element semiconductor element or at least one compound semiconductor material). Alternatively or in addition, the charge storage layer 54 may include an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 may include conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of charge storage layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0129] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used.

[0130] The optional first semiconductor channel layer 601 includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polycrystalline silicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The memory cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 601).

[0131] refer to Fig.8D , the optional first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 are anisotropically etched in sequence using at least one anisotropic etching process. Portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 located above the top surface of the second insulating cap layer 270 may be removed by at least one anisotropic etching process. In addition, horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 at the bottom of each memory cavity 49' may be removed to form openings in the remaining portions thereof. Each of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 may be etched by a corresponding anisotropic etching process using a corresponding etching chemistry, which may be the same or different for the various material layers.

[0132] Each remaining portion of the first semiconductor channel layer 601 may have a tubular configuration. The charge storage layer 54 may include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 may include a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the charge storage layer 54 may be a charge storage layer in which each portion of the adjacent sacrificial material layer (142, 242) constitutes a charge storage region.

[0133] The surface of the base channel portion 11 (or the surface of the memory side substrate 310 in the case where the base channel portion 11 is not used) can be physically exposed below the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54 and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed, so that the recessed semiconductor surface below the memory cavity 49' is vertically offset from the topmost surface of the base channel portion 11 (or the memory side substrate 310 in the case where the base channel portion 11 is not used) by a recessed distance. The tunneling dielectric layer 56 is positioned above the charge storage layer 54. The blocking dielectric layer 52, the charge storage layer 54 and the tunneling dielectric layer 56 in the memory opening 49 constitute a memory film 50, which includes a plurality of charge storage regions (including the charge storage layer 54), and the plurality of charge storage regions are insulated from surrounding materials by the blocking dielectric layer 52 and the tunneling dielectric layer 56. In one embodiment, the first semiconductor channel layer 601 , the tunneling dielectric layer 56 , the charge storage layer 54 , and the blocking dielectric layer 52 may have vertically coincident sidewalls.

[0134] refer to Fig. 8E , the second semiconductor channel layer 602 can be deposited directly on the semiconductor surface of the base channel portion 11 or on the memory side substrate 310 (if the base channel portion 11 is omitted), and directly deposited on the first semiconductor channel layer 601. The second semiconductor channel layer 602 includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 includes amorphous silicon or polycrystalline silicon. The second semiconductor channel layer 602 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer 602 can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The second semiconductor channel layer 602 can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0135] The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as semiconductor channel materials. In other words, the semiconductor channel material is a collection of all semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.

[0136] refer to Figure 8FIn the case where the memory cavity 49' in each memory opening is not completely filled with the second semiconductor channel layer 602, a dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organic silicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarization deposition process such as spin coating.

[0137] refer to Figure 8G , the horizontal portion of the dielectric core layer 62L may be removed, for example, by recess etching from above the top surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62. In addition, the horizontal portion of the second semiconductor channel layer 602 located above the top surface of the second insulating cap layer 270 may be removed by a planarization process that may use recess etching or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 may be positioned entirely within the memory opening 49 or entirely within the support opening 19.

[0138] Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can together form a vertical semiconductor channel 60, and when the vertical NAND device including the vertical semiconductor channel 60 is turned on, current can flow through the vertical semiconductor channel. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds a portion of the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54 and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge with a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0139] refer to Figure 8H , the top surface of each dielectric core 62 may be further recessed into each memory opening, for example by recess etching to a depth between the top surface of the second insulating capping layer 270 and the bottom surface of the second insulating capping layer 270. Drain regions 63 may be formed by depositing a doped semiconductor material in each recessed region above the dielectric core 62. The drain regions 63 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain regions 63 may be between 5.0×10 19 / cm 3 Up to 2.0×1021 / cm 3 The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from above the top surface of the second insulating cap layer 270, for example, by chemical mechanical planarization (CMP) or recess etching to form the drain region 63.

[0140] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunneling dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening filling structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure. Each memory film 50 may include a tunneling dielectric layer 56 laterally surrounding the vertical semiconductor channel 60, a vertical stack of a charge storage region (including the charge storage layer 54) laterally surrounding the tunneling dielectric layer 56, and an optional blocking dielectric layer 52.

[0141] refer to Fig.9A and Fig. 9B , shows a first exemplary structure after forming a memory opening filling structure 58 and a support pillar structure 20 in the memory opening 49 and the support opening 19, respectively. Figure 7 An instance of memory opening fill structure 58 is formed within each memory opening 49 of the structure. Figure 7 An example of forming a support pillar structure 20 within each support opening 19 of the structure. The support pillar structure 20 is formed in the support opening 19 during the formation of the memory opening filling structure 58. Each support pillar structure 20 can have the same set of components as the memory opening filling structure 58. Although the present disclosure is described using the configuration shown for the memory stack structure, the methods of various embodiments can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0142] refer to Fig. 10A and Fig. 10BA first contact level dielectric layer 280 may be formed over the second layer structure (232, 242, 270, 265, 72). The first contact level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be used.

[0143] A photoresist layer may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form elongated openings that extend along the first horizontal direction hd1 between the clusters of the memory opening filling structures 58. Backside trenches 79 may be formed by transferring the pattern in the photoresist layer through the first contact level dielectric layer 280, the second layer structures (232, 242, 270, 265, 72), and the first layer structures (132, 142, 170, 165) and into the memory side substrate 310. Portions of the first contact level dielectric layer 280, the second layer structures (232, 242, 270, 265, 72), the first layer structures (132, 142, 170, 165), and the memory side substrate 310 below the openings in the photoresist layer may be removed to form the backside trenches 79. In one embodiment, the backside trenches 79 may be formed between the clusters of the memory stack structures 55. The clusters of memory stack structures 55 may be laterally spaced apart along the second horizontal direction hd2 by the backside trenches 79 .

[0144] refer to Fig.11 and Fig. 12A , the sacrificial material layer (142, 242) can be removed selectively with respect to the insulating layer (132, 232), the first insulating capping layer 170 and the second insulating capping layer 270, the first contact level dielectric layer 280, and the source contact layer 114, the dielectric semiconductor oxide plate 122, and the annular dielectric semiconductor oxide spacer 124. For example, an etchant that selectively etches the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the first insulating capping layer 170 and the second insulating capping layer 270, the stepped dielectric material portion (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242) may include silicon nitride, and the insulating layer (132, 232), the first insulating capping layer 170 and the second insulating capping layer 270, the stepped dielectric material portion (165, 265) and the outermost layer of the memory film 50 may include silicon oxide material.

[0145] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced in the vapor phase into the backside trench 79. For example, if the sacrificial material layer (142, 242) includes silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0146] A backside recess (143, 243) is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recess (143, 243) includes a first backside recess 143 formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess 243 formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses (143, 243) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) can be greater than the height of the corresponding backside recess (143, 243). Multiple backside recesses (143, 243) can be formed in the volume from which the material of the sacrificial material layer (142, 242) is removed. Each of the backside recesses (143, 243) may extend substantially parallel to the top surface of the memory side substrate 310. The backside recesses (143, 243) may be vertically defined by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) may have a uniform height throughout.

[0147] The optional pedestal channel portion 11 and physically exposed surface portions of the memory side substrate 310 may be converted into dielectric material portions by thermal conversion and / or plasma conversion of semiconductor material into dielectric material. For example, thermal conversion and / or plasma conversion may be used to convert a surface portion of each pedestal channel portion 11 into a tubular dielectric spacer 316 and to convert each physically exposed surface portion of the memory side substrate 310 into a planar dielectric portion 616.

[0148] refer to Fig. 12B , a backside blocking dielectric layer 44 may be optionally formed. The backside blocking dielectric layer 44, if present, comprises a dielectric material that serves as a control gate dielectric for subsequently forming a control gate in the backside recess (143, 243). In the case where a blocking dielectric layer 52 is present within each memory opening, the backside blocking dielectric layer 44 is optional. In the case where the blocking dielectric layer 52 is omitted, the backside blocking dielectric layer 44 is present.

[0149] The backside blocking dielectric layer 44 may be formed in the backside recess (143, 243) and on the sidewalls of the backside trench 79. The backside blocking dielectric layer 44 may be formed directly on the horizontal surface of the insulating layer (132, 232) and on the sidewalls of the memory stack structure 55 within the backside recess (143, 243). If the backside blocking dielectric layer 44 is formed, it is optional to form the tubular dielectric spacer 316 and the planar dielectric portion 616 before forming the backside blocking dielectric layer 44. In one embodiment, the backside blocking dielectric layer 44 may be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer 44 may be substantially composed of aluminum oxide. The thickness of the backside blocking dielectric layer 44 may be in the range of 1nm to 15nm, such as 2nm to 6nm, but smaller and larger thicknesses may also be used.

[0150] The dielectric material of the backside blocking dielectric layer 44 may be a dielectric metal oxide (such as aluminum oxide), a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element and / or at least one lanthanide element. Alternatively or additionally, the backside blocking dielectric layer 44 may include a silicon oxide layer. The backside blocking dielectric layer 44 may be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer 44 is formed on the sidewalls of the backside trench 79, the horizontal surface and sidewalls of the insulating layer (132, 232), the portion of the sidewall surface of the memory stack structure 55 that is physically exposed to the backside recess (143, 243), and the top surface of the planar dielectric portion. A backside cavity 79' exists in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44.

[0151] refer to Fig. 12C , a metal barrier layer 46A may be deposited in the backside recess (143, 243). The metal barrier layer 46A comprises a conductive metal material, which may serve as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer 46A may comprise a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer 46A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer 46A may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller and greater thicknesses may also be used. In one embodiment, the metal barrier layer 46A may consist essentially of a conductive metal nitride such as TiN.

[0152] refer to Fig.12D, the metal filling material is deposited in a plurality of backside recesses (143, 243), on the sidewalls of the at least one backside trench 79 and above the top surface of the first contact level dielectric layer 280 to form a metal filling material layer 46B. The metal filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating or a combination thereof. In one embodiment, the metal filling material layer 46B can be substantially composed of at least one elemental metal. The at least one elemental metal of the metal filling material layer 46B can be selected from, for example, tungsten, cobalt, ruthenium, titanium and tantalum. In one embodiment, the metal filling material layer 46B can be substantially composed of a single elemental metal. In one embodiment, the metal filling material layer 46B can be deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal filling material layer 46B can be a tungsten layer including residual fluorine atoms as impurities. The metal filling material layer 46B is separated from the insulating layer ( 132 , 232 ) and the memory stack structure 55 by the metal barrier layer 46A, which is a metal barrier layer that blocks fluorine atoms from diffusing therethrough.

[0153] A plurality of conductive layers (146, 246) may be formed in the plurality of backside recesses (143, 243), and a continuous metal material layer 46L may be formed on the sidewalls of each backside trench 79 and over the first contact level dielectric layer 280. Each conductive layer (146, 246) includes a portion of a metal barrier layer 46A and a portion of a metal filler material layer 46B located between a pair of vertically adjacent dielectric material layers such as a pair of insulating layers (132, 232). The continuous metal material layer 46L includes a continuous portion of the metal barrier layer 46A and a continuous portion of the metal filler material layer 46B located in the backside trench 79 or over the first contact level dielectric layer 280.

[0154] Each sacrificial material layer (142, 242) can be replaced with a conductive layer (146, 246). A backside cavity 79' exists in a portion of each backside trench 79 that is not filled with a backside blocking dielectric layer 44 and a continuous metal material layer 46L. A tubular dielectric spacer 316 laterally surrounds the base channel portion 11. When the conductive layer (146, 246) is formed, the bottommost conductive layer (146, 246) laterally surrounds each tubular dielectric spacer 316.

[0155] refer to Fig.12E and Fig.13, the deposited metal material of the continuous conductive material layer 46L is etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the backside recess (143, 243) constitutes a conductive layer (146, 246). Each conductive layer (146, 246) can be a conductive line structure. Therefore, the sacrificial material layer (242, 242) is replaced with a conductive layer (146, 246).

[0156] Each conductive layer (146, 246) can be used as a combination of multiple control gate electrodes located at the same level and a word line electrically interconnected (i.e., electrically connected) with the multiple control gate electrodes located at the same level. The multiple control gate electrodes within each conductive layer (146, 246) are control gate electrodes for vertical memory devices including the memory stack structure 55. In other words, each conductive layer (146, 246) can be a word line used as a common control gate electrode for multiple vertical memory devices.

[0157] In one embodiment, the removal of the continuous conductive material layer 46L may be selective to the material of the backside blocking dielectric layer 44. In this case, a horizontal portion of the backside blocking dielectric layer 44 may be present at the bottom of each backside trench 79. In another embodiment, the removal of the continuous conductive material layer 46L may not be selective to the material of the backside blocking dielectric layer 44, or the backside blocking dielectric layer 44 may not be used. The planar dielectric portion 616 may be removed during the removal of the continuous conductive material layer 46L. A backside cavity 79' is present within each backside trench 79.

[0158] Each conductive layer (146, 246) can be a conductive sheet including openings therein. A first subset of the openings through each conductive layer (146, 246) can be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) can be filled with a support pillar structure 20. Due to the first stepped surface and the second stepped surface, each conductive layer (146, 246) can have a smaller area than any underlying conductive layer (146, 246). Due to the first stepped surface and the second stepped surface, each conductive layer (146, 246) can have a larger area than any overlying conductive layer (146, 246).

[0159] In some embodiments, a drain select level isolation structure 72 may be provided at the topmost level of the second conductive layer 246. A subset of the second conductive layer 246 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) positioned below the drain select gate electrode may be used as a combination of a control gate and a word line positioned at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including the memory stack structure 55.

[0160] Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The memory level assembly is positioned above the memory side substrate 310. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 that vertically extends through at least one alternating stack (132, 146, 232, 246).

[0161] refer to FIG. 14A to FIG. 14C , an insulating material layer can be formed in the backside trench 79 and above the first contact level dielectric layer 280 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organic silicate glass, or a combination thereof. In one embodiment, the insulating material layer may include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in the range of 1.5 nm to 60 nm, but smaller and larger thicknesses can also be used.

[0162] If there is a backside blocking dielectric layer 44, the insulating material layer can be formed directly on the surface of the backside blocking dielectric layer 44 and directly on the sidewalls of the conductive layer (146, 246). If the backside blocking dielectric layer 44 is not used, the insulating material layer can be formed directly on the sidewalls of the insulating layer (132, 232) and directly on the sidewalls of the conductive layer (146, 246).

[0163] Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the first contact level dielectric layer 280 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity 79' exists within a volume surrounded by each insulating spacer 74. The top surface of the memory-side substrate 310 may be physically exposed at the bottom of each backside trench 79.

[0164] Source regions 61 may be formed at a surface portion of the memory side substrate 310 below each backside cavity 79′ by implanting electrical dopants into the physically exposed surface portion of the memory side substrate 310. Each source region 61 is formed in a surface portion of the memory side substrate 310 that is located below a corresponding opening through the insulating spacer 74. Due to the spreading of the implanted dopant atoms during the implantation process and the lateral diffusion of the implanted dopant atoms during the subsequent activation annealing process, each source region 61 may have a lateral extent that is greater than the lateral extent of the opening through the insulating spacer 74.

[0165] The upper portion of the memory side substrate 310 extending between the source region 61 and the plurality of base channel portions 11 constitutes a horizontal semiconductor channel 59 for a plurality of field effect transistors. The horizontal semiconductor channel 59 is connected to a plurality of vertical semiconductor channels 60 through the corresponding base channel portions 11. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of base channel portions 11. The bottommost conductive layer (146, 246) provided when forming the conductive layer (146, 246) within the alternating stack {(132, 146), (232, 246)} may include a selection gate electrode of a field effect transistor. Each source region 61 is formed in the upper portion of the memory side substrate 310. The semiconductor channel (59, 11, 60) extends between each source region 61 and a corresponding set of drain regions 63. The semiconductor channel (59, 11, 60) includes the vertical semiconductor channel 60 of the memory stack structure 55.

[0166] A backside contact via structure 76 may be formed in each backside cavity 79'. Each contact via structure 76 may fill a corresponding backside cavity 79'. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of the backside trench 79 (i.e., the backside cavity 79'). For example, the at least one conductive material may include a conductive liner and a conductive filling material portion. The conductive liner may include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The conductive filling material portion may include a metal or a metal alloy. For example, the conductive filling material portion may include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

[0167] The at least one conductive material may be planarized using a first contact level dielectric layer 280 overlying the alternating stack {(132, 146), (232, 246)} as a stop layer. If a chemical mechanical planarization (CMP) process is used, the first contact level dielectric layer 280 may be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes a backside contact via structure 76. The backside contact via structure 76 extends through the alternating stack {(132, 146), (232, 246)} and contacts the top surface of the source region 61.

[0168] refer to Fig.15A and Fig. 15B A second contact level dielectric layer 282 may be formed over the first contact level dielectric layer 280. The second contact level dielectric layer 282 includes a dielectric material such as silicon oxide and may have a thickness in a range of 100 nm to 600 nm, although lesser and greater thicknesses may also be used.

[0169] A photoresist layer may be applied over the second contact level dielectric layer 282 and may be photolithographically patterned to form various contact via openings. For example, an opening for forming a drain contact via structure may be formed in the memory array region 100, and an opening for forming a staircase area contact via structure may be formed in the staircase region 200. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the second and first contact level dielectric layers (282, 280) and the dielectric material portion below. The drain region 63 and the conductive layer (146, 246) may be used as an etching stop structure. A drain contact via cavity may be formed over each drain region 63, and a staircase area contact via cavity may be formed over each conductive layer (146, 246) at a stepped surface below the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265. The photoresist layer may then be removed, for example, by ashing.

[0170] The drain contact via structure 88 is formed in the drain contact via cavity and on the top surface of a corresponding one of the drain regions 63. The staircase area contact via structure 86 is formed in the staircase area contact via cavity and on the top surface of a corresponding one of the conductive layers (146, 246). The staircase area contact via structure 86 may include drain selection level contact via structures that contact a subset of the second conductive layer 246 used as a drain selection level gate electrode. In addition, the staircase area contact via structure 86 may include word line contact via structures that contact the conductive layer (146, 246) below the drain selection level gate electrode and serve as a word line of the memory stack structure 55.

[0171] refer to Fig.16 , a bitline level dielectric layer 284 may be formed over the contact level dielectric layer (280, 282), and a bitline level metal interconnect structure (98, 96) may be formed in the bitline level dielectric layer 284. The bitline level metal interconnect structure (98, 96) includes a bitline 98 electrically connected to a corresponding subset of drain regions 63 through a corresponding subset of drain contact via structures 88. The bitline level metal interconnect structure (98, 96) includes an interconnect line structure 96 electrically connected to at least one of the staircase region contact via structure 86 or other via structures.

[0172] The memory side interconnect level dielectric layer 390 may be formed above the bit line level dielectric layer 284 and the bit line level metal interconnect structure (98, 96). Various memory side metal interconnect structures 370 may be formed in the memory side interconnect level dielectric layer 390 to provide electrical connections to the bit line 98 and the interconnect line structure 96. The memory side metal interconnect structure 370 may include an interconnect level metal line structure 374 and an interconnect level metal via structure 376. The memory side bonding pad 378 may be formed in or on the uppermost layer of the memory side interconnect level dielectric layer 390. The memory side bonding pad 378 may include a copper bonding pad for copper to copper bonding or an under bump metallurgy (UBM) stack pad that may be bonded to other UBM stack pads by solder balls. The first exemplary structure constitutes a memory die 1000 that includes a three-dimensional memory array and a memory side bonding pad 378 that may include a copper bonding pad or a UBM stack pad. The memory side bond pads 378 are die-to-die bond pads that provide bonding of the memory die 1000 to another die.

[0173] refer to Fig.17, showing a logic die 900 that is subsequently incorporated into a first exemplary structure. The logic die 900 includes peripheral circuits 940 that include various semiconductor devices for operating the three-dimensional memory array in the memory die 1000. Specifically, the peripheral circuits may include word line drivers that drive the conductive layers (146, 246) within the memory die 1000; bit line drivers that drive the bit lines 98 in the memory die 1000; word line decoder circuits that decode the addresses of the conductive layers (146, 246); bit line decoder circuits that decode the addresses of the bit lines 98; sense amplifier circuits that sense the states of memory elements within the memory stack structure 55 in the memory die 1000; power supply / distribution circuits that provide power to the memory die 1000; data buffers and / or latches; and / or any other semiconductor circuits that may be used to operate the array of memory stack structures 55 in the memory die 1000. The logic die 900 may include a logic die substrate 910, which may be a semiconductor substrate. The logic die substrate 910 may include a semiconductor wafer or a semiconductor material layer. The logic die substrate 910 includes at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0174] A shallow trench isolation structure 920 may be formed in an upper portion of the logic die substrate 910 to provide electrical isolation between semiconductor devices of the sense amplifier circuit. Various semiconductor devices may include a field effect transistor including a corresponding transistor active region 942 (i.e., source region and drain region), a channel 946, and a gate structure 950. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 950 may include, for example, a gate dielectric 952, a gate electrode 954, a dielectric gate spacer 956, and a gate cap dielectric 958. For example, a semiconductor device may include a word line driver for electrically biasing a word line of a memory die 1000, the word line driver including a conductive layer (146, 246).

[0175] Dielectric material layers are formed over the semiconductor device, which are referred to herein as logic side interconnect level dielectric layers 990. Optionally, dielectric liners 962 (such as silicon nitride liners) may be formed to apply mechanical stress to the various field effect transistors and / or to prevent hydrogen or impurities from diffusing from the logic side interconnect level dielectric layer 990 into the semiconductor device. A logic side metal interconnect structure 970 is included within the logic side interconnect level dielectric layer 990. The logic side metal interconnect structure 970 may include various device contact via structures 972 (e.g., source and drain electrodes contacting the respective source and drain nodes of the device or gate electrode contacts), interconnect level metal line structures 974, interconnect level metal via structures 976, and logic side bonding pads 978 that may include copper bonding pads or UBM stack pads. The logic side bonding pads 978 are die-to-die bonding pads that provide bonding of the logic die 900 to the memory die 1000.

[0176] In one embodiment, one of the levels of the logic side metal interconnect structure 970 may include at least one metal material for forming an external bonding pad. The at least one metal material may include, for example, aluminum or an under-bump metallurgy stack. The at least one metal material for forming an external bonding pad may be patterned into an intermediate metal interconnect structure 975 and an external bonding pad 985, which are used as components of the logic side metal interconnect structure 970, and these external bonding pads are subsequently used to bond the bonding wires thereon. In one embodiment, the levels of the interconnect level metal wire structure 974 may be replaced with a combination of the intermediate metal interconnect structure 975 and the external bonding pad 985.

[0177] In one embodiment, the at least one metal material may include aluminum and / or consist essentially of aluminum. In another embodiment, the at least one metal material may include a UBM layer stack and an optional copper layer located at the top of the UBM stack, and / or consist essentially of a UBM layer stack and an optional copper layer located at the top of the UBM stack. The UBM layer stack may include at least two metal barrier material layers, such as two, three or four metal barrier material layers. The UBM layer stack may include a material on which a solder material portion may be subsequently formed. In the case where the solder material portion subsequently used includes gold, the UBM layer may include a stack of titanium-tungsten layers and gold layers, or a stack of titanium layers and gold layers. In the case where the solder material portion subsequently used includes a lead-tin alloy or a tin-silver-copper alloy, the UBM layer stack may include a stack of titanium layers and copper layers; titanium-tungsten layers and copper layers; aluminum layers, nickel-vanadium layers and copper layers; or chromium layers, chromium-copper layers and copper layers.

[0178] In one embodiment, a logic side etch stop dielectric layer 964 may be formed as a component of the logic side interconnect level dielectric layer 990 before forming the intermediate metal interconnect structure 975 and the external bonding pad 985 within the logic side interconnect level dielectric layer 990. The logic side etch stop dielectric layer 964 includes a dielectric material different from a main component material of the logic side interconnect level dielectric layer 990 (such as silicon oxide or organic silicate glass) and provides higher etching resistance than the main component material of the logic side interconnect level dielectric layer 990. As used herein, the main component material refers to a group of the least amount of materials that collectively provide more than 50% of the total volume of the logic side interconnect level dielectric layer 990. In an exemplary example, if 45% of the total volume of the logic side interconnect level dielectric layer 990 is filled with organic silicate glass, 35% of the total volume of the logic side interconnect level dielectric layer 990 is filled with doped silicate glass, and if 15% of the total volume of the logic side interconnect level dielectric layer 990 is filled with undoped silicate glass, the main component materials include organic silicate glass and doped silicate glass. In one embodiment, the logic side etch stop dielectric layer 964 may include a dielectric metal oxide (such as aluminum oxide) or silicon nitride. The thickness of the logic side etch stop dielectric layer 964 can be in the range of 5nm to 100nm, but smaller and larger thicknesses can also be used. The logic side etch stop dielectric layer 964 can contact the aluminum portion of the external bonding pad 985 or the bottom surface of the UBM layer stack.

[0179] refer to Fig.18A , the memory die 1000 and the logic die 900 are positioned so that the logic side bonding structures 978 of the logic die 900 face the memory side bonding pads 378 of the memory die 1000. In one embodiment, the memory die 1000 and the logic die 900 can be designed so that the pattern of the logic side bonding pads 978 of the logic die 900 mirrors the pattern of the memory side bonding pads 378 of the memory die 1000. The memory die 1000 and the logic die 900 can be bonded to each other by metal-to-metal bonding, such as copper-to-copper bonding.

[0180] In the case of metal-to-metal bonding, the face-to-face of the memory side bonding pads 378 of the memory die 1000 and the logic side bonding structure 978 of the logic die 900 can be in direct contact with each other and can be subjected to elevated temperatures to cause material diffusion across the interface between the adjacent die-to-die bonding pad pairs (378, 978). The mutual diffusion of metallic materials can cause bonding between each adjacent die-to-die bonding pad pair (378, 978). In addition, the logic side interconnect level dielectric layer 990 and the memory side interconnect level dielectric layer 390 can include dielectric materials (such as silicate glass materials) that are capable of bonding to each other. In this case, the physically exposed surfaces of the logic side interconnect level dielectric layer 990 and the memory side interconnect level dielectric layer 390 can be in direct contact with each other and can be subjected to thermal annealing to provide additional bonding.

[0181] Each of the memory die 1000 and the logic die 900 is a semiconductor die. The side of each semiconductor die bonded to another semiconductor die is referred to herein as the near side, and the opposite side of each semiconductor die is referred to herein as the far side. In other words, the reference for determining the near side and the far side of each semiconductor die is the interface between the two semiconductor dies.

[0182] refer to Fig.18B , the logic side substrate 910 can be thinned from the back side, for example by grinding, to provide a thinned logic side substrate 902, which is a semiconductor substrate. The thinned logic side substrate 902 can have a thickness in the range of 1 μm to 100 μm, such as 3 μm to 30 μm, but smaller and larger thicknesses can also be used.

[0183] refer to Fig.18C, a photoresist layer 977 may be applied over the back side of the thinned logic side substrate 902 and photolithographically patterned to form at least one opening therein. Each of the at least one opening in the patterned photoresist layer 977 may cover a corresponding one of the external bonding pads 985. In one embodiment, each opening in the patterned photoresist layer 977 may have an area larger than the total area of ​​at least one underlying external bonding pad 985. An anisotropic etching process may be used to form the recessed region RR. The anisotropic etching process sequentially etches the material of the thinned logic side substrate 902 and the distal portion of the logic side interconnect level dielectric layer 990. The logic side etch stop dielectric layer 964 may be used to prevent over-etching through the level of the external bonding pad 985. The terminal step of the anisotropic etching process may include an etching step that etches a physically exposed portion of the logic side etch stop dielectric layer 964 that is selective to the material of the external bonding pad 985. Each recess region RR may extend vertically from the distal planar surface of the logic die 900, through the thinned logic side substrate 902, through the proximal planar surface of the thinned logic side substrate 902, through the distal portion of the logic side interconnect level dielectric layer 990, through the logic side etch stop dielectric layer 964, and down to the distal planar surface of each external bonding pad 985. A horizontal surface of one of the logic side interconnect level dielectric layers 990 may be physically exposed at the bottom of each recess region RR.

[0184] An external bonding pad 985 is disposed at the bottom of each recessed region RR. Each external bonding pad 985 may be located in one of the physically exposed portions of the logic side interconnect level dielectric layer 990. The external bonding pad 985 may be initially formed within the logic side interconnect level dielectric layer 990 during the formation of the logic side interconnect level dielectric layer 990, and may be physically exposed after the bonding of the memory die 1000 and the logic die 900 and the anisotropic etching process for forming the recessed region RR. The flat horizontal surface of each external bonding pad 985 may be physically exposed after forming the recessed region RR. The patterned photoresist layer 977 may then be removed, for example, by ashing.

[0185] refer to Fig.18D and Fig.18E, solder balls 995 may be attached to each external bonding pad 985. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed regions RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 985 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance in the range of 1 micron to 150 microns (such as 3 microns to 50 microns) relative to the far side flat surface of the thinned logic side substrate 902, but smaller and larger recessed distances may also be used. In one embodiment, each combination of external bonding pads 985 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the memory side substrate 310 and a second horizontal plane HP2 including the near side horizontal surface of the thinned logic side substrate 902. A bonding wire 997 may be bonded to each solder ball 995 .

[0186] refer to Fig.18F , showing Fig.18D and Fig.18E In this case, it is possible to Fig.17 The processing step of forming interconnect level metal line structure 974 in logic side interconnect level dielectric layer 990 replaces intermediate metal interconnect structure 975 and external bonding pad 985. In this case, a subset of interconnect level metal line structure 974 is formed to replace external bonding pad 985. Then, performing 18A to 18C A subset of the interconnect level metal line structures 974 is physically exposed at the bottom of each recessed region RR. A metal bond pad material such as aluminum or a UBM layer stack may be deposited by an anisotropic deposition process or an isotropic deposition process and may be patterned by forming discrete photoresist material portions to cover the physically exposed portions of the interconnect level metal line structures 974 at the bottom of the recessed regions, and by a subsequent etching process to remove the unmasked portions of the metal bond pad material. The remaining portions of the metal bond pad material below the discrete photoresist material portions constitute the external bond pads 985.

[0187] An external bonding pad 985 is disposed at the bottom of each recessed region RR. Each external bonding pad 985 may be located on one of the physically exposed portions of the memory-side interconnect level dielectric layer 390. The external bonding pad 985 may be formed after bonding of the memory die 1000 and the logic die 900 and after the anisotropic etching process that forms the recessed region RR. The discrete photoresist material portions may then be removed, for example, by ashing.

[0188] Solder balls 995 may be attached to each external bonding pad 985. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed regions RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 985 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance (such as 3 microns to 50 microns) in the range of 2 microns to 150 microns relative to the far side flat surface of the thinned logic side substrate 902, but smaller and larger recess distances may also be used. In one embodiment, each combination of external bonding pads 985 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the memory side substrate 310 and a second horizontal plane HP2 including the near side horizontal surface of the thinned logic side substrate 902. A bonding wire 997 may be bonded to each solder ball 995.

[0189] refer to Figure 18G , showing Fig.18D and Fig.18E A second alternative configuration of the first exemplary structure of . A via cavity may be formed through the logic side interconnect level dielectric layer 990 so that the back side of the corresponding logic side bonding pad 978 is physically exposed at the bottom of each via cavity. At least one bonding pad material (such as an under bump metallurgy (UBM) layer stack) may be deposited in the via cavity and may be subsequently patterned to form an external bonding pad 1085. Solder balls and bonding wires may then be attached to each external bonding pad 1085. In this embodiment, the external bonding pad 1085 is formed directly on the logic side bonding pad (e.g., copper pad) 978.

[0190] In an alternative configuration of any of the above embodiments, the memory die may optionally include a silicon-on-insulator type substrate, such as substrate 301 and a semiconductor material layer 309 electrically isolated from substrate 301 by insulating layer 308. Semiconductor material layer 309 covers the top surface of substrate 301, rather than memory side substrate 310, such as Figure 18G In this alternative configuration, the bottom end of the vertical semiconductor channel can be electrically connected to the semiconductor material layer 309 .

[0191] refer to Fig.19A , showing a second configuration of the first exemplary structure, which can be obtained by omitting the terminal step of the anisotropic etching process. Fig.18C The first configuration of the first exemplary structure shown is obtained. In this case, the top surface of the logic side etch stop dielectric layer 964 can be physically exposed at the bottom of each of the recessed regions RR. The photoresist layer 977 can then be removed, for example, by ashing.

[0192] refer to Fig.19B , a conformal dielectric material layer 992 may be deposited on the distal planar surface and sidewalls of the thinned logic side substrate 902, the sidewalls of the logic side interconnect level dielectric layer 990, and over the logic side etch stop dielectric layer 964. For example, the conformal dielectric material layer 992 may include silicon oxide and / or silicon nitride, which may provide passivation of the logic die 900 from the distal side. Another photoresist layer 979 may be applied over the conformal dielectric material layer 992 and may be photolithographically patterned to form openings over the areas of the external bonding pads 985. An etching process may be performed to etch through the conformal dielectric material layer 992 and the physically exposed areas of the logic side etch stop dielectric layer 964. The flat distal planar surface of the external bonding pads 985 is physically exposed under each opening in the photoresist layer 979. The photoresist layer 979 may then be removed, for example, by ashing.

[0193] refer to Fig.19C , solder balls 995 may be attached to each external bonding pad 985. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed regions RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 985 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance in the range of 1 micron to 150 microns (such as 3 microns to 50 microns) relative to the far side flat surface of the thinned logic side substrate 902, but smaller and larger recessed distances may also be used. In one embodiment, each combination of external bonding pads 985 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the memory side substrate 310 and a second horizontal plane HP2 including the near side horizontal surface of the thinned logic side substrate 902. A bonding wire 997 may be bonded to each solder ball 995 .

[0194] refer to Fig. 20A , shows the configuration of the first exemplary structure after forming the memory die 1000. Fig.16The memory die 1000 can be modified so that one of the levels of the memory-side metal interconnect structure 370 includes at least one metal material for forming an external bonding pad. The at least one metal material may include, for example, aluminum or an under-bump metallurgy stack, which may be any of the above-mentioned under-bump metallurgy stacks. The at least one metal material for forming the external bonding pad may be patterned into an intermediate metal interconnect structure 375 and an external bonding pad 385, which are used as components of the memory-side metal interconnect structure 370, and these external bonding pads are subsequently used to bond the bonding wires thereon. In one embodiment, the levels of the interconnect level metal wire structure 374 may be replaced with a combination of the intermediate metal interconnect structure 375 and the external bonding pad 385.

[0195] In one embodiment, after forming the intermediate metal interconnect structure 375 and the external bonding pad 385 within the memory side interconnect level dielectric layer 390, the memory side etch stop dielectric layer 364 can be formed as a component of the logic side interconnect level dielectric layer 990. The memory side etch stop dielectric layer 364 includes a dielectric material different from the main component material of the memory side interconnect level dielectric layer 390 (such as silicon oxide or organic silicate glass) and provides higher corrosion resistance than the main component material of the memory side interconnect level dielectric layer 390. In one embodiment, the memory side etch stop dielectric layer 364 may include a dielectric metal oxide (such as aluminum oxide) or silicon nitride. The thickness of the memory side etch stop dielectric layer 364 can be in the range of 5nm to 100nm, but smaller and larger thicknesses can also be used. The memory side etch stop dielectric layer 364 can contact the aluminum portion of the external bonding pad 385 or the bottom surface of the UBM layer stack. The external bonding pads 385 are located farther from the memory side substrate 310 than the memory side bonding pads 378 are located from the memory side substrate 310 .

[0196] refer to Fig. 20B , showing that the subsequent Fig. 20A The memory die 1000 is bonded to the logic die 900. The logic die 900 includes peripheral circuits such as Fig.17 The logic die 900 may include a logic die substrate 910, which may be a semiconductor substrate. The logic die substrate 910 may include a semiconductor wafer or a semiconductor material layer. Fig. 20B The logic die 900 can be replaced by forming an interconnect level metal line structure 974 instead of the combination of the intermediate metal interconnect structure 975 and the external bonding pad 385. Fig.17 The logic die 900 is obtained. Fig. 20A The memory die 1000 and Fig. 20BThe logic die 900 of FIG. 1 may be designed such that the pattern of the logic side bonding pads 978 of the logic die 900 mirrors the pattern of the memory side bonding pads 378 of the memory die 1000 .

[0197] refer to Fig. 20C , Fig. 20A The memory die 1000 and Fig. 20B The logic dies 900 may be bonded to each other by metal-to-metal bonding, such as copper-to-copper bonding.

[0198] refer to Fig.20D , the logic side substrate 910 can be thinned from the back side, for example by grinding, to provide a thinned logic side substrate 902, which is a semiconductor substrate. The thinned logic side substrate 902 can have a thickness in the range of 1 μm to 100 μm, such as 3 μm to 30 μm, but smaller and larger thicknesses can also be used.

[0199] refer to Fig.20E , a photoresist layer 977 may be applied over the back side of the thinned logic side substrate 902 and photolithographically patterned to form at least one opening therein. Each of the at least one opening in the patterned photoresist layer 977 may cover a corresponding one of the external bonding pads 385. In one embodiment, each opening in the patterned photoresist layer 977 may have an area larger than the total area of ​​at least one underlying external bonding pad 385. An anisotropic etching process may be used to form the recessed region RR. The anisotropic etching process sequentially etches the material of the thinned logic side substrate 902, the logic side interconnect level dielectric layer 990, the proximal portion of the memory side interconnect level dielectric layer 390, and the physically exposed portion of the memory side etch stop dielectric layer 364. The memory side etch stop dielectric layer 364 may be used to prevent over-etching through the level of the external bonding pads 385. The terminal step of the anisotropic etching process may include an etching step that etches physically exposed portions of the memory-side etch stop dielectric layer 364 that are selective to the material of the external bonding pads 385. Each recessed region RR extends vertically from the far planar surface of the logic die 900, through the thinned logic-side substrate 902, through the near planar surface of the thinned logic-side substrate 902, through the entire thickness of the logic-side interconnect level dielectric layer 990, through the interface between the logic die 900 and the memory die 1000, through the near portion of the memory-side interconnect level dielectric layer 390, through the memory-side etch stop dielectric layer 364, and down to the near planar surface of each external bonding pad 385, below the corresponding opening in the patterned photoresist layer 977. The horizontal surface of one of the logic-side interconnect level dielectric layers 990 may be physically exposed at the bottom of each recessed region RR.

[0200] An external bonding pad 385 is disposed at the bottom of each recessed region RR. Each external bonding pad 385 may be located in one of the physically exposed ones in the memory-side interconnection level dielectric layer 390. The external bonding pad 385 may be initially formed in the memory-side interconnection level dielectric layer 390 during the formation of the memory-side interconnection level dielectric layer 390, and may be physically exposed after the bonding of the memory die 1000 and the logic die 900 and the anisotropic etching process for forming the recessed region RR. The flat horizontal surface of each external bonding pad 385 may be physically exposed after forming the recessed region RR. The patterned photoresist layer 977 may then be removed, for example, by ashing.

[0201] refer to Fig.20F and Figure 20G , solder balls 995 may be attached to each external bonding pad 385. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed regions RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 385 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance in the range of 2 microns to 150 microns (such as 3 microns to 50 microns) relative to the far side flat surface of the thinned logic side substrate 902, but smaller and larger recess distances may also be used. In one embodiment, each combination of external bonding pads 385 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the memory side substrate 310 and a second horizontal plane HP2 including the near side horizontal surface of the thinned logic side substrate 902. A bonding wire 997 may be bonded to each solder ball 995 .

[0202] refer to Fig. 20H , showing a fourth configuration of the first exemplary structure. In this case, Fig. 20A The processing step of forming the interconnect level metal line structure 374 in the memory side interconnect level dielectric layer 390 replaces the intermediate metal interconnect structure 375 and the external bonding pad 385. In this case, a subset of the interconnect level metal line structure 974 is formed in the fourth configuration of the first exemplary structure, replacing Fig. 20A The external bonding pad 385 is then FIG. 20C to FIG. 20EA subset of interconnect level metal line structures 374 is physically exposed at the bottom of each recessed region RR. Metal bond pad material such as aluminum or a UBM layer stack may be deposited by an anisotropic deposition process or an isotropic deposition process and may be patterned by forming discrete photoresist material portions to cover the physically exposed portions of interconnect level metal line structures 974 at the bottom of the recessed regions, and by a subsequent etching process to remove the unmasked portions of the metal bond pad material. The remaining portions of the metal bond pad material below the discrete photoresist material portions constitute external bond pads 385.

[0203] An external bonding pad 385 is disposed at the bottom of each recessed region RR. Each external bonding pad 385 may be located on one of the physically exposed portions of the logic-side interconnect level dielectric layer 990. The external bonding pad 385 may be formed after bonding of the memory die 1000 and the logic die 900 and after an anisotropic etching process to form the recessed region RR. The discrete photoresist material portions may then be removed, for example, by ashing.

[0204] Solder balls 995 may be attached to each external bonding pad 385. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed regions RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 385 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance (such as 3 microns to 50 microns) in the range of 1 micron to 150 microns relative to the far side flat surface of the thinned logic side substrate 902, but smaller and larger recess distances may also be used. In one embodiment, each combination of external bonding pads 385 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the memory side substrate 310 and a second horizontal plane HP2 including the near side horizontal surface of the thinned logic side substrate 902. A bonding wire 997 may be bonded to each solder ball 995.

[0205] refer to Fig.21A The configuration of the first exemplary structure can be replaced from the memory die 1000 by forming a combination of an intermediate metal interconnect structure 375 and an external bonding pad 385 instead of the level of the interconnect level metal line structure 374. Fig.16The first exemplary structure is obtained. In this case, one of the levels of the memory-side metal interconnect structure 370 may include at least one metal material for forming an external bonding pad. The at least one metal material may include, for example, aluminum or an under-bump metallurgy (UBM) layer stack. The at least one metal material for forming the external bonding pad may be patterned into an intermediate metal interconnect structure 375 and an external bonding pad 385, which are used as components of the memory-side metal interconnect structure 370, and these external bonding pads are subsequently used to bond the bonding wires thereon. Therefore, the levels of the interconnect level metal wire structure 374 can be replaced by a combination of the intermediate metal interconnect structure 375 and the external bonding pad 385.

[0206] In one embodiment, the at least one metal material may include aluminum and / or consist essentially of aluminum. In another embodiment, the at least one metal material may include a UBM layer stack and an optional copper layer located at the top of the UBM stack, and / or consist essentially of a UBM layer stack and an optional copper layer located at the top of the UBM stack. The UBM layer stack may include at least two metal barrier material layers, such as two, three or four metal barrier material layers. The UBM layer stack may include a material on which a solder material portion may be subsequently formed. In the case where the solder material portion subsequently used includes gold, the UBM layer may include a stack of titanium-tungsten layers and gold layers, or a stack of titanium layers and gold layers. In the case where the solder material portion subsequently used includes a lead-tin alloy or a tin-silver-copper alloy, the UBM layer stack may include a stack of titanium layers and copper layers; titanium-tungsten layers and copper layers; aluminum layers, nickel-vanadium layers and copper layers; or chromium layers, chromium-copper layers and copper layers.

[0207] In one embodiment, the memory side etch stop dielectric layer 364 may be formed as a component of the memory side interconnect level dielectric layer 390 before forming the intermediate metal interconnect structure 375 and the external bonding pad 385 within the memory side interconnect level dielectric layer 390. The memory side etch stop dielectric layer 364 includes a dielectric material different from the main component material of the memory side interconnect level dielectric layer 390 (such as silicon oxide or organic silicate glass) and provides higher corrosion resistance than the main component material of the memory side interconnect level dielectric layer 390. In one embodiment, the memory side etch stop dielectric layer 364 may include a dielectric metal oxide (such as aluminum oxide) or silicon nitride. The thickness of the memory side etch stop dielectric layer 364 can be in the range of 5nm to 100nm, but smaller and larger thicknesses can also be used. The memory side etch stop dielectric layer 364 can contact the aluminum portion of the external bonding pad 385 or the bottom surface of the UBM layer stack.

[0208] refer to Fig. 21B, providing a logic die 900 that can be replaced from a combination of an intermediate metal interconnect structure 975 and an external bonding pad 985 by an interconnect level metal line structure 974 Fig.17 The logic die 900 of FIG. 21 may be omitted. Fig.17 964 is an etch stop dielectric layer on the logic side. Fig.21A The memory die 1000 and Fig. 21B The logic die 900 of FIG. 1 may be designed such that the pattern of the logic side bonding pads 978 of the logic die 900 mirrors the pattern of the memory side bonding pads 378 of the memory die 1000 .

[0209] refer to Fig. 21C , Fig.21A The memory die 1000 and Fig. 21B The logic dies 900 may be bonded to each other by metal-to-metal bonding, such as copper-to-copper bonding.

[0210] refer to Fig.21D , the memory side substrate 310 may be thinned from the back side, for example by grinding, to provide a thinned memory side substrate 302, which is a semiconductor substrate. The thinned memory side substrate 302 may have a thickness in the range of 1 μm to 100 μm, such as 3 μm to 30 μm, although smaller and larger thicknesses may also be used.

[0211] refer to Fig.20E, a photoresist layer 977 may be applied over the back side of the thinned memory side substrate 302 and photolithographically patterned to form at least one opening therein. Each of the at least one opening in the patterned photoresist layer 977 may overlie a corresponding one of the external bonding pads 385. In one embodiment, each opening in the patterned photoresist layer 977 may have an area greater than the total area of ​​at least one underlying external bonding pad 385. An anisotropic etching process may be used to form the recessed region RR. The anisotropic etching process sequentially etches the material of the thinned memory side substrate 302 and the distal portion of the memory side interconnect level dielectric layer 390, as well as the physically exposed portion of the memory side etch stop dielectric layer 364. The memory side etch stop dielectric layer 364 may be used to prevent over-etching through the level of the external bonding pads 385. The terminal step of the anisotropic etching process may include an etching step that etches physically exposed portions of the memory-side etch stop dielectric layer 364 that are selective to the material of the external bonding pads 385. Each recessed region RR extends vertically from the distal planar surface of the memory die 1000, through the thinned memory-side substrate 302, through the proximal planar surface of the thinned memory-side substrate 302, through the distal portion of the memory-side interconnect level dielectric layer 390, through the memory-side etch stop dielectric layer 364, and down to the distal planar surface of each external bonding pad 385, below a corresponding opening in the patterned photoresist layer 977. A horizontal surface of one of the memory-side interconnect level dielectric layers 390 may be physically exposed at the bottom of each recessed region RR.

[0212] An external bonding pad 385 is disposed at the bottom of each recessed region RR. Each external bonding pad 385 may be located in one of the physically exposed ones in the memory-side interconnection level dielectric layer 390. The external bonding pad 385 may be initially formed in the memory-side interconnection level dielectric layer 390 during the formation of the memory-side interconnection level dielectric layer 390, and may be physically exposed after the bonding of the memory die 1000 and the logic die 900 and the anisotropic etching process for forming the recessed region RR. The flat horizontal surface of each external bonding pad 385 may be physically exposed after forming the recessed region RR. The patterned photoresist layer 977 may then be removed, for example, by ashing.

[0213] refer to Fig.21F, solder balls 995 may be attached to each external bonding pad 385. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed regions RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 385 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance in the range of 2 microns to 150 microns (such as 3 microns to 50 microns) relative to the far side flat surface of the thinned memory side substrate 302, but smaller and larger recess distances may also be used. In one embodiment, each combination of external bonding pads 385 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the logic side substrate 910 and a second horizontal plane HP2 including the near side horizontal surface of the thinned memory side substrate 302. A bonding wire 997 may be bonded to each solder ball 995 .

[0214] refer to Figure 21G , showing an alternative embodiment of the fifth configuration of the first exemplary structure. In this case, Fig.21A At the processing step of forming the interconnect level metal line structure 374 in the memory side interconnect level dielectric layer 390, instead of the intermediate metal interconnect structure 375 and the external bonding pad 385. In this case, a subset of the interconnect level metal line structure 374 is formed in an alternative embodiment of the fifth configuration of the first exemplary structure, instead of Fig.21A The external bonding pad 385 is then FIG. 21C to FIG. 21E A subset of interconnect level metal line structures 374 is physically exposed at the bottom of each recessed region RR. Metal bond pad material such as aluminum or a UBM layer stack may be deposited by an anisotropic deposition process or an isotropic deposition process and may be patterned by forming discrete photoresist material portions to cover the physically exposed portions of interconnect level metal line structures 374 at the bottom of the recessed regions, and by a subsequent etching process to remove the unmasked portions of the metal bond pad material. The remaining portions of the metal bond pad material below the discrete photoresist material portions constitute external bond pads 385.

[0215] An external bonding pad 385 is disposed at the bottom of each recessed region RR. Each external bonding pad 385 may be located on one of the physically exposed portions of the memory-side interconnect level dielectric layer 390. The external bonding pad 385 may be formed after bonding of the memory die 1000 and the logic die 900 and after an anisotropic etching process to form the recessed region RR. The discrete photoresist material portions may then be removed, for example, by ashing.

[0216] Solder balls 995 may be attached to each external bonding pad 385. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed region RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 385 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance (such as 3 microns to 50 microns) in the range of 1 micron to 150 microns relative to the far side flat surface of the thinned memory side substrate 302, but smaller and larger recess distances may also be used. In one embodiment, each combination of external bonding pads 385 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the logic side substrate 910 and a second horizontal plane HP2 including the near side horizontal surface of the thinned memory side substrate 302. A bonding wire 997 may be bonded to each solder ball 995.

[0217] refer to Fig.21H , showing the sixth configuration of the first embodiment. In this configuration, the memory side bonding pad 378 is arranged in the region of the recessed region RR, and a through hole cavity can be formed in the recessed region RR in the region covering the memory side bonding pad 378. The through hole cavity can extend vertically to the back surface of a corresponding one of the memory side bonding pads 378. At least one bonding pad material (such as an under-bump metallurgy (UBM) layer stack) can be deposited in the through hole cavity and can be subsequently patterned to form an external bonding pad 1385. Solder balls and bonding wires can then be attached to each external bonding pad 1385. In this embodiment, the external bonding pad 1385 is directly formed on the memory side bonding pad (e.g., copper pad) 378.

[0218] In use Figure 18G In any of the alternative embodiments of the silicon-on-insulator type substrate shown, the substrate 301 may be completely removed to expose the insulating layer 308, such as Fig.21H shown.

[0219] refer to Fig.22A The seventh configuration of the exemplary structure includes a memory die 1000 which can be used with Fig.16 The memory tube die 1000 is the same.

[0220] refer to Fig. 22B , showing the Fig.22A The logic die 900 of the memory die 1000 is shown. Fig. 22B The logic die of the embodiment of the present invention can be formed by forming a logic side etch stop dielectric layer 964 before forming the combination of the intermediate metal interconnect structure 975 and the external bonding pad 985. Fig.17 The logic die 900 is obtained. The thickness of the memory side etch stop dielectric layer 364 can be in the range of 5nm to 100nm, but smaller and larger thicknesses can also be used. The logic side etch stop dielectric layer 964 can contact the aluminum portion of the external bonding pad 985 or the top surface of the UBM layer stack.

[0221] refer to Fig. 22C , Fig. 20A The memory die 1000 and Fig. 20B The logic dies 900 may be bonded to each other by metal-to-metal bonding, such as copper-to-copper bonding.

[0222] refer to Fig.21D , the memory side substrate 310 may be thinned from the back side, for example by grinding, to provide a thinned memory side substrate 302, which is a semiconductor substrate. The thinned memory side substrate 302 may have a thickness in the range of 1 μm to 100 μm, such as 3 μm to 30 μm, although smaller and larger thicknesses may also be used.

[0223] refer to Fig.22E, a photoresist layer 977 may be applied over the back side of the thinned memory side substrate 302 and photolithographically patterned to form at least one opening therein. Each of the at least one opening in the patterned photoresist layer 977 may overlie a corresponding one of the external bonding pads 985. In one embodiment, each opening in the patterned photoresist layer 977 may have an area greater than the total area of ​​at least one underlying external bonding pad 985. An anisotropic etching process may be used to form the recessed region RR. The anisotropic etching process sequentially etches the material of the thinned memory side substrate 302, the memory side interconnect level dielectric layer 390, the proximal portion of the memory side interconnect level dielectric layer 990, and the physically exposed portion of the logic side etch stop dielectric layer 964. The logic side etch stop dielectric layer 964 may be used to prevent over-etching through the level of the external bonding pads 985. The terminal step of the anisotropic etching process may include an etching step that etches physically exposed portions of the logic-side etch stop dielectric layer 964 that are selective to the material of the external bonding pads 985. Each recessed region RR extends vertically from the distal planar surface of the memory die 1000, through the thinned memory-side substrate 302, through the proximal planar surface of the thinned memory-side substrate 302, through the entire thickness of the memory-side interconnect level dielectric layer 390, through the interface between the memory die 1000 and the logic die 900, through the proximal portion of the memory-side interconnect level dielectric layer 390, through the logic-side etch stop dielectric layer 964, and down to the proximal planar surface of each external bonding pad 985, below the corresponding opening in the patterned photoresist layer 977.

[0224] An external bonding pad 985 is disposed at the bottom of each recessed region RR. Each external bonding pad 985 may be located in one of the physically exposed portions of the logic side interconnect level dielectric layer 990. The external bonding pad 985 may be initially formed within the logic side interconnect level dielectric layer 990 during the formation of the logic side interconnect level dielectric layer 990, and may be physically exposed after the bonding of the memory die 1000 and the logic die 900 and the anisotropic etching process for forming the recessed region RR. The flat horizontal surface of each external bonding pad 985 may be physically exposed after forming the recessed region RR. The patterned photoresist layer 977 may then be removed, for example, by ashing.

[0225] refer to Fig.22F, solder balls 995 may be attached to each external bonding pad 985. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool, and in one embodiment, the recessed regions RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 985 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recessed distance in the range of 2 microns to 150 microns (such as 3 microns to 50 microns) relative to the far side flat surface of the thinned memory side substrate 302, but smaller and larger recessed distances may also be used. In one embodiment, each combination of external bonding pads 985 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the memory side substrate 310 and a second horizontal plane HP2 including the near side horizontal surface of the thinned memory side substrate 302. A bonding wire 997 may be bonded to each solder ball 995 .

[0226] refer to Figure 22G , showing the eighth configuration of the first exemplary structure. In this case, it can be Fig. 22B The processing step of forming the interconnect level metal line structure 974 in the logic side interconnect level dielectric layer 990 replaces the intermediate metal interconnect structure 975 and the external bonding pad 985. In this case, a subset of the interconnect level metal line structure 974 is formed in the eighth configuration of the first exemplary structure, replacing Fig. 22B The external bonding pad 985 in the FIG. 22C to FIG. 22E A subset of the interconnect level metal line structures 374 is physically exposed at the bottom of each recessed region RR. A metal bond pad material such as aluminum or a UBM layer stack may be deposited by an anisotropic deposition process or an isotropic deposition process and may be patterned by forming discrete photoresist material portions to cover the physically exposed portions of the interconnect level metal line structures 974 at the bottom of the recessed regions, and by a subsequent etching process that removes the unmasked portions of the metal bond pad material. The remaining portions of the metal bond pad material below the discrete photoresist material portions constitute the external bond pads 985.

[0227] An external bonding pad 985 is disposed at the bottom of each recessed region RR. Each external bonding pad 985 may be located on a physically exposed one of the logic-side interconnection-level dielectric layers 990. The external bonding pad 985 may be formed after bonding of the memory die 1000 and the logic die 900 and after an anisotropic etching process to form the recessed region RR. The discrete photoresist material portions may then be removed, for example, by ashing.

[0228] Solder balls 995 may be attached to each external bonding pad 985. Solder balls 995 may be applied to the bottom of each recessed region RR using a solder material dispensing tool. In one embodiment, the recessed region RR may be arranged as a one-dimensional periodic array or a two-dimensional periodic array. Alternatively, an array of external bonding pads 985 and a corresponding array of solder balls 995 may be formed in each recessed region RR. A single recessed region RR or an array of recessed regions RR may be formed. The bottom surface of the recessed region RR may be recessed by a recess distance (such as 3 microns to 50 microns) in the range of 2 microns to 150 microns relative to the far side flat surface of the thinned memory side substrate 302, but smaller and larger recess distances may also be used. In one embodiment, each combination of external bonding pads 985 and solder balls 995 may be completely located within a first horizontal plane HP1 including the near side horizontal surface of the logic side substrate 910 and a second horizontal plane HP2 including the near side horizontal surface of the thinned memory side substrate 302. A bonding wire 997 may be bonded to each solder ball 995.

[0229] Generally, a first semiconductor die and a second semiconductor die are provided, which include a memory die 1000 and a logic die 900. In one embodiment, the memory die 1000 can be the first semiconductor die and the logic die 900 can be the second semiconductor die. In another embodiment, the logic die 900 can be the first semiconductor die and the memory die 1000 can be the second semiconductor die. The first semiconductor die includes: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device (which may include a three-dimensional memory array or a peripheral circuit) located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer (which may be a memory side interconnect level dielectric layer 390 or a logic side interconnect level dielectric layer 990) including a first metal interconnect structure (which may be a memory side metal interconnect structure 370 or a logic side metal interconnect structure 970) electrically connected to the first semiconductor device, and a first die-to-die bonding pad (which may be a memory side bonding pad 378 or a logic side bonding pad 978) located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure. The second semiconductor die includes: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device (which may include a three-dimensional memory array or a peripheral circuit) located on or above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer (which may be a memory side interconnect level dielectric layer 390 or a logic side interconnect level dielectric layer 990) including a second metal interconnect structure (which may be a memory side metal interconnect structure 370 or a logic side metal interconnect structure 970) electrically connected to the second semiconductor device, and a second die-to-die bonding pad (which may be a memory side bonding pad 378 or a logic side bonding pad 978) located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure.

[0230] The second die-to-die bonding pad may be bonded to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die. In one embodiment, the second die-to-die bonding pad may be bonded to the first die-to-die bonding pad by copper-to-copper bonding. At least one recessed region RR may be formed by removing a portion of material extending vertically from the second distal planar surface through the second substrate and extending into the volume of the second proximal planar surface to provide a physically exposed horizontal surface of one of the first interconnect level dielectric layer and the second interconnect level dielectric layer. One of the first semiconductor die and the second semiconductor die includes a memory die 1000 including a three-dimensional array of memory elements, and the other of the first semiconductor die and the second semiconductor die includes a logic die 900 including peripheral circuits configured to operate the three-dimensional array of memory elements.

[0231] In one embodiment, the first substrate and the second substrate include semiconductor substrates, the memory die 1000 includes a set of word lines for a three-dimensional array of memory elements and a set of bit lines for a three-dimensional array of memory elements, and the peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines.

[0232] In one embodiment, the physically exposed horizontal surface is a horizontal surface of one of the second interconnect level dielectric layers.

[0233] In one embodiment, the external bonding pad (385 or 985) may be located on or in one of the first interconnect level dielectric layer and the second interconnect level dielectric layer. The external bonding pad (385 or 985) may be formed in one of the first interconnect level dielectric layer and the second interconnect level dielectric layer during the formation of the first metal interconnect structure or during the formation of the second metal interconnect structure. The flat horizontal surface of the external bonding pad is physically exposed after forming the recessed region RR. A solder ball may be attached to the surface of the external bonding pad (385 or 985).

[0234] With reference to all figures relating to the configuration of the first exemplary structure and in accordance with various embodiments, there is provided a bonded assembly comprising: a first semiconductor die (900 or 1000) comprising a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer (990 or 390) comprising a first metal interconnect structure (970 or 370) electrically connected to the first semiconductor device, and a first metal interconnect structure (970 or 370) located at a surface portion of the first interconnect level dielectric layer (990 or 390) and electrically connected to the first metal interconnect structure. a first die-to-die bonding pad (978 or 378) of a structure (970 or 370); and a second semiconductor die (1000 or 900), the second semiconductor die including a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located on or above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer (390 or 990) including a second metal interconnect structure (370 or 970) electrically connected to the second semiconductor device, and a second die-to-die bonding pad (378 or 978) located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure. The second die-to-die bonding pad (378 or 978) is bonded to the first die-to-die bonding pad (978 or 378) to provide a die-to-die bond between the first semiconductor die and the second semiconductor die. An external bonding pad (385 or 985) located on or in one of the first interconnect level dielectric layer (990 or 390) and the second interconnect level dielectric layer (390 or 990), the external bonding pad having a physically exposed horizontal surface. The external bonding pad is completely located within a first horizontal plane HP1 and a second horizontal plane HP2, the first horizontal plane including a first proximal planar surface of the first substrate (910 or 310), and the second horizontal plane including a second proximal planar surface of the second substrate (302 or 902).

[0235] In one embodiment, solder ball 995 is bonded to external bond pad (385 or 985). In one embodiment, second die-to-die bond pad (378 or 978) is bonded to first die-to-die bond pad (978 or 378) by copper-to-copper bonding.

[0236] In one embodiment, a recessed region RR including a void may be provided. The recessed region RR extends vertically from the second distal planar surface, through the second proximal planar surface, and to the physically exposed horizontal surface.

[0237] In one embodiment, the recessed region RR includes at least one vertical or substantially vertical sidewall that extends continuously from the second distal planar surface to the physically exposed horizontal surface and to the surface of the external bonding pad (385 or 985).

[0238] In one embodiment, the external bonding pad (385 or 985) is directly located on or included within one of the second interconnect level dielectric layers (390 or 990) in the second semiconductor die, and the physically exposed horizontal surface includes a horizontal surface of one of the second interconnect level dielectric layers (390 or 990).

[0239] In one embodiment, the external bonding pad (385 or 985) is directly located on or included within one of the first interconnect level dielectric layers (990 or 390) in the first semiconductor die, and the physically exposed horizontal surface includes a horizontal surface of one of the first interconnect level dielectric layers (990 or 390).

[0240] In one embodiment, an edge of the interface between the first semiconductor die ( 900 or 1000 ) and the second semiconductor die ( 1000 or 900 ) may be physically exposed to the recessed region RR.

[0241] In one embodiment, one of the first semiconductor die and the second semiconductor die includes a memory die 1000 including a three-dimensional array of memory elements, and the other of the first semiconductor die and the second semiconductor die includes a logic die 900 including peripheral circuits configured to operate the three-dimensional array of memory elements.

[0242] In one embodiment, the first substrate and the second substrate include semiconductor substrates, the memory die 1000 includes a set of word lines for a three-dimensional array of memory elements and a set of bit lines 98 for the three-dimensional array of memory elements, and the peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines 98.

[0243] In one embodiment, the memory die 1000 includes an alternating stack of insulating layers (132, 232) and conductive layers (146, 246), and a two-dimensional array of memory stack structures 55 extending through the alternating stacks {(132, 146), (232, 246)}. Each of the memory stack structures 55 includes a respective vertical stack of memory elements positioned adjacent to respective vertical semiconductor channels 60, the two-dimensional array of memory stack structures 55 constitutes a three-dimensional array of memory elements, the bit lines 98 are connected to respective subsets of the vertical semiconductor channels 60, and the conductive layers (146, 246) include word lines.

[0244] refer to Fig.23A , a second exemplary structure including a memory die 1000 is provided. Fig.23A The memory die 1000 of the embodiment of the present invention can be obtained from the memory die 1000 by forming a subset of the interconnect level metal line structure 374 in the shape of the memory side via landing pad 374P. Fig.16 The memory die 1000 is obtained. The memory side via landing pad 374P may have a rectangular, circular, or elliptical horizontal cross-sectional shape, and may have a maximum lateral dimension in the range of 1 micron to 60 microns (such as 3 microns to 30 microns), but smaller and larger maximum lateral dimensions may also be used. In addition, a patterned memory side etch stop dielectric layer 364 may be formed on the top surface of each of the memory side via landing pads 374P. Each patterned memory side etch stop dielectric layer 364 includes a dielectric material different from the main component material of the memory side interconnect level dielectric layer 390 (such as silicon oxide or organic silicate glass), and provides higher corrosion resistance than the main component material of the memory side interconnect level dielectric layer 390.

[0245] In one embodiment, each memory side etch stop dielectric layer 364 may include a dielectric metal oxide (such as aluminum oxide) or silicon nitride. The thickness of each memory side etch stop dielectric layer 364 may be in the range of 5 nm to 100 nm, although lesser and greater thicknesses may also be used. Each memory side etch stop dielectric layer 364 may be patterned so that a patterned portion of the memory side etch stop dielectric layer 364 is located within each region where a connecting via cavity is subsequently formed.

[0246] refer to Fig. 23B , showing the Fig.23A The logic die 900 of the memory die 1000 is shown. Fig. 23B The logic die 900 may be connected from the substrate by forming a subset of the interconnect level metal line structure 974 in the shape of the logic side via landing pad 974P. Fig. 20BThe logic die of the present invention is obtained. The logic side via landing pad 974P may have a rectangular, circular, or elliptical horizontal cross-sectional shape, and may have a maximum lateral dimension in the range of 1 micron to 60 microns (such as 9 microns to 90 microns), but smaller and larger maximum lateral dimensions may also be used. In addition, each of the logic side via landing pads 974P may be formed on the top surface of a corresponding patterned logic side etch stop dielectric layer 964. Each patterned logic side etch stop dielectric layer 964 includes a dielectric material different from the main component material of the logic side interconnect level dielectric layer 990 (such as silicon oxide or organic silicate glass) and provides higher corrosion resistance than the main component material of the logic side interconnect level dielectric layer 990. In one embodiment, each logic side etch stop dielectric layer 964 may include a dielectric metal oxide (such as aluminum oxide) or silicon nitride. The thickness of each logic side etch stop dielectric layer 964 may be in the range of 5nm to 100nm, but smaller and larger thicknesses may also be used. Each logic side etch stop dielectric layer 964 may be patterned such that a patterned portion of the logic side etch stop dielectric layer 964 is located within each region where a connecting via cavity is subsequently to be formed. Fig.23A The memory die 1000 and Fig. 23B The logic die 900 of FIG. 1 may be designed such that the pattern of the logic side bonding pads 978 of the logic die 900 mirrors the pattern of the memory side bonding pads 378 of the memory die 1000 .

[0247] refer to Fig.23C , Fig.23A The memory die 1000 and Fig. 23B The logic die 900 can be bonded to each other by metal-to-metal bonding (such as copper-to-copper bonding). Subsequently, the logic side substrate 910 can be thinned from the back side, for example by grinding, to provide a thinned logic side substrate 902, which is a semiconductor substrate. The thinned logic side substrate 902 can have a thickness in the range of 1 μm to 100 μm (such as 3 μm to 30 μm), but smaller and larger thicknesses can also be used. A planar dielectric isolation layer 930 can be formed on the far side flat surface of the thinned logic side substrate 902. The planar dielectric isolation layer 930 includes an insulating material such as silicon oxide, silicon nitride and / or a dielectric metal oxide. For example, the planar dielectric isolation layer 930 may include silicon nitride, which can inhibit moisture or contaminants from entering the thinned logic side substrate 902 from the environment. The thickness of the planar dielectric isolation layer 930 can be in the range of 10 nm to 500 nm, but smaller and larger thicknesses can also be used.

[0248] refer to Fig.23D, a photoresist layer 977 may be applied over the planar dielectric isolation layer 930 above the planar distal flat surface of the thinned logic side substrate 902 and photolithographically patterned to form a plurality of openings therein. Each opening in the patterned photoresist layer 977 may be formed entirely within the area of ​​a respective one of the logic side via landing pad 974P and the memory side via landing pad 374P. In one embodiment, the pattern of discrete openings in the photoresist layer 977 may match the general pattern of the logic side via landing pad 974P and the memory side via landing pad 374P by a scale factor of less than 1, such that each opening in the patterned photoresist layer 977 has a smaller area than one of the underlying logic side via landing pad 974P and the memory side via landing pad 374P. In one embodiment, in a plan view (i.e., a view along the vertical direction), the area of ​​each discrete opening in the photoresist layer 977 can be completely within the area of ​​one of the underlying logic side via landing pads 974P and the memory side via landing pads 374P. In one embodiment, the array of logic side via landing pads 974P and the memory side via landing pads 374P and the discrete openings in the photoresist layer 977 can be arranged as a periodic one-dimensional array. In one embodiment, the array of logic side via landing pads 974P and the memory side via landing pads 374P and the discrete openings in the photoresist layer 977 can be arranged as a periodic two-dimensional array.

[0249] An anisotropic etching process may be performed to etch through the thinned logic side substrate 902, portions of the logic side interconnect level dielectric layer 990, and proximal portions of the memory side interconnect level dielectric layer 390 using the patterned photoresist layer 977 as an etching mask. The anisotropic etching process may include a first etching step that etches material of the thinned logic side substrate 902 that is selective to the dielectric material of the logic side interconnect level dielectric layer 990, and a second etching step that etches material of the logic side interconnect level dielectric layer 990 and the memory side interconnect level dielectric layer 390 that is selective to the material of the logic side etch stop dielectric layer 964 and the memory side etch stop dielectric layer 364. Each etch stop dielectric layer (364 or 964) except the etch stop dielectric layer that contacts the farthest memory side via landing pad among the memory side via landing pads 374P (as measured from a horizontal plane including the far side planar surface of the thinned logic side substrate 902) can be patterned during the formation of the logic side interconnect level dielectric layer 990 or during the formation of the memory side interconnect level dielectric layer 390 to ensure that each connecting via cavity 935 formed by the first step and the second step of the anisotropic etching process reaches a corresponding one of the etch stop dielectric layers (364, 964) without being prematurely stopped by an intervening etch stop dielectric layer (364 or 964).

[0250] The anisotropic etching process includes a third step of etching through the physically exposed portion of the etch stop dielectric layer (364, 964) to expose the central portion of the logic side via landing pad 974P and the memory side via landing pad 374P. Optionally, the third step of the anisotropic etching process can be replaced with an isotropic etching process, such as a wet etching process, which etches the material of the etch stop material layer (364, 964) that is selective to the material of the via landing pad (974P, 374P) and the interconnect level dielectric layer (990, 390). The patterned photoresist layer 977 can be removed, for example, by ashing. A suitable cleaning process can then be performed.

[0251] The connection via cavity 935 includes: a first connection via cavity 935A extending through the thinned logic side substrate 902, the logic side interconnection level dielectric layer 990, and the proximal portion of the memory side interconnection level dielectric layer 390 to reach the proximal flat surface of a corresponding one of the memory side via landing pads 374P; and a second connection via cavity 935B extending through the thinned logic side substrate 902 and the distal portion of the logic side interconnection level dielectric layer 990 to reach the distal flat surface of a corresponding one of the logic side via landing pads 974P. Each first connection via cavity 935A includes at least one straight sidewall extending through the thinned logic side substrate 902, the logic side interconnection level dielectric layer 990, and the proximal portion of the memory side interconnection level dielectric layer 390 to reach the proximal flat surface of a corresponding one of the memory side via landing pads 374P. Each second connecting via cavity 935B extends through the thinned logic-side substrate 902 and distal portions of the logic-side interconnect-level dielectric layer 990 to a distal planar surface of a corresponding one of the logic-side via landing pads 974P.

[0252] The memory side via landing pad 374P may be formed at multiple levels within the memory side interconnect level dielectric layer 390. In this case, the first connection via cavity 935A may include multiple subsets of the first connection via cavity 935A extending to reach the proximal planar surface of the memory side via landing pad 374P located at different depths. Similarly, the logic side via landing pad 974P may be formed at multiple levels within the logic side interconnect level dielectric layer 990. In this case, the second connection via cavity 935B may include multiple subsets of the second connection via cavity 935B extending to reach the distal planar surface of the logic side via landing pad 974P located at different depths.

[0253] Each connecting through hole cavity 935 includes at least one straight sidewall. Each straight sidewall of the connecting through hole cavity 935 can be vertical or substantially vertical, that is, a straight sidewall with a taper angle of less than 5 degrees relative to the vertical direction. The maximum lateral dimension (such as a diameter, a major axis, or a diagonal of a rectangular shape) of each connecting through hole cavity 935 can be in the range of 3 microns to 30 microns (such as 6 microns to 15 microns), but smaller and larger maximum lateral dimensions can also be used.

[0254] refer to Fig.23E , a continuous dielectric material layer can be deposited at the periphery of each connecting via cavity 935 and over the thinned logic side substrate 902 by a conformal deposition process. The continuous dielectric material layer may include silicon oxide, silicon nitride and / or a dielectric metal oxide such as aluminum oxide. The thickness of the continuous dielectric material layer may be in the range of 10nm to 200nm (such as 20nm to 100nm), but smaller and larger thicknesses may also be used. An anisotropic etching process may be performed to remove horizontal portions of the continuous dielectric material layer. After the anisotropic etching process, a tubular insulating spacer 934 may be formed at the periphery of each connecting via cavity 935 by the corresponding remaining portion of the continuous dielectric material layer. The top surface of the via landing pad (974P or 374P) is physically exposed at the bottom of each unfilled portion of the connecting via cavity 935, which top surface may be a distal flat surface of the logic side via landing pad 974P or a proximal flat surface of the memory side via landing pad 374P.

[0255] At least one conductive material may be deposited in the remaining volume of the connecting via cavity 935. The at least one conductive material may include, for example, a conductive metal nitride liner material (such as TiN, TaN and / or WN) and at least one conductive filling material (such as W, Cu, Mo and / or heavily doped polysilicon). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the distal flat surface of the thinned logic side substrate 902 by a planarization process. The planarization process may use chemical mechanical planarization (CMP) and / or recess etching. The planarization process may be selective to the semiconductor material of the thinned logic side substrate 902. Each remaining portion of the at least one conductive material in the connecting via cavity 935 constitutes a conductive pillar structure 936.

[0256] The conductive pillar structure 936 includes: a first conductive pillar structure 936A, which extends through the thinned logic side substrate 902, the logic side interconnection level dielectric layer 990 and the proximal portion of the memory side interconnection level dielectric layer 390, and contacts the proximal flat surface of the memory side via landing pad 374P; and a second conductive pillar structure 936B, which extends through the thinned logic side substrate 902 and the distal portion of the logic side interconnection level dielectric layer 990, and contacts the distal side of the logic side via landing pad 974P. Each continuous combination of the first conductive pillar structure 936A and the tubular insulating spacer 934 constitutes a first lateral insulated external connection via structure (936A, 934), and each continuous combination of the second conductive pillar structure 936B and the tubular insulating spacer 934 constitutes a second lateral insulated external connection via structure (936B, 934).

[0257] Each first lateral insulated external connection via structure (936A, 934) contacts the proximal flat surface of the corresponding memory side via landing pad 374P. In the case where the memory side via landing pad 374P is located at multiple levels of the memory side interconnect level dielectric layer 390, multiple types of first lateral insulated external connection via structures (936A, 934) with different heights can be formed. Each second lateral insulated external connection via structure (936B, 934) contacts the distal flat surface of the corresponding logic side via landing pad 974P. In the case where the logic side via landing pad 974P is located at multiple levels of the logic side interconnect level dielectric layer 990, multiple types of second lateral insulated external connection via structures (936A, 934) with different heights can be formed.

[0258] A metal bond pad material such as aluminum or a UBM layer stack may be deposited by an anisotropic deposition process or an isotropic deposition process and may be subsequently patterned to form an external bond pad 938. For example, discrete photoresist material portions may be formed over the deposited metal bond pad material to cover discrete regions of the metal bond pad material that cover the lateral insulating external connection via structures (936, 934). An etching process may be performed to remove unmasked portions of the metal bond pad material. The remaining portions of the metal bond pad material below the discrete photoresist material portions constitute the external bond pad 938.

[0259] A solder ball 995 may be attached to each external bonding pad 938. A solder material dispensing tool may be used to apply the solder ball 995 to the external bonding pad 938. In one embodiment, the lateral insulating external connection via structures (936, 934) and the external bonding pad 938 may be arranged in a one-dimensional periodic array or a two-dimensional periodic array. A bonding wire 997 may be bonded to each solder ball 995.

[0260] refer to Fig.23F , showing a second configuration of a second exemplary structure, in which an electrical connection to a node within a peripheral circuit on a thinned logic side substrate is provided using a generally U-shaped conductive path, the conductive path comprising a first conductive pillar structure 936A in a first lateral insulating external connection via structure (936A, 934), a memory side via landing pad 374P, one or more of a memory side metal interconnect structure 370, a pair of logic side bonding pads 978 and a memory side bonding pad 378, and one or more of a logic side metal interconnect structure 970.

[0261] refer to Figure 23G , an alternative second configuration of the second exemplary structure can be derived from the second exemplary structure by forming a through-hole cavity that extends through the thinned logic side substrate 902 and the logic side interconnect level dielectric layer 990 to the back side of a corresponding one of the logic side bonding pads 978. Lateral insulating external connection through-hole structures (936, 934) can be formed in the through-hole cavity. The conductive pillar structure 936 can serve as a conductive path between the logic side bonding pad 978 and the back side of the logic die. The external bonding pad 938 can be formed on each of the conductive pillar structures 938. In this embodiment, the conductive pillar structure 936 is formed directly on the logic side bonding pad 978.

[0262] refer to Fig.24A , a memory die 1000 is provided, which can be formed from each of the memory side via landing pads 374P on the top surface of the corresponding patterned memory side etch stop dielectric layer 364. Fig.23A Each patterned memory side etch stop dielectric layer 364 may include Fig.23A The patterned memory side etch stop dielectric layer 364 is the same dielectric material.

[0263] refer to Fig. 24B , showing the Fig.24A The logic die 900 of the memory die 1000 is shown. Fig. 24B The logic die 900 of the embodiment of the present invention may be formed from a top surface of each of the logic side via landing pads 974P by forming each patterned logic side etch stop dielectric layer 964 on a top surface of a corresponding one of the logic side via landing pads 974P. Fig. 23B Each patterned logic side etch stop dielectric layer 964 may include Fig.23A The patterned logic side etch stop dielectric layer 964 is the same dielectric material. Fig.24A The memory die 1000 and Fig. 24BThe logic die 900 of FIG. 1 may be designed such that the pattern of the logic side bonding pads 978 of the logic die 900 mirrors the pattern of the memory side bonding pads 378 of the memory die 1000 .

[0264] refer to Fig.24C , Fig.24A The memory die 1000 and Fig. 24B The logic die 900 can be bonded to each other by metal-to-metal bonding (such as copper-to-copper bonding). Subsequently, the memory side substrate 310 can be thinned from the back side, for example by grinding, to provide a thinned memory side substrate 302, which is a semiconductor substrate. The thinned memory side substrate 302 can have a thickness in the range of 1 μm to 100 μm (such as 3 μm to 30 μm), but smaller and larger thicknesses can also be used. A planar dielectric isolation layer 330 can be formed on the far side flat surface of the thinned memory side substrate 302. The planar dielectric isolation layer 330 includes an insulating material such as silicon oxide, silicon nitride and / or a dielectric metal oxide. For example, the planar dielectric isolation layer 330 may include silicon nitride, which can inhibit moisture or contaminants from entering the thinned memory side substrate 302 from the environment. The thickness of the planar dielectric isolation layer 330 can be in the range of 10 nm to 500 nm, but smaller and larger thicknesses can also be used.

[0265] refer to Fig.24D, a photoresist layer 977 may be applied over the planar dielectric isolation layer 330 over the planar distal flat surface of the thinned memory side substrate 302 and photolithographically patterned to form a plurality of openings therein. Each opening in the patterned photoresist layer 977 may be formed entirely within the area of ​​a respective one of the logic side via landing pad 974P and the memory side via landing pad 374P. In one embodiment, the pattern of discrete openings in the photoresist layer 977 may match the general pattern of the logic side via landing pad 974P and the memory side via landing pad 374P by a scale factor of less than 1, such that each opening in the patterned photoresist layer 977 has a smaller area than one of the underlying logic side via landing pad 974P and the memory side via landing pad 374P. In one embodiment, in a plan view (i.e., a view along the vertical direction), the area of ​​each discrete opening in the photoresist layer 977 can be completely within the area of ​​one of the underlying logic side via landing pads 974P and the memory side via landing pads 374P. In one embodiment, the array of logic side via landing pads 974P and the memory side via landing pads 374P and the discrete openings in the photoresist layer 977 can be arranged as a periodic one-dimensional array. In one embodiment, the array of logic side via landing pads 974P and the memory side via landing pads 374P and the discrete openings in the photoresist layer 977 can be arranged as a periodic two-dimensional array.

[0266] An anisotropic etching process may be performed to etch through the thinned memory side substrate 302, portions of the memory side interconnect level dielectric layer 390, and proximal portions of the logic side interconnect level dielectric layer 990 using the patterned photoresist layer 977 as an etching mask. The anisotropic etching process may include a first etching step that etches material of the thinned memory side substrate 302 that is selective to the dielectric material of the memory side interconnect level dielectric layer 390, and a second etching step that etches material of the memory side interconnect level dielectric layer 390 and the logic side interconnect level dielectric layer 990 that is selective to material of the logic side etch stop dielectric layer 964 and the memory side etch stop dielectric layer 364. Each etch stop dielectric layer (364 or 964) except the etch stop dielectric layer that contacts the farthest logic side via landing pad among the logic side via landing pads 974P (as measured from a horizontal plane including the far side planar surface of the thinned memory side substrate 302) can be patterned during the formation of the logic side interconnect level dielectric layer 990 or during the formation of the memory side interconnect level dielectric layer 390 to ensure that each connecting via cavity 335 formed by the first step and the second step of the anisotropic etching process reaches a corresponding one of the etch stop dielectric layers (364, 964) without being prematurely stopped by an intervening etch stop dielectric layer (364 or 964).

[0267] The anisotropic etching process includes a third step of etching through the physically exposed portion of the etch stop dielectric layer (364, 964) to expose the central portion of the logic side via landing pad 974P and the memory side via landing pad 374P. Optionally, the third step of the anisotropic etching process can be replaced with an isotropic etching process, such as a wet etching process, which etches the material of the etch stop material layer (364, 964) that is selective to the material of the via landing pad (974P, 374P) and the interconnect level dielectric layer (990, 390). The patterned photoresist layer 977 can be removed, for example, by ashing. A suitable cleaning process can then be performed.

[0268] The connection via cavity 335 includes: a first connection via cavity 335A extending through the thinned memory side substrate 302, the memory side interconnection level dielectric layer 390, and the near side portion of the logic side interconnection level dielectric layer 990 to reach the near side planar surface of a corresponding one of the logic side via landing pads 974P; and a second connection via cavity 335B extending through the thinned memory side substrate 302 and the far side portion of the memory side interconnection level dielectric layer 390 to reach the far side planar surface of a corresponding one of the memory side via landing pads 374P. Each first connection via cavity 335A includes at least one straight sidewall extending through the thinned memory side substrate 302, the memory side interconnection level dielectric layer 390, and the near side portion of the logic side interconnection level dielectric layer 990 to reach the near side planar surface of a corresponding one of the logic side via landing pads 974P. Each second connection via cavity 335B extends through the thinned memory-side substrate 302 and distal portions of the memory-side interconnect-level dielectric layer 390 to a distal planar surface of a respective one of the memory-side via landing pads 374P.

[0269] The logic side via landing pad 974P may be formed at multiple levels within the logic side interconnect level dielectric layer 990. In this case, the first connection via cavity 335A may include multiple subsets of the first connection via cavity 335A extending to reach the proximal planar surface of the logic side via landing pad 974P located at different depths. Similarly, the memory side via landing pad 374P may be formed at multiple levels within the memory side interconnect level dielectric layer 390. In this case, the second connection via cavity 335B may include multiple subsets of the second connection via cavity 335B extending to reach the distal planar surface of the memory side via landing pad 374P located at different depths.

[0270] Each connecting through hole cavity 335 includes at least one straight sidewall. Each straight sidewall of the connecting through hole cavity 335 can be vertical or substantially vertical, that is, a straight sidewall with a taper angle of less than 5 degrees relative to the vertical direction. The maximum lateral dimension (such as a diameter, a major axis, or a diagonal of a rectangular shape) of each connecting through hole cavity 335 can be in the range of 3 microns to 30 microns (such as 6 microns to 15 microns), but smaller and larger maximum lateral dimensions can also be used.

[0271] refer to Fig.23E, a continuous dielectric material layer can be deposited at the periphery of each connecting via cavity 335 and over the thinned memory side substrate 302 by a conformal deposition process. The continuous dielectric material layer may include silicon oxide, silicon nitride and / or a dielectric metal oxide such as aluminum oxide. The thickness of the continuous dielectric material layer can be in the range of 10nm to 200nm (such as 20nm to 100nm), but smaller and larger thicknesses can also be used. An anisotropic etching process can be performed to remove horizontal portions of the continuous dielectric material layer. After the anisotropic etching process, a tubular insulating spacer 334 can be formed at the periphery of each connecting via cavity 335 by the corresponding remaining portion of the continuous dielectric material layer. The top surface of the via landing pad (374P or 974P) is physically exposed at the bottom of each unfilled portion of the connecting via cavity 335, which top surface can be a distal flat surface of the memory side via landing pad 374P or a proximal flat surface of the logic side via landing pad 974P.

[0272] At least one conductive material may be deposited in the remaining volume of the connecting via cavity 335. The at least one conductive material may include, for example, a conductive metal nitride liner material (such as TiN, TaN and / or WN) and at least one conductive filling material (such as W, Cu, Mo and / or heavily doped polysilicon). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the distal flat surface of the thinned memory side substrate 302 by a planarization process. The planarization process may use chemical mechanical planarization (CMP) and / or recess etching. The planarization process may be selective to the semiconductor material of the thinned memory side substrate 302. Each remaining portion of the at least one conductive material in the connecting via cavity 335 constitutes a conductive pillar structure 336.

[0273] The conductive pillar structure 336 includes: a first conductive pillar structure 336A, which extends through the thinned memory side substrate 302, the memory side interconnect level dielectric layer 390 and the proximal portion of the memory side interconnect level dielectric layer 990, and contacts the proximal flat surface of the logic side via landing pad 974P; and a second conductive pillar structure 336B, which extends through the thinned memory side substrate 302 and the distal portion of the memory side interconnect level dielectric layer 390, and contacts the distal side of the memory side via landing pad 374P. Each continuous combination of the first conductive pillar structure 336A and the tubular insulating spacer 334 constitutes a first lateral insulated external connection via structure (336A, 334), and each continuous combination of the second conductive pillar structure 336B and the tubular insulating spacer 334 constitutes a second lateral insulated external connection via structure (336B, 334).

[0274] Each first lateral insulated external connection via structure (336A, 334) contacts the proximal flat surface of the corresponding logic side via landing pad 974P. In the case where the logic side via landing pad 974P is located at multiple levels of the logic side interconnect level dielectric layer 990, multiple types of first lateral insulated external connection via structures (336A, 334) with different heights can be formed. Each second lateral insulated external connection via structure (336B, 334) contacts the distal flat surface of the corresponding memory side via landing pad 374P. In the case where the memory side via landing pad 374P is located at multiple levels of the memory side interconnect level dielectric layer 390, multiple types of second lateral insulated external connection via structures (336A, 334) with different heights can be formed.

[0275] A metal bond pad material such as aluminum or a UBM layer stack may be deposited by an anisotropic deposition process or an isotropic deposition process and may be subsequently patterned to form an external bond pad 938. For example, discrete photoresist material portions may be formed over the deposited metal bond pad material to cover discrete regions of the metal bond pad material that cover the lateral insulating external connection via structures (336, 334). An etching process may be performed to remove unmasked portions of the metal bond pad material. The remaining portions of the metal bond pad material below the discrete photoresist material portions constitute the external bond pad 338.

[0276] A solder ball 995 may be attached to each external bonding pad 938. A solder material dispensing tool may be used to apply the solder ball 995 to the external bonding pad 938. In one embodiment, the lateral insulating external connection via structures (336, 334) and the external bonding pad 938 may be arranged in a one-dimensional periodic array or a two-dimensional periodic array. A bonding wire 997 may be bonded to each solder ball 995.

[0277] Generally, a first semiconductor die and a second semiconductor die are provided, which include a memory die 1000 and a logic die 900. In one embodiment, the memory die 1000 can be the first semiconductor die and the logic die 900 can be the second semiconductor die. In another embodiment, the logic die 900 can be the first semiconductor die and the memory die 1000 can be the second semiconductor die. The first semiconductor die includes: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device (which may include a three-dimensional memory array or a peripheral circuit) located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer (which may be a memory side interconnect level dielectric layer 390 or a logic side interconnect level dielectric layer 990) including a first metal interconnect structure (which may be a memory side metal interconnect structure 370 or a logic side metal interconnect structure 970) electrically connected to the first semiconductor device, and a first die-to-die bonding pad (which may be a memory side bonding pad 378 or a logic side bonding pad 978) located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure. The second semiconductor die includes: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device (which may include a three-dimensional memory array or peripheral circuit) located on or above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer (which may be a memory side interconnect level dielectric layer 390 or a logic side interconnect level dielectric layer 990) including a second metal interconnect structure (which may be a memory side metal interconnect structure 370 or a logic side metal interconnect structure 970) electrically connected to the second semiconductor device, and a second die-to-die bonding pad (which may be a memory side bonding pad 378 or a logic side bonding pad 978) located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure. The second die-to-die bonding pad is bonded to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die. In one embodiment, the second die-to-die bonding pad is bonded to the first die-to-die bonding pad by copper-to-copper bonding.

[0278] The first connection via cavity (935A or 335A) is formed through the second substrate (902 or 302), the second interconnect level dielectric layer (990 or 390), a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and a subset of the layers within the first interconnect level dielectric layer (390 or 990). One of the first metal interconnect structures (974P or 374P) is physically exposed at the bottom of the first connection via cavity (935A or 335A). The second connection via cavity (935B or 335B) is formed through the second substrate (902 or 302) and a subset of the layers within the second interconnect level dielectric layer (990 or 390). One of the second metal interconnect structures (374P or 974P) is physically exposed at the bottom of the second connection via cavity (935B or 335B). The third connecting via cavity (935A or 335A) can be formed to pass through the second substrate (902 or 302), the second interconnect level dielectric layer (990 or 390), a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and another subset of layers within the first interconnect level dielectric layer (390 or 990), and extend to another one of the first metal interconnect structures (974P or 374P), the other one having a vertical distance from the interface between the first semiconductor die and the second semiconductor die that is different from the vertical distance of the one of the first metal interconnect structures (974P or 374P) from the interface between the first semiconductor die and the second semiconductor die.

[0279] In one embodiment, the first interconnect level dielectric layer (390 or 990) includes a patterned first etch stop dielectric layer (364 or 964) contacting a surface of one of the first metal interconnect structures (974P or 374P), and the second interconnect level dielectric layer (990 or 390) includes a patterned second etch stop dielectric layer (964 or 364) contacting a surface of one of the second metal interconnect structures (374P or 974P), and the first connecting via cavity (935A or 335A), the second connecting via cavity (935B or 335B), and the third connecting via cavity ( 935A or 335A), the anisotropic etching process includes a first etching step, a second etching step and a third etching step, the first etching step etches through the second substrate (902 or 302), the second etching step etches portions of the second interconnect level dielectric layer 390 and the first interconnect level dielectric layer 990 that are selective to the material of the patterned second etch stop dielectric layer (364 or 964) and the patterned first etch stop dielectric layer (964 or 364), and the third etching step etches through the patterned second etch stop dielectric layer (364 or 964) and the patterned first etch stop dielectric layer (364 or 964).

[0280] A first lateral insulating external connection via structure {(936A, 934), (336A, 334)} is formed in a first connection via cavity (935A, 335A) on one of the first metal interconnect structures (374P, 974P), a second lateral insulating external connection via structure {(936B, 934), (336B, 334)} is formed in a second connection via cavity (935B, 335B) on one of the second metal interconnect structures (974P, 374P), and a third lateral insulating external connection via structure {(936A, 934), (336A, 334)} is formed in a third connection via cavity (935A, 335A) on the other of the first metal interconnect structures (374P, 974P).

[0281] Each lateral insulating external connecting via structure {(936, 934), (336, 334)} can be simultaneously formed by: conformally depositing a continuous dielectric material layer at the periphery of the connecting via cavity (935, 335) and above the second substrate (902, 302), forming a tubular insulating spacer (934, 334) within each connecting via cavity (935, 335) by anisotropically etching the continuous dielectric material layer, and forming a conductive pillar structure (936, 336) within the remaining volume of each connecting via cavity (935, 335) inside the tubular insulating spacer (934, 334).

[0282] A first external bonding pad (938, 338) may be formed on the first lateral insulated external connection via structure {(936A, 934), (336A, 334)}, a second external bonding pad (938, 338) may be formed on the second lateral insulated external connection via structure {(936B, 934), (336B, 334)}, and a third external bonding pad (938, 338) may be formed on the third lateral insulated external connection via structure {(936A, 934), (336A, 334)}. A solder ball 995 may be attached to the surface of each external bonding pad (938, 338).

[0283] With reference to all figures of the configuration related to the second exemplary structure and according to various embodiments, a bonding assembly is provided, which includes: a first semiconductor die (1000 or 900), the first semiconductor die including a first substrate (310 or 910) having a first distal planar surface and a first proximal planar surface, a first semiconductor device (which may include a three-dimensional memory array or a peripheral circuit) located on or above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer (which may be a memory side interconnect level dielectric layer 390 or a logic side interconnect level dielectric layer 990) including a first metal interconnect structure (which may be a memory side metal interconnect structure 370 or a logic side metal interconnect structure 970) electrically connected to the first semiconductor device, and a first die-to-die bonding pad (which may be a die-to-die bonding pad) located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure and a second semiconductor die (900 or 1000), the second semiconductor die including a second substrate (902 or 302) having a second distal planar surface and a second proximal planar surface, a second semiconductor device (which may include a peripheral circuit or a three-dimensional memory array) located on or above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer (which may be a memory side interconnect level dielectric layer 390 or a logic side interconnect level dielectric layer 990) including a second metal interconnect structure (which may be a memory side metal interconnect structure 370 or a logic side metal interconnect structure 970) electrically connected to the second semiconductor device, and a second die-to-die bonding pad (which may be a memory side bonding pad 378 or a logic side bonding pad 978) located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure. The second die-to-die bonding pad is bonded to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die. The first external bonding pad (938, 338) is located on or above the second distal planar surface of the second substrate (902, 302). The first lateral insulating external connection via structure {(936A, 934), (336A, 334)} extends vertically from at least the second distal planar surface of the second substrate (902, 302) through the second substrate (902, 302), the second interconnect level dielectric layer (990 or 390), a horizontal plane including the interface between the first semiconductor die and the second semiconductor die, and a subset of the layers within the first interconnect level dielectric layer (390 or 990), and extends to one of the first metal interconnect structures (374P or 974P) and contacts the first external bonding pad (938, 338). The bonding assembly may include a solder ball 995 bonded to the first external bonding pad (938, 338). In one embodiment, the second die-to-die bonding pad is bonded to the first die-to-die bonding pad by copper-to-copper bonding.

[0284] In one embodiment, the bonding assembly may include a second external bonding pad (938, 338) located on or above a second distal planar surface of the second substrate, and a second lateral insulating external connection via structure {(936B, 934), (336B, 334)}, which second lateral insulating external connection via structure extends vertically from at least the second distal planar surface of the second substrate (902, 302), through a subset of layers within the second substrate (902, 302) and the second interconnect level dielectric layer (902, 302), and extends to one of the second metal interconnect structures (370 or 970) and contacts the second external bonding pad (938, 338).

[0285] In one embodiment, the bonding assembly includes a third external bonding pad (938, 338) located on or above the second distal planar surface of the second substrate (902, 302), and a third lateral insulated external connecting via structure {(936A, 934), (336A, 334)}, the third lateral insulated external connecting via structure contacting the third external bonding pad (938, 338) and extending vertically from at least the second distal planar surface of the second substrate (902, 302), through the second substrate (902, 302), the second interconnect A level dielectric layer (990 or 390), a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and another subset of layers within the first interconnect level dielectric layer (390 or 990), and extending to another one of the first metal interconnect structures (374P or 974P), the other one having a vertical distance from the interface between the first semiconductor die and the second semiconductor die that is different from the vertical distance of the one of the first metal interconnect structures (374P or 974P) from the interface between the first semiconductor die and the second semiconductor die.

[0286] In one embodiment, the bonding assembly includes a first etch stop dielectric layer (364 or 964) that contacts a surface of said one of the first metal interconnect structures (374P or 974P) and laterally surrounds a first lateral insulating external connection via structure {(936A, 934), (336A, 334)}, and a second etch stop dielectric layer (964 or 364) that contacts a surface of said one of the second metal interconnect structures (974P or 374P) and laterally surrounds an end portion of a second lateral insulating external connection via structure {(936A, 934), (336A, 334)}.

[0287] In one embodiment, each lateral insulated external connection via structure {(936, 934), (336, 334)} includes: a tubular insulating spacer (934, 334) that contacts the sidewalls of the second substrate (902, 302), the second interconnect level dielectric layer (990 or 390), and a subset of layers within the first interconnect level dielectric layer (390 or 990); and a conductive post structure (936, 336) that is laterally surrounded by the tubular insulating spacer (934, 334) and contacts a planar surface of one of the first metal interconnect structures (374P or 974P).

[0288] A planar dielectric isolation layer (930, 330) may be located on the second distal planar surface of the second substrate (902, 302) and may contact the planar surface of each external bond pad (938, 338).

[0289] In one embodiment, one of the first semiconductor die and the second semiconductor die includes a memory die 1000 including a three-dimensional array of memory elements, and the other of the first semiconductor die and the second semiconductor die includes a logic die 900 including peripheral circuits configured to operate the three-dimensional array of memory elements.

[0290] In one embodiment, the first substrate and the second substrate include semiconductor substrates, the memory die 1000 includes a set of word lines for a three-dimensional array of memory elements and a set of bit lines 98 for the three-dimensional array of memory elements, and the peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines 98.

[0291] In one embodiment, the memory die 1000 includes an alternating stack of insulating layers (132, 232) and conductive layers (146, 246), and a two-dimensional array of memory stack structures 55 extending through the alternating stacks {(132, 146), (232, 246)}. Each of the memory stack structures 55 includes a respective vertical stack of memory elements positioned adjacent to respective vertical semiconductor channels 60, the two-dimensional array of memory stack structures 55 constitutes a three-dimensional array of memory elements, the bit lines 98 are connected to respective subsets of the vertical semiconductor channels 60, and the conductive layers (146, 246) include word lines.

[0292] refer to Fig.25A , a third exemplary structure is shown, which includes an exemplary process memory die. Fig.25A The memory die can be connected to the external connection via structure 386 by forming a through-dielectric external connection via structure 386 through the stepped dielectric material portion (165, 265) during the process. Fig.15A and Fig. 15BAn exemplary structure of is obtained. Specifically, a photoresist layer (not shown) may be applied over the second contact level dielectric layer 282 and photolithographically patterned to form an opening in the region of the interface between the first stepped dielectric material portion 165 and the memory side substrate 310. An anisotropic etching process is performed to form a through-hole cavity extending through the first contact level dielectric layer 280 and the second contact level dielectric layer 282 and the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265. The terminal portion of the anisotropic etching process may use the memory side substrate 310 as an etching stop structure. The photoresist layer may then be removed, for example, by ashing.

[0293] At least one conductive material may be deposited in the through-hole cavity and above the first contact level dielectric layer 280 and the second contact level dielectric layer 282. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the second contact level dielectric layer 282. The remaining portion of the at least one conductive material in the through-hole cavity constitutes a through-dielectric external connection via structure 386. In one embodiment, the at least one conductive material may be deposited simultaneously in the through-hole cavity extending to the top surface of the memory side substrate 310 and in the through-hole cavity used to form the drain contact via structure 88 and the staircase area contact via structure 86. In this case, the through-dielectric external connection via structure 386 may include the same conductive material as the drain contact via structure 88 and the staircase area contact via structure 86. Alternatively, the at least one conductive material may be deposited in the through-hole cavity extending to the top surface of the memory side substrate 310 before or after the drain contact via structure 88 and the staircase area contact via structure 86 are formed.

[0294] refer to Fig.25B , executable Fig.16 A bitline level dielectric layer 284 may be formed over the contact level dielectric layer (280, 282), and a bitline level metal interconnect structure (98, 96) may be formed in the bitline level dielectric layer 284. The bitline level metal interconnect structure (98, 96) includes a bitline 98 electrically connected to a corresponding subset of drain regions 63 through a corresponding subset of drain contact via structures 88. The bitline level metal interconnect structure (98, 96) includes an interconnect line structure 96 electrically connected to at least one of the staircase region contact via structure 86 or other via structures.

[0295] The memory side interconnect level dielectric layer 390 may be formed above the bit line level dielectric layer 284 and the bit line level metal interconnect structure (98, 96). Various memory side metal interconnect structures 370 may be formed in the memory side interconnect level dielectric layer 390 to provide electrical connections to the bit line 98 and the interconnect line structure 96. The memory side metal interconnect structure 370 may include an interconnect level metal line structure 374 and an interconnect level metal via structure 376. The memory side bonding pad 378 may be formed in or on the uppermost layer of the memory side interconnect level dielectric layer 390. The memory side bonding pad 378 is a die-to-die bonding pad that provides bonding of the memory die 1000 to another die. In one embodiment, a subset of the memory side interconnect level dielectric layer 390 and the memory side bonding pad 378 are formed above the through dielectric external connection via structure 386. A subset of the memory-side bond pads 378 may be electrically connected to a through-dielectric external connection via structure 386 .

[0296] The third exemplary structure includes a memory die 1000. The memory die 1000 includes a memory side substrate 310, an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) having a stepped surface and located on the memory side substrate 310, a memory stack structure 55 extending vertically through the alternating stacks [(132, 146), (232, 246)], a stepped dielectric material portion (165 and / or 265) contacting the stepped surface of the alternating stacks {(132, 146), (232, 246)}, a through dielectric external connection via structure 386 extending vertically through the stepped dielectric material portion (165 and / or 265), a memory side metal interconnect structure 370 included in a memory side interconnect level dielectric layer 390, and a memory side bonding pad 378. The memory stack structure 55 may include a three-dimensional array of memory elements.

[0297] The memory die 1000 may include a set of word lines (including conductive layers (146, 246) for a three-dimensional array of memory elements and a set of bit lines 98 for a three-dimensional array of memory elements. Each of the memory stack structures 55 may include a corresponding vertical semiconductor channel 60, the vertical semiconductor channel including a distal end (such as a distal end) electrically connected to a surface portion of a memory side substrate 310 directly or through a corresponding base channel portion 11. Figure 8H shown).

[0298] refer to Fig.25C , a logic die 900 is provided, such as Fig. 20BLogic die 900. Logic die 900 includes a logic side substrate, which is a semiconductor substrate. Logic die 900 includes: a semiconductor device located on the semiconductor substrate and including a peripheral circuit configured to control the operation of the memory stack structure 55 within the memory die 1000, a logic side metal interconnect structure 970 included in a logic side interconnect level dielectric layer 990, and a logic side bonding pad 978. Specifically, logic die 900 includes a peripheral circuit configured to drive at least one of the group of word lines (including conductive layers (146, 246)) and the group of bit lines 98 in memory die 1000. In one embodiment, memory die 1000 and logic die 900 can be designed so that the pattern of the logic side bonding pad 978 of logic die 900 is mirrored with the pattern of the memory side bonding pad 378 of memory die 1000.

[0299] The memory die 1000 and the logic die 900 can be bonded to each other by metal-to-metal bonding (such as copper-to-copper bonding). The memory side bonding pads 378 can be bonded to the logic side bonding pads 978 to form a die-to-die bonding interface between the memory die 1000 and the logic die 900. The bit lines 98 are connected to corresponding subsets of the vertical semiconductor channels 60 and are connected to bit line drivers within the peripheral circuit through a first conductive path, which includes the memory side bonding pads 378 and a first bonded subset of the logic side bonding pads 978. The conductive layer (146, 246) includes word lines and is connected to word line drivers within the peripheral circuit through a second conductive path, which includes the memory side bonding pads 378 and a second bonded subset of the logic side bonding pads 978.

[0300] refer to Fig.25D , the memory side substrate 310 can be thinned from the back side, for example by grinding the back side portion of the memory side substrate 310 to provide a thinned memory side substrate 302, which is a semiconductor material layer used as a source contact layer of the vertical semiconductor channel 60. The source semiconductor layer is electrically connected to the distal end of the vertical semiconductor channel 60 (i.e., the end located on the opposite side of the drain region 63). The thinned memory side substrate 302 can have a thickness in the range of 100μm to 100μm (such as 3μm to 30μm), but smaller and larger thicknesses can also be used. Optionally, ion implantation can be performed into the thinned memory side substrate 302 to provide suitable doping to the source layer.

[0301] refer to Fig.25E, the distal flat surface of each through-dielectric external connection via structure 386 can be physically exposed by removing at least a portion of the thinned memory side substrate 302. For example, a photoresist layer (not shown) can be applied over the back side of the thinned memory side substrate 302 and photolithographically patterned over the memory array area 100 without covering the area of ​​the interface between the first stepped dielectric material portion 165 and the thinned memory side substrate 302. The area of ​​the staircase area may or may not be covered by the patterned photoresist layer. An anisotropic etch can be performed using the photoresist layer as an etch mask, which anisotropically etches the material of the thinned memory side substrate 302 that is selective to the material of the first stepped dielectric material portion 165 and the through-dielectric external connection via structure 386. The thinned memory side substrate 302 is patterned by anisotropic etching. The distal surface of the through-dielectric external connection via structure 386 is physically exposed. In one embodiment, the distal surface of the through-dielectric external connection via structure 386 may be coplanar with the distal planar surface of the first stepped dielectric material portion 165 .

[0302] refer to Fig.25F , a metal bonding pad material such as aluminum or a UBM layer stack may be deposited by an anisotropic deposition process or an isotropic deposition process, and may be subsequently patterned to form an external bonding pad 338. For example, a discrete photoresist material portion may be formed over the deposited metal bonding pad material to cover discrete regions of the metal bonding pad material that cover a portion of the source contact layer that penetrates the dielectric external connection via structure 386 and the thinned memory side substrate 302. An etching process may be performed to remove the unmasked portion of the metal bonding pad material. The remaining portion of the metal bonding pad material below the discrete photoresist material portion constitutes the external bonding pad 338.

[0303] A solder ball 995 may be attached to each external bonding pad 338. A solder material dispensing tool may be used to apply the solder ball 995 to the external bonding pad 338. In one embodiment, the through dielectric external connection via structure 386 and the external bonding pad 938 may be arranged in a one-dimensional periodic array or a two-dimensional periodic array. A bonding wire 997 may be bonded to each solder ball 995.

[0304] Generally, the external bonding pad 338 may be formed on the distal flat surface of each through-dielectric external connection via structure 386. Each through-dielectric external connection via structure 386 contacts the sidewalls of the dielectric material portion such as the stepped dielectric material portion (165, 265) and the first contact level dielectric layer 280 and the second contact level dielectric layer 282. In one embodiment, the entire sidewall of each through-dielectric external connection via structure 386 may contact only the dielectric surface.

[0305] In one embodiment, the memory die 1000 includes a source contact layer (including the thinned memory side substrate 302) electrically connected to the distal end of the vertical semiconductor channel 60 after physically exposing the distal planar surface of the through-dielectric external connection via structure 386. In one embodiment, each of the memory stack structures 55 includes a corresponding vertical semiconductor channel 60 including a distal end electrically connected to the source contact layer, which is embodied as the thinned memory side substrate 302. The thinned memory side substrate 302 is the remaining portion of the memory side substrate 310 after removing the distal portion of the memory side substrate 310. In this case, the source contact layer includes the remaining portion of the doped semiconductor material portion disposed within the memory side substrate 310.

[0306] In general, the external bonding pads 338 may be formed by depositing and patterning a conductive material on the distal planar surface of the through-dielectric external connection via structure 386 and the first planar horizontal surface (i.e., the distal planar surface) of the stepped dielectric material portion 165. A solder ball 995 may be bonded to each of the external bonding pads 338. Additional external bonding pads 338 may be formed on the distal planar surface of the source semiconductor layer.

[0307] refer to Figure 25G , an alternative configuration of the third exemplary structure can be derived from the third exemplary structure. If a silicon-on-insulator type substrate is used, the memory side substrate 301 can be completely removed to expose the insulating layer 308. In this case, the bottom end of the vertical semiconductor channel can be electrically connected to the semiconductor material layer 309. After the memory tube core is bonded to the logic tube core, the substrate 301 can be removed, for example, by grinding, polishing, isotropic etching and / or anisotropic etching. The through-hole cavity can be formed to pass through the backward stepped dielectric material portion (165, 265) and the memory side interconnection level dielectric layer 390, so that the back side of the corresponding memory side bonding pad 378 is physically exposed at the bottom of each through-hole cavity. A through-dielectric external connection through-hole structure 386 can be formed in the through-hole cavity. The through-dielectric external connection through-hole structure 386 can be used as a conductive path between the memory side bonding pad 378 and the back side of the memory tube core. The external bonding pad 338 may be formed on each of the through-dielectric external connection via structures 386. In this embodiment, the through-dielectric external connection via structures 386 may be formed directly on the memory-side bonding pad 378.

[0308] refer to Fig.26A and Fig.26B , shows another in-process memory die that can be used in another configuration of the third exemplary structure. Fig.26A and Fig.26BIn the process of the memory die can be formed between the memory side substrate 310 and the first alternating stack (132, 142) by forming the source material layer 101' in the process. Figure 1 A first exemplary structure results.

[0309] The source level material layer 101' in the process may include various layers that are subsequently modified to form the source level material layer. The source level material layer includes a source contact layer when formed, which is used as a common source region of the vertical field effect transistor of the three-dimensional memory device. In one embodiment, the source level material layer 10' in the process may include a lower sacrificial liner 103, a source level sacrificial layer 104, a higher sacrificial liner 105, a higher source level material layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118 from bottom to top.

[0310] The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in the range of 2nm to 30nm, although smaller and larger thicknesses can also be used.

[0311] The source level sacrificial layer 104 comprises a sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the upper sacrificial pad 105. In one embodiment, the source level sacrificial layer 104 can comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30nm to 400nm, such as 60nm to 200nm, but smaller and larger thicknesses can also be used.

[0312] The higher source level material layer 116 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the higher source level material layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the higher source level material layer 116 has a doping of a second conductivity type opposite to the first conductivity type. The thickness of the higher source level material layer 116 may be in the range of 10nm to 300nm (such as 20nm to 150nm), but smaller and larger thicknesses may also be used.

[0313] The source level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 may be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, although smaller and larger thicknesses may also be used. The optional source select level conductive layer 118 may include a conductive material that may be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which may subsequently be converted into doped polysilicon by an annealing process. The thickness of the optional source select level conductive layer 118 may be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0314] Then, you can execute Figures 2 to 7 The processing steps are performed to form the storage opening 49 and the support opening 19. FIG. 27A to FIG. 27D The processing steps shown are to form a reservoir opening fill structure 58 within each reservoir opening 49 and to form a support structure 20 within each support opening 19 .

[0315] refer to Fig.27A , showing Fig.26A and Fig.26B The memory opening 49 in the third exemplary device structure of FIG. 4 extends through the first layer structure and the second layer structure.

[0316] refer to Fig.27B , a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0317] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2nm to 20nm, although smaller and larger thicknesses can also be used.

[0318] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0319] The semiconductor channel material layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. There is a memory cavity 49' in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0320] refer to Fig.27C , in the case where the memory cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating cap layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0321] refer to Fig.27D , a doped semiconductor material may be deposited in the cavity covering the dielectric core 62. The doped semiconductor material has a doping of a conductivity type opposite to the doping of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has a doping of a second conductivity type. Portions of the deposited doped semiconductor material, the semiconductor channel material layer 60L, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 covering the horizontal plane (which includes the top surface of the second insulating cap layer 270) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0322] Each remaining portion of the doped semiconductor material having the doping of the second conductivity type constitutes a drain region 63. The drain region 63 may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain region 63 may be between 5.0×10 19 / cm 3Up to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0323] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0324] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunnel dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 158. In the process, the source level material layer 101', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265, 72), the interlayer dielectric layer 180, and the memory opening filling structure 158 together constitute a memory level component.

[0325] refer to Fig.28 , which can be done by executing Fig. 10A and Fig. 10B The first contact level dielectric layer 280 and the backside trench 79 are formed by the processing steps. The backside trench can extend vertically through the source level material layer 101', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265, 72), the interlayer dielectric layer 180, and into the top portion of the memory side substrate 310.

[0326] refer to Fig.29A, backside trench spacers 174 may be formed on the sidewalls of each backside trench 79. For example, a conformal spacer material layer may be deposited in the backside trenches 79 and over the first contact-level dielectric layer 280, and may be anisotropically etched to form the backside trench spacers 174. The backside trench spacers 174 include a material different from that of the source-level sacrificial layer 104. For example, the backside trench spacers 174 may include silicon nitride.

[0327] refer to Fig.29B In an isotropic etching process, an etchant that selectively etches the material of the source level sacrificial layer 104 to the material of the first alternating stack (132, 142), the second alternating stack (232, 242), the first insulating capping layer 170 and the second insulating capping layer 270, the first contact level dielectric layer 280, the upper sacrificial liner 105, and the lower sacrificial liner 103 can be introduced into the backside trench. For example, if the source level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, the backside trench spacers 174 comprise silicon nitride, and the upper and lower sacrificial liners (105, 103) comprise silicon oxide, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) can be used to selectively remove the source level sacrificial layer 104 to the backside trench spacers 174 and the upper and lower sacrificial liners (105, 103). A source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0328] Wet etching chemistries such as hot TMY and TMAH are selective to doped semiconductor materials such as p-doped semiconductor materials and / or doped semiconductor materials of the higher source level semiconductor layer 116 and the memory side substrate 310. Therefore, the use of selective wet etching chemistries such as hot TMY and TMAH in the wet etching process of forming the source cavity 109 provides a larger process window against etching depth variations during the formation of the backside trench 79. Specifically, when forming the source cavity 109 and / or the backside trench spacer 174, even if the sidewalls of the higher source level semiconductor layer 116 are physically exposed or even if the surface of the memory side substrate 310 is physically exposed, the incidental etching of the higher source level semiconductor layer 116 and / or the memory side substrate 310 is minimal, and structural changes of the exemplary structure caused by accidental physical exposure of the surface of the higher source level semiconductor layer 116 and / or the memory side substrate 310 during the manufacturing steps do not cause device failure. Each of the memory opening filling structures 158 is physically exposed to the source cavity 109 . Specifically, each of the memory opening filling structures 158 includes a sidewall and a bottom surface that are physically exposed to the source cavity 109 .

[0329] refer to Fig.29C , a series of isotropic etchants (such as wet etchants) may be applied to the physically exposed portions of the memory film 50 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower sacrificial liners (105, 103) may be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The volume of the source cavity 109 may be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower sacrificial liners (105, 103). The top surface of the memory-side substrate 310 and the bottom surface of the higher source-level semiconductor layer 116 may be physically exposed to the source cavity 109. The source cavity 109 is formed by isotropically etching the source level sacrificial layer 104 and the bottom portion of each memory film 50 selectively to at least one source level semiconductor layer such as the memory side substrate 310 and the upper source level semiconductor layer 116 and the vertical semiconductor channel 60 .

[0330] refer to Fig.29D , a semiconductor material having a doping of the second conductivity type may be deposited on physically exposed semiconductor surfaces around the source cavity 109. The physically exposed semiconductor surfaces include the bottom portion of the outer sidewalls of the vertical semiconductor channel 60, the bottom surface of the higher source level semiconductor layer 116, and the top surface of the memory side substrate 310.

[0331] In one embodiment, a doped semiconductor material of a second conductivity type may be deposited on the physically exposed semiconductor surface around the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and an n-type dopant precursor gas may flow simultaneously into a processing chamber including the exemplary structure. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, and the etchant gas may include gaseous hydrogen chloride and an n-type dopant precursor gas such as phosphine, arsine, or antimonide. In this case, the selective semiconductor deposition process grows an n-doped semiconductor material from the physically exposed semiconductor surface around the source cavity 109. The deposited n-doped semiconductor material forms a source contact layer 114, which may contact the sidewalls of the vertical semiconductor channel 60. The atomic concentration of the n-type dopant in the deposited semiconductor material may be between 1.0×10 20 / cm 3 Up to 2.0×10 21 / cm 3 In the range (such as 2.0×10 20 / cm 3 Up to 8.0×10 20 / cm 3). The initially formed source contact layer 114 may consist essentially of semiconductor atoms and n-type dopant atoms. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch-back processes may be used in combination with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0332] The duration of the selective semiconductor deposition process can be selected so that the source cavity 109 is filled with the source contact layer 114, and the source contact layer 114 contacts the bottom end portion of the inner sidewall of the back trench spacer 174. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material from a semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material can include doped polysilicon. Therefore, the source level sacrificial layer 104 can be replaced by the source contact layer 114.

[0333] The layer stack including source contact layer 114 and higher source level semiconductor layer 116 constitutes buried source layer (114, 116). The layer group including buried source layer (114, 116), source level insulating layer 117 and source selection level conductive layer 118 constitutes source level material layer 101, which replaces source level material layer 101' during the replacement process.

[0334] refer to Fig.29E , an isotropic etching process may be used to selectively remove the backside trench spacers 174 with respect to the insulating layer (132, 232), the first insulating capping layer 170 and the second insulating capping layer 270, the first contact level dielectric layer 280, and the source contact layer 114. For example, if the backside trench spacers 174 include silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the backside trench spacers 174. In one embodiment, the isotropic etching process to remove the backside trench spacers 174 may be combined with a subsequent isotropic etching process that selectively etches the sacrificial material layer (142, 242) with respect to the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the first contact level dielectric layer 280, and the source contact layer 114.

[0335] An oxidation process may be performed to convert physically exposed surface portions of semiconductor material into dielectric semiconductor oxide portions. For example, surface portions of source contact layer 114 and upper source level material layer 116 may be converted into dielectric semiconductor oxide plates 122, and surface portions of source select level conductive layer 118 may be converted into annular dielectric semiconductor oxide spacers 124.

[0336] refer to Fig.30, executable Fig.11 , Fig. 12A and Fig. 12B and Fig.13 The process steps are to replace the sacrificial material layer (142, 242) with the conductive layer (146, 246). The first conductive layer 146 replaces the first sacrificial material layer 142, and the second conductive layer 246 replaces the second sacrificial material layer 242. A dielectric material is deposited in the backside trench 79 to form a dielectric wall structure 176. Each of the dielectric wall structures 176 can extend laterally along the first horizontal direction hd1, and can extend vertically through each layer of the alternating stack of insulating layers (132, 232) and conductive layers (146, 246). Each dielectric wall structure 176 can contact the sidewalls of the first and second insulating capping layers (170, 270).

[0337] refer to Fig.31 The second contact level dielectric layer 282, the drain contact via structure 88 and the staircase area contact via structure 86 can be formed by performing Fig.15A and Fig. 15B The processing steps are formed. Fig.25A The processing steps are performed to form a through-dielectric external connection via structure 386 passing through the stepped dielectric material portion (165, 265).

[0338] refer to Fig.32 , you can execute Fig.25B The processing steps are to form the bit line level dielectric layer 284, the bit line level metal interconnect structure (98, 96), the memory side interconnect level dielectric layer 390, the various memory side metal interconnect structures 370 and the memory side bonding pads 378.

[0339] The third exemplary structure includes a memory die 1000. The memory die 1000 includes a memory side substrate 310, an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) having a stepped surface and located on the memory side substrate 310, a memory stack structure 55 extending vertically through the alternating stack {(132, 146), (232, 246)}, a stepped dielectric material portion (165 and / or 265) contacting the stepped surface of the alternating stack {(132, 146), (232, 246)}, a through dielectric external connection via structure 386 extending vertically through the stepped dielectric material portion (165 and / or 265), a memory side metal interconnect structure 370 included in a memory side interconnect level dielectric layer 390, and a memory side bonding pad 378. The memory stack structure 55 may include a three-dimensional array of memory elements.

[0340] The memory die 1000 may include a set of word lines (including conductive layers (146, 246) for a three-dimensional array of memory elements and a set of bit lines 98 for a three-dimensional array of memory elements. Each of the memory stack structures 55 may include a corresponding vertical semiconductor channel 60, the vertical semiconductor channel including a distal end (such as a distal end) electrically connected to a surface portion of a memory side substrate 310 directly or through a corresponding base channel portion 11. Figure 8H shown).

[0341] refer to Fig.33A , a logic die 900 is provided, such as Fig. 20B Logic die 900. Logic die 900 includes a logic side substrate, which is a semiconductor substrate. Logic die 900 includes: a semiconductor device located on the semiconductor substrate and including a peripheral circuit configured to control the operation of the memory stack structure 55 within the memory die 1000, a logic side metal interconnect structure 970 included in a logic side interconnect level dielectric layer 990, and a logic side bonding pad 978. Specifically, logic die 900 includes a peripheral circuit configured to drive at least one of the group of word lines (including conductive layers (146, 246)) and the group of bit lines 98 in memory die 1000. In one embodiment, memory die 1000 and logic die 900 can be designed so that the pattern of the logic side bonding pad 978 of logic die 900 is mirrored with the pattern of the memory side bonding pad 378 of memory die 1000.

[0342] The memory die 1000 and the logic die 900 can be bonded to each other by metal-to-metal bonding (such as copper-to-copper bonding). The memory side bonding pad 378 can be bonded to the logic side bonding pad 978 to form a die-to-die bonding interface between the memory die 1000 and the logic die 900. The bit line 98 is connected to a corresponding subset of the vertical semiconductor channel 60 and is connected to a bit line driver within the peripheral circuit through a first conductive path, which includes the memory side bonding pad 378 and a first bonding subset of the logic side bonding pad 978. The conductive layer (146, 246) includes a word line and is connected to a word line driver within the peripheral circuit through a second conductive path, which includes the memory side bonding pad 378 and a second bonding subset of the logic side bonding pad 978. The memory die 1000 includes a source material layer 101 located between the memory side substrate 310 and the alternating stack {(132, 146), (232, 246)}. The source level material layer includes a source contact layer 114 contacting the sidewalls of the vertical semiconductor channel 60. The source contact layer 114 includes a doped semiconductor material portion disposed between the memory side substrate 310 and the alternating stacks {(132, 146), (232, 246)}.

[0343] refer to Fig.33B , the memory side substrate 310 can be thinned from the back side, for example by grinding the back side portion of the memory side substrate 310 to provide a thinned memory side substrate 302, which is a semiconductor material layer used as a source contact layer of the vertical semiconductor channel 60. The source semiconductor layer is electrically connected to the distal end of the vertical semiconductor channel 60 (i.e., the end located on the opposite side of the drain region 63). The thinned memory side substrate 302 can have a thickness in the range of 100μm to 100μm (such as 3μm to 30μm), but smaller and larger thicknesses can also be used. Optionally, ion implantation can be performed into the thinned memory side substrate 302 to provide suitable doping to the source layer.

[0344] refer to Fig.33C , the thinned memory side substrate 302 can be removed by an etching process that is selective to the material of the first stepped dielectric material portion 165 and the through dielectric external connection via structure 386. In one embodiment, the anisotropic etching process can be performed using the first stepped dielectric material portion 165 as an endpoint detection layer. The thinned memory side substrate 302 can be removed to physically expose the horizontal surface of the source level material layer 101. For example, after removing the thinned memory side substrate 302, the distal surface of the source contact layer 114 can be physically exposed.

[0345] After the memory-side bonding pad 378 is bonded to the logic-side bonding pad 978 , the entire memory-side substrate 310 is removed to physically expose the flat surface of the source level material layer 101 . The source level material layer 101 includes a source contact layer 114 .

[0346] refer to Fig.33D , a metal bonding pad material such as aluminum or a UBM layer stack may be deposited on the distal flat surface of the first stepped dielectric material portion 165 and the source level material layer 101 (such as the distal surface of the source contact layer 114) by an anisotropic deposition process or an isotropic deposition process, and may be subsequently patterned to form an external bonding pad 338. For example, a discrete photoresist material portion may be formed over the deposited metal bonding pad material to cover discrete areas of the metal bonding pad material that cover a portion of the through dielectric external connection via structure 386 and the source contact layer 114. An etching process may be performed to remove the unmasked portion of the metal bonding pad material. The remaining portion of the metal bonding pad material below the discrete photoresist material portion constitutes the external bonding pad 338.

[0347] A solder ball 995 may be attached to each external bonding pad 338. A solder material dispensing tool may be used to apply the solder ball 995 to the external bonding pad 338. In one embodiment, the through dielectric external connection via structure 386 and the external bonding pad 338 may be arranged in a one-dimensional periodic array or a two-dimensional periodic array. A bonding wire 997 may be bonded to each solder ball 995.

[0348] Generally, the external bonding pad 338 may be formed on the distal flat surface of each through-dielectric external connection via structure 386. Each through-dielectric external connection via structure 386 contacts the sidewalls of the dielectric material portion such as the stepped dielectric material portion (165, 265) and the first contact level dielectric layer 280 and the second contact level dielectric layer 282. In one embodiment, the entire sidewall of each through-dielectric external connection via structure 386 may contact only the dielectric surface.

[0349] In one embodiment, the memory die 1000 includes a source contact layer 114 electrically connected to a distal end of the vertical semiconductor channel 60 after physically exposing a distal planar surface of the through-dielectric external connection via structure 386. In one embodiment, each of the memory stack structures 55 includes a corresponding vertical semiconductor channel 60 including a distal end electrically connected to the source semiconductor layer 114.

[0350] In general, the external bonding pads 338 may be formed by depositing and patterning a conductive material on the distal planar surface of the through-dielectric external connection via structure 386 and the first planar horizontal surface (i.e., the distal planar surface) of the stepped dielectric material portion 165. A solder ball 995 may be bonded to each of the external bonding pads 338. Additional external bonding pads 338 may be formed on the distal planar surface of the source semiconductor layer.

[0351] With reference to all figures related to the third exemplary structure and in accordance with various embodiments of the present disclosure, a bonding assembly includes: a memory die 1000 including an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) having stepped surfaces, a memory stack structure 55 extending vertically through the alternating stack {(132, 146), (232, 246)}, a stepped dielectric material portion 165 contacting the stepped surface of the alternating stack {(132, 146), (232, 246)}, a through dielectric external connection via structure 386 extending vertically through the stepped dielectric material portion; and a memory side metal interconnect structure including a memory side interconnect level dielectric layer 390. 370, and a memory side bonding pad 378; a logic die 900, the logic die including a semiconductor substrate (910 or 902), a semiconductor device located on the semiconductor substrate (910 or 902) and including peripheral circuits configured to control the operation of a memory stack structure 55 within the memory die, a logic side metal interconnect structure 970 included in a logic side interconnect level dielectric layer 990, and a logic side bonding pad 978 bonded to the memory side bonding pad 378 of the memory die 1000 at a die-to-die bonding interface; and an external bonding pad 338, the external bonding pad being located on a surface of the stepped dielectric material portion 165 and contacting a distal flat surface of a through-dielectric external connection via structure 386.

[0352] In one embodiment, the distal planar surface of the through-dielectric external connection via structure 386 lies within a horizontal plane that includes the first planar horizontal surface of the stepped dielectric material portion 165 .

[0353] In one embodiment, the through dielectric external connection via structure 386 includes a proximal planar surface that contacts one of the memory side metal interconnect structures 370; and the proximal planar surface is vertically spaced apart from a horizontal plane including the die-to-die bonding interface by a vertical spacing distance that is smaller than a vertical spacing distance between the memory stack structure 55 and the horizontal plane including the die-to-die bonding interface.

[0354] In one embodiment, a solder ball 995 may be bonded to each external bond pad 338 .

[0355] In one embodiment, the logic side bond pads are bonded to the memory side bond pads by copper to copper bonding.

[0356] In one embodiment, each of the memory stack structures 55 includes a corresponding vertical semiconductor channel 60, which includes a proximal end and a distal end, the distal end being vertically spaced apart from a horizontal plane including a die-to-die bonding interface by a vertical distance greater than the vertical distance between the proximal end and the horizontal plane including the die-to-die bonding interface; and a source semiconductor layer (114 or 302) is located on the alternating stack {(132, 146), (232, 246)} and is electrically connected to the distal end of the vertical semiconductor channel 60.

[0357] In one embodiment, the distal planar surface of the through-dielectric external connection via structure 386 lies within a horizontal plane including the planar surface of the source semiconductor layer (114 or 302), which is parallel to a horizontal plane including the die-to-die bonding interface.

[0358] In one embodiment, the source semiconductor layer including the thinned memory side substrate 302 is electrically connected to the distal end of the vertical semiconductor channel 60 by: direct contact between the source semiconductor layer (114, 302) and the horizontal planar surface of the distal end of the vertical semiconductor channel 60 (in the absence of the base channel portion 11), or direct contact between the source semiconductor layer (114, 302) and the horizontal planar surface of the distal end of the vertical semiconductor channel 60 through the base channel portion 11.

[0359] In one embodiment, the source contact layer is electrically connected to the distal end of the vertical semiconductor channel 60 through direct contact between the cylindrical sidewall surface of the distal end of the vertical semiconductor channel 60 and the source semiconductor layer 114 .

[0360] In one embodiment, additional external bonding pads 338 may be located on the distal planar surface of the source semiconductor layer (302, 114).

[0361] In one embodiment, the memory stack structure 55 includes a three-dimensional array of memory elements; the memory die 1000 includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines 98 for the three-dimensional array of memory elements; and the peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines 98.

[0362] In one embodiment, the bit lines 98 are connected to a corresponding subset of the vertical semiconductor channels 60 and are connected to a bit line driver within the peripheral circuit via a first conductive path, the first conductive path including a first bonding subset of the memory side bonding pads 378 and the logic side bonding pads 978; and the conductive layer (146, 246) includes a word line and is connected to a word line driver within the peripheral circuit via a second conductive path, the second conductive path including a second bonding subset of the memory side bonding pads 378 and the logic side bonding pads 978.

[0363] Various embodiments include bonded semiconductor structures and methods of fabricating such structures suitable for use in three-dimensional memory devices that can be fabricated at a lower cost than conventional structures and methods, thereby saving on manufacturing costs.

[0364] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the claims. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the claims may be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A joint assembly comprising: a first semiconductor die comprising: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer including a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bond pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; and a second semiconductor die comprising: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer including a second metal interconnect structure electrically connected to the second semiconductor device, and a second die-to-die bond pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure, in: the second die-to-die bond pad being bonded to the first die-to-die bond pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; an external bonding pad on or in one of the first interconnect level dielectric layer and the second interconnect level dielectric layer, the external bonding pad having a physically exposed horizontal surface; and The external bond pad is entirely within a first horizontal plane including the first proximal planar surface of the first substrate and a second horizontal plane including the second proximal planar surface of the second substrate. 2 . The bonded assembly of claim 1 , further comprising a solder ball bonded to the external bond pad. 3 . The bonded assembly of claim 1 , wherein the second die-to-die bond pad is bonded to the first die-to-die bond pad by copper-to-copper bonding.

4. The engagement assembly of claim 1, further comprising a recessed region having a void, wherein the recessed region extends vertically from the second distal planar surface, through the second proximal planar surface, and to the physically exposed horizontal surface.

5. The bonding assembly of claim 4, wherein the recessed region comprises at least one substantially vertical sidewall extending continuously from the second distal planar surface to the physically exposed horizontal surface and to a surface of the external bonding pad.

6. The joint assembly of claim 4, wherein: The external bond pad is directly on or included within one of the second interconnect level dielectric layers in the second semiconductor die; and The physically exposed horizontal surface includes a horizontal surface of one of the second interconnect level dielectric layers.

7. The joint assembly of claim 4, wherein: The external bond pad is directly on or included within one of the first interconnect level dielectric layers in the first semiconductor die; and The physically exposed horizontal surface includes a horizontal surface of one of the first interconnect level dielectric layers. 8 . The bonded assembly of claim 7 , wherein an edge of an interface between the first semiconductor die and the second semiconductor die is physically exposed to the recessed region.

9. The joint assembly of claim 1, wherein: One of the first semiconductor die and the second semiconductor die comprises a memory die including a three-dimensional array of memory elements; and The other of the first semiconductor die and the second semiconductor die includes a logic die including peripheral circuitry configured to operate the three-dimensional array of memory elements.

10. The joint assembly of claim 9, wherein: The first substrate and the second substrate include semiconductor substrates; The memory die includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines for the three-dimensional array of memory elements; and The peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines.

11. The bonded assembly of claim 10, wherein the memory die comprises: Alternating stacking of insulating and conducting layers; and extending through the two-dimensional array of alternately stacked memory stack structures, in: Each of the memory stack structures includes a respective vertical stack of memory elements positioned adjacent to a respective vertical semiconductor channel; The two-dimensional array of memory stacked structures constitutes the three-dimensional array of memory elements; The bit lines are connected to respective subsets of the vertical semiconductor channels; and The conductive layer includes the word line.

12. A bonding assembly according to claim 1, wherein the external bonding pad is electrically connected to one of the first die-to-die bonding pad and the second die-to-die bonding pad through a vertically extending portion of the external bonding pad or a vertically extending conductive structure, and the vertically extending portion or the vertically extending conductive structure directly contacts the external bonding pad and one of the first die-to-die bonding pad and the second die-to-die bonding pad.

13. A method of forming a joint assembly, comprising: providing a first semiconductor die, wherein the first semiconductor die comprises: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer including a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bond pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; providing a second semiconductor die, wherein the second semiconductor die comprises: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer including a second metal interconnect structure electrically connected to the second semiconductor device, and a second die-to-die bond pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure; bonding the second die-to-die bond pad to the first die-to-die bond pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; forming a recessed region by removing a portion of material extending vertically from the second distal planar surface through the second substrate and into the volume of the second proximal planar surface to provide a physically exposed horizontal surface of one of the first interconnect level dielectric layer and the second interconnect level dielectric layer; and An external bond pad is provided on or in one of the first interconnect level dielectric layer and the second interconnect level dielectric layer.

14. The method according to claim 13, wherein: The external bond pad is formed in one of the first interconnect level dielectric layer and the second interconnect level dielectric layer during formation of the first metal interconnect structure or during formation of the second metal interconnect structure; and The flat horizontal surface of the outer bonding pad is physically exposed after forming the recessed area.

15. The method of claim 13, wherein the external bonding pad is formed by depositing and patterning a metal material on a flat horizontal surface of a metal interconnect structure, the metal interconnect structure included within one of the first interconnect level dielectric layer and the second interconnect level dielectric layer, the first interconnect level dielectric layer and the second interconnect level dielectric layer being physically exposed after forming the recessed area.

16. The method of claim 13, further comprising attaching a solder ball to a surface of the external bond pad. 17 . The method of claim 13 , wherein the second die-to-die bond pad is bonded to the first die-to-die bond pad by copper-to-copper bonding.

18. The method of claim 13, wherein the physically exposed horizontal surface is a horizontal surface of one of the second interconnect level dielectric layers.

19. The method of claim 13, wherein the physically exposed horizontal surface is a horizontal surface of one of the first interconnect level dielectric layers.

20. The method of claim 13, wherein: One of the first semiconductor die and the second semiconductor die comprises a memory die including a three-dimensional array of memory elements; and The other of the first and second semiconductor dies includes a logic die including peripheral circuitry configured to operate the three-dimensional array of memory elements.

21. The method of claim 20, wherein: The first substrate and the second substrate include semiconductor substrates; The memory die includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines for the three-dimensional array of memory elements; and The peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines.

22. A joint assembly comprising: a first semiconductor die comprising: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer including a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bond pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; and a second semiconductor die comprising: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer including a second metal interconnect structure electrically connected to the second semiconductor device, and a second die-to-die bond pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure, in: the second die-to-die bond pad being bonded to the first die-to-die bond pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; a first external bond pad is located over the second distal planar surface of the second substrate; and a first lateral insulating external connecting via structure extending vertically from at least the second distal planar surface of the second substrate, through the second substrate, the second interconnect level dielectric layer, a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and a subset of layers within the first interconnect level dielectric layer, and extending to one of the first metal interconnect structures and contacting the first external bonding pad, a second external bonding pad located above the second distal planar surface of the second substrate; a second lateral insulated external connecting via structure extending vertically from the second distal planar surface of the second substrate through at least a subset of layers within the second substrate and the second interconnect level dielectric layer and extending to one of the second metal interconnect structures and contacting the second external bonding pad, a third external bonding pad located above the second distal planar surface of the second substrate; a third lateral insulated external connecting via structure contacting the third external bonding pad and extending vertically from at least the second distal planar surface of the second substrate, through the second substrate, the second interconnect level dielectric layer, the horizontal plane including the interface between the first semiconductor die and the second semiconductor die, and another subset of layers within the first interconnect level dielectric layer, and to another one of the first metal interconnect structures, the other one having a vertical distance from the interface between the first semiconductor die and the second semiconductor die that is different from a vertical distance of the one of the first metal interconnect structures from the interface between the first semiconductor die and the second semiconductor die, and A solder ball is bonded to the first external bond pad.

23. The bonded assembly of claim 22, wherein the second die-to-die bond pad is bonded to the first die-to-die bond pad by copper-to-copper bonding.

24. The engagement assembly of claim 22, further comprising: a first etch stop dielectric layer contacting a surface of said one of said first metal interconnect structures and laterally surrounding an end portion of said first lateral insulating external connecting via structure; and A second etch stop dielectric layer contacts a surface of said one of the second metal interconnect structures and laterally surrounds an end portion of the second lateral insulating external connecting via structure.

25. The joint assembly of claim 22, wherein the first lateral insulating external connecting via structure comprises: a tubular insulating spacer contacting a sidewall of the second substrate, the second interconnect level dielectric layer, and a subset of the layers within the first interconnect level dielectric layer; and A conductive pillar structure is laterally surrounded by the tubular insulating spacer and contacts a planar surface of the one of the first metal interconnect structures.

26. The bonded assembly of claim 22, further comprising a planar dielectric isolation layer located on the second distal planar surface of the second substrate and contacting a planar surface of the first external bond pad.

27. The engagement assembly of claim 22, wherein: One of the first semiconductor die and the second semiconductor die comprises a memory die including a three-dimensional array of memory elements; and The other of the first and second semiconductor dies includes a logic die including peripheral circuitry configured to operate the three-dimensional array of memory elements.

28. The joint assembly of claim 27, wherein: The first substrate and the second substrate include semiconductor substrates; The memory die includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines for the three-dimensional array of memory elements; and The peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines.

29. The bonded assembly of claim 28, wherein the memory die comprises: Alternating stacking of insulating and conducting layers; and A two-dimensional array of memory stack structures extending through the alternating stacks, wherein: Each of the memory stack structures includes a respective vertical stack of memory elements positioned adjacent to a respective vertical semiconductor channel; The two-dimensional array of memory stacked structures constitutes the three-dimensional array of memory elements; The bit lines are connected to respective subsets of the vertical semiconductor channels; and The conductive layer includes the word line.

30. A method of forming a joint assembly, comprising: providing a first semiconductor die, wherein the first semiconductor die comprises: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer including a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bond pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; providing a second semiconductor die, wherein the second semiconductor die comprises: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer including a second metal interconnect structure electrically connected to the second semiconductor device, and a second die-to-die bond pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure; bonding the second die-to-die bond pad to the first die-to-die bond pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; forming a first connecting via cavity through the second substrate, the second interconnect level dielectric layer, a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and a subset of layers within the first interconnect level dielectric layer, wherein one of the first metal interconnect structures is physically exposed at a bottom of the first connecting via cavity; forming a first lateral insulated external connection via structure in the first connection via cavity on the one of the first metal interconnect structures; and A first external bonding pad is formed on the first lateral insulated external connection via structure.

31. The method of claim 30, further comprising attaching a solder ball to a surface of the external bond pad.

32. The method of claim 30, wherein the second die-to-die bond pad is bonded to the first die-to-die bond pad by copper-to-copper bonding.

33. The method of claim 30, further comprising: forming a second connecting via cavity through a subset of the layers within the second substrate and the second interconnect level dielectric layer, wherein one of the second metal interconnect structures is physically exposed at a bottom of the second connecting via cavity; forming a second lateral insulated external connection via structure in the second connection via cavity on the one of the second metal interconnect structures; and A second external bonding pad is formed on the second lateral insulated external connection via structure.

34. The method of claim 33, further comprising: forming a third connecting via cavity that passes through the second substrate, the second interconnect level dielectric layer, the horizontal plane including the interface between the first semiconductor die and the second semiconductor die, another subset of layers within the first interconnect level dielectric layer, and extends to another one of the first metal interconnect structures that has a different vertical distance from the interface between the first semiconductor die and the second semiconductor die than the one of the first metal interconnect structures has from the interface between the first semiconductor die and the second semiconductor die; forming a third lateral insulated external connection via structure in the third connection via cavity on the other one of the second metal interconnect structures; and A third external bonding pad is formed on the third lateral insulated external connection via structure.

35. The method of claim 33, wherein: the first interconnect level dielectric layer comprising a patterned first etch stop dielectric layer, the patterned first etch stop dielectric layer contacting a surface of the one of the first metal interconnect structures; the second interconnect level dielectric layer comprises a patterned second etch stop dielectric layer contacting a surface of the one of the second metal interconnect structures; and The first connecting via cavity and the second connecting via cavity are formed by the same anisotropic etching process, the anisotropic etching process comprising a first etching step, a second etching step and a third etching step, the first etching step etches through the second substrate, the second etching step etches portions of the second interconnect level dielectric layer and the first interconnect level dielectric layer that are selective to the material of the patterned second etch stop dielectric layer and the patterned first etch stop dielectric layer, and the third etching step etches through the patterned second etch stop dielectric layer and the patterned first etch stop dielectric layer.

36. The method of claim 30, wherein the first lateral insulating external connection via structure is formed by: conformally depositing a continuous layer of dielectric material at a perimeter of the first connecting via cavity and over the second substrate; forming a tubular insulating spacer within the first connecting via cavity by anisotropically etching the continuous dielectric material layer; and A conductive pillar structure is formed within a remaining volume of the first connecting via cavity inside the tubular insulating spacer.

37. The method of claim 30, wherein: One of the first semiconductor die and the second semiconductor die comprises a memory die including a three-dimensional array of memory elements; and The other of the first semiconductor die and the second semiconductor die includes a logic die including peripheral circuitry configured to operate the three-dimensional array of memory elements.

38. The method of claim 37, wherein: The first substrate and the second substrate include semiconductor substrates; The memory die includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines for the three-dimensional array of memory elements; and The peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines.

39. A joint assembly comprising: a first semiconductor die comprising: a first substrate having a first distal planar surface and a first proximal planar surface, a first semiconductor device located above the first proximal planar surface of the first substrate, a first interconnect level dielectric layer including a first metal interconnect structure electrically connected to the first semiconductor device, and a first die-to-die bond pad located at a surface portion of the first interconnect level dielectric layer and electrically connected to the first metal interconnect structure; and a second semiconductor die comprising: a second substrate having a second distal planar surface and a second proximal planar surface, a second semiconductor device located above the second proximal planar surface of the second substrate, a second interconnect level dielectric layer including a second metal interconnect structure electrically connected to the second semiconductor device, and a second die-to-die bonding pad located at a surface portion of the second interconnect level dielectric layer and electrically connected to the second metal interconnect structure, wherein the second die-to-die bonding pad is bonded to the first die-to-die bonding pad to provide a die-to-die bond between the first semiconductor die and the second semiconductor die; a first external bonding pad located above the second distal planar surface of the second substrate; a first lateral insulating external connection via structure extending vertically from at least the second distal planar surface of the second substrate through the second substrate, the second interconnect level dielectric layer, a horizontal plane including an interface between the first semiconductor die and the second semiconductor die, and a subset of layers within the first interconnect level dielectric layer, and extending to one of the first metal interconnect structures and contacting the first external bond pad; a second external bond pad located above the second distal planar surface of the second substrate; and a second lateral insulated external connecting via structure contacting the second external bonding pad and extending vertically from at least the second distal planar surface of the second substrate, through the second substrate, the second interconnect level dielectric layer, the horizontal plane including the interface between the first semiconductor die and the second semiconductor die, and another subset of layers within the first interconnect level dielectric layer, and extending to another one of the first metal interconnect structures, the other one having a vertical distance from the interface between the first semiconductor die and the second semiconductor die that is different from the vertical distance of the one of the first metal interconnect structures from the interface between the first semiconductor die and the second semiconductor die.

40. The bonded assembly of claim 39, further comprising a solder ball bonded to the first external bond pad.

41. The bonded assembly of claim 39, wherein the second die-to-die bond pad is bonded to the first die-to-die bond pad by a copper-to-copper bond.

42. The bonded assembly of claim 39, further comprising a third external bond pad located above the second distal planar surface of the second substrate.

43. The bonded assembly of claim 42, further comprising a third lateral insulated external connecting via structure contacting the third external bonding pad and contacting one of the second metal interconnect structures.

44. The engagement assembly of claim 39, further comprising: a first etch stop dielectric layer contacting a surface of said one of said first metal interconnect structures and laterally surrounding an end portion of said first lateral insulating external connecting via structure; and A second etch stop dielectric layer contacts a surface of said one of the second metal interconnect structures and laterally surrounds an end portion of the second lateral insulating external connecting via structure.

45. The joint assembly of claim 39, wherein the first lateral insulating external connecting via structure comprises: a tubular insulating spacer contacting a sidewall of the second substrate, the second interconnect level dielectric layer, and a subset of the layers within the first interconnect level dielectric layer; and A conductive pillar structure is laterally surrounded by the tubular insulating spacer and contacts a planar surface of the one of the first metal interconnect structures.

46. ​​The bonded assembly of claim 39, further comprising a planar dielectric isolation layer located on the second distal planar surface of the second substrate and contacting a planar surface of the first external bond pad.

47. The engagement assembly of claim 39, wherein: One of the first semiconductor die and the second semiconductor die comprises a memory die including a three-dimensional array of memory elements; and The other of the first and second semiconductor dies includes a logic die including peripheral circuitry configured to operate the three-dimensional array of memory elements.

48. The engagement assembly of claim 47, wherein: The first substrate and the second substrate include semiconductor substrates; The memory die includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines for the three-dimensional array of memory elements; and The peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines.

49. The bonded assembly of claim 48, wherein the memory die comprises: Alternating stacking of insulating and conducting layers; and A two-dimensional array of memory stack structures extending through the alternating stacks, wherein: Each of the memory stack structures includes a respective vertical stack of memory elements positioned adjacent to a respective vertical semiconductor channel; The two-dimensional array of memory stacked structures constitutes the three-dimensional array of memory elements; The bit lines are connected to respective subsets of the vertical semiconductor channels; and The conductive layer includes the word line.

50. A joint assembly comprising: A memory die comprising: an alternating stack of insulating layers and conductive layers having a stepped surface, a memory stack structure extending vertically through the alternating stack, a stepped dielectric material portion contacting the stepped surface of the alternating stack, a through-dielectric external connection via structure extending vertically through the stepped dielectric material portion; a memory side metal interconnect structure included in a memory side interconnect level dielectric layer, and a memory side bonding pad; a logic die comprising: a semiconductor substrate, a semiconductor device located on the semiconductor substrate and comprising peripheral circuitry configured to control operation of the memory stack structure within the memory die, a logic side metal interconnect structure included in a logic side interconnect level dielectric layer, and a logic side bonding pad bonded to the memory side bonding pad of the memory die at a die-to-die bonding interface; and an external bonding pad located on a surface of the stepped dielectric material portion and contacting a distal planar surface of the through-dielectric external connection via structure, wherein: the distal flat surface of the through dielectric external connection via structure is located within a horizontal plane including the first flat horizontal surface of the stepped dielectric material portion; The through-dielectric external connection via structure includes a proximal planar surface contacting one of the memory-side metal interconnect structures; and The proximal planar surface is vertically spaced apart from a horizontal plane including the die-to-die bonding interface by a vertical separation distance that is smaller than a vertical separation distance of the memory stack structure from the horizontal plane including the die-to-die bonding interface.

51. The bonded assembly of claim 50 further comprising a solder ball bonded to the external bond pad.

52. The bond assembly of claim 50, wherein the logic side bond pad is bonded to the memory side bond pad by a copper to copper bond.

53. The engagement assembly of claim 50, wherein: Each of the memory stack structures includes a respective vertical semiconductor channel, the vertical semiconductor channel including a proximal end and a distal end, the distal end being vertically spaced apart a vertical distance from a horizontal plane including the die-to-die bonding interface that is greater than a vertical distance of the proximal end from the horizontal plane including the die-to-die bonding interface; and A source semiconductor layer is located on the alternating stack and is electrically connected to the distal ends of the vertical semiconductor channels.

54. The bonding assembly of claim 53, wherein the distal planar surface of the through-dielectric external connection via structure lies within a horizontal plane including a planar surface of the source semiconductor layer, the horizontal plane being parallel to the horizontal plane including the die-to-die bonding interface.

55. The bonded assembly of claim 53, wherein the source semiconductor layer is electrically connected to the distal end of the vertical semiconductor channel by: direct contact between the source semiconductor layer and the horizontal planar surface of the distal end of the vertical semiconductor channel; or A base channel portion directly contacts the source semiconductor layer and a horizontal planar surface of the distal end of the vertical semiconductor channel.

56. The bonded assembly of claim 53, wherein a source contact layer is electrically connected to the distal end of the vertical semiconductor channel through direct contact between a cylindrical sidewall surface of the distal end of the vertical semiconductor channel and the source semiconductor layer.

57. The bonded assembly of claim 53, further comprising an additional external bond pad on a distal planar surface of the source semiconductor layer.

58. The engagement assembly of claim 50, wherein: The memory stack structure includes a three-dimensional array of memory elements; The memory die includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines for the three-dimensional array of memory elements; and The peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines.

59. The engagement assembly of claim 58, wherein: The bit lines are connected to respective subsets of vertical semiconductor channels and to bit line drivers within the peripheral circuitry through first conductive paths, the first conductive paths comprising the memory side bonding pads and a first bonding subset of the logic side bonding pads; and The conductive layer includes the word line and is connected to a word line driver within the peripheral circuit through a second conductive path including the memory side bond pad and a second bond subset of the logic side bond pad.

60. A method of forming a joint assembly, comprising: Providing a memory die, the memory die comprising a memory side substrate, an alternating stack of insulating layers and conductive layers having a stepped surface and located on the memory side substrate, a memory stack structure extending vertically through the alternating stack, a stepped dielectric material portion contacting the stepped surface of the alternating stack, a through-dielectric external connection via structure extending vertically through the stepped dielectric material portion, a memory side metal interconnect structure included in a memory side interconnect level dielectric layer, and a memory side bonding pad; Providing a logic die, the logic die comprising: a semiconductor substrate, a semiconductor device located on the semiconductor substrate and comprising a peripheral circuit configured to control the operation of the memory stack structure within the memory die, a logic side metal interconnect structure included in a logic side interconnect level dielectric layer, and a logic side bonding pad; bonding the memory side bond pads to the logic side bond pads, wherein a die-to-die bonding interface is formed; physically exposing a distal planar surface of the through-dielectric external connection via structure by removing at least a portion of the memory-side substrate; and An external bonding pad is formed on the distal planar surface of the through-dielectric external connection via structure.

61. The method of claim 60, wherein the external bonding pad is formed by depositing and patterning a conductive material on the distal planar surface of the through-dielectric external connection via structure and the first planar horizontal surface of the stepped dielectric material portion.

62. The method of claim 60, wherein the through-dielectric external connection via structure is formed by: forming a via cavity extending through the stepped dielectric material portion after forming the alternating stack and the memory stack structure, wherein the via cavity extends to a surface of the memory side substrate; and A conductive material is deposited in the via cavity to form the through-dielectric external connection via structure, wherein the memory-side interconnect level dielectric layer and a subset of the memory-side bonding pads are formed over the through-dielectric external connection via structure.

63. The method of claim 60, further comprising bonding a solder ball to the external bond pad, wherein the second die-to-die bond pad is bonded to the first die-to-die bond pad by a copper-to-copper bond.

64. The method of claim 60, wherein: Each of the memory stack structures includes a respective vertical semiconductor channel including a distal end electrically connected to a surface portion of the memory-side substrate; and After removing the portion of the memory side substrate, the remaining portion of the memory side substrate includes a source semiconductor layer electrically connected to the distal end of the vertical semiconductor channel.

65. The method of claim 60, wherein: The memory die includes a source level material layer between the memory side substrate and the alternating stack; The source level material layer includes a source contact layer in contact with a sidewall of the vertical semiconductor channel; and After the memory-side bonding pads are bonded to the logic-side bonding pads, the entire memory-side substrate is removed to physically expose the planar surface of the source-level material layer.

66. The method of claim 60, wherein: The memory die includes a source contact layer electrically connected to a distal end of a vertical semiconductor channel after physically exposing the distal planar surface of the through-dielectric external connection via structure, wherein the source contact layer includes a doped semiconductor material portion disposed within the memory-side substrate or between the memory-side substrate and the alternating stack; and The method also includes forming an additional external bonding pad on the distal planar surface of the source semiconductor layer.

67. The method of claim 60, wherein: The memory stack structure includes a three-dimensional array of memory elements; The memory die includes a set of word lines for the three-dimensional array of memory elements and a set of bit lines for the three-dimensional array of memory elements; The peripheral circuit is configured to drive at least one of the set of word lines and the set of bit lines; The bit lines are connected to respective subsets of vertical semiconductor channels and to bit line drivers within the peripheral circuitry through first conductive paths, the first conductive paths comprising the memory side bonding pads and a first bonding subset of the logic side bonding pads; and The conductive layer includes the word line and is connected to a word line driver within the peripheral circuit through a second conductive path including the memory side bond pad and a second bond subset of the logic side bond pad.

68. A joint assembly comprising: A memory die comprising: an alternating stack of insulating layers and conductive layers having a stepped surface, a memory stack structure extending vertically through the alternating stack, a stepped dielectric material portion contacting the stepped surface of the alternating stack, a through-dielectric external connection via structure extending vertically through the stepped dielectric material portion; a memory side metal interconnect structure included in a memory side interconnect level dielectric layer, and a memory side bonding pad; a logic die comprising: a semiconductor substrate, a semiconductor device located on the semiconductor substrate and comprising peripheral circuitry configured to control operation of the memory stack structure within the memory die, a logic side metal interconnect structure included in a logic side interconnect level dielectric layer, and a logic side bonding pad bonded to the memory side bonding pad of the memory die at a die-to-die bonding interface; and an external bonding pad located on a surface of the stepped dielectric material portion and contacting a distal planar surface of the through-dielectric external connection via structure, wherein: Each of the memory stack structures includes a respective vertical semiconductor channel including a proximal end and a distal end, the distal end being vertically spaced apart from a horizontal plane including the die-to-die bonding interface by a vertical distance greater than a vertical distance of the proximal end from the horizontal plane including the die-to-die bonding interface; and A source semiconductor layer is located on the alternating stack and is electrically connected to the distal ends of the vertical semiconductor channels.

69. The bonding assembly of claim 68, wherein a proximal planar surface of the through-dielectric external connection via structure lies within a horizontal plane including a planar surface of the source semiconductor layer, the horizontal plane being parallel to the horizontal plane including the die-to-die bonding interface.

70. The bonded assembly of claim 68, wherein the source semiconductor layer is electrically connected to the distal end of the vertical semiconductor channel by: direct contact between the source semiconductor layer and the horizontal planar surface of the distal end of the vertical semiconductor channel; or A base channel portion directly contacts the source semiconductor layer and a horizontal planar surface of the distal end of the vertical semiconductor channel.

71. The bonded assembly of claim 68, wherein a source contact layer is electrically connected to the distal end of the vertical semiconductor channel through direct contact between a cylindrical sidewall surface of the distal end of the vertical semiconductor channel and the source semiconductor layer.

72. The bonded assembly of claim 68, further comprising an additional external bond pad located on a distal planar surface of the source semiconductor layer.

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