Group III nitride device with single particle irradiation resistance

Abstract

The invention discloses an III-group nitride device with single particle irradiation resistance. According to the invention, the hole storage layer is introduced between the buffer layer and the channel layer of the epitaxial layer structure, and the hole storage layer forms a hole potential well on the energy band structure so as to effectively collect irradiation-induced excess holes in the channel layer; meanwhile, an extraction electrode and a second source electrode are arranged to respectively collect irradiation-induced excess holes in a nearby area below the grid electrode and between the grid electrode and the source electrode. Wherein the extraction electrode is arranged between the grid electrodes which are sequentially arranged at intervals, and the extraction electrode and the second source electrode are connected with the first source electrode through the metal interconnection layer. The single particle irradiation resistance of the device can be effectively improved, the manufacturing process is compatible with the existing process, and complex process steps do not need to be additionally introduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, relates to a gallium nitride power device, and in particular to a group III nitride device with radiation resistance. Background Art

[0002] GaN HEMT devices have the advantages of low on-resistance, fast switching speed, and high switching frequency, which are conducive to the realization of lightweight, miniaturized, efficient, and high-power density power systems. They have broad application prospects in the fields of new generation mobile communications, data centers, smart cars, aerospace, etc. In particular, they have great application potential in fields such as aerospace that are sensitive to the volume and weight of power systems. In aerospace applications, electronic devices are exposed to high-energy particles, which may cause single-particle effects, resulting in device degradation or even failure. In conventional GaN HEMT devices, due to the lack of effective radiation-induced carrier regulation structure, non-equilibrium holes introduced by heavy ion irradiation may accumulate in the area near the bottom of the gate, causing a "back barrier effect", causing a negative drift in the threshold voltage, leading to source-drain punch-through of the device in the blocking state, and then causing leakage to increase or even device burnout. At present, the single-particle burnout voltage of GaN HEMT devices is still relatively low, which limits the application of GaN power devices in aerospace scenarios.

[0003] Therefore, in order to improve the single-particle irradiation resistance of GaN HEMT devices and promote the application of GaN HEMT devices in aerospace scenarios, it is necessary to propose corresponding designs from the energy band structure and device structure to effectively collect, store and extract radiation-induced holes. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention provides a III-group nitride device with single-particle irradiation resistance. The present invention introduces a hole storage layer between the buffer layer and the channel layer of the epitaxial layer structure. The hole storage layer forms a hole potential well on the band structure to collect the excess holes induced by radiation in the channel layer. The extraction electrode and the second source are provided to respectively collect the excess holes induced by radiation in the vicinity of the area below the gate and between the gate and the source. The extraction electrode, the second source and the first source are connected through a metal interconnection layer. The manufacturing process of the present invention is compatible with the existing process, and there is no need to introduce additional complex process steps, which provides a solution for improving the device's ability to resist single-particle irradiation.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] The present invention provides a III-group nitride device with single particle irradiation resistance. The III-group nitride device comprises, from bottom to top, a substrate, a buffer layer, a hole storage layer, a channel layer, a barrier layer and a first passivation layer. A first source and a drain are provided on both sides of the channel layer, respectively. A p-GaN layer is provided between the first source and the drain near the first source side. Gates arranged at intervals along the y direction are provided on the p-GaN layer. Etching holes are provided between the gates arranged at intervals. The etching holes are etched to the channel layer, the hole storage layer or the buffer layer. Extraction electrodes are provided in the etching holes. The extraction electrodes are in contact with the side walls and the bottom along the etching holes. A second source is also provided near the first source. The second source is connected to the first source and the extraction electrode through a metal interconnection layer. Except for the top surfaces of the extraction electrode, the first source, the second source and the drain, the rest of the surface area is filled with a second passivation layer.

[0007] As a preferred solution of the present invention, the depth of the extraction electrode and the depth of the second source are independent.

[0008] As a preferred embodiment of the present invention, the etching holes are etched to the upper surface or the interior of the buffer layer; or the etching holes are etched to the upper surface or the interior of the hole storage layer; or the etching holes are etched to the upper surface or the interior of the channel layer.

[0009] As a preferred solution of the present invention, the depths of adjacent etched holes are the same or different.

[0010] In the present invention, each etched hole may have a bottom located on the upper surface or inside of the buffer layer, a bottom located on the upper surface or inside of the hole storage layer, or a bottom located on the upper surface or inside of the channel layer, or more thereof.

[0011] As a preferred solution of the present invention, the extraction electrode forms a Schottky contact or an Ohmic contact with the semiconductor layer on the sidewall and the bottom.

[0012] As a preferred embodiment of the present invention, the second source electrode extends into the buffer layer through the barrier layer, the channel layer and the hole storage layer; or the second source electrode extends into the hole storage layer through the barrier layer and the channel layer; or the second source electrode extends into the channel layer through the barrier layer; or the second source electrode passes through the barrier layer, the channel layer and the hole storage layer to contact the upper surface of the buffer layer; or the second source electrode passes through the barrier layer and the channel layer to contact the upper surface of the hole storage layer; or the second source electrode passes through the barrier layer and contacts the upper surface of the channel layer.

[0013] As a preferred solution of the present invention, the shape of the etched cross-section of the etched hole forming the extraction electrode in the xy plane is circular, elliptical, polygonal or other irregular edge shapes, the shape and size of the etched cross-sections of adjacent etched holes in the xy plane are the same or different, and the ratio of the projection length of the etched hole in the y direction to the length of the p-GaN layer in the y direction is 5%-90%.

[0014] As a preferred solution of the present invention, the gate is one or a combination of Schottky-type p-GaN gate, ohmic p-GaN gate, recessed gate structure, MIS gate, or a complex gate structure having the above gate structure characteristics.

[0015] As a preferred solution of the present invention, the bottom of the extraction electrode is located on the upper surface of the hole storage layer, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

[0016] As a preferred solution of the present invention, the extraction electrode with its bottom located on the upper surface of the hole storage layer and the extraction electrode with its bottom located inside the channel layer are arranged in sequence and spaced apart, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1) The present invention introduces a hole storage layer between the buffer layer and the channel layer to form a hole potential well, which can effectively collect the radiation-induced excess holes in the channel layer and prevent them from accumulating between the gate source and the area near the gate, thereby achieving the regulation of the radiation-induced excess holes, suppressing the back barrier effect, and improving the device's ability to resist single-particle radiation.

[0019] 2) The present invention sets an extraction electrode between the spaced-apart gates, sets a second source near the first source, and connects the extraction electrode, the second source and the first source through a metal interconnection layer, which can efficiently extract radiation-induced holes caused by single particle incident between the gate and source and near the gate, further suppress the back barrier effect, and thus improve the device's ability to resist single particle radiation.

[0020] 3) The manufacturing process of the device structure in the present invention is fully compatible with the traditional process, and there is no need to introduce additional complex process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] FIG. 1( a ) is a schematic diagram of Embodiment 1 of the present invention.

[0023] FIG1(b) is a cross-sectional view taken along line AA' in FIG1(a), which shows the role of the hole storage layer, the extraction electrode and the second source electrode in collecting and extracting radiation-induced holes.

[0024] FIG. 1( c ) is a cross-sectional view taken along line BB′ in FIG. 1( a ).

[0025] FIG1( d ) is a schematic diagram of the energy band structure from the p-GaN layer to the buffer layer in Example 1 of the present invention.

[0026] Figure 2 It is a schematic diagram of step 1 of the present invention.

[0027] Figure 3 It is a schematic diagram of step 2 of the present invention.

[0028] Figure 4 It is a schematic diagram of step 3 of the present invention.

[0029] Figure 5 It is a schematic diagram of step 4 of the present invention.

[0030] Figure 6 It is a schematic diagram of step 5 of the present invention.

[0031] Figure 7 It is a schematic diagram of step 6 of the present invention.

[0032] Figure 8 It is a schematic diagram of step 7 of the present invention.

[0033] Fig. 9 It is a schematic diagram of step 8 of the present invention.

[0034] Fig.10 It is a schematic diagram of step 9 of the present invention.

[0035] Fig.11 It is a schematic diagram of step 10 of the present invention.

[0036] Fig.12 It is a schematic diagram of step 11 of the present invention.

[0037] Fig.13 It is a schematic diagram of step 12 of the present invention.

[0038] Fig.14 It is a schematic diagram of step 13 of the present invention.

[0039] Fig.15 It is a schematic diagram of step 14 of the present invention.

[0040] Fig.16 It is a schematic diagram of step 15 of the present invention.

[0041] Fig.17 It is a schematic diagram of step 16 of the present invention.

[0042] FIG. 18( a ) is a schematic diagram of Embodiment 2 of the present invention.

[0043] FIG. 18( b ) is a cross-sectional view taken along line AA′ in FIG. 18( a ).

[0044] FIG. 18( c ) is a cross-sectional view taken along line BB′ in FIG. 18( a ).

[0045] FIG. 18( d ) is a cross-sectional view taken along line CC′ in FIG. 18( a ).

[0046] FIG. 19( a ) is a schematic diagram of Embodiment 3 of the present invention.

[0047] FIG. 19( b ) is a cross-sectional view taken along line AA′ in FIG. 19( a ).

[0048] FIG. 19( c ) is a cross-sectional view taken along line BB′ in FIG. 19( a ).

[0049] In the figure, 1. substrate; 2. buffer layer; 3. hole storage layer; 4. channel layer; 5. barrier layer; 6. first passivation layer; 7. first source; 8. drain; 9. p-GaN layer; 10. gate; 11. extraction electrode; 12. second source; 13. metal interconnect layer; 14. second passivation layer. DETAILED DESCRIPTION

[0050] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0051] The preparation processes of the present invention are all existing processes, and the preparation method of the present invention comprises the following steps:

[0052] 1) Select a substrate layer. The material of the substrate layer includes but is not limited to one of silicon, silicon carbide, sapphire, gallium nitride, gallium oxide and diamond, or several of them, or other complex materials with the above material components, or a complex material substrate such as a QST substrate. The size of the substrate layer includes but is not limited to two inches, four inches, and six inches.

[0053] 2) The growth method of the buffer layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the buffer layer includes but is not limited to growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials under the conditions of temperature of 0-1500°C and pressure of 0-300Torr, or several of them, or other complex materials with the above material components as the device buffer layer. The buffer layer structure is composed of at least one layer of material, and also includes but is not limited to one of the various complex structure designs such as AlGaN stress release layer with gradient Al component, superlattice structure, low-temperature grown AlN structure, or a combination of several of them, or other complex structures with the above structural characteristics.

[0054] 3) The growth method of the hole storage layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the hole storage layer includes but is not limited to growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components as the device hole storage layer under the conditions of temperature of 0-1500°C and pressure of 0-300Torr. The hole storage layer is composed of at least one layer of semiconductor material, and also includes but is not limited to various complex structural designs.

[0055] 4) The growth method of the channel layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the channel layer includes but is not limited to growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components as the device channel layer under the conditions of temperature of 0-1500°C and pressure of 0-300Torr. The channel layer is composed of at least one layer of semiconductor material, and also includes but is not limited to various complex structural designs.

[0056] 5) The growth method of the barrier layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the barrier layer includes but is not limited to growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components as the device barrier layer under the conditions of temperature of 0-1500°C and pressure of 0-300Torr. The barrier layer is composed of at least one layer of semiconductor material, and also includes but is not limited to various complex structural designs.

[0057] 6) The growth method of the p-GaN layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the p-GaN layer includes but is not limited to growing the p-GaN layer at a temperature of 0 to 1500°C and a pressure of 0 to 300 Torr. The p-GaN layer is composed of at least one layer of semiconductor material, and also includes but is not limited to various complex structural designs.

[0058] 7) The etching method of the p-GaN layer includes but is not limited to one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the p-GaN layer includes but is not limited to etching the p-GaN layer under the conditions of RF power of 0 to 600W and pressure of 0 to 100mTorr.

[0059] 8) The growth method of the first source and drain includes but is not limited to one of the coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The growth process of the first source and drain includes but is not limited to growing one of the materials including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials with the above material components as the first source and drain of the device under the conditions of temperature of 0-1200°C and pressure of 0-300Torr, and the annealing method includes but is not limited to annealing at 95-1500°C.

[0060] 9) The deposition method of the first passivation layer and the second passivation layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The deposition process of the first passivation layer and the second passivation layer includes but is not limited to deposition under the conditions of temperature of 0 to 1500°C and pressure of 0 to 300 Torr, including but not limited to (Al x Ga 1-x )2O3, Al2O3, AlN, SiN x , SiO2, HfO2, ZrO2, SOG, PI, SiON, HfZrO and other materials, or several of them, or a composite material composed of multiple other materials with the above material components as the first passivation layer and the second passivation layer of the device. The first passivation layer and the second passivation layer structure are composed of at least one layer, and include but are not limited to various complex structure designs.

[0061] 10) The etching method of the first passivation layer and the second passivation layer includes but is not limited to one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the first passivation layer and the second passivation layer includes but is not limited to etching the first passivation layer and the second passivation layer under the conditions of RF power of 0 to 600 W and pressure of 0 to 100 mTorr.

[0062] 11) The gate growth method includes but is not limited to one of the coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The gate growth process includes but is not limited to growing one of the materials including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of them, or other complex materials with the above-mentioned material components as the device gate under the conditions of temperature of 0-1200°C and pressure of 0-300Torr, and the annealing method includes but is not limited to annealing at 95-1500°C.

[0063] 12) The etching methods of the buffer layer, hole storage layer, channel layer and barrier layer include but are not limited to one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the buffer layer, hole storage layer, channel layer and barrier layer includes but is not limited to etching under the conditions of RF power of 0 to 600W and pressure of 0 to 100mTorr.

[0064] 13) The growth method of the extraction electrode, the second source electrode and the metal interconnection layer includes but is not limited to one of the coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The growth process of the extraction electrode, the second source electrode and the metal interconnection layer includes but is not limited to growing one of the materials including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of them, or other complex materials with the above-mentioned material components as the device extraction electrode, the second source electrode and the metal interconnection layer under the conditions of temperature of 0-1200°C and pressure of 0-300Torr, and the annealing method includes but is not limited to annealing at 95-1500°C.

[0065] Example 1

[0066] See also Figure 1(a)-Figure 1(c) The present invention provides a III-group nitride device, which includes a substrate 1, a buffer layer 2, a hole storage layer 3, a channel layer 4, a barrier layer 5 and a first passivation layer 6 from bottom to top. A first source 7 and a drain 8 are provided on both sides of the channel layer 4, respectively. A p-GaN layer 9 is provided between the first source 7 and the drain 8 and close to the first source 7. A gate 10 arranged at intervals in the y direction is provided on the p-GaN layer 9. Etching holes are provided between the arranged gates 10, and extraction electrodes 11 are provided in the etching holes, and the extraction electrodes 11 are in contact with the side walls and the bottom along the etching holes. A second source 12 is also provided near the first source 7, and the second source 12 is connected to the first source 7 and the extraction electrode 11 through a metal interconnection layer 13. Except for the top surfaces of the extraction electrode 11, the first source 7, the second source 12 and the drain 8, the remaining surface areas are filled with a second passivation layer 14.

[0067] FIG1(d) is a schematic diagram of the energy band structure from the p-GaN layer to the buffer layer of Example 1 of the present invention. It can be seen from the figure that the hole storage layer forms a hole potential well on the energy band structure, which can effectively collect the radiation-induced excess holes in the channel layer.

[0068] In this embodiment, the size of the p-GaN layer in the x-direction is 3μm, and the size in the y-direction is 60μm. The number of gates arranged at intervals on the p-GaN layer is 4, and the number of extraction electrodes arranged at intervals is 4; the opening shape of each gate on the first passivation layer is rectangular, with a size of 2μm in the x-direction and a size of 5μm in the y-direction. The gate metal completely covers the opening of each gate on the first passivation layer, and except for the side close to the drain, the edge of the gate metal extends out of the sidewall of the corresponding direction of the corresponding first passivation layer gate opening by 0.2μm, and the gate metal extends out of the p-GaN layer close to the drain by 0.5μm.

[0069] The bottom of the etched hole of the extraction electrode is located on the upper surface of the hole storage layer. The shape of the etched holes on the first and second passivation layers are rectangular, the size in the x direction is 2μm, and the size in the y direction is 6μm. The shape and size of the opening of each extraction electrode on the first passivation layer and the second passivation layer are consistent. The shape of the etched holes forming the extraction electrodes on the buffer layer, the hole storage layer, the channel layer, and the barrier layer are rectangular, the size in the x direction is 1.2μm, and the size in the y direction is 5μm. The spacing from the gate adjacent to the etched hole to the side wall of the etched hole is 2.5μm.

[0070] The distance between the gate and the first source is 3μm, and the distance between the gate and the drain is 15μm; the size of the first source and the drain in the x direction is 3μm; the spacing from the second source to the first source is 1μm, the size of the second source in the x direction is 3μm, and the bottom of the second source is located on the upper surface of the storage layer.

[0071] The distance between the metal interconnection layer connecting the extraction electrode, the second source and the first source and the drain electrode close to the drain electrode is 12 μm.

[0072] The substrate material of the device of the present invention includes but is not limited to one of silicon, silicon carbide, sapphire, gallium nitride, gallium oxide and diamond, or several of them, or other complex materials with the above material components, or complex material substrates such as QST substrates. In this embodiment, silicon is selected as the substrate.

[0073] The buffer layer of the device of the present invention includes but is not limited to one of the materials of group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components. The buffer layer structure of the device of the present invention is composed of at least one layer of material, and also includes but is not limited to one of various complex structure designs such as AlGaN stress release layer with gradual Al component change, superlattice structure, low temperature grown AlN structure, or a combination of several of them, or other complex structures with the above structural characteristics. In this embodiment, an AlN layer with a thickness of 50nm and a GaN layer with a thickness of 3000nm are selected from bottom to top as the buffer layer.

[0074] The hole storage layer of the device of the present invention includes but is not limited to one of the materials of group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components. The hole storage layer is composed of at least one layer of semiconductor material, and includes but is not limited to various complex structural designs. In this embodiment, AlGaN with an Al component of 0.2 and a thickness of 10nm is selected as the hole storage layer.

[0075] The channel layer of the device of the present invention includes but is not limited to one of the materials such as group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components. The channel layer is composed of at least one layer of semiconductor material, and includes but is not limited to various complex structural designs. In this embodiment, GaN with a thickness of 300nm is selected as the channel layer.

[0076] The barrier layer of the device of the present invention includes but is not limited to one of the materials such as group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components. The barrier layer is composed of at least one layer of semiconductor material, and includes but is not limited to various complex structural designs. In this embodiment, an AlGaN layer with an Al component of 0.2 and a thickness of 15nm is selected as the barrier layer.

[0077] The Mg doping concentration of the p-GaN layer of the device of the present invention can be 1×10 17 ~1×10 21 cm -3 The thickness can be 0 to 500 nm. In this embodiment, the doping concentration is 1×10 19 cm -3 , a p-GaN layer with a thickness of 100nm.

[0078] The gate material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon and other materials, or several of them, or other complex materials with the above material components. The gate structure of the device of the present invention includes but is not limited to one or several combinations of Schottky-type p-GaN gate, ohmic p-GaN gate, recessed gate, MIS gate, or other complex gate structures with the above gate features. In this embodiment, 20nm Ni and 80nm Au are selected as the gate metal of the device to form a Schottky contact with the p-GaN layer.

[0079] The first source and drain materials of the device of the present invention include but are not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon and other materials, or several of them, or other complex materials with the above material components. The structure of the drain of the device of the present invention includes but is not limited to one of Schottky drain and ohmic drain or a combination of two, or other complex drain structures with Schottky drain and ohmic drain characteristics. The structure of the first source of the device of the present invention includes but is not limited to one of Schottky source and ohmic source or a combination of two, or other complex source structures with Schottky source and ohmic source characteristics. In this embodiment, 20nm Ti, 150nm Al, 50nm Ni, and 80nm Au are selected as the first source and drain metals of the device to form ohmic contacts with the channel layer.

[0080] The second source material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon and the like, or several of them, or other complex materials having the above material components. The structure of the source of the device of the present invention includes but is not limited to one of Schottky source and ohmic source or a combination of two, or other complex source structures having Schottky source and ohmic source characteristics. In this embodiment, 20nm Ni and 200nm Au are selected as the second source material of the device to form Schottky contact with the semiconductor layer at the side wall and bottom of the etched hole.

[0081] The extraction electrode material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials with the above material components. In this embodiment, 20nm Ni and 200nm Au are selected as the extraction electrode material of the device to form Schottky contact with the semiconductor layer on the side wall and bottom of the etched hole.

[0082] The metal interconnection layer material of the device of the present invention includes but is not limited to one of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials having the above material components. In this embodiment, 20nm Ni and 200nm Au are selected as the metal interconnection layer materials of the device.

[0083] See also Figure 2-Figure 16 This embodiment provides a process for preparing a III-group nitride device with single particle irradiation resistance, and the device is prepared as follows Figure 1(a)-Figure 1(c) The III-nitride device shown in the figure has the following specific steps:

[0084] 1) Select a substrate. In this embodiment, a two-inch Si (111) substrate is used as the substrate. First, it is placed in a mixed solution of three parts sulfuric acid, one part hydrogen peroxide and one part water for pickling, and then placed in a 5% hydrofluoric acid solution to remove surface oxides. Finally, acetone, isopropanol and anhydrous ethanol are used to clean the substrate surface in sequence, and finally the substrate is placed in water, taken out and blown dry. Figure 2 .

[0085] 2) Growth of buffer layer. In this embodiment, trimethylaluminum (TMAl) and NH3 are introduced into the MOCVD reaction chamber to grow a 50nm thick AlN layer on the substrate at a temperature of 1120°C and a pressure of 70Torr. The introduction of TMAl is stopped, and the introduction of NH3 is continued to raise the temperature to 1200°C for high temperature treatment. After the AlN layer is grown, trimethylgallium (TMGa) and NH3 are introduced into the MOCVD reaction chamber to grow a 3000nm thick GaN layer at a temperature of 900°C and a pressure of 70Torr. Figure 3 .

[0086] 3) Growing a hole storage layer. In this embodiment, after growing the buffer layer, TMAl is gradually introduced into the MOCVD reaction chamber and TMGa is reduced. AlGaN with an Al component of 0.20 and a thickness of 10 nm is grown as a hole storage layer at a temperature of 960°C and a pressure of 70 Torr. Figure 4 .

[0087] 4) Growing the channel layer. In this embodiment, after the hole storage layer is grown, TMGa and NH3 are introduced into the MOCVD reaction chamber to grow GaN with a thickness of 300 nm as the channel layer at a temperature of 900°C and a pressure of 70 Torr. Figure 5 .

[0088] 5) Growth of barrier layer. In this embodiment, after the channel layer is grown, TMAl is gradually introduced into the MOCVD reaction chamber and TMGa is reduced. AlGaN with an Al component of 0.20 and a thickness of 15 nm is grown as a barrier layer at a temperature of 960° C. and a pressure of 70 Torr. Figure 6 .

[0089] 6) Growth of p-GaN layer. In this embodiment, the p-GaN layer is epitaxially grown after the barrier layer is grown. TMGa, dipentyl magnesium (Cp2Mg), NH3 and H2 are introduced into the MOCVD reaction chamber. The growth temperature is 940°C and the pressure is 70 Torr. The doping concentration is 1×10 19 cm -3 , a p-GaN layer with a thickness of 100 nm, and annealed at a temperature of 700°C, such as Figure 7 .

[0090] 7) Etching the p-GaN layer. In this embodiment, after the p-GaN layer is grown, ICP etching is performed to partially remove the p-GaN. The ICP power is set to 100W, the pressure is set to 5mTorr, and Cl2, O2 and Ar are introduced. Figure 8 .

[0091] 8) Etch and deposit the drain and the first source, use ICP etching to remove the barrier layer in the area below the first source and drain, set the ICP power to 100W, the pressure to 5mTorr, and pass Cl2, O2 and Ar. Use E-beam evaporation deposition to deposit 20nm of Ti, 150nm of Al, 50nm of Ni, and 80nm of Au in sequence, and selectively remove the metal in the area other than the first source and drain by stripping, and anneal at 830℃, as shown in FIG. Fig. 9 .

[0092] 9) Grow the first passivation layer by using PECVD at a temperature of 300°C and a pressure of 850 mTorr, introducing N2O and 5% SiH4 / N2 to deposit 80 nm of SiO2 as the first passivation layer. Fig.10 .

[0093] 10) Etching the first passivation layer, using RIE etching to remove the first passivation layer of the gate region, the extraction electrode region, the first source region, the drain region, and the second source region, setting the RIE power to 200W, the pressure to 3-10mTorr, and passing CHF3 and Ar, such as Fig.11 .

[0094] 11) Deposit the gate electrode, use E-beam evaporation deposition to deposit 20nm Ni and 80nm Au in sequence, selectively remove the metal in the area other than the gate electrode by stripping, and anneal at 300℃, as shown in FIG. Fig.12 .

[0095] 12) growing a second passivation layer, using PECVD at a temperature of 300°C and a pressure of 850 mTorr to pass N2O and 5% SiH4 / N2 to deposit 500 nm of SiO2 as the second passivation layer, as shown in FIG. Fig.13 .

[0096] 13) Etching the second passivation layer, using RIE etching to remove the second passivation layer of the extraction electrode region, the first source region, the drain region, and the second source region, setting the RIE power to 200W, the pressure to 3-10mTorr, and passing CHF3 and Ar, such as Fig.14 .

[0097] 14) Etching the barrier layer and the channel layer of the second source region, using ICP etching to remove the barrier layer and the channel layer of the second source region. In this embodiment, etching is performed to the upper surface of the hole storage layer. The ICP power is set to 100W, the pressure is set to 5mTorr, and Cl2, O2 and Ar are introduced. Fig.15 .

[0098] 15) Etching the barrier layer and the channel layer in the extraction electrode region, using ICP etching to remove the barrier layer and the channel layer in the extraction electrode region. In this embodiment, etching is performed to the upper surface of the hole storage layer. The ICP power is set to 100 W, the pressure is set to 5 mTorr, and Cl2, O2 and Ar are introduced. Fig.16 .

[0099] 16) Deposit the extraction electrode, the second source electrode and the metal interconnection layer, use E-beam evaporation deposition to deposit 20nm of Ni and 200nm of Au in sequence, and selectively remove the metal in the area other than the extraction electrode, the second source electrode, the metal interconnection layer and the area above the first source electrode and the drain electrode by stripping, such as Fig.17 .

[0100] Example 2

[0101] like Figure 18(a)-Figure 18(d) In this embodiment, the extraction electrode 11 whose bottom is located on the upper surface of the hole storage layer 3 and the extraction electrode 11 whose bottom is located inside the channel layer 4 are arranged alternately in sequence, and the bottom of the second source electrode 12 is located on the upper surface of the hole storage layer 3. The preparation process is the same as that of Example 1.

[0102] Example 3

[0103] like Figure 19(a)-Figure 19(c) In this embodiment, the bottom of the extraction electrode 11 is located inside the buffer layer 2, and the bottom of the second source electrode 12 is located inside the channel layer 4. The preparation process is the same as that of Embodiment 1.

[0104] The above embodiments are only part of the possible structures of the present invention. In practical applications, parameters such as material selection, thickness and doping concentration design of each layer, specific HEMT structure design (such as whether there are other semiconductor layers between the buffer layer, hole storage layer, channel layer and barrier layer, whether there are other semiconductor layers between the substrate and the buffer layer, other gate types, SOI structure devices, gradient semiconductor layer composition, drain similar design), the size ratio of the extraction electrode relative to the p-GaN layer in the y direction, the specific depth of the etching hole for forming the extraction electrode, the specific shape and size of the etching hole for forming the extraction electrode, the specific shape and size of the gate, the specific shape and size of the gate electrode, the specific spacing between the extraction electrode and the gate electrode, the specific depth of the second source, the specific shape and size of the second source, the specific shape and size of other key structures, the type of gold semiconductor contact, the position, depth and shape of the gold semiconductor contact formation can be appropriately changed according to different application conditions. In addition, the buffer layer, the hole storage layer, the channel layer and the barrier layer refer to the layer having at least one structure, not only one structure. Without departing from the principle of the present invention, these changes should also be regarded as the protection scope of the present invention.

[0105] The above is only a preferred embodiment of the present invention, and is not any formal or substantial limitation of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention, and these improvements and supplements should also be regarded as the protection scope of the present invention. Any technician familiar with this profession, without departing from the spirit and scope of the present invention, can make some changes, modifications and evolutions of the technical content disclosed above, which are equivalent embodiments of the present invention; at the same time, any changes, modifications and evolutions of any equivalent changes made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A III-nitride device having single particle irradiation resistance, characterized in that: The III-group nitride device comprises, from bottom to top, a substrate, a buffer layer, a hole storage layer, a channel layer, a barrier layer and a first passivation layer. A first source and a drain are provided on both sides of the channel layer, respectively. A p-GaN layer is provided between the first source and the drain near the first source side. Gates arranged at intervals along the y direction are provided on the p-GaN layer. Etching holes are provided between the gates arranged at intervals. The etching holes are etched to the channel layer, the hole storage layer or the buffer layer. Extraction electrodes are provided in the etching holes. The extraction electrodes are in contact with the side walls and the bottom along the etching holes. A second source is also provided near the first source. The second source is connected to the first source and the extraction electrode through a metal interconnection layer. Except for the top surfaces of the extraction electrode, the first source, the second source and the drain, the rest of the surface area is filled with a second passivation layer.

2. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The depth of the extraction electrode is independent of the depth of the second source.

3. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The bottom of the etching hole is located on the upper surface or inside of the buffer layer; or the bottom of the etching hole is located on the upper surface or inside of the hole storage layer; or the bottom of the etching hole is located on the upper surface or inside of the channel layer.

4. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The depths of adjacent etched holes are the same or different.

5. The III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The extraction electrode forms a Schottky contact or an Ohmic contact with the semiconductor layer at the sidewall and the bottom.

6. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The second source electrode extends into the buffer layer through the barrier layer, the channel layer and the hole storage layer; or the second source electrode extends into the hole storage layer through the barrier layer and the channel layer; or the second source electrode extends into the channel layer through the barrier layer; or the second source electrode passes through the barrier layer, the channel layer and the hole storage layer to contact the upper surface of the buffer layer; or the second source electrode passes through the barrier layer and the channel layer to contact the upper surface of the hole storage layer; or the second source electrode passes through the barrier layer to contact the upper surface of the channel layer.

7. A III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The shape of the etched cross section of the etched hole in the xy plane is circular, elliptical, polygonal or other irregular edge shapes, and the shapes and sizes of the etched cross sections of adjacent etched holes in the xy plane are the same or different; the ratio of the projection length of the etched hole in the y direction to the length of the p-GaN layer in the y direction is 5%-90%.

8. The III-nitride device with single particle irradiation resistance according to claim 1, characterized in that: The gate structure is one or a combination of Schottky-type p-GaN gate, ohmic p-GaN gate, recessed gate structure, MIS gate, or a complex gate structure having the above gate structure features.

9. A III-nitride device having single particle irradiation resistance according to any one of claims 1 to 8, characterized in that: The bottom of the extraction electrode is located on the upper surface of the hole storage layer, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

10. A III-nitride device having single particle irradiation resistance according to any one of claims 1 to 8, characterized in that: The extraction electrode with its bottom located on the upper surface of the hole storage layer and the extraction electrode with its bottom located inside the channel layer are arranged in sequence and spaced apart, and the bottom of the second source electrode is located on the upper surface of the hole storage layer.

Images