Display device and method of manufacturing the same

Abstract

The present application relates to a display device and a method for manufacturing the same. A display device according to one embodiment of the present invention includes: a base layer including a display area and a non-display area; and a plurality of pixels arranged in the display area and each including a plurality of sub-pixels. Each sub-pixel includes a pixel circuit layer and a display element layer arranged on the pixel circuit layer. The display element layer includes: a partition wall arranged in each sub-pixel; a levee arranged between sub-pixels adjacent to each other; a first electrode and a second electrode arranged on the partition wall and arranged to be spaced apart from each other; a reflective pattern arranged on the levee; and at least one light-emitting element arranged between the first electrode and the second electrode to emit light.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device, and more particularly, to a display device including an ultra-small light emitting element and a method of manufacturing the display device. Background Art

[0002] Even under adverse environmental conditions, a light emitting element can have relatively satisfactory durability and has excellent performance in terms of life span and brightness. Recently, research on a technology for applying such a light emitting element to various display devices has become significantly more active.

[0003] As part of such research, technology is being developed to manufacture an LED having a small size corresponding to a micrometer or nanometer scale using an inorganic crystal structure (for example, a structure obtained by growing a nitride-based semiconductor). Summary of the invention

[0004] Technical issues

[0005] Various embodiments of the present disclosure are directed to a display device having enhanced light efficiency and a method of manufacturing the display device.

[0006] Technical Solution

[0007] A display device according to an embodiment of the present disclosure may include: a base layer including a display area and a non-display area; and a plurality of pixels arranged in the display area and each including a plurality of sub-pixels. Each of the sub-pixels may include a pixel circuit layer and a display element layer arranged on the pixel circuit layer. The display element layer may include: a partition wall arranged in each of the sub-pixels; a levee arranged between sub-pixels adjacent to each other in the sub-pixels; a first electrode and a second electrode arranged on the partition wall and arranged to be spaced apart from each other; a reflective pattern arranged on the levee; and at least one light-emitting element arranged between the first electrode and the second electrode and configured to emit light.

[0008] In an implementation, the reflective pattern may have a structure surrounding an upper surface and a side surface of the bank.

[0009] In an embodiment, a partition wall may be provided between the bank and the light emitting element.

[0010] In an implementation, the bank and the partition wall may include the same material disposed on the same layer.

[0011] In an embodiment, the partition wall and the bank may be disposed on respective different layers.

[0012] In an implementation, the first electrode and the second electrode may include the same material disposed on the same layer on which the reflective pattern is disposed.

[0013] In an implementation, the first electrode and the second electrode may be disposed on a layer different from a layer on which the reflective pattern is disposed.

[0014] In an embodiment, the pixel circuit layer may include: at least one transistor disposed on the base layer; and a passivation layer disposed on the transistor.

[0015] In an implementation, the partition wall and the bank may be integrally formed on the passivation layer.

[0016] In an embodiment, the sub-pixel may include a light conversion pattern layer, wherein the light conversion pattern layer is disposed in a space defined by the bank and includes color conversion particles that convert light into light of a specific color.

[0017] In an embodiment, the display device may include a capping layer disposed on the light conversion pattern layer to overlap the display area.

[0018] In an implementation, the light conversion pattern layer may further include a color filter.

[0019] A method for manufacturing a display device according to an embodiment of the present disclosure may include: providing a base layer on which a plurality of sub-pixels are to be disposed; and forming a pixel circuit layer on the base layer, and forming a display element layer on the pixel circuit layer. Forming the display element layer includes: forming a partition wall in each of the sub-pixels; forming a bank between adjacent sub-pixels in the sub-pixels; forming a first electrode and a second electrode spaced apart from each other on the partition wall; forming a reflective pattern on the bank; and forming at least one light-emitting element, the light-emitting element being disposed between the first electrode and the second electrode and configured to emit light.

[0020] In an implementation, forming the reflective pattern may include forming the reflective pattern such that the reflective pattern surrounds an upper surface and a side surface of the bank.

[0021] In an embodiment, the partition wall and the bank may be formed on the same layer through the same process.

[0022] In an implementation, the partition walls and the banks may be formed on corresponding different layers through corresponding different processes.

[0023] In an embodiment, the first electrode and the second electrode may be formed on the same layer through the same process as forming the reflective pattern.

[0024] In an embodiment, the first electrode and the second electrode may be formed on a different layer from the reflective pattern through a process different from a process of forming the reflective pattern.

[0025] In an embodiment, forming the at least one light emitting element may include aligning the at least one light emitting element between the first electrode and the second electrode by applying corresponding alignment voltages to the first electrode and the second electrode, respectively.

[0026] In an embodiment, the method may further include forming a light conversion pattern layer in a space defined by the bank in the sub-pixel, the light conversion pattern layer including color conversion particles that convert light into light of a specific color.

[0027] Beneficial Effects

[0028] The display device and the method of manufacturing the display device according to the present disclosure may have the following effects.

[0029] First, light emitted from the light emitting element may be reflected toward the capping layer by the reflective pattern provided on the bank, and thus light efficiency may be improved.

[0030] Second, the pixel circuit layer, the display element layer and the light conversion pattern layer are all disposed on the base layer, thereby shortening the optical path along which the light emitted from the light emitting element is emitted to the outside through the capping layer, thereby minimizing the light loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a perspective view showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 2 A display device according to an embodiment of the present disclosure is shown, and a display device using Figure 1 Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0033] Figures 3a to 3d It is shown that according to various embodiments Figure 2 A circuit diagram of an example of a unit light emitting area of ​​a display device.

[0034] Figure 4a It is schematically shown that the Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG.

[0035] Figure 4b It is shown Figure 4a Figure 4 shows a diagram of the dike and reflection pattern.

[0036] Figure 5 It is along Figure 4a A cross-sectional view taken along line II'.

[0037] Figures 6a to 6c A display device according to an embodiment of the present disclosure is schematically shown and corresponds to Figure 4aCross-sectional view along line II'.

[0038] Figure 7 A display device according to an embodiment of the present disclosure is shown, and a light conversion pattern layer is connected to Figure 5 A schematic cross-sectional view of the structure of a display device.

[0039] Figures 8a to 8k is shown in order to manufacture Figure 5 A cross-sectional view of a method of displaying a device.

[0040] Figure 9a and Figure 9b is a cross-sectional view showing a display device according to an embodiment of the present disclosure, and corresponds to Figure 4a Cross-sectional view along line II'. DETAILED DESCRIPTION

[0041] The same components will be represented by the same reference numerals. In addition, it should be noted that the thickness, proportions and sizes of the components of the drawings may be exaggerated only for ease of description and clarity. The term "and / or" may include any and all combinations of one or more of the related listed items.

[0042] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In the present disclosure, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise.

[0043] In addition, the terms "under", "below", "above", "upper", etc. are used herein to describe the relationship between one or more components shown in the drawings. These terms may be relative terms describing the positions of components in the drawings, but the positions of components are not limited thereto.

[0044] It will also be understood that when used in this specification, the terms "comprising", "including", "having", etc. indicate the presence of stated features, integers, steps, operations, elements, parts and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or combinations thereof.

[0045] Figure 1 is a perspective view showing a light emitting element according to an embodiment of the present disclosure.

[0046] like Figure 1As shown in , the light emitting element LD according to the embodiment of the present disclosure may include a first conductive semiconductor layer 11 , a second conductive semiconductor layer 13 , and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 .

[0047] For example, the light emitting element LD may have a structure formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13. The light emitting element LD may be provided in a rod shape extending in one direction. Here, the term "rod shape" may include a rod-like shape or a rod-like shape extending in a longitudinal direction (ie, having an aspect ratio greater than 1).

[0048] The light emitting element LD may have a rod shape formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13 in a longitudinal direction of the light emitting element LD, and has a first end and a second end based on the active layer 12. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the first end of the light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the second end.

[0049] The light emitting element LD can be manufactured in a small size, having a diameter and / or length corresponding to, for example, a micrometer-scale or nanometer-scale size. However, the size of the light emitting element LD according to the embodiment of the present disclosure is not limited thereto, and the size of the light emitting element LD can be changed to meet the requirements of the display device to which the light emitting element LD is applied.

[0050] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include a semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. The material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0051] The active layer 12 may be formed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. According to an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In addition, the active layer 12 may be formed using a material such as AlGaN or AlInGaN.

[0052] If an electric field having a predetermined voltage or more is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by recombination of electron-hole pairs in the active layer 12 .

[0053] The second conductive semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlNh, and InN, and doped with a second conductive dopant such as Mg. The material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of a variety of other materials.

[0054] According to an embodiment of the present disclosure, the light emitting element LD may include not only the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13, but may also include a fluorescent layer, another active layer, another semiconductor layer, and / or an electrode layer disposed on and / or under each layer. For example, the light emitting element LD may include an electrode layer disposed on the second conductive semiconductor layer 13.

[0055] The light emitting element LD may further include an insulating film 14. In the embodiment of the present disclosure, the insulating film 14 may be omitted, or may be provided to cover only some of the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0056] For example, the insulating film 14 may be provided on a portion of the light emitting element LD except for the opposite ends thereof, so that the opposite ends of the light emitting element LD may be exposed. Figure 1 , the insulating film 14 is shown in FIG. 1 (a portion of which has been removed from the insulating film 14 for illustration), but the light emitting element LD may be formed such that the entire side surface of its cylindrical body is surrounded by the insulating film 14 .

[0057] The insulating film 14 may be provided to surround at least a portion of the outer peripheral surface of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13. For example, the insulating film 14 may be provided to surround at least the outer peripheral surface of the active layer 12.

[0058] According to an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2At least one insulating material in the group consisting of, but the present disclosure is not limited thereto. In other words, various materials having insulating properties can be used.

[0059] If the insulating film 14 is provided on the light emitting element LD, the active layer 12 may be prevented from being short-circuited with the first electrode and / or the second electrode (not shown).

[0060] Due to the insulating film 14, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In the case where a plurality of light emitting elements LD are arranged in close contact with each other, the insulating film 14 can prevent an undesirable short circuit from occurring between adjacent light emitting elements LD.

[0061] The light emitting element LD can be used as a light source for various display devices. For example, the light emitting element LD can be used in a lighting device or a self-emitting display device.

[0062] Hereinafter, a display device including a light emitting element LD according to an embodiment of the present disclosure will be described in detail.

[0063] Figure 2 A display device according to an embodiment of the present disclosure is shown, and a display device using Figure 1 Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0064] To illustrate, Figure 2 The structure of the display device is schematically shown, which focuses on the display area DA in which the image is displayed. In some embodiments, although not shown, at least one driving circuit (eg, a scan driver and a data driver) and / or a plurality of signal lines may be further provided in the display device.

[0065] Reference Figure 1 and Figure 2 According to an embodiment of the present disclosure, a display device may include: a base layer BSL; a plurality of pixels PXL, which are disposed on the base layer BSL and each include at least one light emitting element LD; a driver (not shown) which is disposed on the base layer BSL and configured to drive the pixels PXL; and a line component (not shown) which is configured to connect the pixels PXL to the driver.

[0066] According to the method of driving the light emitting element LD, the display device can be divided into a passive matrix type display device and an active matrix type display device. In the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD, and a switching transistor configured to transmit a data signal to the driving transistor.

[0067] Recently, considering resolution, contrast and operating speed, an active matrix display device capable of selectively turning on each pixel PXL has become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix display device in which the pixels PXL can be turned on in groups may also employ components (e.g., a first electrode and a second electrode) for driving the light emitting element LD.

[0068] The base layer BSL may be a substrate of a display device and include a display area DA and a non-display area NDA. The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driver for driving the pixels PXL and some of the line components for connecting the pixels PXL to the driver are disposed.

[0069] Although an example in which the display area DA is disposed in the central area of ​​the display device and the non-display area NDA is disposed in the peripheral area of ​​the display device to surround the display area DA is shown in the drawings, the present disclosure is not limited thereto and positions thereof may be changed.

[0070] The display area DA may have various shapes. For example, the display area DA may be provided in various forms, such as a closed polygon including sides formed by linear lines, a circle, an ellipse, etc. including sides formed by curved lines, and a semicircle, a semiellipse, etc. including sides formed by linear lines and curved lines. The non-display area NDA may be provided on at least one side of the display area DA. Although a structure in which the non-display area NDA surrounds the display area DA is shown in the drawings, the present disclosure is not limited thereto.

[0071] The base layer BSL may be a rigid substrate or a flexible substrate, and the present disclosure is not limited thereto. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, or may be a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer BSL may be a transparent substrate, but is not limited thereto. In addition, the base layer BSL may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0072] The pixels PXL may be disposed in the display area DA on the base layer BSL. Each of the pixels PXL represents a minimum unit for displaying an image, and a plurality of pixels may be provided.

[0073] Each of the pixels PXL may include a light emitting element LD configured to be driven in response to a scan signal and a data signal. The light emitting element LD may have a small size corresponding to a nanometer or micrometer level and be connected in parallel with a light emitting element LD disposed adjacent thereto. The light emitting element LD may form a light source of the corresponding pixel PXL.

[0074] In addition, each of the pixels PXL may include a plurality of sub-pixels SP1, SP2, and SP3. For example, each pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, which are configured to emit light of different colors. For example, the first sub-pixel SP1 may be a red sub-pixel configured to emit red light, the second sub-pixel SP2 may be a green sub-pixel configured to emit green light, and the third sub-pixel SP3 may be a blue sub-pixel configured to emit blue light. However, the color, type, and / or number of sub-pixels forming each pixel PXL are not limited to the above examples.

[0075] Although Figure 2 The pixels PXL are shown to be arranged in the display area DA in a first direction DR1 and a second direction DR2 different from the first direction DR1 in a matrix form, but the arrangement of the pixels PXL may be changed in various ways without being limited to the above examples. In addition, the arrangement of the plurality of sub-pixels in each of the pixels PXL may also be changed in various ways.

[0076] The driver may provide a driving signal to each pixel PXL through the line component and thereby control the operation of the pixel PXL. Figure 2 In the figure, for the convenience of explanation, the line components are omitted.

[0077] The driver may include: a scan driver configured to provide a scan signal to the pixel PXL through a scan line; an emission driver configured to provide an emission control signal to the pixel PXL through an emission control line; a data driver configured to provide a data signal to the pixel PXL through a data line; and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0078] Figures 3a to 3d It is shown that according to various embodiments Figure 2 A circuit diagram of an example of a unit light emitting area of ​​a display device.

[0079] Reference Figures 3a to 3d , each of the first to third sub-pixels can be configured as an active pixel. However, the type, configuration and / or driving method of each of the first to third sub-pixels are not particularly limited. For example, each of the first to third sub-pixels can be configured as a pixel of a passive display device or an active display device that can have various known structures.

[0080] In addition, refer to Figures 3a to 3d , the first to third sub-pixels may have substantially the same structure or a similar structure. Hereinafter, for convenience, the first sub-pixel among the first to third sub-pixels will be described as a representative example.

[0081] Reference Figure 1 , Figure 2 and Figure 3a The first sub-pixel SP1 may include an emission area EMA configured to generate light having brightness corresponding to a data signal and a pixel driving circuit 144 configured to drive the emission area EMA.

[0082] In an embodiment, the emission area EMA may include a plurality of light emitting elements LD connected in parallel to each other between a first driving power source VDD and a second driving power source VSS. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source. Here, during the emission period of the first sub-pixel SP1, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage of the light emitting element LD or a voltage greater than that.

[0083] A first electrode (e.g., an anode electrode) of each of the light emitting elements LD may be coupled to a first driving power source VDD via a pixel driving circuit 144. A second electrode (e.g., a cathode electrode) of each of the light emitting elements LD may be coupled to a second driving power source VSS. Each of the light emitting elements LD may emit light at a brightness corresponding to a driving current controlled by the pixel driving circuit 144.

[0084] Although Figures 3a to 3d The light emitting elements LD are shown to be connected in parallel with each other in the same direction (e.g., forward direction) between the first driving power source VDD and the second driving power source VSS, but the present disclosure is not limited thereto. For example, some of the light emitting elements LD may be connected to each other in the forward direction between the first driving power source VDD and the second driving power source VSS, while other light emitting elements LD may be connected to each other in the reverse direction.

[0085] One of the first driving power source VDD and the second driving power source VSS may be provided in the form of an AC voltage. In this case, the light emitting elements LD may emit light alternately in groups in the same connection direction. Alternatively, the first sub-pixel SP1 may include only a single light emitting element LD.

[0086] The pixel driving circuit 144 may include a first transistor T1 and a second transistor T2, and a storage capacitor Cst. The structure of the pixel driving circuit 144 is not limited to Figure 3a The structure of the embodiment shown in .

[0087] A first electrode of a first transistor (T1; a switching transistor) is coupled to a data line Dj, and a second electrode thereof is coupled to a first node N1. Here, the first electrode and the second electrode of the first transistor T1 may be different electrodes. If the first electrode is a source electrode, the second electrode is a drain electrode. A gate electrode of the first transistor T1 is coupled to a scan line Si.

[0088] When a scan signal having a voltage (e.g., a low level voltage) capable of turning on the first transistor T1 is supplied from the scan line Si, the first transistor T1 is turned on to electrically couple the data line Dj with the first node N1. Here, a data signal of a corresponding frame is supplied to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged to the storage capacitor Cst.

[0089] A first electrode of the second transistor (T2; driving transistor) is coupled to the first driving power supply VDD, and a second electrode of the second transistor (T2; driving transistor) is electrically coupled to a first electrode of each of the light emitting elements LD. A gate electrode of the second transistor T2 is coupled to the first node N1. Thus, the second transistor T2 can control the amount of driving current to be provided to the light emitting element LD in response to the voltage of the first node N1.

[0090] One electrode of the storage capacitor Cst is coupled to the first driving power source VDD, and the other electrode thereof is coupled to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1, and maintains the charged voltage until a data signal of a subsequent frame is supplied.

[0091] For illustration, Figure 3a A pixel driving circuit 144 having a relatively simple structure is shown, which includes: a first transistor T1, which is configured to transmit a data signal to a first sub-pixel SP1; a storage capacitor Cst, which is configured to store the data signal; and a second transistor T2, which is configured to provide a driving current corresponding to the data signal to the light emitting element LD.

[0092] However, the present disclosure is not limited thereto, and the structure of the pixel driving circuit 144 may be changed in various ways. For example, the pixel driving circuit 144 may further include at least one transistor element (such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light emitting element LD) or other circuit elements (such as a boost capacitor for boosting the voltage of the first node N1).

[0093] In addition, although Figure 3aThe transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel driving circuit 144 are shown to be formed of P-type transistors, but the type of transistor is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 included in the pixel driving circuit 144 may be an N-type transistor.

[0094] like Figure 3b As shown in , in addition to the first transistor T1 and the second transistor T2, the pixel driving circuit 144 may further include a third transistor T3. The third transistor T3 may be coupled between the j-th data line Dj and the anode electrode of each of the light emitting elements LD. The gate electrode of the third transistor T3 may be coupled to the control line CLi, so that the third transistor T3 may be turned on when a control signal is provided to the control line CLi, and the third transistor T3 may be turned off in other cases.

[0095] For convenience, Figure 3b It is shown that all of the first transistor T1 to the third transistor T3 are formed by P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 included in the pixel driving circuit 144 may be formed by an N-type transistor, or all of the first transistor T1 to the third transistor T3 may be N-type transistors.

[0096] Next, refer to Figure 1 , Figure 2 and Figure 3c , the first transistor T1 and the second transistor T2 may be N-type transistors. In addition to the change in the connection position of some components due to the change in the type of transistor, Figure 3c The configuration and operation of the pixel driving circuit 144 shown in FIG. 1 are similar to those of FIG. Figure 3a Therefore, detailed descriptions thereof will be omitted.

[0097] Reference Figure 1 , Figure 2 and Figure 3d , the pixel driving circuit 144 can be connected to the scan line Si and the data line Dj of the first sub-pixel SP1. For example, if the first sub-pixel SP1 is disposed in the i-th row and the j-th column of the display area DA, the pixel driving circuit 144 of the first sub-pixel SP1 can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0098] In addition, the pixel driving circuit 144 may also be coupled to at least one other scan line. For example, the first subpixel SP1 disposed on the i-th row of the display area DA may be further coupled to the i-1th scan line Si-1 and / or the i+1th scan line Si+1.

[0099] The pixel driving circuit 144 may be coupled not only to the first driving power source VDD and the second driving power source VSS, but also to a third power source. For example, the pixel driving circuit 144 may also be coupled to an initialization power source Vint.

[0100] The pixel driving circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0101] A first electrode (e.g., source electrode) of the first transistor (T1; driving transistor) may be coupled to a first driving power source VDD via a fifth transistor T5, and a second electrode (e.g., drain electrode) thereof may be coupled to one end of the light emitting element LD via a sixth transistor T6. A gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 may control a driving current flowing through the light emitting element LD between the first driving power source VDD and the second driving power source VSS in response to a voltage of the first node N1.

[0102] The second transistor (T2; switching transistor) may be coupled between the j-th data line Dj coupled to the first sub-pixel SP1 and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 is coupled to the i-th scan line Si coupled to the first sub-pixel SP1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is provided from the i-th scan line Si, the second transistor T2 is turned on to electrically couple the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the j-th data line Dj may be transmitted to the first transistor T1.

[0103] The third transistor T3 is coupled between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is coupled to the i-th scan line Si. When a scan signal having a gate-on voltage is provided from the i-th scan line Si, the third transistor T3 is turned on to electrically couple the drain electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0104] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is coupled to the previous scan line, for example, the i-1th scan line Si-1. When a scan signal having a gate-on voltage is provided to the i-1th scan line Si-1, the fourth transistor T4 is turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be equal to or less than the minimum voltage of the data signal.

[0105] The fifth transistor T5 is coupled between the first driving power source VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is coupled to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0106] The sixth transistor T6 is coupled between the first transistor T1 and the first end of the light emitting element LD. The gate electrode of the sixth transistor T6 may be coupled to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0107] The seventh transistor T7 is connected between the first end of the light emitting element LD and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first end of the light emitting element LD.

[0108] The storage capacitor Cst is coupled between the first driving power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both a data signal applied to the first node N1 during each frame period and a threshold voltage of the first transistor T1.

[0109] For convenience, Figure 3d It is shown that all of the first transistor T1 to the seventh transistor T7 are formed by P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 included in the pixel driving circuit 144 may be formed by an N-type transistor, or all of the first transistor T1 to the seventh transistor T7 may be N-type transistors.

[0110] Hereinafter, the following will be described in detail with reference to the accompanying drawings. Figure 2 pixels of a display device.

[0111] Figure 4a It is schematically shown that the Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG. Figure 4b It is shown Figure 4a Figure 4 shows a diagram of the dike and reflection pattern. Figure 5 It is along Figure 4a A cross-sectional view taken along line II'.

[0112] Although for the sake of explanation, Figure 4aIt is shown that the plurality of light emitting elements LD disposed in each sub-pixel SP1, SP2, and SP3 are horizontally aligned, but the arrangement of the light emitting elements LD is not limited thereto. For example, at least some of the light emitting elements LD may be aligned in a direction intersecting the horizontal direction. Figure 4a The transistor connected to the light emitting element LD and the signal line connected to the transistor are omitted in the figure. Figure 4a and Figure 5 A simplified structure of one pixel PXL is shown, for example, each electrode is shown to have only a single electrode layer, but the present disclosure is not limited thereto.

[0113] Reference Figures 1 to 5 , a display device according to an embodiment of the present disclosure may include a base layer BSL on which a plurality of pixels PXL are provided.

[0114] Each of the pixels PXL may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 disposed on the base layer BSL. In an embodiment of the present disclosure, the first subpixel SP1 may be a red subpixel configured to emit red light, the second subpixel SP2 may be a green subpixel configured to emit green light, and the third subpixel SP3 may be a blue subpixel configured to emit blue light.

[0115] Each of the first to third sub-pixels SP1 to SP3 may include an emission area EMA configured to emit light, and a non-emission area PPA disposed near a periphery of the emission area EMA.

[0116] Each of the first to third sub-pixels SP1 to SP3 may include a base layer BSL, a pixel circuit layer PCL, and a display element layer DPL.

[0117] The pixel circuit layer PCL may include a buffer layer BFL disposed on the base layer BSL, a first transistor T1 and a second transistor T2 disposed on the buffer layer BFL, and a driving voltage line DVL. In addition, the pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3 may further include a passivation layer PSV disposed on the first transistor T1 and the second transistor T2 and the driving voltage line DVL.

[0118] The base layer BSL may be a rigid substrate or a flexible substrate, and there is no particular limitation on its material or characteristics. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer BSL may be a transparent substrate, but the present disclosure is not limited thereto, and the base layer BSL may be a translucent substrate, an opaque substrate, or a reflective substrate. In addition, although the base layer BSL is shown in the drawings as having a single-layer structure, the base layer BSL may have a multi-layer structure.

[0119] The buffer layer BFL may prevent impurities from diffusing into the first transistor T1 and the second transistor T2. Depending on the material or processing conditions of the base layer BSL, the buffer layer BFL may be omitted.

[0120] The first transistor T1 may be electrically coupled to some of the light emitting elements LD disposed in the display element layer DPL of the corresponding sub-pixel. In this case, the first transistor T1 may be a driving transistor configured to drive the light emitting element LD. The second transistor T2 may be a switching transistor configured to switch the first transistor T1.

[0121] Each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0122] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a source region contacting the source electrode SE and a drain region contacting the drain electrode DE. A region between the source region and the drain region may be a channel region.

[0123] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the source region and the drain region may be a semiconductor pattern doped with impurities.

[0124] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. The source electrode SE and the drain electrode DE may respectively contact the source region and the drain region of the semiconductor layer SCL through corresponding contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0125] In the drawings, although the first transistor T1 and the second transistor T2 are LTPS thin film transistors, the first transistor T1 and the second transistor T2 are not limited thereto.

[0126] In addition, although the driving voltage line DVL is shown as being disposed on the interlayer insulating layer ILD in the drawings, the location of the driving voltage line DVL is not limited thereto. For example, the driving voltage line DVL may be disposed on any insulating layer included in the pixel circuit layer PCL. Figure 3a VSS) may be applied to the driving voltage line DVL.

[0127] The passivation layer PSV may include a first contact hole CH1 exposing a portion of the drain electrode DE of the first transistor T1 , and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

[0128] The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a partition wall PW, a bank BNK, a reflective pattern RP, first and second electrodes REL1 and REL2, first and second connection lines CNL1 and CNL2, a plurality of light emitting elements LD, first and second contact electrodes CNE1 and CNE2, and the like.

[0129] The partition wall PW may be disposed in the first to third sub-pixels SP1 to SP3. In detail, the partition wall PW may be disposed on the passivation layer PSV in the emission area EMA of each of the first to third sub-pixels SP1 to SP3. At least two partition walls PW may be disposed in each of the sub-pixels SP1, SP2, and SP3. The partition walls PW disposed adjacent to each other are spaced apart from each other by a predetermined distance. In the accompanying drawings, a case where three partition walls PW are disposed at positions spaced apart from each other by a predetermined distance in each of the sub-pixels SP1, SP2, and SP3 is shown.

[0130] Adjacent partition walls PW may be disposed on the passivation layer PSV and spaced apart from each other by a length L of one light emitting element LD (see Figure 1 ) or more. The light emitting element LD may be disposed between adjacent partition walls PW in the emission area EMA. In the periphery of the emission area EMA, the partition wall PW is disposed between the light emitting element LD and the bank BNK.

[0131] The partition wall PW may include a curved surface having a cross-sectional shape (such as a semicircular or semi-elliptical shape) whose width decreases upward from one surface of the passivation layer PSV. In the accompanying drawings, the partition wall PW is shown as having a trapezoidal cross-section. In the cross-sectional view, the shape of each of the partition walls PW is not limited to the above example, and can be changed in various ways within the range that can improve the efficiency of light emitted from each of the light-emitting elements LD. Two adjacent partition walls PW can be set on the same layer on the passivation layer PSV and have the same height.

[0132] The bank BNK may be further disposed on the passivation layer PSV. The bank BNK may be disposed between adjacent sub-pixels SP1 to SP3, separate adjacent sub-pixels SP1 to SP3 from each other, and prevent light emitted from the sub-pixels SP1 to SP3 from traveling toward the adjacent sub-pixels SP1 to SP3. To this end, the bank BNK may have a thickness T2 greater than a thickness T1 of the partition wall PW.

[0133] In addition, the bank BNK may define an emission area EMA of each of the sub-pixels SP1 to SP3. Although the region in which the bank BNK is disposed corresponds to the non-emission area PPA of each of the sub-pixels SP1 to SP3, light emitted from the light emitting element LD may be reflected by the reflective pattern RP disposed on the bank BNK and travel upward. Therefore, although the bank BNK is disposed in the non-emission area PPA, the display device according to the present disclosure enables light to be emitted even in the region in which the bank BNK is disposed.

[0134] The partition wall PW and the bank BNK may be formed of the same material on the same layer. For example, although the partition wall PW and the bank BNK may be formed of an organic insulating material including an organic material, the present disclosure is not limited thereto.

[0135] The bank BNK may be formed of a material different from that of the partition wall PW. For example, the bank BNK may include Cr, Cr / CrO x In the case where the bank BNK is formed of a resin including a carbon pigment, a black dye, graphite, etc., the carbon pigment may be carbon black, which is a black pigment having a light shielding function. In this case, the bank BNK may be used as a black matrix capable of preventing color mixing from being caused between the sub-pixels SP1, SP2, and SP3.

[0136] The bank BNK may include a curved surface having a cross-sectional shape (such as a semicircular or semi-elliptical shape) whose width decreases upward from one surface of the passivation layer PSV. In the drawings, the bank BNK is shown as having a trapezoidal cross-section. However, in the cross-sectional view, the shape of the bank BNK is not limited to the aforementioned embodiment, and may be changed in various ways within a range capable of preventing light interference between adjacent sub-pixels SP1 to SP3.

[0137] The first connection line CNL1 may be electrically coupled to the pixel circuit layer PCL through a first contact hole CH1 formed in the passivation layer PSV. In detail, the first connection line CNL1 may be connected to a portion of the drain electrode DE of the first transistor T1 of the pixel circuit layer PCL. Figure 4a It is shown that the first contact hole CH1 is formed in the non-emission area PPA, but the first contact hole CH1 may be formed in the emission area EMA.

[0138] The first connection line CNL1 may extend from each of the first to third sub-pixels SP1 to SP3 in the first direction DR1. The first connection line CNL1 may be disposed only in one corresponding sub-pixel to independently drive each of the first to third sub-pixels SP1 to SP3.

[0139] The second connection line CNL2 may also be electrically coupled to the pixel circuit layer PCL through a second contact hole CH2 formed in the passivation layer PSV. In detail, the second connection line CNL2 may be connected to a portion of the driving voltage line DVL of the pixel circuit layer PCL.

[0140] The second connection line CNL2 may extend in a direction parallel to the direction in which the first connection line CNL1 extends. The second connection line CNL2 may be common to the first to third subpixels SP1 to SP3. Therefore, the first to third subpixels SP1 to SP3 may be commonly coupled to the second connection line CNL2.

[0141] Each of the first and second electrodes REL1 and REL2 may be disposed in the emission area EMA of each of the first to third subpixels SP1 to SP3 and extend in a second direction DR2 intersecting the first direction DR1. The first and second electrodes REL1 and REL2 may be disposed on the same plane and spaced apart from each other by a predetermined distance.

[0142] The first electrode REL1 may be coupled to the first connection line CNL1. For example, the first electrode REL1 may be integrally coupled to the first connection line CNL1. In the drawings, a case is shown where the first electrode REL1 includes a 1-1 electrode REL1_1 and a 1-2 electrode REL1_2, wherein the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 branch from the first connection line CNL1 extending in the first direction DR1 in the second direction DR2. The 1-1 electrode REL1_1, the 1-2 electrode REL1_2, and the first connection line CNL1 may be integrally provided and electrically and / or physically coupled to each other.

[0143] In the case where the first electrode REL1 and the first connection line CNL1 are formed and / or disposed integrally with each other, the first connection line CNL1 may be considered as a region of the first electrode REL1. However, the present disclosure is not limited thereto. For example, in some embodiments, the first electrode REL1 and the first connection line CNL1 may be formed separately and electrically coupled to each other through a contact hole, a through hole, etc., not shown.

[0144] The second electrode REL2 may be coupled to the second connection line CNL2. For example, the second electrode REL2 may be integrally coupled to the second connection line CNL2. In the drawings, a structure is shown in which the second connection line CNL2 extends in the first direction DR1 and the second electrode REL2 branches from the second connection line CNL2 in the second direction DR2.

[0145] In the case where the second electrode REL2 and the second connection line CNL2 are formed and / or arranged integrally with each other, the second connection line CNL2 can be considered as a region of the second electrode REL2. However, the present disclosure is not limited thereto. For example, in some embodiments, the second electrode REL2 and the second connection line CNL2 can be formed separately and electrically connected to each other through a contact hole, a through hole, etc. not shown.

[0146] Each of the first electrode REL1 and the second electrode REL2 may serve as an alignment electrode for aligning the light emitting element LD in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 .

[0147] In detail, before aligning the light emitting element LD in the emission area EMA of each of the first to third sub-pixels SP1 to SP3, a first alignment voltage may be applied to the first electrode REL1 through the first connection line CNL1, and a second alignment voltage may be applied to the second electrode REL2 through the second connection line CNL2. The first alignment voltage and the second alignment voltage may have different voltage levels. When predetermined alignment voltages having different voltage levels are respectively applied to the first electrode REL1 and the second electrode REL2, an electric field may be formed between the first electrode REL1 and the second electrode REL2. Therefore, the light emitting element LD may be aligned between the first electrode REL1 and the second electrode REL2.

[0148] In a plan view, the second electrode REL2 may be disposed between the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 and spaced apart from each of the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 by a predetermined distance.

[0149] After aligning the light emitting element LD in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 , each of the first and second electrodes REL1 and REL2 may function as a driving electrode for driving the light emitting element LD.

[0150] The first electrode REL1 and the second electrode REL2 may each have a shape corresponding to the shape of the partition wall PW, and thus may be made of a material having a predetermined reflectivity to allow light emitted from opposite ends EP1 and EP2 of each of the light emitting elements LD to travel in a direction along which an image of the display device is displayed (e.g., in a forward direction). In this case, the first electrode REL1 and the second electrode REL2 may function as a reflector to enhance the efficiency of light emitted from the light emitting element LD.

[0151] In detail, the first and second electrodes REL1 and REL2, and the first and second connection lines CNL1 and CNL2 may be formed of a conductive material having a predetermined reflectivity. Metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof may be used as the conductive material. However, the materials of the first and second electrodes REL1 and REL2, and the first and second connection lines CNL1 and CNL2 are not limited to the above materials.

[0152] Although the drawings show a case where each of the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 has a single-layer structure, it may have a multi-layer structure formed by stacking two or more materials of metal, alloy, conductive oxide, and conductive polymer.

[0153] Any one of the first electrode REL1 and the second electrode REL2 may be an anode electrode, and the other may be a cathode electrode. In an embodiment of the present disclosure, the first electrode REL1 may be an anode electrode, and the second electrode REL2 may be a cathode electrode.

[0154] Each of the light emitting elements LD may be formed as a light emitting element which is made of a material having an inorganic crystal structure and has an ultra-small size corresponding to, for example, a nanometer order or a micrometer order.

[0155] Although at least two or tens of light emitting elements LD are disposed in the emission area EMA of each of the first to third subpixels SP1 to SP3, the present disclosure is not limited thereto. In an embodiment, the number of light emitting elements LD disposed in each of the subpixels SP1, SP2, and SP3 may be varied in various ways.

[0156] Each of the light emitting elements LD may include a stacked emission pattern formed by continuously stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13 in a longitudinal direction of each light emitting element LD. In addition, each of the light emitting elements LD may further include an insulating film 14 that surrounds the outer peripheral surface of the stacked emission pattern. In an embodiment of the present disclosure, each of the light emitting elements LD may have a cylindrical shape. In this case, each light emitting element LD may have a first end EP1 corresponding to any one of the lower part of the cylinder and the upper part of the cylinder, and a second end EP2 corresponding to the other of the lower part of the cylinder and the upper part of the cylinder. Any one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the first end EP1 of each light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the second end EP2 of each light emitting element LD.

[0157] In an embodiment of the present disclosure, the light emitting element LD may be divided into a plurality of first light emitting elements LD1 aligned between the 1-1 electrode REL1_1 and the second electrode REL2, and a plurality of second light emitting elements LD2 aligned between the second electrode REL2 and the 1-2 electrode REL1_2. A second insulating layer INS2 for covering a portion of an upper surface of each of the light emitting elements LD may be disposed on the light emitting element LD. A first insulating layer INS1 may be disposed between each of the light emitting elements LD and the passivation layer PSV.

[0158] The first insulating layer INS1 may be filled into the space between the passivation layer PSV and each of the light emitting elements LD to stably support the light emitting element LD and prevent the light emitting element LD from being removed from the passivation layer PSV. The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although in an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer having an advantage in protecting the light emitting element LD from the pixel circuit layer PCL, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer having an advantage in planarizing the supporting surface of the light emitting element LD.

[0159] Specifically, the first insulating layer INS1 may extend to the non-emission area PPA of the sub-pixels SP1, SP2, and SP3 to cover even a portion of the bank BNK. Although the drawings show a case where the first insulating layer INS1 completely covers the side surface and the upper surface of the bank BNK, the first insulating layer INS1 may be provided to cover only a portion of the bank BNK.

[0160] The reflective pattern RP may be disposed on the bank BNK. The reflective pattern RP may be disposed to reflect light traveling toward a side of each of the sub-pixels SP1, SP2, and SP3 upward.

[0161] The light emitting element LD may emit light having a Lambertian form. In detail, the light emitted from the light emitting element LD is distributed to have a spherical shape. Therefore, in the emission area EMA of each sub-pixel SP1, SP2, and SP3, the periphery of the emission area EMA adjacent to the non-emission area PPA is smaller than the central portion of the emission area EMA in terms of the amount of light emitted from the light emitting element LD.

[0162] In an embodiment of the present disclosure, the reflective pattern RP disposed on the bank BNK may reflect light emitted from the sub-pixels SP1, SP2, and SP3 that travels toward the periphery of the sub-pixels SP1, SP2, and SP3 (in other words, light that travels toward the non-emitting area PPA) in the direction in which the image is displayed. Specifically, the reflective pattern RP is formed along the shape of the bank BNK. Therefore, as shown in the drawings, in the case where the bank BNK has a trapezoidal cross-section, the light reflected by the reflective pattern RP may effectively travel in the direction in which the image is displayed.

[0163] To this end, the reflective pattern RP may include a conductive material having a predetermined reflectivity. As the conductive material, metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof may be used.

[0164] The reflection pattern RP may be formed not only on the side surface of the bank BNK but also on the upper surface of the bank BNK. For example, the reflection pattern RP may be formed to completely cover the upper and side surfaces of the bank BNK.

[0165] The second insulating layer INS2 may be disposed on the light emitting element LD. The second insulating layer INS2 may be an organic insulating layer including an organic material. In an embodiment of the present disclosure, the second insulating layer INS2 may be disposed on a portion of the upper surface of each of the light emitting elements LD so that the opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside. In addition, the second insulating layer INS2 may also be disposed on the reflective pattern RP, thereby preventing the reflective pattern RP from being connected to the first contact electrode CNE1 or the second contact electrode CNE2.

[0166] The first contact electrode CNE1 may be disposed on the first insulating layer INS1 and thus coupled to the first electrode REL1 exposed by removing a portion of the first insulating layer INS1. The first contact electrode CNE1 may reliably electrically and / or physically couple the first electrode REL1 to one of the opposite ends EP1 and EP2 of the light emitting element LD. The first contact electrode CNE1 may be formed of a transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the first electrode REL1 in a forward direction of the display device to travel in the forward direction without loss.

[0167] Here, the first contact electrode CNE1 may include a 1-1th contact electrode CNE1_1 disposed on the 1-1th electrode REL1_1, and a 1-2th contact electrode CNE1_2 disposed on the 1-2th electrode REL1_2.

[0168] A third insulating layer INS3 for covering the first contact electrode CNE1 may be disposed on the first contact electrode CNE1. The third insulating layer INS3 may prevent the first contact electrode CNE1 from being exposed to the outside, thereby preventing the first contact electrode CNE1 from being corroded.

[0169] The third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although the third insulating layer INS3 may have a single-layer structure as shown in the drawings, the present disclosure is not limited thereto. For example, the third insulating layer INS3 may have a multi-layer structure. In the case where the third insulating layer INS3 has a multi-layer structure, the third insulating layer INS3 may have a structure formed by alternately stacking a plurality of inorganic insulating layers and a plurality of organic insulating layers. For example, the third insulating layer INS3 may have a structure formed by sequentially stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer.

[0170] The second contact electrode CNE2 may also be electrically coupled to the second electrode REL2 exposed by removing a portion of the first insulating layer INS1. The second contact electrode CNE2 may reliably electrically and / or physically couple the second electrode REL2 to the other of the opposite ends EP1 and EP2 of the light emitting element LD, the other end not being connected to the first electrode REL1. The second contact electrode CNE2 may be formed of a transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the second electrode REL2 in the forward direction of the display device to travel in the forward direction without loss.

[0171] As described above, the opposite ends EP1 and EP2 of the light emitting element LD may be coupled to the first electrode REL1 and the second electrode REL2, respectively, through the first contact electrode CNE1 and the second contact electrode CNE2, so that a predetermined voltage may be applied to the opposite ends EP1 and EP2, respectively, and each of the light emitting elements LD may emit light by recombination of electron-hole pairs in the active layer 12 of the light emitting element LD. Here, the active layer 12 may emit light having a wavelength range from 400 nm to 900 nm. However, the wavelength range of the light emitted from the active layer 12 is not limited thereto and may be changed in various ways.

[0172] A fourth insulating layer INS4 for covering the second contact electrode CNE2 may be provided on the second contact electrode CNE2. The fourth insulating layer INS4 may prevent the second contact electrode CNE2 from being exposed to the outside, thereby preventing the second contact electrode CNE2 from being corroded. The fourth insulating layer INS4 may be formed of an inorganic insulating layer or an organic insulating layer. Here, in the case where the fourth insulating layer INS4 is formed of an organic insulating layer, a step difference caused by the partition wall PW, the first and second electrodes REL1 and REL2, the first contact electrode CNE1 and the second contact electrode CNE2, etc. may be mitigated.

[0173] As described above, in an embodiment of the present disclosure, the reflective pattern RP may be formed on the bank BNK so that light emitted from each of the sub-pixels SP1, SP2, and SP3 and traveling toward the bank BNK may be reflected by the reflective pattern RP in a direction along which an image is displayed. Therefore, in a display device according to an embodiment of the present disclosure, the light output efficiency of the light emitting element LD may be enhanced, thereby enhancing the light efficiency of the display device.

[0174] Although the bank BNK is shown as being disposed on the same layer as the partition wall PW in the drawings, the bank BNK may be disposed on a layer different from the partition wall PW. In addition, although the reflection pattern RP is shown as being disposed on a layer different from the first electrode REL1 and the second electrode REL2, the reflection pattern RP may be disposed on the same layer as the first electrode REL1 and the second electrode REL2.

[0175] In other words, the positions where the bank BNK and the reflective pattern RP are formed may be changed in various ways without limitation. Hereinafter, a display device according to an embodiment of the present disclosure including the bank BNK and the reflective pattern RP formed at different positions will be described with reference to the accompanying drawings.

[0176] Figures 6a to 6c A display device according to an embodiment of the present disclosure is schematically shown and corresponds to Figure 4a Cross-sectional view along line II'.

[0177] like Figure 6a As shown in FIG, the bank BNK and the partition wall PW may be formed on the same layer. The reflective pattern RP and the first and second electrodes REL1 and REL2 may also be disposed on the same layer.

[0178] In detail, the bank BNK and the partition wall PW may be formed on the passivation layer PSV of the pixel circuit layer PCL. In this case, the bank BNK and the partition wall PW may include the same material disposed on the same layer. The reflection pattern RP, and the 1-1 electrode REL1_1 and the second electrode REL2 may be disposed on the bank BNK and the partition wall PW, respectively. Here, the reflection pattern RP, the 1-1 electrode REL1_1 and the second electrode REL2 may also include the same material disposed on the same layer.

[0179] The first insulating layer INS1 may be disposed on the passivation layer PSV to cover the reflective pattern RP and the 1-1st electrode REL1_1 and the second electrode REL2. The 1-1st electrode REL1_1 and the second electrode REL2 may be exposed by removing a portion of the first insulating layer INS1. The exposed 1-1st electrode REL1_1 and the exposed second electrode REL2 may be coupled to the light emitting element LD through the 1-1st contact electrode CNE1_1 and the second contact electrode CNE2, respectively.

[0180] like Figure 6b and Figure 6c As shown in FIG. 4 , the bank BNK and the partition wall PW may be disposed on different layers.

[0181] For example, Figure 6b As shown in , the bank BNK and the partition wall PW may be disposed on different layers with the first insulating layer INS1 interposed therebetween. For example, the partition wall PW may be disposed under the first insulating layer INS1, and the bank BNK may be disposed on the first insulating layer INS1. The reflection pattern RP and the 1-1st electrode REL1_1 and the second electrode REL2 may also be disposed on different layers with the first insulating layer INS1 interposed therebetween. For example, the 1-1st electrode REL1_1 and the second electrode REL2 may be disposed under the first insulating layer INS1, and the reflection pattern RP may be disposed on the first insulating layer INS1.

[0182] like Figure 6c As shown in FIG, although the bank BNK and the partition wall PW may be disposed on different layers, all of the reflection pattern RP and the first and second electrodes REL1 and REL2 may be disposed on the first insulating layer INS1. The reflection pattern RP and the first and second electrodes REL1 and REL2 may include the same material disposed on the same layer.

[0183] As mentioned above, Figures 6a to 6c Some of the various embodiments of the present disclosure are shown, and positions where the bank BNK, the partition wall PW, the 1-1th and second electrodes REL1_1 and REL2 , and the reflection pattern RP are formed are not limited to those of the aforementioned embodiments.

[0184] Hereinafter, a display device including a light conversion pattern layer according to an embodiment of the present disclosure will be described.

[0185] Figure 7 A display device according to an embodiment of the present disclosure is shown, and a light conversion pattern layer is connected to Figure 5 A schematic cross-sectional view of the structure of a display device.

[0186] For ease of explanation, Figure 7 Schematically shows a pixel area of ​​one pixel among a plurality of pixels included in a display device. Figure 7 , schematically shown with reference to Figure 5 The structures of some components are equivalent to those of the display device described in detail, and a detailed description thereof will be omitted.

[0187] Reference Figure 4a , Figure 5 and Figure 7 , the display device DP according to an embodiment of the present disclosure may include: a base layer BSL on which at least one pixel PXL including a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 is disposed; and a capping layer CPL coupled to the base layer BSL. Each of the sub-pixels SP1, SP2, and SP3 may include a light conversion pattern layer LCP disposed between the base layer BSL and the capping layer CPL.

[0188] The capping layer CPL may be arranged to overlap the display area of ​​the base layer BSL and cover the display element layer DPL, thereby preventing oxygen and water from penetrating the display element layer DPL. For example, the capping layer CPL may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the capping layer CPL may be formed of the same material as that of the base layer BSL, or may be formed of a material different from that of the base layer BSL.

[0189] The capping layer CPL may be disposed to be in close contact with the uppermost layer of the display element layer DPL. In the drawings, the capping layer CPL is shown to be in close contact with the light conversion pattern layer LCP.

[0190] The light conversion pattern layer LCP may include a first light conversion pattern layer LCP1 disposed in the first sub-pixel SP1, a second light conversion pattern layer LCP2 disposed in the second sub-pixel SP2, and a third light conversion pattern layer LCP3 disposed in the third sub-pixel SP3. At least some of the first light conversion pattern layer LCP1, the second light conversion pattern layer LCP2, and the third light conversion pattern layer LCP3 may include a color conversion layer CCL and / or a color filter CF.

[0191] In an embodiment of the present disclosure, a case is shown where each sub-pixel SP1, SP2, and SP3 includes a light emitting element LD configured to emit blue light (eg, light in the range of 430 nm to 480 nm), but the wavelength range of light emitted from the light emitting element LD is not limited thereto.

[0192] For example, the first light conversion pattern layer LCP1 may include a first color conversion layer CCL1 and a first color filter CF1, wherein the first color conversion layer CCL1 includes first color conversion particles corresponding to a first color, and the first color filter CF1 is configured to allow light of the first color to selectively pass through the first color filter CF1. The second light conversion pattern layer LCP2 may also include a second color conversion layer CCL2 and a second color filter CF2, wherein the second color conversion layer CCL2 includes second color conversion particles corresponding to a second color, and the second color filter CF2 is configured to allow light of the second color to selectively pass through the second color filter CF2. The third light conversion pattern layer LCP3 may include at least one of a light scattering layer LSL and a third color filter CF3, wherein the light scattering layer LSL includes light scattering particles SCT, and the third color filter CF3 is configured to allow light of a third color to selectively pass through the third color filter CF3.

[0193] In an embodiment of the present disclosure, the light emitting elements LD aligned in the emission area EMA of each of the first sub-pixel SP1 to the third sub-pixel SP3 may emit light of the same color. The color conversion layer CCL may be disposed on at least some of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the first color conversion layer CCL1 and the second color conversion layer CCL2 may be disposed on the first sub-pixel SP1 and the second sub-pixel SP2, respectively. The display device DP according to an embodiment of the present disclosure may display a full-color image.

[0194] The first color conversion layer CCL1 may be disposed between the base layer BSL and the capping layer CPL to correspond to the first sub-pixel SP1, and more precisely, it may be directly formed on the display element layer DPL and filled into the emission area EMA of the first sub-pixel SP1. In other words, the first color conversion layer CCL1 may be formed on the base layer BSL so that light emitted from the light emitting element LD may be directly incident on the first color conversion layer CCL1.

[0195] In the case where the first sub-pixel SP1 is a red sub-pixel, the first color conversion layer CCL1 may include red quantum dots QDr as first color conversion particles that convert blue light emitted from the light emitting element LD into red light.

[0196] The first color filter CF1 may be disposed on the first color conversion layer CCL1 and include a color filter material that allows light of a first color converted by the first color conversion layer CCL1 to selectively pass therethrough. For example, the first color filter CF1 may be a red color filter.

[0197] The second color conversion layer CCL2 may be disposed between the base layer BSL and the capping layer CPL to correspond to the second sub-pixel SP2, and more precisely, it may be directly formed on the display element layer DPL and filled into the emission area EMA of the second sub-pixel SP2. In the case where the second sub-pixel SP2 is a green sub-pixel, the second color conversion layer CCL2 may include green quantum dots QDg as second color conversion particles that convert blue light emitted from the light emitting element LD into green light.

[0198] The second color filter CF2 may be disposed on the second color conversion layer CCL2 and include a color filter material that allows the light of the second color converted by the second color conversion layer CCL2 to selectively pass therethrough. For example, the second color filter CF2 may be a green color filter.

[0199] The light scattering layer LSL can be arranged between the base layer BSL and the capping layer CPL to correspond to the third sub-pixel SP3, and more precisely, it can be directly formed on the display element layer DPL and filled into the emission area EMA of the third sub-pixel SP3. In addition, a third color filter CF3 can be further arranged on the light scattering layer LSL.

[0200] The third color filter CF3 may include a color filter material that allows blue light emitted from the light emitting element LD disposed in the third sub-pixel SP3 to selectively pass therethrough. For example, the third color filter CF3 may be a blue color filter.

[0201] In the display device DP having the above structure, light emitted from each sub-pixel SP1, SP2, and SP3 can pass through the light conversion pattern layer LCP and pass through the capping layer CPL to be emitted to the outside, whereby the display device DP can form an image. Here, the capping layer CPL can be directly disposed on the light conversion pattern layer LCP, so that the light conversion pattern layer LCP can be filled into the space between the bank BNK and the capping layer CPL in each sub-pixel SP1, SP2, and SP3. Therefore, the length of the light path along which the light emitted from the light emitting element LD is emitted to the outside through the capping layer CPL can be minimized, thereby maximizing the light efficiency.

[0202] In addition, in the display device DP according to the present disclosure, by directly forming the pixel circuit layer PCL, the display element layer DPL, and the light conversion pattern layer LCP on the base layer BSL, the light conversion pattern layer LCP can be disposed in a space defined by the bank BNK instead of being formed on a separate substrate. Therefore, the process of manufacturing the display device DP can be simplified.

[0203] In the case where the light conversion pattern layer LCP is formed on a separate substrate, it is necessary to perform a process of aligning the base layer BSL with the substrate on which the light conversion pattern layer LCP is formed. However, in the display device DP according to the present disclosure, the capping layer CPL is directly formed on the light conversion pattern layer LCP, thereby reducing process risks.

[0204] Hereinafter, a method of manufacturing a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0205] Figures 8a to 8k is shown in order to manufacture Figure 5 A cross-sectional view of a method of displaying a device.

[0206] Reference Figure 4a , Figure 5 and Figure 8a The pixel circuit layer PCL is formed on the base layer BSL in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The pixel circuit layer PCL may include first and second transistors T1 and T2, a driving voltage line DVL, and a passivation layer PSV.

[0207] The first contact hole CH1 and the second contact hole CH2 may be formed in the passivation layer PSV. Although not shown, the first contact hole CH1 may expose the drain electrode DE of the first transistor T1, and the second contact hole CH2 may expose the driving voltage line DVL.

[0208] Here, the first and second contact holes CH1 and CH2 may be formed at any step before forming the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2. For example, the first and second contact holes CH1 and CH2 may be formed after forming the partition wall PW and the bank BNK.

[0209] Reference Figure 4a , Figure 5 and Figure 8b , a partition wall PW and a bank BNK are formed on the pixel circuit layer PCL. The partition wall PW and the bank BNK may be formed by applying an insulating material layer (not shown) to the passivation layer PSV and patterning the insulating material layer. The partition wall PW may be formed on the passivation layer PSV in the emission area EMA of each of the first to third sub-pixels SP1 to SP3. The bank BNK may be formed in the non-emission area PPA between adjacent sub-pixels SP1 to SP3.

[0210] The partition wall PW and the bank BNK may be formed of the same material through a process using a single mask. In this case, the partition wall PW and the bank BNK may be formed to have different thicknesses by using a halftone mask or the like.

[0211] Furthermore, the partition wall PW and the bank BNK may be continuously formed using different masks.

[0212] Reference Figure 4a , Figure 5 and Figure 8c , first and second electrodes REL1 and REL2 and first and second connection lines CNL1 and CNL2 are formed on the passivation layer PSV in each of the sub-pixels SP1, SP2, and SP3 including the partition wall PW and the bank BNK. The first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 may be formed by patterning a conductive material having high reflectivity.

[0213] Each of the first and second electrodes REL1 and REL2 may be disposed and / or formed on a corresponding partition wall PW in an emission area EMA of each sub-pixel SP1, SP2, and SP3. Each of the first and second connection lines CNL1 and CNL2 may be disposed and / or formed in a non-emission area PPA of each sub-pixel SP1, SP2, and SP3.

[0214] Although not shown, the first connection line CNL1 may be electrically coupled to the first transistor T1 of the pixel circuit layer PCL through the first contact hole CH1 of the passivation layer PSV. The first connection line CNL1 may be integrally provided with the first electrode REL1 and electrically and / or physically coupled to the first electrode REL1. Therefore, a signal (or voltage) applied to the first transistor T1 may be transmitted to the first electrode REL1 through the first connection line CNL1.

[0215] Although not shown, the second connection line CNL2 may be electrically coupled to the driving voltage line DVL of the pixel circuit layer PCL through the second contact hole CH2 of the passivation layer PSV. The second connection line CNL2 may be integrally provided with the second electrode REL2 and electrically and / or physically coupled to the second electrode REL2. Therefore, the voltage of the second driving power source VSS of the driving voltage line DVL may be transmitted to the second electrode REL2 through the second connection line CNL2.

[0216] Reference Figure 4a , Figure 5 and Figure 8d , a first insulating layer INS1 is formed on the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2. The first insulating layer INS1 may be formed between the first and second electrodes REL1 and REL2 in the emission area EMA of each of the sub-pixels SP1, SP2, and SP3. The first insulating layer INS1 may be formed to extend to a region in which the first insulating layer INS1 overlaps the bank BNK.

[0217] Reference Figure 4a , Figure 5 and Figure 8e , a reflective pattern RP is formed on the bank BNK. Here, a first insulating layer INS1 is disposed between the reflective pattern RP and the bank BNK. The reflective pattern RP may be formed by patterning a conductive material having a predetermined reflectivity. Metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof may be used as the conductive material.

[0218] The reflective pattern RP may serve to reflect light traveling toward the bank BNK, among lights emitted from the sub-pixels SP1 , SP2 , and SP3 , toward an upper portion of the base layer BSL.

[0219] Reference Figure 4a , Figure 5 and Figure 8f, an electric field is formed between the first electrode REL1 and the second electrode REL2 by applying corresponding alignment voltages to the first electrode REL1 and the second electrode REL2 of each sub-pixel SP1, SP2, and SP3 through the first connection line CNL1 and the second connection line CNL2, respectively. In the case where a DC power or an AC power having a predetermined voltage and a period is repeatedly applied to each of the first electrode REL1 and the second electrode REL2 several times through the first connection line CNL1 and the second connection line CNL2, an electric field can be formed between the first electrode REL1 and the second electrode REL2 by the potential difference between the first electrode REL1 and the second electrode REL2.

[0220] After an electric field is formed between the first electrode REL1 and the second electrode REL2 formed in the emission area EMA of each sub-pixel SP1, SP2 and SP3, the light-emitting element LD is provided by an inkjet printing scheme or the like. For example, by providing a nozzle above the passivation layer PSV and dripping a solvent including the light-emitting element LD onto the passivation layer PSV through the nozzle, the light-emitting element LD can be provided to the passivation layer PSV in the emission area EMA of the sub-pixel. The solvent may be any one of acetone, water, ethanol and toluene, but the present disclosure is not limited thereto. For example, the solvent may include a material that can evaporate at room temperature or by heating. In addition, the solvent may have the form of ink or paste. The method for providing the light-emitting element LD is not limited to the aforementioned method. The method for providing the light-emitting element LD may be changed. Subsequently, the solvent may be removed.

[0221] In the case where the light emitting element LD is input onto the passivation layer PSV, the self-alignment of the light emitting element LD can be induced by the electric field formed between the first electrode REL1 and the second electrode REL2, so that the light emitting element LD can be aligned between the first electrode REL1 and the second electrode REL2. In other words, the light emitting element LD can be centrally aligned in the target area (for example, centrally aligned in the emission area EMA of each sub-pixel SP1, SP2 and SP3).

[0222] Reference Figure 4a , Figure 5 and Figure 8g After the light emitting elements LD are aligned, a second insulating layer INS2 covering a portion of the upper surface of each light emitting element LD is formed by applying an insulating material layer (not shown) onto the passivation layer PSV and patterning the insulating material layer using a mask (not shown). Therefore, opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

[0223] Here, the second insulating layer INS2 may be formed to completely surround the reflective pattern RP. The reason for this is to prevent the reflective pattern RP from being connected to the first and second contact electrodes CNE1 and CNE2 to be described below.

[0224] Reference Figure 4a , Figure 5 and Figure 8h , portions of the first electrode REL1 and the second electrode REL2 may be exposed by removing a portion of the first insulating layer INS1.

[0225] Afterwards, refer to Figure 4a , Figure 5 and Figure 8i , forming a first contact electrode CNE1 to be electrically coupled to the exposed first electrode REL1. The first contact electrode CNE1 can electrically couple the first electrode REL1 to one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. Therefore, a signal (e.g., a voltage of the first driving power source VDD) applied to the first electrode REL1 of the first transistor T1 can be transmitted to each of the light emitting elements LD through the first contact electrode CNE1.

[0226] The first contact electrode CNE1 may be formed of a transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the first electrode REL1 in a forward direction of the display device (eg, a direction in which an image is displayed) to travel in the forward direction without loss.

[0227] Here, the first contact electrode CNE1 may include a 1-1th contact electrode CNE1_1 disposed on the 1-1th electrode REL1_1, and a 1-2th contact electrode CNE1_2 disposed on the 1-2th electrode REL1_2.

[0228] Reference Figure 4a , Figure 5 and Figure 8j , a third insulating layer INS3 may be formed to cover the first contact electrode CNE1. The third insulating layer INS3 may prevent the first contact electrode CNE1 from being exposed to the outside, thereby preventing the first contact electrode CNE1 from being corroded.

[0229] Reference Figure 4a , Figure 5 and Figure 8k , forming a second contact electrode CNE2 to be electrically coupled to the exposed second electrode REL2. The second contact electrode CNE2 can electrically couple the second electrode REL2 to the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD, the other end not being coupled to the first contact electrode CNE1. Therefore, the voltage of the second driving power source VSS applied to the second electrode REL2 can be transmitted to each of the light emitting elements LD.

[0230] The second contact electrode CNE2 may be formed of a transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the second electrode REL2 in a forward direction of the display device to travel in the forward direction without loss.

[0231] A fourth insulating layer INS4 for covering the second contact electrode CNE2 may be formed on the second contact electrode CNE2. The fourth insulating layer INS4 may prevent the second contact electrode CNE2 from being exposed to the outside, thereby preventing the second contact electrode CNE2 from being corroded. Here, the fourth insulating layer INS4 is formed of an organic insulating layer so that the fourth insulating layer INS4 may alleviate a step difference caused by the partition wall PW, the first and second electrodes REL1 and REL2, the first and second contact electrodes CNE1 and CNE2, and the like.

[0232] By forming the first contact electrode CNE1 and the second contact electrode CNE2 on the same layer, the number of masks required to manufacture a display device may be reduced.

[0233] Hereinafter, a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, in which the first contact electrode CNE1 and the second contact electrode CNE2 are formed on the same layer.

[0234] Figure 9a and Figure 9b is a cross-sectional view showing a display device according to an embodiment of the present disclosure, and corresponds to Figure 4a Cross-sectional view along line II'.

[0235] Reference Figure 1 , Figure 4a , Figure 9a and Figure 9b , a display device according to an embodiment of the present disclosure may include a base layer BSL on which a plurality of pixels PXL are disposed.

[0236] Each of the pixels PXL may include first, second, and third subpixels SP1, SP2, and SP3 disposed on the base layer BSL. Each of the first to third subpixels SP1 to SP3 may include an emission area EMA configured to emit light and a non-emission area PPA disposed around a periphery of the emission area EMA.

[0237] Each of the first to third sub-pixels SP1 to SP3 may include a base layer BSL, a pixel circuit layer PCL, and a display element layer DPL.

[0238] The pixel circuit layer PCL may include a buffer layer BFL disposed on the base layer BSL, a first transistor T1 and a second transistor T2 disposed on the buffer layer BFL, and a driving voltage line DVL. In addition, the pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3 may further include a passivation layer PSV disposed on the first transistor T1 and the second transistor T2 and the driving voltage line DVL.

[0239] A light blocking pattern SDL may be further disposed between the base layer BSL and the buffer layer BFL. The light blocking pattern SDL may be a light blocking layer formed of a conductive material, an insulating material, etc., and blocks light introduced into the rear surface of the base layer BSL so as to block light from being introduced into the pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3.

[0240] The light blocking pattern SDL may include Cr, Cr / CrO x A double layer of a light shielding pattern SDL, a resin including a carbon pigment, a black dye, graphite, etc. In the case where the light shielding pattern SDL is formed of a resin including a carbon pigment, the carbon pigment may be carbon black which is a black pigment having a light shielding function.

[0241] The light blocking pattern SDL may be disposed on the base layer BSL to correspond to a lower portion of the semiconductor layer SCL of each of the first transistor T1 and the second transistor T2. The light blocking pattern SDL may be formed of a metal (which is a conductive material). The light blocking pattern SDL may be electrically coupled to some components of any one of the first transistor T1 and the second transistor T2. Although the light blocking pattern SDL is shown in the drawings as being coupled to the drain electrode DE of the first transistor T1, the present disclosure is not limited thereto.

[0242] The display element layer DPL may include a partition wall PW, a bank BNK, first and second electrodes REL1 and REL2 , first and second connection lines CNL1 and CNL2 , a plurality of light emitting elements LD, first and second contact electrodes CNE1 and CNE2 , and the like.

[0243] As shown in the figure, the partition wall PW and the bank BNK may be formed on the passivation layer PSV and formed on the same layer. The partition wall PW may be formed and / or disposed in the emission area EMA of each sub-pixel SP1, SP2, and SP3. The bank BNK may be formed and / or disposed in the non-emission area PPA of each sub-pixel SP1, SP2, and SP3.

[0244] The reflection pattern RP disposed on the bank BNK may be disposed on the same layer as that of the first and second electrodes REL1 and REL2 , or on a different layer from that of the first and second electrodes REL1 and REL2 .

[0245] For example, Figure 9a As shown in , the reflective pattern RP may include the same material disposed on the same layer as the first and second electrodes REL1 and REL2. The first insulating layer INS1 may be disposed to cover the reflective pattern RP and the first and second electrodes REL1 and REL2. A plurality of light emitting elements LD may be disposed on the first insulating layer INS1.

[0246] The second insulating layer INS2 may be provided to cover portions of the upper surfaces of the light emitting elements LD such that opposite ends EP1 and EP2 of each of the light emitting elements LD are exposed.

[0247] The first contact electrode CNE1 and the second contact electrode CNE2 may be respectively coupled to the first electrode REL1 and the second electrode REL2 exposed from the first insulating layer INS1. For example, the first contact electrode CNE1 may electrically couple the first end EP1 of the light emitting element LD with the first electrode REL1. The second contact electrode CNE2 may electrically couple the second end EP2 of the light emitting element LD with the second electrode REL2.

[0248] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same plane. The first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other by a predetermined distance on the second insulating layer INS2 and thus electrically and / or physically separated from each other. In other words, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer and formed by the same manufacturing process.

[0249] A third insulating layer INS3 for covering the first and second contact electrodes CNE1 and CNE2 may be disposed on the first and second contact electrodes CNE1 and CNE2. The third insulating layer INS3 may prevent the first and second contact electrodes CNE1 and CNE2 from being exposed to the outside, thereby preventing the first and second contact electrodes CNE1 and CNE2 from being corroded.

[0250] Although not shown, a fourth insulating layer INS4 for planarization of the display element layer DPL may be further disposed on the third insulating layer INS3 .

[0251] like Figure 9bAs shown in , the reflection pattern RP and the first electrode REL1 and the second electrode REL2 may be disposed on different layers. For example, the first electrode REL1 and the second electrode REL2 may be disposed under the first insulating layer INS1, and the reflection pattern RP may be disposed on the first insulating layer INS1. Although the reflection pattern RP and the first electrode REL1 and the second electrode REL2 are disposed on different layers, the reflection pattern RP and the first electrode REL1 and the second electrode REL2 may include the same material.

[0252] Although Figure 9a and Figure 9b FIG. 4 shows that the partition wall PW and the bank BNK are formed on the same layer on the passivation layer PSV, but the partition wall PW and the bank BNK may be formed as shown in FIG. Figure 6b and Figure 6c As shown in FIG. 1 , the electrodes INS1 and INS2 are formed on different layers with the first insulating layer INS1 interposed therebetween.

[0253] Although the embodiments of the present disclosure have been disclosed, it will be appreciated by those skilled in the art that the present disclosure may be implemented in other specific forms without departing from the scope and spirit of the disclosure as disclosed in the appended claims. Therefore, it should be understood that the exemplary embodiments are only for illustrative purposes, but do not limit the scope of the present invention.

Claims

1. A display device, comprising: A base layer, including a display area and a non-display area; as well as A plurality of pixels are arranged in the display area and each of which includes a plurality of sub-pixels, Each of the sub-pixels includes a pixel circuit layer and a display element layer disposed on the pixel circuit layer. Wherein, the display element layer comprises: a partition wall disposed in each of the sub-pixels; A bank portion is provided between adjacent sub-pixels in the sub-pixels; A first electrode and a second electrode, disposed on the partition wall and disposed to be spaced apart from each other; at least one light emitting element disposed between the first electrode and the second electrode and configured to emit light; a reflective pattern, disposed on the bank; an insulating layer, disposed on the reflective pattern and exposing the first end of the light emitting element and the second end of the light emitting element; a first contact electrode disposed on the insulating layer and electrically connecting the first electrode and the first end of the light emitting element; and The second contact electrode is disposed on the insulating layer and electrically connects the second electrode and the second end of the light emitting element.

2. The display device according to claim 1, wherein: The reflective pattern has a structure surrounding an upper surface and a side surface of the bank.

3. The display device according to claim 1, wherein: The partition wall is provided between the bank and the light emitting element.

4. The display device according to claim 1, wherein: The bank and the partition wall include the same material disposed on the same layer.

5. The display device according to claim 1, wherein: The partition walls and the bank are disposed on respective different layers.

6. The display device according to claim 1, wherein: The first electrode and the second electrode include a same material disposed on a same layer on which the reflective pattern is disposed.

7. The display device according to claim 1, wherein: The first electrode and the second electrode are disposed on a layer different from a layer on which the reflective pattern is disposed.

8. The display device according to claim 1, wherein: The pixel circuit layer comprises: at least one transistor disposed on the base layer; and A passivation layer is disposed on the transistor.

9. The display device according to claim 8, wherein: The partition wall and the bank are integrally formed on the passivation layer.

10. The display device according to claim 1, wherein: The sub-pixel includes a light conversion pattern layer disposed in a space defined by the bank and including color conversion particles that convert the light into light of a specific color.

11. The display device according to claim 10, wherein: The display device includes a capping layer disposed on the light conversion pattern layer to overlap the display area.

12. The display device according to claim 10, wherein: The light conversion pattern layer further includes a color filter.

13. A method for manufacturing a display device, comprising: providing a base layer on which a plurality of sub-pixels are to be disposed; as well as forming a pixel circuit layer on the base layer, and forming a display element layer on the pixel circuit layer; Wherein, forming the display element layer comprises: forming a partition wall in each of the sub-pixels; forming a bank between adjacent sub-pixels among the sub-pixels; forming a first electrode and a second electrode spaced apart from each other on the partition wall; forming a reflective pattern on the bank; forming at least one light emitting element disposed between the first electrode and the second electrode and configured to emit light; Disposing an insulating layer on the reflective pattern, wherein the insulating layer exposes the first end of the light emitting element and the second end of the light emitting element; forming a first contact electrode, the first contact electrode being disposed on the insulating layer and electrically coupling the first electrode and the first end of the light emitting element; and A second contact electrode is formed, the second contact electrode being disposed on the insulating layer and electrically coupling the second electrode and the second end of the light emitting element.

14. The method according to claim 13, wherein: Forming the reflective pattern includes forming the reflective pattern so that the reflective pattern surrounds an upper surface and a side surface of the bank.

15. The method according to claim 13, wherein: The partition wall and the bank are formed on the same layer by the same process.

16. The method according to claim 13, wherein: The partition walls and the bank are formed on corresponding different layers through corresponding different processes.

17. The method according to claim 13, wherein: The first electrode and the second electrode are formed on the same layer by the same process as forming the reflective pattern.

18. The method according to claim 13, wherein: The first electrode and the second electrode are formed on a different layer from the reflective pattern through a process different from a process of forming the reflective pattern.

19. The method according to claim 13, wherein: Forming the at least one light emitting element includes aligning the at least one light emitting element between the first electrode and the second electrode by applying corresponding alignment voltages to the first electrode and the second electrode, respectively.

20. The method according to claim 13, wherein: The method further includes forming a light conversion pattern layer in a space defined by the bank in the sub-pixel, the light conversion pattern layer including color conversion particles that convert the light into light of a specific color.

Images