Method and apparatus for using multiple linked memory lists

Abstract

An apparatus and method for queuing data to a memory buffer, the method comprising selecting a queue from a plurality of queues; receiving a data token from the selected queue and requesting, by a queue module, an address and a pointer from a buffer manager for an address allocated by the buffer manager for storing the data token. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers to the allocated addresses are generated in the memory list, including a plurality of linked memory lists for additional address allocations. The method further comprises writing pointers for the allocated addresses to the accessed memory list, wherein the pointers link the allocated addresses together, and upon receiving subsequent data tokens from the queue, transplanting additional address allocations to other memory lists and generating additional pointers linking the allocated addresses in the other memory lists together.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201510290966.8, application date May 29, 2015, and invention name “Method and device for using multiple linked memory lists”. Technical Field

[0002] The present disclosure relates generally to the field of network data transmission, and more particularly to a system and method for linking multiple memory lists during dequeuing and enqueuing of data tokens from selected queues in order to increase the throughput of a switching network when transmitting data packets. Background Art

[0003] In a data switching network, data traffic is classified into various flows stored in a large number of queues in a buffer. In a router or other network element, the stored queues usually compete for a common outbound communication link or outbound port (e.g., a physical communication link or a pseudowire). Therefore, the buffered queues need to be scheduled on the outbound side. Therefore, a token scheduling device on the output side in the router needs to perform processing before transmission to select which of the queued packets will be the next packet in the queue for outbound transmission.

[0004] Typically, during the routing process, data tokens from different source ports are classified based on their source and destination ports and the type of business. They are then classified into different queues in the buffer. Data tokens that pass through and / or are processed by the router network are at least temporarily maintained in a buffer memory. Typically, a memory data structure called a linked list queue is maintained in association with the buffer memory. The linked list queue contains a list of pointers to each storage location in the buffer memory that stores data associated with each data token. Conventional queue structures typically store each pointer associated with each data token currently stored in the buffer memory in a continuous sequential list. When a data token enters a queue, the state of each queue is updated and the associated linked list pointer is updated. Based on the availability of the output port, the scheduler selects the correct scheduling algorithm to dequeue the data token from the queue. When a data token is removed from the queue, the state and linked list pointer of each queue will then be updated again.

[0005] Due to the need to classify the tokens based on the source and destination ports and the type of service, additional delay time is generated in the processing of multicast service data packets. First, the data tokens associated with the data packets are then classified into different queues, and then when entering the queue, the state of the queue is updated. Then, based on the port availability, the scheduler selects a scheduling algorithm to dequeue the tokens from the corresponding queues in the buffer memory. This step of waiting for port availability must be repeated for each data token in the data tokens to be sent. In addition, if a copy of the data token is required to be repeated and sent to an additional port, a quality of service (QoS) algorithm check is required. In addition, when priority service needs to be guaranteed for, for example, high priority services (such as control services or voice / video delay sensitive services, transmission), some additional checks must be performed when transmitting the data token.

[0006] The performance of the buffer manager is limited by the pipeline flow of data tokens in the enqueue and dequeue processing operations. When the buffer is full, the buffer manager must wait until the data token is dequeued before it can enqueue additional data tokens. In order to reduce the latency here, parallel buffers are introduced to enable the enqueue of additional data tokens. However, such additional parallel buffers use additional resources and processing power. In addition, each time the buffer memory is to be processed in some operation performed by the router, the queue must be accessed or addressed in order to obtain the pointer associated with the token.

[0007] As the processing speeds associated with routers or other packet switches increase (e.g., 10 Gigabits per second or higher), the input and output bandwidth and access latency associated with the memory used to maintain the queues become critical. That is, the queue memory may become a significant bottleneck in view of the fact that the conventional queue must be accessed each time a token pointer is needed. Summary of the invention

[0008] It would therefore be advantageous to provide a buffer memory management using linked lists of addresses that can increase the current limited number of enqueue and dequeue operations that can be performed in current devices by using virtual queue technology based on linked lists providing multiple enqueue and dequeue token buffer operations.

[0009] Embodiments of the present disclosure provide a technique for forming a linked list of virtual queues using multiple list-type sub-queues, the implementation of which enables multiple data token transmissions to be scheduled in parallel, thereby significantly increasing the throughput of a switching mechanism in a router.

[0010] Therefore, an embodiment of the present disclosure adopts a method of queuing data to a memory buffer, the method comprising selecting a queue from a plurality of queues and receiving a data token from the selected queue. The queue module requests a pointer and an address for an address allocated by the buffer manager for storing the data token from the buffer manager. Then, a memory list is accessed through the buffer manager, and a pointer and an address pointing to the allocated address are generated in the memory list. The accessed memory list includes a plurality of linked memory lists for additional address allocations. In addition, a pointer for the allocated address is written to the accessed memory list. The pointer links the allocated addresses together. The method also comprises: transplanting additional address allocations to other memory lists when subsequent data tokens are received from the queue, and generating additional pointers linking the allocated addresses in the other memory lists together.

[0011] According to another embodiment of the present disclosure, a device for queuing data to a memory buffer is used, the device comprising: a selector module for selecting a queue from a plurality of queues and receiving a data token from the selected queue; a manager responsive to the module for requesting a pointer and an address for storing the data token allocated by the manager; an allocation module responsive to the manager for accessing a memory list and generating a pointer and an address pointing to the allocated address in the memory list. The accessed memory list includes a plurality of linked memory lists for additional address allocations. The allocation module writes a pointer for the allocated address to the accessed memory list, wherein the pointer links the allocated addresses together, and the allocation module transplants the additional address allocation to other memory lists when receiving subsequent data tokens from the queue, and generates additional pointers linking the allocated addresses in the other memory lists together.

[0012] According to another embodiment of the present disclosure, the queue module includes an enqueue module for enqueuing data tokens into the assigned addresses of the linked memory lists and a dequeue module for dequeuing data tokens from the assigned addresses of the linked memory lists. The enqueue module is configured to generate a request to the buffer manager for enqueuing a plurality of data tokens at once, wherein the plurality of data tokens have addresses linked across the plurality of memory lists through pointers. The dequeue module is configured to generate a request to the buffer manager for dequeuing a plurality of data tokens at once, wherein the plurality of data tokens have addresses linked across the plurality of memory lists through pointers.

[0013] The present disclosure necessarily includes simplifications, generalizations and omissions of details. Therefore, it should be understood by those skilled in the art that the present disclosure is illustrative only and is not intended to be limiting in any way. Other aspects, inventive features and advantages of the present disclosure, which are limited only by the claims, will become clear in the non-limiting detailed description given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Embodiments of the present disclosure will be better understood by reading the following detailed description in conjunction with the accompanying drawings, in which like reference numerals refer to like elements, and in which:

[0015] Figure 1 is a block diagram depicting a configuration of a buffer manager in an exemplary router according to an embodiment of the present disclosure;

[0016] Figure 2 is a block diagram of a buffer manager depicting configuration of queue tail pointers and queue head pointers in an exemplary router according to an embodiment of the present disclosure;

[0017] Figure 3 illustrates an exemplary virtual queue linked list configuration according to an embodiment of the present disclosure;

[0018] Figure 4 illustrates an exemplary queue link list configuration according to an embodiment of the present disclosure;

[0019] Figure 5A , Figure 5B A block diagram illustrating an exemplary head pointer and tail pointer configuration with a linked list structure according to an embodiment of the present disclosure;

[0020] Fig. 6A , Figure 6B illustrates a block diagram of linking data tokens together in a plurality of memory list structures according to an embodiment of the present disclosure;

[0021] Figure 7 is a flowchart illustrating the operation of a buffer manager having a linked list structure according to an embodiment of the present disclosure;

[0022] Figure 8 is a block diagram of a buffer manager depicting configuration of queue tail pointers and queue head pointers in an exemplary router according to an embodiment of the present disclosure; and

[0023] Fig. 9 is a block diagram depicting the configuration of a buffer manager module in an exemplary router according to the present disclosure. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Although the present invention is described in conjunction with the preferred embodiments, it should be understood that it is not intended to limit the present invention to these embodiments. On the contrary, the present invention is intended to cover alternatives, modifications and equivalents, which may be included in the spirit and scope of the present invention as defined by the appended claims. In addition, in the following detailed description of the embodiments of the present invention, a large number of specific details are proposed in order to provide a thorough understanding of the present invention. However, it should be recognized by those of ordinary skill in the art that the present invention can be practiced without these specific details. In other cases, known methods, processes, components and circuits are not described in detail to avoid unnecessary confusion of various aspects of the embodiments of the present invention. The drawings showing the embodiments of the present invention are semi-illustrated and not drawn to scale, in particular, some of the scales are for clear presentation and are shown in the drawings by enlargement. Similarly, although the views in the drawings generally show similar orientations for the purpose of ease of understanding, this depiction in the drawings is arbitrary to a great extent. Generally, the present invention may operate in any orientation.

[0025] It should be borne in mind, however, that all of these terms and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applicable to these physical quantities. Unless otherwise expressly noted or apparent from the following discussion, it should be understood that throughout the present invention, discussions using terms such as "processing" or "accessing" or "executing" or "storing" or "rendering" refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories and other computer-readable media into data represented as physical quantities within a computer system's memory or registers or other such information storage, transmission, or client device. When a component appears in several embodiments, the use of the same figure number indicates that the component is the same as the component illustrated in the original embodiment.

[0026] Enqueue and dequeue buffer memory management

[0027] Figure 1A data token processing system 100 is shown in which the present disclosure may be implemented. The system 100 includes a processor 110 having a replication, QoS and enqueue processor 120, a buffer manager 130, a scheduling dequeue 140, and a buffer memory 150. The processor 110 is configured to provide an interface between a network from which data tokens and other data tokens are received and a network to an output port 160 controlled by the scheduling dequeue 140. The processor 110 having the replication, QoS and enqueue processor 120, the buffer manager 130, the scheduling dequeue 140, and the buffer memory 150 may be implemented as one or more integrated circuits installed, for example, on a line or port of a router or switch. The data token may be considered, but not limited to, a representative portion of a data packet to be transmitted. For example, a data packet may have both a header and a payload portion. The data token will typically contain a header of the data packet or a collection of metadata or various aspects associated with the header or various aspects associated with the entire data packet. In addition, if the header is between 64 bits and 128 bits, the data token required may be 45-50 bits depending on network needs. The data token may be associated with the data packet pointed to by the pointer, and the data packet may be stored in the external memory block pointed to by the associated pointer coupled to the data packet.

[0028] It should be understood that Figure 1 The particular arrangement of system elements shown is merely an illustrative example.More particularly, as previously noted, the present disclosure may be implemented in accordance with any type of packet or token processor and is not limited to any particular packet processing application.

[0029] Figure 2 2 shows a queue tail pointer 240, a queue head pointer 250, and a null pointer 260 in a queue memory in a buffer memory manager 200 and a buffer management operation 210 according to an embodiment of the present disclosure. It should be understood that the linked list pointers 240 to 260 may be in the processors 120 and 140 ( Figure 1 ) resides under the control of and is maintained in the buffer manager 130 ( Figure 1 ). Each queue has both a queue head pointer 250 and a queue tail pointer 240. The queue tail pointer 240 specifies the location of write operations and the queue head pointer 250 specifies the location of read operations. When performing a read operation, the queue head pointer 250 will shift along the queue of each new read operation. Similarly, the queue tail pointer 240 will shift along the queue of each new write operation. Therefore, the last queue tail pointer 240 identifies the last write operation in the cycle, and the last queue head pointer 250 identifies the last read operation in the cycle.

[0030] like Figure 2As shown, when accessing a specific queue according to a queue tail pointer request 220, a new queue head pointer 250 and a new queue tail pointer 240 are read. A token for a queue is received. After receiving the token, information about the next head pointer can be accessed to read and process.

[0031] Figure 3 The parallel linked list configuration of the selected Q0 is shown, which is filled in the order in which the tokens are received. The pointer of the initial request can be the queue head pointer or the queue tail pointer. Each Q0 will be divided into 4 linked lists Q 00 To Q 03 Therefore, Q 00 can be divided into 4 memory locations Q 00 To Q 03 , which is Figure 3 The list Q' shown in 000 To Q' 002 .Q 00 To Q 03 The single linked list in is further divided into 4 sub-linked lists Q 00 To Q 03 This allows, for example, four memory location reads Q to be included in one read cycle from Q0 to now. 00 To Q 03 Or each Q 00 Read N / 4 read cycles. In other words, each additional Q 00 To Q 03 Chaining together enables the ability to receive in a single clock cycle Q0 an additional set of data tokens which initially have been read in without chaining to an additional linked list in a time of up to 4 cycles.

[0032] Figure 4 The diagram shows the 00 The first clock control cycle may include a read cycle of each Q0 of N / 4. 00 , Q 01 , Q 12 and Q 00 The next clock cycle shifts N / 4 to Q 01 , Q 12 , Q 00 and Q 01 The subsequent cycles start at Q 12 Each shift starts at N / 4. Therefore, each subsequent read and write cycle is performed N / 4 times the shift. Therefore, within a specific Q0 clocking time, there are approximately up to 4 clocked register shifts of N / 4 to shorten the cycle distance of each register shift.

[0033] exist Figure 5A, after selecting a queue, a read request is performed and a data token 505 needs to be dequeued. The scheduler pops the data token in the selected queue in response to the read request. The requested data token is placed by the buffer manager in the first available memory location of the set of memory banks, in this example, memory bank 0 is the allocated address represented as the requested data token. A head pointer 520 is selected by the linked list type manager application of the buffer memory to point to the requested token 505. This memory location is marked as Q by the buffer manager. 000 The buffer manager's internal clock application allocates a 4-tuple of memory locations for the data token being requested. After receiving the first token of data 505, the start of the first clocking cycle Q0 can be ascertained. This start point is where the initial head pointer 510 is pointed to and is identified again after the initial token request 505 is read and processed.

[0034] The set Q of each memory location 00N Up to 4 memory locations are allocated for data tokens received from the selected queue. The next memory location is linked to Q via tail pointer 515. 000 The buffer manager sends the next read request and receives a second data token from the queue. The second data token is dynamically allocated to the queue denoted as Q 001 The next pointer 515 received from the buffer manager becomes the memory location Q 001 This daisy chain coupling of the head pointer and the tail pointer implements a two-step process of dequeuing data tokens from across the memory banks. For example, the two data tokens at the start 515 and 550 are the initial request data tokens Q requested from the queue. 000 515 and Q 001 550. Token Q 000 515 and Q 001 550 Both dequeue and process the data from Q0 in a two-step process involving the initial read of the Q0 head pointer 510. 000 The data token of the location. 000 Afterwards, the next tail pointer 515 may then be read and identified by the buffer manager. That is, when Q0 is requested, Q0 is read. 000 , and receive Q 000 and then receive with Q 000 Associated data and marked to the next Q 001 It also identifies the path from Q 001 Next tail pointer 550 to Q 002and the path of the next pointer 565 that follows. In addition, when the request Q0 is transpired, the location for transmitting the set of objects associated with Q0 is known. In addition, FIG. 5 shows other paths of the daisy chain for the links of additional sets of data tokens 525 and 570. Memory allocation Q 030 Linked to Q 031 and then the address Q pointing to group 2 032 The tail pointer 535. Address Q 020 The memory list allocated is connected to Q via its tail pointer 021 540. Additional Allocation Q 01N 545 Additional allocations are presented in the memory list in subsequent cycles.

[0035] As the buffer manager continues to send read requests, tuples or sets of 4 linked memory locations are created. Upon completion of the first set of 4 linked locations, the buffer manager begins the next set of 4 linked locations and continues this process of creating tuples or sets of 4 memory locations until all data tokens are popped from the selected queue. If there is an odd number of data tokens or insufficient data tokens to fill a set of 4 linked locations that may have occurred in the previous set, there will be empty locations in the list.

[0036] Next, the third memory location is similarly coupled to the second memory location Q via tail pointer 550. 001 The tail pointer 550 is now the third memory location Q 002 The third memory location in group 2 is accessed by Q 002 , and each of the memory locations is dynamically represented and allocated in a round-robin fashion that migrates across multiple memory banks. This round-robin specifies the frequency with which data can be forwarded to the bandwidth output outside the identified queue at a given time or data can be dequeued from a given queue according to the network switching algorithm. For example, in Figure 5A In, from Q 000 515 to Q 001 550 to Q 002 The loop configuration of 565 is shown as a collection of linked memory bank lists 1 and 2. Each memory bank list 510, 530, and 555 includes a list of tokens Q linked together in a path. 000 To Q 03N , so that each token can be associated with a set of Q0.

[0037] Figure 5B The queue tail pointer 585 and the associated sub-block Q of the queue tail pointer 590 are shown in a block diagram. 00 To Q 03Also shown are the queue head pointer 586 and the associated sub-block Q of the queue head pointer 595. 00 To Q 03 Each of the stacked sub-blocks of the queue tail pointer 590 and the stacked sub-blocks of the queue head pointer 595 are linked together in the parallel linked lists shown in groups 1 and 2 of FIG. 5 .

[0038] Fig. 6A and Figure 6B FIG. 1 shows a block diagram of an example of a queue 100 parallel linked list for a single queue consisting of 4 parallel linked lists. It should be noted that if Fig. 6A If one or more parallel linked lists are added or removed from the exemplary embodiment of the dynamic linked list, the possible concepts of the exemplary embodiments of the present disclosure will not change.

[0039] Fig. 6A An example of a queue 100 parallel linked list for a separate queue consisting of four parallel linked lists is illustrated in block diagram 600: Q100-0, a first parallel linked list 605; Q100-1, a second parallel linked list 610; Q100-2, a third parallel linked list 615; and Q100-3, a fourth parallel linked list 620. External virtual couplings 625, 630 between sublists of blocks illustrate first and second coupled sets in a loop configuration of linked lists Q100-01 to Q100-11 to Q100-21 to Q100-31 and back to Q100-01, and Q100-02 to Q100-12 to Q100-22 to Q100-32 and back to Q100-02. The couplings include tail pointers and head pointers linked together to a set of 4 data tokens, where the previous couplings 625, 630 together serve as the tail pointer of the previous data token in the set and the head pointer of the next data token. The internal couplings Q100-01 to Q100-02 to Q100-03 represent respective parallel lists of respective data token sets in consecutive order. Thus, the previous tail pointer of data token set 1 is connected to the next data token set 2, and the previous tail pointer of set 1 serves as the first head pointer of data token set 2. In Fig. 6A In the example, because there are two complete sets of data tokens in the linked lists Q100-01 to Q100-11 to Q100-21 to Q100-31 and back to Q100-01, and Q100-02 to Q100-12 to Q100-22 to Q100-32 and back to Q100-02, there are two head pointers generated by tail pointers 525 and 630 pointing to data token sets 2 and 3.

[0040] In addition, Fig. 6AThe entire linked list loop type cycle or loop process of queuing and popping memory list allocations and queuing multiple sets of memory allocations of 4 sets of data tokens is shown in FIG. The coupling of the first set of data tokens between sublists 605, 610, 615 and 620 is shown in FIG. Fig. 6A The buffer manager relies on an external counter application to track each of the 4 sets of data tokens and creates a virtual table in the buffer memory to store all count values ​​with associated head and tail pointers. In addition, the data tokens can have additional pointers associated with additional data sets for each of the 4 sets in the sub-list, allowing data storage at an external location. Upon completion of the initial 4 sets, the buffer manager increments its internal count and represents the next set as "2-2-2-2". This process is repeated until all data tokens are enqueued or dequeued from the selected queue. The buffer manager uses an internal counter application to follow a FIFO type ordering of blocks of the 4 sets, and each set is also ordered as shown. Fig. 6A The example shows a 1-2-3 set of numerical sequential couplings.

[0041] Figure 6B An example of a queue list generated for a specific purpose (not shown) in business class 4 and port 4 of queue 100 is illustrated in the block diagram. Parallel memory sublists 635, 640, 645 and 650 are shown. For example, the queue tail pointer memory for Q100 is Q100-0, which is in the memory sublist 635 given the current pointer 1000. In addition, the null pointer read from the memory is 1000 and is written to the queue tail memory for queue 100-0. Therefore, the queue tail memory for Q100-0 has a current pointer 1000 and a next pointer 1100. A list of each of the "tail requests" with a current pointer and a next pointer is also shown in Table 1.2 below. Each of these queue tail requests, current pointers and next pointers constitutes an internal parallel linked list. Memory allocation is random in Q100-0 and is dynamically selected according to availability. Therefore, the order in the memory list changes according to the availability of the memory location. The generated dynamic list is shown in Tables 1, 2 below, where during the enqueue process, the buffer manager assigns a current pointer 1000 to the first set of 4 data tokens and then a next pointer 1100 for the next set of 4 data tokens. Figure 6B1 and counter 0. The next pointer for the first set of data tokens is shown by the coupling of the tail pointer from 1000-0 to 2000-1. The counter is updated to 1 and the current pointer in sublist Q100-1 is 2000. In sublist Q100-2, the current pointer is 3000 with counter 2, and in sublist Q100-3, the current pointer is 4000 with counter 3. Each of the sublists 635-650 is assigned a current pointer as the buffer manager migrates to each list and updates its internal counter, thereby creating a set of head pointers and tail pointers for each set of 4 data tokens. After migrating through each of the sublists, the buffer manager returns a null pointer 655, 660 as the next current pointer for the next set of data tokens. Using this round-robin approach, all sublists are used to store data tokens in 4 sets, and the previous tail pointer of each set is one step ahead of the subsequent head pointer of the next set. Thus, the counter values ​​of the initial Q100-0 linked list 635 are represented in four sets of 0, 4, 8, etc., corresponding to the sets of pointers assigned to each set of data tokens.

[0042] Table 1.1

[0043] Enqueue and buffer manager interaction

[0044] Qtail Teq-100-0->Current pointer -1000, next pointer -1100

[0045] Qtail Teq-100-1->Current pointer - 2000, next pointer - 2100

[0046] Qtail Teq-100-2->Current pointer - 3000, next pointer - 3100

[0047] Qtail Teq-100-3->Current pointer - 4000, next pointer - 4100

[0048] Qtail Teq-100-4->Current pointer - 1100, next pointer - 1200

[0049] Qtail Teq-100-5->Current pointer - 2100, next pointer - 2200

[0050] Qtail Teq-100-6->Current pointer - 3100, next pointer - 3200

[0051] Qtail Teq-100-7->Current pointer - 4100, next pointer - 4200

[0052] Qtail Teq-100-8->Current pointer - 1200, next pointer - 1300

[0053] Figure 7 The diagram is provided by Figure 2 A flowchart of exemplary steps performed by the buffer manager operation of Figure 7 1 is a flow chart of the steps of FIG. 1 for the continuous packet traffic of queue 100. In step 705, a queue is selected based on the destination port and the class of traffic associated with the data. In step 710, ( Figure 1 The) queue module 120 to ( Figure 1 The buffer manager 130 requests a pointer to the Figure 1 The buffer memory 150 stores data. Fig. 6A and 6B The queue 100 identified in the queue 100, the enqueue module can request the pointer position for the queue 100. In step 715, the buffer manager checks the queue tail pointer memory to find the identified queue and sets the current pointer to its position. In addition, the buffer manager pops an additional null pointer from the null pointer memory and writes it to the queue tail pointer memory and also identifies this null pointer as the next pointer to the enqueue module.

[0054] In step 720, the enqueue module uses the current pointer to write the token and the next position into the buffer memory. The enqueue module uses position 1000 to write the token and 1100 as the next storage location as shown in Table 1.1. In addition, for the next queue tail request 100-1, the enqueue module uses the current pointer at storage location 3000 and the next pointer at storage location 3100. Table 1.1 illustrates the subsequent queue tail request and the current pointer and next pointer positions.

[0055] In step 725, after the queue is scheduled to be dequeued, the dequeue module requests the queue head pointer of the queue from the buffer manager. As an example, when queue 100 is scheduled to be dequeued, the dequeue module requests the head pointer 1000 of queue 100 to be sent to the buffer manager. As shown in Figure 1.2, in step 730, the buffer manager assigns the head pointer value 1000 to the requested queue.

[0056] Step 735 illustrates the operation of the dequeue module as the dequeue module reads the packet and the next pointer from the buffer memory and then forwards the next pointer to the buffer manager as a head pointer update. The dequeue module reads from the location 1000 in the buffer where it receives the token and the next pointer 1100. The dequeue module sends 1100 as a head pointer update request for the queue 100. Pointer 1000 is now a null pointer and the dequeue module forwards the null pointer to the buffer manager. (Refer to Figure 1.2 below for the dequeue operation)

[0057] Dequeue and buffer manager interaction

[0058] Table 1.2

[0059] Head Req-100->Head Pointer-1000

[0060] Head update-1100

[0061] Head Req-101->Head Pointer-2000

[0062] Head update-2100

[0063] Head Req-102->Head Pointer-3000

[0064] Head update-3100

[0065] Head Req-103->Head Pointer-4000

[0066] Head update-4100

[0067] Head Req-100->Head Pointer-1100

[0068] Head update-1200

[0069] Head Req-101->Head Pointer-2100

[0070] Head update-2200

[0071] Head Req-102->Head Pointer-3100

[0072] Head update-3200

[0073] Head Req-103->Head Pointer-4100

[0074] Head update-4200

[0075] Head Req-101->Head Pointer-1200

[0076] Head update-1300

[0077] When the dequeue module starts the queue operation of the scheduling of queue 100, this operation is performed by the scheduler in each Q0 separated equally across multiple queues within 4 clock control cycles. The scheduler requests the head pointer information of queues 100, 101, 102 and 103 in turn, so that the dequeue operation is performed according to the priority requested by the scheduler. When the queue is dequeued in the queue 100 scheduled by the scheduler every 4 clocks, the entire Q0 can be regarded as accessing the Q0 of the data linked together by 4 different parallel linked lists. Therefore, for each single parallel linked list, the dequeue operation can occur within the cycle at a maximum speed of up to 16 clocks. For requests with throughput and delay constraints, the parallel linked list dequeue can be increased from 4 to 8 and above.

[0078] Figure 8 For similar Figure 2 , but illustrates the steps of enqueue and dequeue operations. Figure 8 In the example, an input token (1) is received for classification by the enqueue module 820. Next, the output (3) requests a new queue tail pointer from the buffer memory 830. The queue tail memory for the parallel linked list (2) is sent to the memory (4) for a write operation into the buffer memory 850. The data token is written to the buffer memory 850. The scheduler 840 selects Q (Q0) (5) and requests the queue head pointer of the parallel linked list (6). The buffer manager reads the queue head pointer and uses this head pointer as the updated head pointer and then writes the updated head pointer to the parallel linked list.

[0079] exist Fig. 9 , an exemplary process performed by the buffer manager when an input token is received and classified as Q0 according to an embodiment of the present disclosure is illustrated. A request for a tail pointer (3) for a new queue is sent to the queue tail pointer module 920. A queue tail pointer for a parallel linked list is generated with each request, and when a token is received, a write operation to the buffer memory is performed for the token. For scheduler operation, when Q0 is selected, a queue head pointer (6) is requested to be sent to the queue head pointer module 930. The queue head pointer for the parallel linked list is sent from each parallel linked list in the parallel linked list. The requested queue head pointer is read and the token associated with the head pointer is forwarded (8) along with the updated head pointer of the queue and the now empty old pointer.

[0080] Therefore, as shown in the exemplary embodiment of the present disclosure, by linking together four parallel sub-lists, the enqueue and dequeue operations, read and write operations within a given N cycles of the selected Q0 are minimized. In addition, the routing process according to the present disclosure advantageously provides an increased throughput of limited buffer space allocation for enqueue and dequeue operations, thereby reducing the delay time wasted by the buffer manager in this bottleneck operation. By dividing the queue allocation into multiple virtual sub-queues for enqueue and dequeue, data tokens can be acquired and transmitted faster without making significant changes to the physical buffer configuration while reducing the overall delay time generated in such enqueue and dequeue operations.

[0081] It should be understood that the circuits in the router may be implemented as an application specific integrated circuit (ASIC), an application specific standard part (ASSP), a system on a chip (SoC), a field programmable gate array (FPGA), etc. In addition, it should be understood that the router may include various other functions and components known in the art.

[0082] Although certain preferred embodiments and methods have been disclosed herein, those skilled in the art will appreciate from the above disclosure that changes and modifications to such embodiments and methods may be made without departing from the spirit and scope of the present disclosure. It is intended that the present disclosure shall be limited to the scope required by the appended claims and applicable legal rules and principles.

Claims

1. A method of queuing data to a memory buffer performed by a buffer manager, the method comprising: receiving a request for a pointer and an address of an address allocated by the buffer manager for storing a set of data tokens for a queue selected from a plurality of queues, wherein the set of data tokens includes more than two data tokens; accessing a memory list and generating a pointer to the allocated address and an address in the memory list, wherein the memory list comprises two or more memory lists linked in parallel; writing a pointer for the assigned address into the memory list to form a set of more than two linked memory locations, wherein each memory location in the set of more than two linked memory locations is assigned a different one of the more than two parallel linked memory lists, wherein the pointer externally links together each memory location in the set of more than two linked memory locations, and wherein each of the more than two parallel linked memory lists is divided into more than two memory locations; and Additional address allocations are transplanted to another set of two or more linked memory locations upon receipt of another set of data tokens from the queue, and additional pointers are generated linking together memory locations in the another set of two or more linked memory locations.

2. The method according to claim 1, further comprising: A tail pointer and a head pointer are generated that link the two or more assigned addresses of the set of data tokens across the two or more parallel-linked memory lists.

3. The method according to claim 1, wherein The buffer manager is coupled to an enqueue processor operable to enqueue the set of data tokens into the assigned addresses of the two or more parallel-linked memory lists, and The buffer manager is also coupled to a dequeue module operable to dequeue the set of data tokens from the assigned addresses of the two or more parallel-linked memory lists.

4. The method according to claim 3, further comprising: A request is received from the enqueue processor for enqueuing the two or more data tokens, wherein the two or more data tokens have addresses linked by pointers across the two or more parallel-linked memory lists.

5. The method according to claim 3, further comprising: A request is received from the dequeue module for dequeuing the two or more data tokens, wherein the two or more data tokens have addresses linked by pointers across the two or more parallel-linked memory lists.

6. The method according to claim 1, further comprising: The two or more parallel-linked memory lists for the additional address allocations are populated according to address availability.

7. The method of claim 6, wherein the filling is performed in a loop successively across each of the different parallel-linked memory lists until all requested addresses are allocated.

8. A computer system comprising: Memory buffer; and a buffer manager coupled to the memory buffer, the buffer manager being configured to: receiving a request for a pointer and an address of an address allocated by the buffer manager for storing a set of data tokens for a queue selected from a plurality of queues, wherein the set of data tokens includes more than two data tokens; accessing a memory list and generating a pointer to the allocated address and an address in the memory list, wherein the memory list comprises two or more memory lists linked in parallel; writing a pointer for the assigned address into the memory list to form a set of more than two linked memory locations, wherein each memory location in the set of more than two linked memory locations is assigned a different one of the more than two parallel linked memory lists, wherein the pointer externally links together each memory location in the set of more than two linked memory locations, and wherein each of the more than two parallel linked memory lists is divided into more than two memory locations; and Additional address allocations are transplanted to another set of two or more linked memory locations upon receipt of another set of data tokens from the queue, and additional pointers are generated linking together memory locations in the another set of two or more linked memory locations.

9. The computer system of claim 8, wherein the two or more memory lists linked in parallel include a first memory list, a second memory list, a third memory list, and a fourth memory list linked in parallel.

10. The computer system of claim 8, wherein the two or more assigned addresses of the set of data tokens are linked across the two or more parallel-linked memory lists via a tail pointer and a head pointer.

11. The computer system of claim 8, further comprising an enqueue processor configured to: The set of data tokens are enqueued into the assigned addresses of the two or more parallel-linked memory lists, and a request is generated to the buffer manager for enqueuing the two or more data tokens, and wherein the two or more data tokens have addresses that are linked across the two or more parallel-linked memory lists by pointers.

12. The computer system according to claim 8, further comprising a dequeue module, wherein the dequeue module is configured to: The set of data tokens are dequeued from the assigned addresses of the two or more parallel-linked memory lists, and a request is generated to the buffer manager for dequeuing the two or more data tokens, and wherein the two or more data tokens have addresses that are linked across the two or more parallel-linked memory lists by pointers.

13. The computer system of claim 8, wherein the two or more parallel-linked memory lists for the additional address allocations are dynamically populated based on address availability.

14. The computer system of claim 13, wherein the populating of the two or more parallel-linked memory lists is performed in a loop that successively spans each of the different parallel-linked memory lists until all requested addresses are allocated.

15. A data processing system comprising: at least one processor operable to enqueue a set of data tokens to a memory list and to dequeue the set of data tokens from the assigned address of the parallel-linked memory list, wherein the set of data tokens comprises more than two data tokens, and wherein the memory list comprises more than two parallel-linked memory lists; and a buffer manager coupled to the at least one processor, the buffer manager being operable to perform a method of queuing data to a memory buffer, the method comprising: receiving a request for a pointer and an address allocated by the buffer manager for storing the set of data tokens; accessing a memory list and generating a pointer to the allocated address and an address in the memory list; writing a pointer for the assigned address into the memory list to form a set of more than two linked memory locations, wherein each memory location in the set of more than two linked memory locations is assigned a different one of the more than two parallel linked memory lists, wherein the pointer externally links together each memory location in the set of more than two linked memory locations, and wherein each of the more than two parallel linked memory lists is divided into more than two memory locations; and Additional address allocations are transplanted to another set of two or more linked memory locations upon receipt of another set of data tokens, and additional pointers are generated linking together memory locations in the another set of two or more linked memory locations. 16 . The data processing system of claim 15 , wherein the two or more memory lists linked in parallel include a first memory list, a second memory list, a third memory list, and a fourth memory list linked in parallel.

17. The data processing system of claim 15, wherein the two or more assigned addresses of the set of data tokens are linked across the two or more parallel-linked memory lists via a tail pointer and a head pointer.

18. The data processing system according to claim 15, further comprising an enqueue processor, wherein the enqueue processor is configured to: The set of data tokens are enqueued into the assigned addresses of the two or more parallel-linked memory lists, and a request is generated to the buffer manager for enqueuing the two or more data tokens, and wherein the two or more data tokens have addresses that are linked across the two or more parallel-linked memory lists by pointers.

19. The data processing system according to claim 15, further comprising a dequeue module, wherein the dequeue module is configured to: The set of data tokens are dequeued from the assigned addresses of the two or more parallel-linked memory lists, and a request is generated to the buffer manager for dequeuing the two or more data tokens, and wherein the two or more data tokens have addresses that are linked across the two or more parallel-linked memory lists by pointers.

20. The data processing system of claim 15 , wherein the two or more parallel-linked memory lists for the additional address allocations are dynamically populated based on address availability, and wherein the populating of the two or more parallel-linked memory lists is performed in a loop sequentially across each of the different parallel-linked memory lists until all requested addresses are allocated.

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