Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. Semiconductor devices and methods of forming semiconductor devices are described herein. A method includes forming a first fin and a second fin in a substrate. A low concentration source / drain region is epitaxially grown above the first fin and above the second fin. The material of the low concentration region has a germanium volume of less than 50%. A high concentration contact landing region is formed above the low concentration region. The material of the high concentration contact landing region has a germanium volume of at least 50%. The high concentration contact landing region has a thickness of at least 1 nm above the top surface of the low concentration source / drain region.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods of fabrication. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a first fin in a substrate; forming a first source / drain region to a first height above the first fin, the first source / drain region comprising a first germanium concentration; and forming a top layer to a second height above the first source / drain region, the top layer comprising a second germanium concentration, the second germanium concentration being greater than the first germanium concentration, and the second height being greater than 1 nm.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: placing a wafer in a deposition chamber, the wafer comprising a fin; introducing a first precursor into the deposition chamber at a first flow rate; introducing a second precursor into the deposition chamber at a second flow rate, a first flow rate ratio being a ratio of the second flow rate to the first flow rate; using the first flow rate ratio for a first process time to form a source / drain region above the fin, the source / drain region comprising a first germanium concentration level; adjusting the first flow rate to a third flow rate and adjusting the second flow rate to a fourth flow rate, the second flow rate ratio being a ratio of the fourth flow rate to the third flow rate, the second flow rate ratio being greater than the first flow rate ratio; and using the second flow rate ratio for a second process time to form a contact landing area above the source / drain region to a first thickness, the first thickness being at least 1 nm, the contact landing area comprising a second germanium concentration level greater than the first germanium concentration level.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first fin within a substrate; a second fin within the substrate and adjacent to the first fin; a first source / drain region above the first fin, wherein the first source / drain region comprises a low germanium concentration; a second source / drain region above the second fin, wherein the second source / drain region comprises the low germanium concentration; a contact landing area above the first source / drain region and the second source / drain region, the contact landing area comprising a high germanium concentration and having a first height of at least 1 nm above a top surface of the first source / drain region and the second source / drain region; and a source / drain contact, wherein at least a portion of the source / drain contact contacts the contact landing area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A FinFET is shown in a three-dimensional view in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B and Fig. 10C is a cross-sectional view of an intermediate stage in fabricating a FinFET according to some embodiments.

[0010] Fig.11A and Fig. 11B Deposition and etching systems for use in forming FinFETs are shown in accordance with some embodiments.

[0011] Fig. 12A , Fig. 12B and Fig. 12C is a cross-sectional view of other intermediate stages in fabricating a FinFET according to some embodiments.

[0012] Fig.12D is a graph showing germanium concentration gradient as a function of depth through source / drain regions of a FinFET, according to some embodiments.

[0013] Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig.18A and Fig.18B is a cross-sectional view of yet another intermediate stage in fabricating a FinFET according to some embodiments.

[0014] Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 and Fig.24 is a cross-sectional view of other FinFETs according to some other embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] Figure 1An example of a first FinFET 100 in a three-dimensional view according to some embodiments is shown. The first FinFET 100 includes a fin 103 on a substrate 101 (e.g., a semiconductor substrate). Shallow trench isolation (STI) regions 105 are disposed in the substrate 101, and the fin 103 is above and protrudes from adjacent STI regions 105. Although the STI regions 105 are described / illustrated as being separated from the substrate 101, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate, or a semiconductor substrate including an isolation region. In addition, although the fin 103 is shown as a single continuous material such as the substrate 101, the fin 103 and / or the substrate 101 may include a single material or multiple materials. In this context, the fin 103 refers to a portion extending between adjacent STI regions 105.

[0018] The gate dielectric layer 107 is along the sidewalls of the fin 103 and over the top surface of the fin 103, and the gate electrode 109 is located over the gate dielectric layer 107. The source / drain region 111 is disposed on the opposite side of the fin 103 relative to the gate dielectric layer 107 and the gate electrode 109. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of the gate electrode 109 and in a direction perpendicular to, for example, the direction of current flow between the source / drain regions 111 of the first FinFET 100. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 103 and in a direction of current flow between, for example, the source / drain regions 111 of the first FinFET 100. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the first FinFET 100. For clarity, subsequent figures refer to these reference cross sections.

[0019] Furthermore, although some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process, this is illustrative only and not limiting. For example, in other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices (e.g., planar FETs), nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs), and the like.

[0020] Figures 2 to 10C , FIG. 12A to FIG. 12C ,as well as FIG. 13A to FIG. 18B is a cross-sectional view of an intermediate stage in fabricating a FinFET according to some embodiments. Figures 2 to 7 Shows Figure 1 Reference cross section AA is shown, except for multiple fins / FinFETs. Fig. 8A , Fig.9A , Fig. 10A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A and Fig.18A Along Figure 1 The reference cross section AA shown is shown, and Figure 8B , Fig. 9B , Fig. 10B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 16C , Fig. 17B and Fig.18B Along Figure 1 A similar cross section BB is shown, with the difference being multiple fins / FinFETs. Fig. 10C , Fig. 12A , Fig. 12B and Fig. 12C Along Figure 1 The reference cross section CC shown shows that the difference lies in the multiple fins / FinFETs.

[0021] exist Figure 2 In the invention, a substrate 101 is provided. The substrate 101 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, doped with a p-type or n-type dopant) or undoped. The substrate 101 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, for example, a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 101 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0022] The substrate 101 has an n-type region 200N and a p-type region 200P. The n-type region 200N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type FinFET). The p-type region 200P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type FinFET). The n-type region 200N can be physically separated from the p-type region 200P (as shown by the separator 201), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 200N and the p-type region 200P.

[0023] exist Figure 3 In the embodiment of the present invention, fins 103 are formed in substrate 101. Fins 103 are semiconductor strips. In some embodiments, fins 103 can be formed in substrate 101 by etching trenches in substrate 101. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic.

[0024] The fin 103 may be patterned by any suitable method. For example, the fin 103 may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process and a self-alignment process, allowing the creation of a pattern having a smaller pitch than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin. In some embodiments, a mask (or other layer) may remain on the fin 103.

[0025] exist Figure 4 In the embodiment, an insulating material 401 is formed over the substrate 101 and between adjacent fins 103. The insulating material 401 may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it into another material (e.g., oxide)), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 401 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 401 is formed so that excess material of the insulating material 401 covers the fins 103. Although the insulating material 401 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 101 and the fins 103. Thereafter, a filling material such as the above-described filling material may be formed over the liner.

[0026] exist Figure 5In the embodiment, a removal process is applied to the insulating material 401 to remove excess material of the insulating material 401 above the fin 103. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes the fin 103 so that after the planarization process is completed, the top surfaces of the fin 103 and the insulating material 401 are flush. In embodiments where a mask remains on the fin 103, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the mask or the top surfaces of the fin 103 and the insulating material 401 are flush, respectively.

[0027] exist Figure 6 In the embodiment of the present invention, the insulating material 401 is recessed to form the STI region 105. The insulating material 401 is recessed so that the upper portions of the fins 103 in the n-type region 200N and the p-type region 200P protrude from between the adjacent STI regions 105. In addition, the top surface of the STI region 105 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish shape), or a combination thereof. The top surface of the STI region 105 may be formed to be flat, convex, and / or concave by appropriate etching. The STI region 105 may be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material 401 (e.g., etching the material of the insulating material 401 at a faster rate than the material of the fin 103). For example, oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.

[0028] about Figures 2 to 6 The process described is only one example of how the fin 103 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 101, and a trench may be etched through the dielectric layer to expose the substrate 101 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin 103. For example, Figure 5The fin 103 in the substrate 101 may be recessed, and a material different from the fin 103 may be epitaxially grown over the recessed fin 103. In such an embodiment, the fin 103 includes a recessed material, and an epitaxially grown material arranged over the recessed material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 101, and a trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 101, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 103. In some embodiments in which a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and subsequent implantations, but in-situ doping and implantation doping may be used together.

[0029] Furthermore, it may be advantageous to epitaxially grow a different material in the n-type region 200N (eg, NMOS region) than in the p-type region 200P (eg, PMOS region). In various embodiments, the upper portion of the fin 103 may be made of silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to: indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0030] Further in Figure 6 In the embodiment of the present invention, a suitable well (not shown) may be formed in the fin 103 and / or the substrate 101. In some embodiments, a P-well may be formed in the n-type region 200N, and an N-well may be formed in the p-type region 200P. In some embodiments, a P-well or an N-well is formed in both the n-type region 200N and the p-type region 200P.

[0031] In embodiments with different well types, photoresists and / or other masks (not shown) may be used to implement different implantation steps for the n-type region 200N and the p-type region 200P. For example, a photoresist may be formed over the fins 103 and the STI regions 105 in the n-type region 200N. The photoresist is patterned to expose the p-type region 200P of the substrate 101. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 200P, and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 200N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0032] After the implantation of the p-type region 200P, a photoresist is formed over the fin 103 and the STI region 105 in the p-type region 200P. The photoresist is patterned to expose the n-type region 200N of the substrate 101. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-type region 200N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 200P. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region, and its concentration is equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0033] After implantation of n-type region 200N and p-type region 200P, an annealing process may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0034] exist Figure 7In the embodiment of the present invention, a dummy dielectric layer 701 is formed on the fin 103. For example, the dummy dielectric layer 701 may be silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. The dummy dielectric layer 701 may be referred to herein as a dummy gate dielectric layer, a dummy gate dielectric, a dummy dielectric layer, or a dummy dielectric. A dummy gate layer 703 is formed on the dummy dielectric layer 701, and a mask layer 705 is formed on the dummy gate layer 703. The dummy gate layer 703 may be deposited on the dummy dielectric layer 701 and then planarized, for example, by CMP. The mask layer 705 may be deposited on the dummy gate layer 703. The dummy gate layer 703 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 703 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 703 may be made of other materials having high etching selectivity relative to etching of the isolation region (e.g., STI region 105 and / or dummy dielectric layer 701). For example, the mask layer 705 may include one or more layers of silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 703 and a single mask layer 705 are formed across the n-type region 200N and the p-type region 200P. Note that the dummy dielectric layer 701 is shown as covering only the fin 103 for illustration purposes only. In some embodiments, the dummy dielectric layer 701 may be deposited so that the dummy dielectric layer 701 covers the STI region 105, extends above the STI region and between the dummy gate layer 703 and the STI region 105.

[0035] FIG. 8A to FIG. 10C Various additional steps in fabricating example devices are shown. FIG. 8A to FIG. 10C Features in either the n-type region 200N or the p-type region 200P are shown. For example, FIG. 8A to FIG. 10C The structure shown may apply to both the n-type region 200N and the p-type region 200P. The differences, if any, in the structure of the n-type region 200N and the p-type region 200P are described in the text of each figure.

[0036] exist Fig. 8A and Figure 8B In the embodiment, the mask layer 705 may be patterned using acceptable photolithography and etching techniques (see Figure 7) to form a mask 801. The pattern of the mask 801 can then be transferred to the dummy gate layer 703. In some embodiments (not shown), the pattern of the mask 801 can also be transferred to the dummy dielectric layer 701 by an acceptable etching technique to form a dummy gate 803. The dummy gate 803 covers the corresponding channel region 805 of the fin 103. The pattern of the mask 801 can be used to physically separate each dummy gate 803 from an adjacent dummy gate. The dummy gate 803 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 103.

[0037] Further in Fig. 8A and Figure 8B In the embodiment, a gate sealing spacer 807 may be formed on the exposed surface of the dummy gate 803, the mask 801 and / or the fin 103. Thermal oxidation or deposition followed by anisotropic etching may form the gate sealing spacer 807. The gate sealing spacer 807 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0038] After forming the gate sealing spacer 807, an implant for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the above Figure 6 As discussed in the implantation described above, a mask (e.g., photoresist) may be formed over the n-type region 200N while exposing the p-type region 200P, and an impurity of an appropriate type (e.g., p-type) may be implanted into the exposed fins 103 in the p-type region 200P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 200P while exposing the n-type region 200N, and an impurity of an appropriate type (e.g., n-type) may be implanted into the exposed fins 103 in the n-type region 200N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities, and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have a doping range from about 10 15 cm -3 to about 10 19 cm -3 An annealing process can be used to repair implant damage and activate the implanted impurities.

[0039] exist Fig.9A and Fig. 9B , a gate spacer 901 is formed on the gate sealing spacer 807 along the sidewalls of the dummy gate 803 and the mask 801. The gate spacer 901 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 901 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, and the like.

[0040] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the gate sealing spacer 807 may not be etched before the gate spacer 901 is formed, resulting in an "L-shaped" gate sealing spacer), spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type and p-type devices. For example, the LDD region of an n-type device may be formed before the gate sealing spacer 807 is formed, and the LDD region of a p-type device may be formed after the gate sealing spacer 807 is formed.

[0041] FIG. 10A to FIG. 10C An intermediate structure 1000 for forming a first FinFET 100 according to some embodiments is shown. Specifically, according to some embodiments, FIG. 10A to FIG. 10C 1 shows a patterning process for forming a first opening 1001 for the p-type region 200P in the source / drain region 111 of the fin 103. According to some embodiments, the patterning process includes applying one or more masks and a photoresist over the n-type region 200N, and then developing and etching the photoresist to form a first opening 1001 for the p-type region 200P. Fig.9A and Fig. 9B A mask is formed over the intermediate structure shown. Once formed, the mask is used to transfer the pattern of the mask to the underlying layer during the etching process and form a first opening 1001 in the source / drain region 111 of the fin 103. In the embodiment shown, the first opening 1001 is formed through the dummy dielectric layer 701 and into the material of the fin 103 using an anisotropic etching process. The etching process can be a wet etch, a dry etch, a combination, etc., and can be performed using any suitable anisotropic etching process, an isotropic etching process, a combination, etc. In addition, the first opening 1001 can be formed into any suitable size and shape for forming such an opening.

[0042] Relative to along Figure 1 The cutting line of the reference section BB is shown, Fig. 10B It is further shown that the first openings 1001 are formed such that each dummy gate 803 is disposed between a corresponding adjacent pair of the first openings 1001 . Fig. 10B Also shown is a first opening 1001 formed using an anisotropic etch through the dummy dielectric layer 701 and into the material of the fin 103 , in accordance with some embodiments.

[0043] Relative to along Figure 1 The cutting line of the reference section CC is shown, Fig. 10CIt is shown that according to some embodiments, first opening 1001 is formed between gate spacers 901 and recesses fin 103 below the level of STI region 105. However, first opening 1001 may also be formed at the level of STI region 105, or may be formed at any suitable level below STI region 105, or even formed through fin 103. All of these levels of recessing fin 103 are within the scope of embodiments.

[0044] Go to Fig.11A and Fig. 11B , these figures show a deposition system 1105 used in various steps of manufacturing the embodiment devices described herein. The deposition system 1105 can be used to receive precursor materials from the first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112, and form a material layer in the first opening 1001 between the gate spacers 901. In an embodiment, the first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 can work in conjunction with each other to supply various different precursor materials and etching materials to the deposition chamber 1113 in which the intermediate structure 1000 is placed. However, the first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 can have similar physical components to each other.

[0045] For example, the first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 may each include a gas supply source 1115 and a flow controller 1117 (in Fig.11A 1107 is labeled with respect to the first precursor delivery system 1107, but for the sake of clarity, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 are not labeled). In embodiments in which the first precursor is stored in a gaseous state, a gas supply source 1115 can supply the first precursor to the deposition chamber 1113. The gas supply source 1115 can be a container such as a gas storage tank, which is located locally relative to the deposition chamber 1113, or can be located remotely relative to the deposition chamber 1113. In other embodiments, the gas supply source 1115 can be a facility that independently prepares the first precursor and delivers it to the flow controller 1117. Any suitable first precursor source can be used as the gas supply source 1115, and all such sources are fully intended to be included within the scope of the embodiments.

[0046] The gas supply source 1115 can supply the desired precursor to the flow controller 1117. The flow controller 1117 can be used to control the flow of the precursor to the precursor gas controller 1119, and ultimately to the deposition chamber 1113, thereby also helping to control the pressure within the deposition chamber 1113. The flow controller 1117 can be, for example, a proportional valve, a regulating valve, a needle valve, a pressure regulator, a mass flow controller, a combination of these, etc. However, any suitable method for controlling and regulating the flow of the carrier gas to the precursor tank (not shown separately) can be used, and all such components and methods are fully intended to be included within the scope of the embodiments.

[0047] However, as will be appreciated by one of ordinary skill in the art, although the first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 are described herein as having the same components, this is merely an illustrative example and is not intended to limit the embodiments in any way. Any type of suitable precursor delivery system may be used, having any type and number of individual components that are the same or different than any other precursor delivery system within the deposition system 1105. All such precursor systems are fully intended to be included within the scope of the embodiments.

[0048] In addition, in embodiments where the first precursor is stored in a solid or liquid state, the gas supply 1115 may store a carrier gas (e.g., hydrogen (H2)), and the carrier gas may be introduced into a precursor tank (not shown separately), which stores the first precursor in a solid or liquid state. The carrier gas is then used to push and carry the first precursor (as it evaporates or sublimates) into the gaseous portion of the precursor tank and then sent to the precursor gas controller 1119. Any suitable method and combination of units may be used to provide the first precursor, and all such combinations of units are fully intended to be included within the scope of the embodiments.

[0049] The first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 can supply their respective precursor materials to the precursor gas controller 1119. The precursor gas controller 1119 connects and isolates the first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 with the deposition chamber 1113 to deliver the required precursor materials to the deposition chamber 1113. The precursor gas controller 1119 may include devices such as valves, flow meters, sensors, etc. to control the delivery rate of each precursor, and the precursor gas controller 1119 may be controlled by instructions received from the control unit 1121 (described below with respect to Fig. 11B further described).

[0050] The precursor gas controller 1119, upon receiving instructions from the control unit 1121, can open and close valves to connect one of the first precursor delivery system 1107, the second precursor delivery system 1009, the third precursor delivery system 1111, and the etching precursor delivery system 1112 to the deposition chamber 1113, and guide the desired precursor material into the deposition chamber 1113 through the manifold 1123 and to the nozzle 1125. The nozzle 1125 can be used to disperse the selected precursor material into the deposition chamber 1113, and can be designed to disperse the precursor material uniformly to minimize undesirable process conditions that may be generated due to non-uniform dispersion. In an embodiment, the nozzle 1125 can have a circular design with openings uniformly dispersed around the nozzle 1125 to allow the desired precursor material to be dispersed into the deposition chamber 1113.

[0051] However, as will be appreciated by one of ordinary skill in the art, the introduction of precursor material into the deposition chamber 1113 through a single showerhead 1125, or through a single introduction point, as described above, is intended to be illustrative only and is not intended to limit the embodiments. Any number of separate and independent showerheads 1125, or other openings for introducing precursor material into the deposition chamber 1113 may be utilized. All such combinations of showerheads 1125 and other introduction points are fully intended to be included within the scope of the embodiments.

[0052] The deposition chamber 1113 may receive a desired precursor material and expose the precursor material to the fin 103 at the bottom of the first opening 1001. The deposition chamber 1113 may be any desired shape suitable for dispersing the precursor material and contacting the precursor material with the fin 103. Fig.11A In the illustrated embodiment, the deposition chamber 1113 has cylindrical sidewalls, and a bottom. However, the deposition chamber 1113 is not limited to a cylindrical shape, and any other suitable shape may be utilized, such as a hollow square tube, an octagon, etc. In addition, the deposition chamber 1113 may be surrounded by a housing 1127, which is made of a material that is inert to the various process materials. Thus, while the housing 1127 may be any suitable material that can withstand the chemistry and pressures involved in the deposition process, in embodiments, the housing 1127 may be steel, stainless steel, nickel, aluminum, alloys thereof, combinations thereof, etc.

[0053] Within the deposition chamber 1113, the intermediate structure 1000 may be placed on a mounting platform 1129 to position and control the intermediate structure 1000 during the deposition process. The mounting platform 1129 may include a heating mechanism to heat the intermediate structure 1000 during the deposition process. Fig.11A A single mounting platform 1129 is shown in FIG. 1 , but any number of mounting platforms 1129 may additionally be included within the deposition chamber 1113 .

[0054] In addition, the deposition chamber 1113 and the mounting platform 1129 can be part of a cluster tool system (not shown). The cluster tool system can be used in conjunction with an automated handling system to position and place the intermediate structure 1000 in the deposition chamber 1113 prior to a deposition and / or etching process, position and hold the intermediate structure 1000 during the deposition and / or etching process, and remove the intermediate structure 1000 from the deposition chamber 1113 after the deposition and / or etching process is completed.

[0055] The deposition chamber 1113 may also have an exhaust outlet 1131 for exhaust gas to leave the deposition chamber 1113. A vacuum pump 1133 may be connected to the exhaust outlet 1131 to assist in exhausting the exhaust gas from the deposition chamber 1113. Under the control of the control unit 1121, the vacuum pump 1133 may also be used to reduce and control the pressure within the deposition chamber 1113 to a desired pressure.

[0056] Fig.11A A purge gas delivery system 1135 is further shown. In embodiments, the purge gas delivery system 1135 may be a gas tank or other facility that provides a purge gas such as nitrogen, argon, xenon, or other non-reactive gas to the deposition chamber 1113. In addition, under the control of the control unit 1121, the purge gas delivery system 1135 and / or the vacuum pump 1133 may also be used to exhaust the precursor material from the deposition chamber 1113 in preparation for the introduction of the next precursor material.

[0057] Fig. 11B An embodiment of a control unit 1121 that can be used to control a precursor gas controller 1119 and a vacuum pump 1133 is shown. The control unit 1121 can be any form of computer processor that can be used to control a process machine in an industrial environment. In an embodiment, the control unit 1121 may include a processing unit 1137, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit customized for a specific application. The control unit 1121 may be equipped with a display 1139 and input / output (I / O) components 1141, such as command output, sensor input, mouse, keyboard, printer, combinations of these items, etc. The processing unit 1137 may include a central processing unit (CPU) 1143 connected to a bus 1153, a memory 1145, a mass storage device 1147, a video adapter 1149, and an I / O interface 1151.

[0058] The bus 1153 may be one or more of any type of several bus architectures, including a memory bus or memory controller, a peripheral bus, or a video bus. The CPU 1143 may include any type of electronic data processor, and the memory 1145 may include any type of system memory, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), or a read-only memory (ROM). The mass storage device 1147 may include any type of storage device configured to store data, programs, and other information, and make such data, programs, and other information accessible via the bus 1153. The mass storage device 1147 may include, for example, one or more of a hard drive, a magnetic disk drive, or an optical disk drive.

[0059] Video adapter 1149 and I / O interface 1151 provide interfaces for coupling external input and output devices to processing unit 1137. Fig. 11B As shown, examples of input and output devices include a display 1139 coupled to a video adapter 1149, and an I / O component 1141 coupled to an I / O interface 1151, such as a mouse, keyboard, printer, etc. Other devices may be coupled to the processing unit 1137, and more or fewer interface cards may be used. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit 1137 may also include a network interface 1155, which may be a wired link to a local area network (LAN) or a wide area network (WAN) 1157, and / or a wireless link.

[0060] It should be noted that the control unit 1121 may include other components. For example, the control unit 1121 may include a power supply, a cable, a motherboard, a removable storage medium, a housing, etc. Although not shown in FIG. Fig. 11B , but these other components are considered part of the control unit 1121.

[0061] FIG. 12A to FIG. 18B Other steps for fabricating an embodiment device are shown, some of which may be performed in deposition system 1105. In addition, FIG. 12A to FIG. 18B Features in either the n-type region 200N or the p-type region 200P are shown. For example, FIG. 12A to FIG. 18B The structure shown is applicable to both the n-type region 200N and the p-type region 200P. The differences, if any, in the structure of the n-type region 200N and the p-type region 200P are described in the text of each figure.

[0062] exist FIG. 12A to FIG. 12C, with respect to reference cross section CC, these figures illustrate intermediate stages of forming a multilayer source / drain region 1201 according to some embodiments. The multilayer source / drain region 1201 may be epitaxially grown in the deposition chamber 1113 using any acceptable material, such as a material suitable for the first FinFET 100. For example, if the fin 103 is silicon, the multilayer source / drain region 1201 in the p-type region 200P may include a material that applies compressive strain in the channel region 805, such as boron-doped silicon germanium, silicon germanium, germanium, germanium tin, etc. The multilayer source / drain region 1201 in the p-type region 200P may have a surface that protrudes from a corresponding surface of the fin 103. In addition, the multilayer source / drain region 1201 may have any acceptable shape, such as a diamond, a circle, a square, a rectangle, etc. The multilayer source / drain region 1201 may also have a faceted surface, a flat surface, a rounded surface, an irregular surface, a rough surface, a smooth surface, etc.

[0063] The layers of the multi-layer source / drain region 1201 may be formed in the deposition chamber 1113 by initially placing the intermediate structure 1000 in the deposition chamber 1113. In embodiments where the multi-layer source / drain region 1201 is to be formed as a boron-doped silicon germanium structure, the first precursor material may be a source material such as silane (SiH4), dichlorosilane, i.e., DCS (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4), etc., and the first precursor material is placed in the first precursor delivery system 1107. The second precursor material may be a source material such as germane (GeH4), digermane (Ge2H6), etc., and the second precursor material is placed in the second precursor delivery system 1109. The third precursor material may be a source material such as diborane (B2H6), etc., and the third precursor material is placed in the third precursor delivery system 1111. The etching precursor material can be a source material such as hydrogen chloride (HCl), chlorine (Cl2), etc., and the etching precursor material is placed in the etching precursor delivery system 1112. However, those skilled in the art will recognize that the source materials listed above are not the only precursor materials that can be used to form boron-doped silicon germanium, and the use of these source materials is not intended to limit the embodiment. Any suitable precursor material in any suitable phase (solid, liquid or gaseous) can be utilized.

[0064] Fig. 12AThe first epitaxial growth layer 1201a is shown formed in the first opening 1001 of the p-type region 200P according to some embodiments. According to some embodiments, the first epitaxial growth layer 1201a may be formed as a silicon germanium structure doped with boron using dichlorosilane (SiH2Cl2) or silane (SiH4) as a first precursor and using germane (GeH4) or digermane (Ge2H6) as a second precursor. In such an embodiment, the control unit 1121 may direct the flow controller 1117 of the first precursor delivery system 1107 to flow the first precursor into the deposition chamber 1113 at a first flow rate fr1 between about 10 sccm and about 200 sccm, and direct the flow controller 1117 of the second precursor delivery system 1109 to flow the second precursor into the deposition chamber 1113 at a second flow rate fr2 between about 10 sccm and about 1000 sccm. However, any suitable flow rate may be used. The first flow rate ratio R1 may be calculated as a ratio of the second flow rate fr2 to the first flow rate fr1 (eg, R1 = fr2 / fr1). According to some embodiments, the first flow rate ratio R1 is a ratio between about 1:1 and about 50:1. However, any suitable flow rate may be used.

[0065] In addition, according to some embodiments, hydrogen (H2) may be used as a carrier gas. For each precursor using a carrier gas, the control unit 1121 may control the flow rate so that the carrier gas flows at a fifth rate between about 1 slm and about 40 slm. In addition, during the deposition of the first epitaxial growth layer 1201a, the deposition chamber 1113 may be maintained in a process temperature range between about 400°C and about 700°C, and a process pressure range between about 1 Torr and about 100 Torr. However, any suitable carrier gas, process temperature, and process pressure may be used.

[0066] The first epitaxial growth layer 1201a may be doped in situ during growth, or may be doped by implantation after growth. In an embodiment in which the first epitaxial growth layer 1201a is doped in situ during growth, diborane (B2H6) may be used as the third precursor. In such an embodiment, the control unit 1121 may direct the flow controller 1117 of the third precursor delivery system 1111 to flow the third precursor into the deposition chamber 1113 at a third flow rate between about 10 sccm and about 200 sccm. In an embodiment in which the first epitaxial growth layer 1201a is doped by implantation after growth, an acceptable process such as ion implantation may be used to implant p-type dopants. In such an embodiment, the p-type dopant may be implanted after the first epitaxial growth layer 1201a is grown and before other layers of the multilayer source / drain region 1201 are formed on the first epitaxial growth layer 1201a. However, the p-type dopant may also be implanted after all epitaxial growth layers of the multilayer source / drain region 1201 have been formed.

[0067] In some embodiments, hydrogen chloride (HCl) or chlorine (Cl2) may be used as an etching precursor to control the epitaxial growth and shape of the first epitaxial growth layer 1201a. In such an embodiment, the control unit 1121 may direct the flow controller 1117 of the etching precursor delivery system 1112 to flow the etching precursor into the deposition chamber 1113 at a fourth flow rate between about 10 sccm and about 300 sccm. Fig. 12A In the illustrated embodiment, the first epitaxial growth layer 1201a is formed into a first rhombus having a first faceted surface, wherein the top surface is flat. In addition, according to some embodiments, the first epitaxial growth layers 1201a are formed to be separated from each other. In other embodiments, the first epitaxial growth layers 1201a may be formed to be merged together.

[0068] In addition, in an embodiment in which the first epitaxial growth layer 1201a is grown as a boron-doped silicon germanium structure, the first epitaxial growth layer 1201a is grown to have a first concentration ratio (Ge% 1). The first concentration ratio (Ge% 1) represents the germanium (Ge) concentration level of the first epitaxial growth layer 1201a relative to the silicon (Si) concentration level, and can be expressed as Si (1-x) Ge x :B, where x is a decimal representing the volume percentage concentration of germanium (Ge), and B indicates a p-type dopant (e.g., boron (B)).

[0069] In addition, the first epitaxial growth layer 1201a may be formed with a relatively low germanium concentration to silicon concentration. The low germanium percentage concentration (Ge%) is within a first volume concentration range, wherein 0% ≤ Ge% <50%. According to some embodiments, the first concentration ratio (Ge% 1) represents a constant germanium (Ge) concentration level throughout the structure of the first epitaxial growth layer 1201a. In other embodiments, the first concentration ratio (Ge% 1) represents a gradient germanium (Ge) concentration level throughout the structure of the first epitaxial growth layer 1201a. For example, the structure of the first epitaxial growth layer 1201a may have a concentration level gradient, for which the germanium concentration level increases as the distance from the fin 103 increases. In this way, the gradient germanium (Ge) concentration level may reach about 50% at the top of the first epitaxial growth layer 1201a from 0% at the bottom of the first epitaxial growth layer 1201a in contact with the fin 103. In such an embodiment, the concentration level gradient may be formed during growth by adjusting one or more of the flow rates of the first precursor and the second precursor to increase the germanium percentage concentration.

[0070] According to some embodiments, the first epitaxial growth layer 1201a can be formed in a time period between about 50 seconds to about 500 seconds using a first timed deposition process and a first flow rate ratio R1. However, any suitable time period can be used. According to some embodiments, the first epitaxial growth layer 1201a is formed above the fin 103 to a first height H1. According to some embodiments, the first height H1 can be between about 10nm and about 50nm. However, any suitable height can be used. The first epitaxial growth layer 1201a may be referred to herein as a first layer, a bottom layer, a first source / drain layer, a bottom source / drain layer, etc.

[0071] Go to Fig. 12B , which shows that a second epitaxial growth layer 1201b is formed on top of a first epitaxial growth layer 1201a according to some embodiments. According to some embodiments, the second epitaxial growth layer 1201b is formed with a relatively low germanium concentration of a second concentration ratio (Ge% 2), which is within a second volume concentration range, wherein 0% ≤ Ge% 2 < 50%. In such an embodiment, the second concentration ratio (Ge% 2) of the second epitaxial growth layer 1201b may also be greater than or equal to the maximum concentration level of the first concentration ratio (Ge% 1) of the first epitaxial growth layer 1201a. The second epitaxial growth layer 1201b may be grown with a second concentration ratio (Ge% 2) by adjusting the flow rates of the first precursor and the second precursor during growth. In some embodiments, the second concentration ratio (Ge% 2) may be a constant germanium (Ge) concentration level throughout the structure of the second epitaxial growth layer 1201b. In other embodiments, the second concentration ratio (Ge% 2) may be a gradient germanium (Ge) concentration level that increases with increasing distance from the first epitaxial growth layer 1201a. In such an embodiment, a second germanium concentration level (Ge%2) can be formed during growth by adjusting one or more of the flow rates of the first precursor and the second precursor used in the formation of the first epitaxial growth layer 1201a to increase the germanium percentage concentration during the growth of the second epitaxial growth layer 1201b. For example, the first flow rate fr1 of the first precursor can be adjusted to a third flow rate fr3. According to some embodiments, the third flow rate fr3 can be less than the first flow rate fr1. In addition, the second flow rate fr2 of the second precursor can be adjusted to a fourth flow rate fr4. In some embodiments, the fourth flow rate fr4 can be greater than the second flow rate fr2. The second flow rate ratio R2 can be calculated as the ratio of the fourth flow rate fr4 to the third flow rate fr3 (for example, R2=fr4 / fr3). In some embodiments, the second flow rate ratio R2 is greater than the first flow rate ratio R1. In this way, during the growth of the second epitaxial growth layer 1201b, the germanium volume percentage (Ge%) can be increased from the first germanium volume percentage (Ge%1) to the second germanium volume percentage (Ge%2).

[0072] In such an embodiment, the second concentration ratio (Ge% 2) of the second epitaxial growth layer 1201b may also be greater than or equal to the maximum concentration level (Ge% 1 max ). Due to the difference in germanium concentration levels between the second concentration ratio (Ge% 2) and the first concentration ratio (Ge% 1), a first interface is formed between the first epitaxial growth layer 1201a and the second epitaxial growth layer 1201b. In embodiments where the second concentration ratio (Ge% 2) at the first interface is substantially the same as the first concentration ratio (Ge% 1), the first interface may be considered to be a continuous interface. For example, the first concentration ratio (Ge% 1) may be a first concentration gradient of a first volume concentration range, wherein 0% ≤ Ge% 1 < 25%, and the second concentration ratio (Ge% 2) may be a second concentration gradient of a second volume concentration range, wherein 25% ≤ Ge% 2 < 50%. However, any suitable concentration range may be used for the first range and the second range.

[0073] In addition, in an embodiment where the second concentration ratio (Ge%2) represents a second concentration level gradient at the first interface and the second concentration ratio (Ge%2) is different from the first concentration ratio (Ge%1) representing the first concentration level gradient, the first interface may be considered a discontinuous interface. For example, the first concentration ratio (Ge%1) may be a first concentration gradient of a first volume concentration range, wherein 0%≤Ge%1<20%, and the second concentration ratio (Ge%2) may be a second concentration gradient of a second volume concentration range, wherein 30%≤Ge%2<50%. However, any suitable concentration range may be used for the first range and the second range. As another example of a discontinuous interface, the first concentration ratio (Ge%1) may be a first constant concentration level, wherein 0%≤Ge%1<50% (e.g., Ge%1=25%), and the second concentration ratio (Ge%2) may be a second constant concentration level, wherein 0%≤Ge%2<50% (e.g., Ge%2=40%). However, any suitable concentration level may be used for the first constant concentration level and the second constant concentration level. According to some embodiments, the concentration level ratio of the first interface may be a maximum level of the second germanium concentration level (Ge% 2 max ) compared to the maximum level of the first germanium concentration level (Ge% 1 max ), which can be expressed as Ge%2 max / Ge%1 max , and can be between about 1: 1 to about 2.5: 1. However, any suitable ratio can be used.

[0074] In addition, the second epitaxial growth layer 1201b can be doped with a p-type dopant (e.g., boron (B)) in situ during growth, or implanted after growth. In embodiments where the second epitaxial growth layer 1201b is doped in situ during growth, the control unit 1121 maintains the flow rate of the third precursor at the third flow rate (if this is the case), or the control unit 1121 directs the flow controller 1117 of the third precursor delivery system 1111 to deliver the third precursor to the deposition chamber 1113 at a third rate between about 10 sccm and about 200 sccm. In embodiments where the dopant is implanted into the second epitaxial growth layer 1201b after growth, the flow rate of the third precursor can be kept off (if this is the case), or can be turned off to stop doping in situ during growth. After the second epitaxial growth layer 1201b has been formed, a process such as ion implantation can be used to implant the p-type dopant.

[0075] In addition, in the illustrated embodiment, the second epitaxial growth layer 1201b is formed into second rhombuses having second faceted surfaces, wherein the top surface is flat. The shape and surface of the second epitaxial growth layer 1201b are controlled during growth by adjusting the flow rate of the etching precursor. In addition, according to some embodiments, the second epitaxial growth layers 1201b are formed to be separated from each other. In other embodiments, the second epitaxial growth layers 1201b may be formed to be merged together.

[0076] According to some embodiments, the second epitaxial growth layer 1201b may be formed with a second concentration ratio (Ge% 2) using a second flow ratio R2. However, any suitable flow ratio may be used. In addition, according to some embodiments, the second epitaxial growth layer 1201b may be formed with a second height H2 above the first epitaxial growth layer 1201a using a second timed deposition process within a time period between about 5 seconds and about 100 seconds. However, any suitable time period may be used. According to some embodiments, the second height H2 is between about 1nm and about 30nm. However, any suitable height may be used. The second epitaxial growth layer 1201b may be referred to herein as a second layer, an intermediate layer, an intermediate layer, a second source / drain layer, an intermediate source / drain layer, an intermediate source / drain layer, etc.

[0077] Fig. 12C An enlarged view (not to scale) of multiple layers of source / drain regions 1201 adjacent to source / drain regions is shown forming one possible completion of source / drain regions 1201 . Fig. 12CIt is further shown that a third epitaxial growth layer 1201c is formed on top of the second epitaxial growth layer 1201b according to some embodiments. According to some embodiments, the third epitaxial growth layer 1201c is formed with a relatively high germanium concentration to silicon concentration of a third concentration ratio (Ge%3), or even pure germanium. The high germanium percentage concentration (Ge%) may be within a volume concentration range where 50%≤Ge%<100%. In such an embodiment, the third concentration ratio (Ge%3) of the third epitaxial growth layer 1201c is greater than the second concentration ratio (Ge%2) of the second epitaxial growth layer 1201b and the first concentration ratio (Ge%1) of the first epitaxial growth layer 1201a. The third epitaxial growth layer 1201c may be grown with a third concentration ratio (Ge%3) by adjusting the flow rates of the first precursor and the second precursor during growth. For example, the third flow rate fr3 of the first precursor may be adjusted to a fifth flow rate fr5. According to some embodiments, the fifth flow rate fr5 may be less than the third flow rate fr3. In addition, the fourth flow rate fr4 of the second precursor may be adjusted to a sixth flow rate fr6. In some embodiments, the sixth flow rate fr6 may be greater than the fourth flow rate fr4. The third flow rate ratio R3 may be calculated as the ratio of the sixth flow rate fr6 to the fifth flow rate fr5 (e.g., R3=fr6 / fr5). In some embodiments, the third flow rate ratio R3 is greater than the second flow rate ratio R2. Thus, during the growth of the third epitaxial source / drain layer 1201c, the germanium volume percentage (Ge%) may be increased from the second germanium volume percentage (Ge%2) to the third germanium volume percentage (Ge%3). The second epitaxial growth layer 1201b prevents strain relaxation of the third epitaxial growth layer 1201c caused by the high lattice mismatch between the first epitaxial growth layer 1201a and the third epitaxial growth layer 1201c. In addition, the third epitaxial growth layer 1201c provides a low contact resistance between the multilayer source / drain region 1201 and the subsequently formed metal contact.

[0078] In addition, the third epitaxial growth layer 1201c can be doped with a p-type dopant (e.g., boron (B)) in situ during growth, or implanted after growth. In embodiments where the third epitaxial growth layer 1201c is doped in situ during growth, the control unit 1121 maintains the flow rate of the third precursor at the third flow rate (if this is the case), or the control unit 1121 directs the flow controller 1117 of the third precursor delivery system 1111 to deliver the third precursor to the deposition chamber 1113 at a third rate between about 10 sccm and about 200 sccm. In embodiments where the dopant is implanted into the third epitaxial growth layer 1201c after growth, the flow rate of the third precursor can be kept off (if this is the case), or can be turned off to stop doping in situ during growth. After the third epitaxial growth layer 1201c has been formed, the p-type dopant can be implanted using a process such as ion implantation.

[0079] In addition, in the illustrated embodiment, the third epitaxial growth layer 1201c is formed into third rhombuses having third facets, wherein the top surface is flat. The shape and surface of the third epitaxial growth layer 1201c are controlled during growth by adjusting the flow rate of the etching precursor. In addition, according to some embodiments, the third epitaxial growth layers 1201c are formed together. In other embodiments, the third epitaxial growth layers 1201c may be formed to be separated from each other.

[0080] According to some embodiments, a third timed deposition process may be used to form the third epitaxial growth layer 1201c to have a third height H3 above the second epitaxial growth layer 1201b within a time period between about 5 seconds and about 100 seconds. However, any suitable time period may be used. According to some embodiments, the third height H3 is between about 1nm and about 40nm. However, any suitable height may be used. In addition, according to some embodiments, the third epitaxial growth layer 1201c may be formed with a third concentration ratio (Ge% 3) using a third flow rate ratio R3. However, any suitable flow rate ratio may be used. The third epitaxial growth layer 1201c may be referred to herein as a third layer, a top layer, a third source / drain layer, a top source / drain layer, etc.

[0081] Fig. 12C Further shown are multilayer source / drain regions 1201 of adjacent source / drain regions according to some embodiments, wherein the third epitaxial growth layer 1201c of the adjacent source / drain regions has been merged. In some embodiments, gate spacers 901 are used to separate the multilayer source / drain regions 1201 from the dummy gate 803 ( Fig. 10B ) are separated by an appropriate lateral distance so that the multi-layer source / drain region 1201 does not short-circuit the subsequently formed gate of the resulting FinFET. In addition, the material of the multi-layer source / drain region 1201 can be selected to be spaced apart between each channel region 805 ( Fig. 10B ) to improve performance.

[0082] As a result of the epitaxial process used to form the multi-layer source / drain regions 1201 in the p-type region 200P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fins 103. In some embodiments, these facets allow adjacent source / drain regions 1201 of the same FinFET to merge, such as Fig. 12C As shown. FIG. 12A to FIG. 12CIn the illustrated embodiment, the gate spacer 901 is formed to cover a portion of the sidewalls of the fin 103 that extend over the STI region 105, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacer 901 can be adjusted to remove the spacer material to allow the epitaxial growth area to extend to the surface of the STI region 105.

[0083] although Figure 12A-12C In the illustrated embodiment, the third epitaxial growth layer 1201c is fused to each other, and the remaining epitaxial growth layers of the adjacent multi-layer source / drain region 1201 remain separated, but other embodiments are possible. For example, in some embodiments, the third epitaxial growth layer 1201c and the second epitaxial growth layer 1201b of the adjacent multi-layer source / drain region 1201 may be merged together, and the first epitaxial growth layer 1201a of the adjacent multi-layer source / drain region 1201 may remain separated. In addition, in some embodiments, the third epitaxial growth layer 1201c, the second epitaxial growth layer 1201b, and the first epitaxial growth layer 1201a of the adjacent multi-layer source / drain region 1201 may be merged together. All of these examples of merged epitaxial growth layers of the adjacent multi-layer source / drain region 1201 are within the scope of the embodiments.

[0084] Once the multi-layer source / drain regions 1201 are formed in the p-type region 200P, epitaxial source / drain regions may be formed in the n-type region 200N by initially removing the mask from the n-type region 200N and placing another mask over the p-type region 200P. Once the mask in the n-type region 200N is removed, the source / drain regions may be epitaxially grown using any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 103 is silicon, the source / drain regions formed in the n-type region 200N may include a material that applies tensile strain in the channel region 805, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. In addition, the source / drain regions and / or fins 103 in the n-type region 200N may be implanted with n-type dopants to form n-type source / drain regions, similar to the process previously discussed for implanting dopants in the multi-layer source / drain regions 1201 of the p-type region 200P, followed by annealing. The source / drain regions in the n-type region 200N may have a thickness of about 10 19 cm -3 to about 10 21 cm -3According to some embodiments, the source / drain region of the n-type region 200N can be epitaxially grown with a single material concentration level throughout the source / drain region. In other embodiments, the source / drain region of the n-type region can be grown with a concentration level gradient of the material in the source / drain region. In other embodiments, the source / drain region of the n-type region 200N can also be formed as a multi-layer source / drain region similar to the multi-layer source / drain region 1101 of the p-type region 200P, except that there are different carbon and / or phosphate concentration levels in each layer instead of different germanium concentration levels. Once the source / drain region in the n-type region 200N has been formed, the mask can be removed from the p-type region 200P for further processing.

[0085] According to some embodiments, the first multilayer concentration ratio of the multilayer source / drain region 1201 can be the ratio of the combined height of the layers having the highest concentration ratio (e.g., Ge% 3) to the combined height of the layers having the lowest concentration ratio (e.g., Ge% 1). According to some embodiments, the first multilayer concentration ratio (H3 / H1) is about 0.1:1 to about 3:1. In this way, the first shared contact landing area 1203 is formed with a relatively large volume of material having the highest concentration ratio (e.g., Ge% 3). The first shared contact landing area 1203 and other shared contact landing areas described herein may be collectively referred to herein as MD landing, contact landing area, contact landing zone, contact landing, etc.

[0086] The first shared contact landing area 1203 includes a very deep extension area of ​​high concentration germanium (Ge% 3) material formed between the second epitaxial growth layer 1201b. The boundary of the first shared contact landing area 1203 is at Fig.12D1201c . The first shared contact landing area 1203 includes a volume of high concentration germanium (Ge% 3) below the flat top of the merged third layer 1201c, which volume is up to and includes the volume between the sidewalls of the second epitaxial growth layer 1201b. The first shared contact landing area 1203 extends a first depth D1 from the top of the third epitaxial growth layer 1201c to the bottom of the third epitaxial growth layer 1201c along the centerline between the third epitaxial growth layers 1201c. According to some embodiments, the first depth D1 is between about 10nm and about 50nm. However, any suitable depth can be used. In addition, the first shared contact landing area 1203 has a first width W1 between the tops of the second epitaxial growth layers 1201b. According to some embodiments, the first width W1 is between about 15nm and about 30nm. However, any suitable width can be used. The first shared contact landing area 1203 also has a second width W2, which is the minimum distance between the second epitaxial growth layers 1201b. According to some embodiments, the second width W2 is between about 0 nm and about 30 nm. However, any suitable width may be used. Thus, embodiments of the first shared contact landing area 1203 provide a large volume landing area with a very deep extension area having a low contact resistance for ultimately forming the source drain contact 1803 ( Fig.18B shown).

[0087] In some embodiments, the third concentration ratio (Ge% 3) can be a constant germanium (Ge) concentration level throughout the structure of the third epitaxial growth layer 1201c. In other embodiments, the third concentration ratio (Ge% 3) can be a gradient germanium (Ge) concentration level that increases with increasing distance from the fin 103. In such embodiments, the third germanium concentration level (Ge% 3) can be modified by adjusting one or more of the flow rates of the first precursor and the second precursor to increase the germanium percentage concentration during the growth of the third epitaxial growth layer 1201c. In some such embodiments, the increase in the germanium percentage concentration can be linear throughout the epitaxial growth. For example, as Fig. 12C As shown by the first directional arrow 1205a, the third germanium concentration level (Ge% 3) increases from the minimum concentration level (eg, Ge% min ) increases linearly to a maximum concentration level (e.g., Ge% max ). In other such embodiments, the increase in germanium percentage concentration may be non-linear throughout the epitaxial growth. For example, Fig. 12C As shown by the second directional arrow 1205b, the third germanium concentration level (Ge% 3) increases from the first minimum concentration level (eg, Ge% min1 ) to a maximum concentration level (e.g., Ge% max), and then the third germanium concentration level (Ge% 3) decreases from the maximum value to the second minimum concentration level (eg, Ge% min2 Thus, the maximum concentration level (e.g., Ge% max ) is located at the midpoint along the first distance D1.

[0088] In such an embodiment, the third concentration ratio (Ge% 3) of the third epitaxial growth layer 1201c is greater than or equal to the maximum concentration level (Ge% 2 max Due to the difference in germanium concentration levels between the third concentration ratio (Ge% 3) and the second concentration ratio (Ge% 2), a second interface is formed between the second epitaxial growth layer 1201b and the third epitaxial growth layer 1201c. The concentration level range from the second concentration ratio (Ge% 2) to the third concentration ratio (Ge% 3) across the second interface may be a continuous range or a discontinuous range.

[0089] Furthermore, the second ratio between the concentration levels at the second interface may be a maximum level of the third germanium concentration level (Ge% 3 max ) compared to the maximum level of the second germanium concentration level (Ge% 2 max ), which can be expressed as Ge%3 max / Ge%2 max , and can be between about 1: 1 to about 2: 1. However, any suitable ratio can be used.

[0090] Although the multilayer source / drain region 1201 has been shown using three layers, the multilayer source / drain region 1201 may have any suitable number of layers with low concentrations, and / or any suitable number of layers with high concentrations. For example, in some embodiments, the multilayer source / drain region 1201 may have one low-concentration layer and one high-concentration layer. In some embodiments, the multilayer source / drain region 1201 may have more than one (e.g., two, three, or more) low-concentration layers. In some embodiments, the multilayer source / drain region 1201 may have more than one (e.g., two, three, or more) high-concentration layers. All such combinations of low-concentration layers and high-concentration layers are within the scope of the embodiments. Fig. 12C A third directional arrow 1205c is further shown, which indicates the depth direction of the epitaxial growth through the third epitaxial growth layer 1201c and will be Fig.12D Referenced in the discussion.

[0091] continue Fig.12D , which is a diagram according to some embodiments according to the third directional arrow 1205c passing through Fig. 12C1205c). The line represents the germanium concentration (Ge%) of the multilayer source / drain region 1201 for an embodiment in which the germanium concentration is gradient along the third directional arrow 1205c. The graph further shows that the germanium percentage concentration (Ge%) of the source / drain region 1201 according to some embodiments ranges from a minimum germanium percentage concentration (Ge0%) of about 0% to a maximum germanium percentage concentration (Ge3%) of about 100% germanium. max The graph further shows a gradient along the third directional arrow 1205c, which increases at a first rate from its minimum percentage (Ge0%) to its maximum percentage (Ge%3) as depth increases to a midpoint along the third directional arrow 1205c starting above the multi-layer source / drain region 1201. max ). The graph further shows that the gradient along the third directional arrow 1205c increases continuously with depth from the midpoint along the third directional arrow 1205c to a point below the multi-layer source / drain region 1201, while decreasing from its maximum percentage (Ge% 3 max ) is reduced to its minimum percentage (Ge0%).

[0092] Fig.13A and Fig. 13B The formation of a contact etch stop layer (CESL) 1301 and a first interlayer dielectric (ILD) 1303 with respect to cut lines AA and BB, respectively, according to some embodiments is shown. Once the multi-layer source / drain region 1201 has been formed in the first opening 1001, the contact etch stop layer 1301 and the first interlayer dielectric 1303 may be formed. In some embodiments, the contact etch stop layer 1301 is formed over the exposed surfaces of the multi-layer source / drain region 1201, the dummy dielectric layer 701, the gate spacer 901, the gate sealing spacer 807, and the mask 801. The contact etch stop layer 1301 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. However, any suitable dielectric material may be used.

[0093] Once the contact etch stop layer 1301 has been formed, a first interlayer dielectric 1303 is deposited over the contact etch stop layer 1301. The first interlayer dielectric 1303 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like. Other insulating materials formed by any acceptable process may also be used. According to some embodiments, the dielectric material of the contact etch stop layer 1301 has a lower etching rate than the dielectric material of the first interlayer dielectric 1303.

[0094] Fig. 13B Further shown are first shared contact landing areas 1203 in each multi-layer source / drain region 1201. The first shared contact landing areas 1203 are shown in perspective to indicate their Fig. 13B The profile of the first shared contact landing area 1203 shown relative to the cutting line BB is similar to that shown relative to the cutting line CC. Fig.12D The contours of the first shared contact landing area 1203 are shown, but they can also be different.

[0095] exist Fig.14A and Fig. 14B In the process, a planarization process (e.g., CMP) may be performed to make the top surface of the first interlayer dielectric 1303 flush with the top surface of the dummy gate 803 or the mask 801. The planarization process may also remove the mask 801 on the dummy gate 803, and the portions of the gate sealing spacer 807 and the gate spacer 901 along the sidewalls of the mask 801. After the planarization process, the top surfaces of the dummy gate 803, the gate sealing spacer 807, the gate spacer 901, and the first interlayer dielectric 1303 are flush. Therefore, the top surface of the dummy gate 803 is exposed through the first interlayer dielectric 1303. In some embodiments, the mask 801 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric 1303 flush with the top surface of the mask 801.

[0096] exist Fig.15A and Fig. 15BIn the embodiment of the present invention, the dummy gate 803 and the mask 801 (if present) are removed in (one or more) etching steps, thereby forming a second opening 1501. The portion of the dummy dielectric layer 701 in the second opening 1501 may also be removed. In some embodiments, only the dummy gate 803 is removed, and the dummy dielectric layer 701 remains and is exposed by the second opening 1501. In some embodiments, the dummy dielectric layer 701 is removed from the second opening 1501 in the first area of ​​the die (e.g., the core logic area) and remains in the second opening 1501 in the second area of ​​the die (e.g., the input / output area). In some embodiments, the dummy gate 803 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 803 and hardly etches or does not etch the first interlayer dielectric 1303 or the gate spacer 901. Each second opening 1501 exposes and / or overlies a channel region 805 of a corresponding fin 103. Each channel region 805 is disposed between adjacent pairs of multi-layer source / drain regions 1201. During removal, the dummy dielectric layer 701 may be used as an etch stop layer when etching the dummy gate 803. The dummy dielectric layer 701 may then be optionally removed after the dummy gate 803 is removed.

[0097] exist Fig.16A and Fig. 16B In the embodiment, a gate dielectric layer 107 and a gate electrode 109 are formed for replacing the gate. Fig. 16C Shows Fig. 16B Detailed view of region 1601 of . The gate dielectric layer 107 may be formed of one or more layers deposited in the second opening 1501, for example, on the top surface and sidewalls of the fin 103, and on the sidewalls of the gate sealing spacer 807 and / or the gate spacer 901. The gate dielectric layer 107 may also be formed on the top surface of the first interlayer dielectric 1303. In some embodiments, the gate dielectric layer 107 includes one or more dielectric layers, for example, one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 107 includes an interfacial layer of silicon oxide formed by thermal oxidation or chemical oxidation, and a high-k dielectric material thereon, for example, a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 107 may include a dielectric layer having a k value greater than about 7.0. The formation method of the gate dielectric layer 107 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where portions of the dummy dielectric layer 701 remain in the second opening 1501 , the gate dielectric layer 107 includes the material of the dummy dielectric layer 701 (eg, SiO 2 ).

[0098] The gate electrode 109 is deposited on the gate dielectric layer 107 and fills the remaining portion of the second opening 1501. The gate electrode 109 may include a metal-containing material, for example, titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. Fig. 16B A single layer is shown for the gate electrode 109, but the gate electrode 109 may include any number of liner layers 109A, any number of work function adjustment layers 109B, and filler materials 109C, such as Fig. 16C As shown. After filling and / or overfilling the second opening 1501, a planarization process such as CMP may be performed to remove the material of the gate electrode 109 and the excess portion of the gate dielectric layer 107 from the top surface of the first interlayer dielectric 1303. The material of the gate electrode 109 and the remaining portion of the gate dielectric layer 107 thus form a replacement gate of the resulting FinFET. The gate electrode 109 and the gate dielectric layer 107 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 805 of the fin 103.

[0099] The formation of the gate dielectric layer 107 in the n-type region 200N and the p-type region 200P may occur simultaneously, such that the gate dielectric layer 107 in each region is formed of the same material, and the formation of the gate electrode 109 may occur simultaneously, such that the gate electrode 109 in each region is formed of the same material. In some embodiments, the gate dielectric layer 107 in each region may be formed by different processes, such that the gate dielectric layer 107 may be a different material, and / or the gate electrode 109 in each region may be formed by different processes, such that the gate electrode 109 may be a different material. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0100] exist Fig.17A and Fig. 17B In the embodiment of the present invention, a gate mask 1701 is formed over a gate stack (including a gate dielectric layer 107 and a gate electrode 109), and the gate mask 1701 may be disposed between opposing portions of a gate spacer 901. In some embodiments, forming the gate mask 1701 includes recessing the gate stack so that a recess is formed directly above the gate stack and between opposing portions of the gate spacer 901. The gate mask 1701 includes one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., filled and / or overfilled in the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first interlayer dielectric 1303.

[0101] Also like Fig.17A and Fig. 17BAs shown, a second interlayer dielectric 1703 is deposited on the first interlayer dielectric 1303. In some embodiments, the second interlayer dielectric 1703 is a flowable film formed by a flowable CVD method. In some embodiments, the second interlayer dielectric 1703 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The gate contact 1801 ( Fig.18A and Fig.18B ) passes through the second interlayer dielectric 1703 and the gate mask 1701 to contact the top surface of the recessed gate electrode 109.

[0102] Fig.18A and Fig.18B The gate contact 1801 and source / drain contacts 1803 of the second FinFET 1800 are shown formed in accordance with some embodiments. The gate contact 1801 and the source / drain contacts 1803 are formed by initially forming openings through one or more of the second interlayer dielectric 1703, the first interlayer dielectric 1303, the contact etch stop layer 1301, or the gate mask 1701.

[0103] Specifically, an opening for the source / drain contact 1803 is formed through the second interlayer dielectric 1703, the first interlayer dielectric 1303, the contact etch stop layer 1301, and into the first shared contact landing area 1203 of the multi-layer source / drain region 1201. The opening for the source / drain contact 1803 may be formed using acceptable photolithography and etching techniques.

[0104] In addition, an opening for the gate contact 1801 may be formed in combination with the opening for the source / drain contact 1803 or in addition to the opening for the source / drain contact 1803. The opening for the gate contact 1801 is formed to pass through the second interlayer dielectric 1703, the gate mask 1701, and into the material of the gate electrode 109. The opening for the gate contact 1801 may be formed using acceptable photolithography and etching techniques.

[0105] Once the openings for the source / drain contacts 1803 and / or the gate contacts 1801 have been formed, a liner (not shown) such as a diffusion barrier, an adhesion layer, etc., and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second interlayer dielectric 1703. The remaining liner and conductive material form the source / drain contacts 1803 and / or the gate contacts 1801 in their respective openings. An annealing process may be performed to form silicide at the interface between the multilayer source / drain region 1201 and the source / drain contacts 1803. The source / drain contact 1803 is physically and electrically coupled to the first shared contact landing area 1203 of the multi-layer source / drain region 1201, and the gate contact 1801 is physically and electrically coupled to the gate electrode 109 and provides an external connection to the second FinFET 1800. The source / drain contact 1803 and the gate contact 1801 can be formed in different processes, or can be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contact 1803 and the gate contact 1801 can be formed in different cross sections, which can avoid shorting of the contacts.

[0106] Although the embodiments of the multilayer source / drain region 1201 have been discussed as diamonds and / or surfaces of each layer being similar shapes to each other from one layer to another, each layer of the multilayer source / drain region 1201 may have any suitable shape and / or surface from one layer to another. Each layer of the multilayer source / drain region 1201 may be grown to have a surface protruding from the corresponding surface of the fin 103, and its shape is, for example, square, diamond, circular, etc. In some embodiments, each layer of the multilayer source / drain region 1201 may have a smooth surface, a faceted limited surface, etc. For example, one layer of the multilayer source / drain region 1201 may be a square with a flat surface, and another layer may be a diamond with a faceted surface. Any layer of the multilayer source / drain region 1201 may be any acceptable shape and acceptable surface, and any layer may have a different shape and / or have a different surface from any other layer. All such shapes and surfaces of the multilayer source / drain region 1201, and all such combinations of shapes and surfaces of the layers are within the scope of the embodiments.

[0107] Reference now Figures 19 to 24 , these graphs are along the Figure 1 The reference cross section CC shown is different in that multiple fins / FinFETs are provided. Figures 19 to 24 Similar to Fig.12D, and illustrates an intermediate step in forming a multi-layer source / drain region 1201 according to other embodiments.

[0108] Go to Fig.19 , which shows an enlarged view (not to scale) of a multi-layer source / drain region 1201 adjacent to a source / drain region according to another embodiment. Fig.19 The embodiment shown is similar to Fig.12D The embodiment shown; however, Fig.19 The multi-layer source / drain region 1201 is shown to include two layers instead of three layers. Fig.19 It is also shown that the first epitaxial growth layer 1201a adjacent to the source / drain region is formed with a relatively low germanium concentration of a first concentration ratio (Ge% 1), where 0% ≤ Ge% 1 < 50%, and the second epitaxial growth layer 1201b is formed to fill the top volume of the multilayer source / drain region 1201 with a relatively high germanium concentration of a third concentration ratio (Ge% 3), where 50% ≤ Ge% 3 ≤ 100%. In this way, a third interface is formed between the first epitaxial growth layer 1201a having the first concentration ratio (Ge% 1) and the second epitaxial growth layer 1201b having the third concentration ratio (Ge% 3). According to some embodiments, the third concentration level of the third interface may be a maximum level of the third germanium concentration level (Ge% 3). max ) relative to the maximum level of the first germanium concentration level (Ge% 1 max ), which can be expressed as Ge%3 max / Ge%1 max , and can be between about 1:1 and about 4:1. However, any suitable ratio can be used. In addition, the concentration level at the third interface can be continuous or discontinuous.

[0109] exist Fig.19In the illustrated embodiment, the first epitaxial growth layer 1201a is formed into a rhombus shape with a flat top and merged together instead of being kept separate. In some embodiments, the first epitaxial growth layer 1201a is formed using a fourth timed deposition process in a time period between about 50 seconds and about 200 seconds. However, any suitable time period may be used. According to some embodiments, the first epitaxial growth layer 1201a is formed on the fin 103 to a fourth height H4, which is between about 20nm and about 50nm. However, any suitable height may be used. In addition, the second epitaxial growth layer 1201b is also formed into a rhombus shape and has a flat top. In some embodiments, the second epitaxial growth layer 1201b is formed using a fifth timed deposition process in a time period between about 10 seconds and about 100 seconds. However, any suitable time period may be used. In some embodiments, the second epitaxial growth layer 1201b is formed on the first epitaxial growth layer 1201a to a fifth height H5, which is between about 10nm and about 30nm. However, any suitable height may be used. As such, the multilayer source / drain region 1201 of the illustrated embodiment has a second multilayer concentration ratio, which can be a combined height of layers having a highest concentration ratio (e.g., Ge% 3) relative to a combined height of layers having a lowest concentration ratio (e.g., Ge% 1). According to some embodiments, the fifth height H5 is between about 0.1:1 and about 1.5:1 relative to the fourth height H4 (H5 / H4). As such, the second shared contact landing area 1901 is formed with a relatively large volume of material having the highest concentration ratio (e.g., Ge% 3).

[0110] Fig.19 Also shown is a second shared contact landing area 1901 of the multi-layer source / drain region 1201 according to some embodiments. The boundary of the second shared contact landing area 1901 is at Fig.19 The boundary of the second shared contact landing area 1901 includes a volume of high germanium concentration (Ge% 3) below the flat top of the merged second layer 1201b, down to the flat top of the merged first layer 1201a with low germanium concentration (Ge% 1). In this way, the second shared contact landing area 1901 provides a large volume landing area with low contact resistance for the ultimate formation of the source drain contact 1803.

[0111] Fig. 20 An enlarged view (not to scale) of a multi-layer source / drain region 1201 adjacent source / drain regions according to yet another embodiment is shown. Fig. 20 The embodiment shown is similar to Fig.19 However, the first epitaxial growth layer 1201a of the adjacent source / drain regions is only partially merged. Thus, according to yet another embodiment, Fig. 20 An embodiment includes a third shared contact landing area 2001.

[0112] exist Fig. 20 In the illustrated embodiment, the second epitaxial growth layer 1201b is formed with a third concentration ratio (Ge% 3) and fills the top volume of the multilayer source / drain region 1201 (on top of the first layer 1201a formed with the first concentration ratio (Ge% 1)). According to some embodiments, the first epitaxial growth layer 1201a is formed using a sixth timed deposition process in a time period between about 50 seconds and about 200 seconds. In this way, the first epitaxial growth layer 1201a is formed over the fin 103 to a sixth height (H6). According to some embodiments, the first epitaxial growth layer 1201a is formed over the fin 103 to a sixth height H6, which is between about 20nm and about 50nm. However, any suitable height may be used. However, any suitable time period and any suitable height may be used. In addition, according to some embodiments, the second epitaxial growth layer 1201b is formed using a seventh timed deposition process in a time period between about 10 seconds and about 100 seconds. Thus, the second epitaxial growth layer 1201b is formed over the first epitaxial growth layer 1201a to a seventh height (H7). In some embodiments, the second epitaxial growth layer 1201b is formed over the first epitaxial growth layer 1201a to a seventh height H7 between about 10 nm and about 30 nm. However, any suitable time period and any suitable height may be used. Thus, the multilayer source / drain region 1201 of the illustrated embodiment includes a second multilayer concentration ratio (H7 / H6) between about 0.1:1 and about 1.5:1. Thus, the third shared contact landing area 2001 is formed with a relatively large volume of material having the highest concentration ratio (e.g., Ge%3).

[0113] The third shared contact landing area 2001 also includes a deep extension region of high germanium concentration (Ge% 3) material formed between the unmerged portions of the first epitaxial growth layer 1201a. The boundary of the third shared contact landing area 2001 is at Fig. 20. The third shared contact landing area 2001 includes a volume with a high germanium concentration (Ge% 3) below the flat top of the merged second layer 1201b, down to and including the volume between the sidewalls of the partially merged first layer 1201a. The third shared contact landing area 2001 extends to a second depth D2 above the partially merged first layer 1201a. According to some embodiments, the second depth D2 is between about 10nm and about 50nm. However, any suitable depth may be used. In addition, the third shared contact landing area 2001 has a third width W3 between the top of the first epitaxial growth layer 1201a. According to some embodiments, the third width W3 is between about 15nm and about 30nm. However, any suitable width may be used. In this way, embodiments of the third shared contact landing area 2001 provide a large volume landing area with a deep extension area having a low contact resistance for ultimately forming a source drain contact 1803.

[0114] Fig.21 FIG. 1 is an enlarged view (not to scale) of a multi-layer source / drain region 1201 adjacent to a source / drain region according to yet another embodiment. Fig.21 The embodiment shown is similar to Fig. 20 The embodiment shown; however, the first epitaxial growth layer 1201a of the adjacent source / drain region is formed to an eighth height H8, and the first epitaxial growth layer 1201a remains separated. According to some embodiments, the first epitaxial growth layer 1201a is formed using an eighth timed deposition process in a time period between about 50 seconds and about 100 seconds. In this way, the first epitaxial growth layer 1201a is formed above the fin 103 to an eighth height (H8), and the eighth height (H8) is between about 20nm and about 50nm. However, any suitable time period and height may be used. In addition, according to some embodiments, the second epitaxial growth layer 1201b is formed using a ninth timed deposition process in a time period between about 30 seconds and about 100 seconds. Therefore, the second epitaxial growth layer 1201b of the adjacent source / drain region is formed above the first epitaxial growth layer 1201a to a ninth height H9 and fills the top volume of the multilayer source / drain region 1201. According to some embodiments, the ninth height H9 is between about 10nm and about 30nm. However, any suitable time period and height may be used. Thus, the multilayer source / drain region 1201 of the illustrated embodiment includes a third multilayer concentration ratio (H9 / H8) between about 0.1:1 and about 1.5:1. In addition, according to yet another embodiment, the multilayer source / drain region 1201 of the illustrated embodiment includes a fourth shared contact landing region 2101 formed with a relatively large volume of material having a highest concentration ratio (e.g., Ge% 3).

[0115] The fourth shared contact landing area 2101 includes a very deep extension area of ​​high concentration germanium (Ge% 3) material formed between the first epitaxial growth layer 1201a. The boundary of the fourth shared contact landing area 2101 is at Fig.21 . The fourth shared contact landing area 2101 includes a volume of high concentration germanium (Ge% 3) below the flat top of the merged second layer 1201b, down to and including the volume between the sidewalls of the first epitaxial growth layer 1201a. The fourth shared contact landing area 2101 extends to a third depth D3 along the centerline between the first epitaxial growth layers 1201a toward the bottom of the second epitaxial growth layer 1201b. According to some embodiments, the third depth D3 is between about 30nm and about 50nm. However, any suitable depth may be used. In addition, the fourth shared contact landing area 2101 has a fourth width W4 between the tops of the first epitaxial growth layers 1201a. According to some embodiments, the fourth width W4 is between about 15nm and about 30nm. However, any suitable width may be used. In addition, the fourth shared contact landing area 2101 has a fifth width W5, which is the minimum distance between the sidewalls of the first epitaxial growth layer 1201a. According to some embodiments, the fifth width W5 is between about 0 nm and about 30 nm. However, any suitable width may be used. Thus, embodiments of the fourth shared contact landing area 2101 provide a large volume landing area with a very deep extension area with low contact resistance for ultimately forming a source drain contact 1803.

[0116] Fig. 22 is an enlarged view (not to scale) of a multi-layer source / drain region 1201 adjacent to a source / drain region according to another embodiment. Fig. 22 The multi-layer source / drain region 1201 shown includes a second epitaxial growth layer 1201b, which is formed to have an eleventh height H11 with a third concentration ratio (Ge% 3) and is formed to fill the top volume of the multi-layer source / drain region 1201 (above the first epitaxial growth layer 1201a (which is formed to have a tenth height H10 with a first concentration ratio (Ge% 1))). According to some embodiments, the first epitaxial growth layer 1201a is formed above the fin 103 to a tenth height H10, which is between about 20nm and about 50nm. However, any suitable height may be used. In some embodiments, the second epitaxial growth layer 1201b is formed above the first epitaxial growth layer 1201a to an eleventh height H11, which is between about 10m and about 30nm. Fig. 22 The embodiment shown is similar to Fig. 20The embodiment shown; however, the first epitaxial growth layer 1201a remains separated, and the first epitaxial growth layer 1201a is formed into a circle rather than a rhombus. According to some embodiments, the first epitaxial growth layer 1201a can be formed into a circle by adjusting the first precursor, the second precursor and / or the etching precursor during the formation when the epitaxial growth is shaped using appropriate multi-cycle deposition and etching steps. According to some embodiments, the first epitaxial growth layer 1201a is formed in a time period between about 50 seconds and about 100 seconds using the tenth timing deposition process. In this way, the first epitaxial growth layer 1201a is formed above the fin 103 to the tenth height H10. However, any suitable time period and any suitable height can be used. In addition, according to some embodiments, the second epitaxial growth layer 1201b is formed in a time period between about 30 seconds and about 100 seconds using the eleventh timing deposition process. Therefore, the second epitaxial growth layer 1201b is formed above the first epitaxial growth layer 1201a to the eleventh height H11. However, any suitable time period and any suitable height may be used. Thus, the multilayer source / drain region 1201 of the illustrated embodiment includes a third multilayer concentration ratio (H11 / H10) between about 0.1:1 and about 1.5:1. In addition, according to another embodiment, the multilayer source / drain region 1201 of the illustrated embodiment includes a fourth shared contact landing region 2101 formed with a relatively large volume of material having a highest concentration ratio (e.g., Ge% 3).

[0117] According to another embodiment, Fig. 22 The multilayer source / drain region 1201 of the illustrated embodiment includes a fifth shared contact landing area 2201 of high germanium concentration (Ge% 3) material. The fifth shared contact landing area 2201 includes a very deep and wide extension of high concentration germanium (Ge% 3) material formed between the first epitaxial growth layers 1201a. The boundary of the fifth shared contact landing area 2201 is at Fig. 22. The fifth shared contact landing area 2201 includes a volume with a high germanium concentration (Ge% 3) below the flat top of the merged second layer 1201b, down to and including the volume between the sidewalls of the first epitaxial growth layer 1201a. The fifth shared contact landing area 2201 extends to a fourth depth D4 along the centerline between the second epitaxial growth layers 1201b to the bottom of the second epitaxial growth layer 1201b. The fifth shared contact landing area 2201 extends to a fourth depth D4 along the centerline between the first epitaxial growth layers 1201a from the top of the second epitaxial growth layer 1201b to the bottom of the second epitaxial growth layer 1201b. According to some embodiments, the fourth depth D4 is between about 30nm and about 50nm. However, any suitable depth may be used. Due to the rounded shape of the first epitaxial growth layer 1201a, this very deep extension area is also relatively wide. In accordance with some embodiments, the fifth shared contact landing area 2201 has a sixth width W6 between the top of the first epitaxial growth layer 1201a. In accordance with some embodiments, the sixth width W6 is between about 15nm and about 30nm. However, any suitable width can be used. In addition, the minimum width between the first epitaxial growth layer 1201a is a seventh width W7 between about 0nm and about 30nm. However, any suitable width can be used. In this way, an embodiment of the fifth shared contact landing area 2201 provides a large volume landing area with a very deep and wide extension area, which has a low contact resistance for ultimately forming a source drain contact 1803.

[0118] Fig.23 FIG. 1 is an enlarged view (not to scale) of a multi-layer source / drain region 1201 adjacent to a source / drain region according to yet another embodiment. Fig.23 The multilayer source / drain region 1201 shown includes a second epitaxial growth layer 1201b, which is formed to have a thirteenth height H13 of a third concentration ratio (Ge%3), and is formed to fill the top volume of the multilayer source / drain region 1201 above the first epitaxial growth layer 1201a (which is formed to have a twelfth height H12 of the first concentration ratio (Ge%1)). According to some embodiments, the first epitaxial growth layer 1201a is formed above the fin 103 to a twelfth height H12 between about 20nm and about 50nm. However, any suitable height may be used. In some embodiments, the second epitaxial growth layer 1201b is formed above the first epitaxial growth layer 1201a to a thirteenth height H13 between about 10nm and about 30nm. Fig.23 The embodiment shown is similar to Fig. 22 the embodiment shown; however, the first epitaxial growth layer 1201a is formed in a rectangular shape instead of a circular shape.

[0119] According to some embodiments, the first epitaxial growth layer 1201a can be formed by using appropriate mask and etching techniques and / or adjusting the flow rate of the etching precursor during deposition to perform a substantially vertical etch of the first epitaxial growth layer 1201a. In some embodiments, the first epitaxial growth layer 1201a is formed as follows: a dielectric mask layer (e.g., an insulating material layer, an interlayer dielectric, a hard mask, etc.) is initially deposited over the fin 103 and planarized with the top of the fin 103 using a suitable planarization process (e.g., CMP). Once formed, the fin 103 is recessed to form the first opening 1001, as described above. In this way, the first opening 1001 is formed with an eighth width W8 between the sidewalls of the dielectric mask layer (not shown), the gate spacer 901, and / or the STI region 105. In such an embodiment, the first epitaxial growth layer 1201a may then be grown to fill and / or overfill the opening 1001, as described above, except that the growth of the first epitaxial growth layer 1201a is limited within the first opening 1001 by the sidewalls of the dielectric mask layer. Once formed, excess material of the first epitaxial growth layer 1201a is removed, and the top of the first epitaxial growth layer 1201a is planarized with the dielectric mask layer to a twelfth height H12. Once planarized, the dielectric mask layer may be removed using appropriate etching materials and techniques that are selective to the material of the mask layer and non-selective to the material of the first epitaxial growth layer 1201a. In this way, the first epitaxial growth layer 1201a is formed into a square or rectangular shape having an eighth width W8, and above the fin 103 to the twelfth height H12, and the sidewalls of the first epitaxial growth layer 1201a above the spacer 901 are exposed for further processing.

[0120] According to some embodiments, the first epitaxial growth layer 1201a is formed to an eighth width W8 between about 1nm and about 15nm. However, any suitable width may be used. In some embodiments, the eighth width W8 is substantially the same as the width of the fin 103. In addition, according to some embodiments, the first epitaxial growth layer 1201a is formed using a twelfth timing deposition process in a time period between about 10 seconds and about 100 seconds. In this way, the first epitaxial growth layer 1201a is formed on the fin 103 to a twelfth height H12. However, any suitable time period and any suitable height may be used. In addition, according to some embodiments, the second epitaxial growth layer 1201b is formed using a thirteenth timing deposition process in a time period between about 50 seconds and about 200 seconds. Therefore, the second epitaxial growth layer 1201b is formed on the first epitaxial growth layer 1201a to a thirteenth height H13. However, any suitable time period and any suitable height may be used. Thus, the multilayer source / drain region 1201 of the illustrated embodiment includes a fourth multilayer concentration ratio (H13 / H12) between about 0.1:1 and about 1.5:1. In addition, according to yet another embodiment, the multilayer source / drain region 1201 in the illustrated embodiment includes a sixth shared contact landing area 2301 formed with a relatively large volume of material having a highest concentration ratio (e.g., Ge%3). The sixth shared contact landing area 2301 includes a very deep and very wide extension area of ​​high concentration germanium (Ge%3) material formed between the first epitaxial growth layers 1201a. The boundary of the sixth shared contact landing area 2301 is at Fig.23 . The sixth shared contact landing area 2301 includes a volume of high germanium concentration (Ge% 3) below the flat top of the merged second layer 1201b, down to and including the volume between the sidewalls of the first epitaxial growth layer 1201a. The sixth shared contact landing area 2301 extends to a fourth depth D4 along the centerline between the first epitaxial growth layers 1201a, from the top of the second epitaxial growth layer 1201b to the bottom of the second epitaxial growth layer 1201b. Due to the rectangular shape of the first epitaxial growth layer 1201a, this very deep extension area is also very wide. According to some embodiments, the minimum width of the high concentration germanium (Ge% 3) between the first epitaxial growth layers 1201a can be a ninth width W9 between about 10nm and about 50nm. However, any suitable width may be used. Thus, embodiments of the sixth shared contact landing area 2301 provide a high volume landing area with a very deep and very wide extension area that also has a low contact resistance for ultimately forming the source drain contact 1803 .

[0121] Fig.24 FIG. 1 is an enlarged view (not to scale) of a multi-layer source / drain region 1201 adjacent to a source / drain region according to yet another embodiment. Fig.24The multilayer source / drain region 1201 shown includes a second epitaxial growth layer 1201b, which is formed to have a fifteenth height H15 of a third concentration ratio (Ge% 3) and is formed above the first epitaxial growth layer 1201a (which is formed to have a fourteenth height H14 of a first concentration ratio (Ge% 1)). According to some embodiments, the first epitaxial growth layer 1201a is formed above the fin 103 to a fourteenth height H14, which is between about 20nm and about 50nm. However, any suitable height may be used. In some embodiments, the second epitaxial growth layer 1201b is formed above the first epitaxial growth layer 1201a to a fifteenth height H15, which is between about 10nm and about 30nm. Fig.24 The embodiment shown is similar to Fig.23 The embodiment shown; however, Fig.23 Compared with the embodiment of the present invention, the first epitaxial growth layer 1201a is formed into a very wide rectangle. According to some embodiments, the same method as described above can be used. Fig.23Similar mask and etching techniques discussed for forming a square shape and / or adjusting the etching precursor during formation to form a rectangular shape of the first epitaxial growth layer 1201a. In some embodiments, the first epitaxial growth layer 1201a may be formed to a tenth width W10 between about 10nm and about 30nm. However, any suitable width may be used. In addition, the first epitaxial growth layer 1201a may be shaped to have an undercut feature between the second epitaxial growth layer 1201b and the gate spacer 901. The undercut feature may be formed by adjusting (e.g., between about 10% and about 30%) the precursor of the low concentration material (e.g., Ge%1) used to grow the first epitaxial growth layer 1201a. According to some embodiments, the tenth width W10 is much wider than the width of the fin 103. According to some embodiments, the first epitaxial growth layer 1201a is formed using a fourteenth timed deposition process over a time period between about 10 seconds and about 200 seconds. Thus, the first epitaxial growth layer 1201a is formed on the fin 103 to a fourteenth height H14. However, any suitable time period and any suitable height may be used. In addition, according to some embodiments, the second epitaxial growth layer 1201b is formed using a fifteenth timed deposition process in a time period between about 50 seconds and about 100 seconds. Therefore, the second epitaxial growth layer 1201b is formed on the first epitaxial growth layer 1201a to a fifteenth height H15. However, any suitable time period and any suitable height may be used. Thus, the multilayer source / drain region 1201 of the illustrated embodiment includes a fifth multilayer concentration ratio (H15 / H14) between about 0.1:1 and about 1.5:1. In addition, according to another embodiment, the multilayer source / drain region 1201 in the illustrated embodiment includes a seventh shared contact landing area 2401, which is formed with a relatively large volume of material having a highest concentration ratio (e.g., Ge%3).

[0122] The seventh shared contact landing area 2401 includes a very wide upper portion of a high germanium concentration (Ge% 3) material below the flat top of the merged second layer 1201b and a very deep and narrow extension of a high germanium concentration (Ge% 3) material formed between the first epitaxial growth layers 1201a. The boundary of the seventh shared contact landing area 2401 is at Fig.24The seventh shared contact landing area 2401 includes a volume with a high germanium concentration (Ge% 3) below the flat top of the merged second layer 1201b, angled downward to and including the volume between the sidewalls of the first epitaxial growth layer 1201a. The seventh shared contact landing area 2401 extends along the centerline between the first epitaxial growth layers 1201a, from the top of the second epitaxial growth layer 1201b to the bottom of the second epitaxial growth layer 1201b to a fourth depth D4. Due to the wide rectangular shape of the first epitaxial growth layer 1201a, the seventh shared contact landing area 2401 is substantially parallel to the first epitaxial growth layer 1201a. Fig.23 Compared to the embodiments of the present invention, the very deep extension area is also narrower. According to some embodiments, the minimum width of the high germanium concentration (Ge% 3) between the first epitaxial growth layer 1201a can be an eleventh width W11 between about 5nm and about 20nm. However, any suitable width can be used. In this way, the embodiment of the seventh shared contact landing area 2401 provides a large volume landing area with a very deep but narrow extension area, and also has a low contact resistance for ultimately forming the source drain contact 1803.

[0123] According to the disclosed embodiments, these structures and material compositions allow for low contact resistance (Rcsd) design of multi-layer source / drain regions 1201 for PMOS devices (e.g., EDX at P-FET I / O regions). Specifically, a shared contact landing region 1203 (e.g., a bulk MD landing region) having a relatively high germanium concentration percentage (Ge%3) (which has a lower bandgap than silicon) allows for the design of multi-layer source / drain regions 1201 with low Schottky barrier height (SBH) and low contact resistance (Rcsd). Rp resistivity is a measure of the resistivity between the p-type doped epitaxial material of the third epitaxial growth layer 1201c and the metal material of the source drain contact 1803. According to some embodiments, the multi-layer source / drain region 1201 has a reduced Rp resistivity (e.g., -0.2k). In addition, the Rch resistivity represents the channel region 805 ( Fig.18BAccording to some embodiments, the multi-layer source / drain region 1201 has a reduced Rch resistivity (e.g., -0.2k). According to embodiments disclosed herein, the reduction in Rp resistivity and / or the reduction in Rch resistivity provide the second FinFET 1800 with the additional benefit of a +4% DC gain and / or a +2% RO performance gain. In embodiments where an intermediate epitaxial growth layer (e.g., the second epitaxial growth layer 1201b) is formed, the intermediate epitaxial growth layer prevents strain relaxation of the third epitaxial growth layer 1201c due to a high lattice mismatch between the epitaxial growth layers separated by the intermediate epitaxial growth layer (e.g., the first epitaxial growth layer 1201a and the third epitaxial growth layer 1201c). In addition, the third epitaxial growth layer 1201c provides a low contact resistance between the multi-layer source / drain region 1201 and a subsequently formed metal contact.

[0124] The disclosed FinFET embodiments may also be applied to nanostructured devices, for example, nanostructured (e.g., nanosheets, nanowires, gate all around, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. The dummy gate stack and source / drain regions are formed in a manner similar to the above-described embodiments. After removing the dummy gate stack, the sacrificial layer may be partially or completely removed in the channel region. A replacement gate structure is formed in a manner similar to the above-described embodiments, the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. An interlayer dielectric (ILD) and contacts to the replacement gate structure and source / drain regions may be formed in a manner similar to the above-described embodiments. Nanostructured devices may be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0125] According to one embodiment, a method includes: forming a first fin in a substrate; forming a first source / drain region to a first height above the first fin, the first source / drain region including a first germanium concentration; and forming a top layer to a second height above the first source / drain region, the top layer including a second germanium concentration, the second germanium concentration being greater than the first germanium concentration, and the second height being greater than 1 nm. In one embodiment, the method also includes: forming a second fin in the substrate; forming a second source / drain region to a first height above the second fin, the second source / drain region including the first germanium concentration; and wherein forming the top layer also includes: forming the top layer to the second height above the second source / drain region. In one embodiment of the method, forming the top layer also includes: filling a gap between the first source / drain region and the second source / drain region with the top layer. In one embodiment of the method, the second source / drain region is at least partially merged with the first source / drain region. In an embodiment of the method, the second source / drain region is not merged with the first source / drain region. In one embodiment of the method, the first germanium concentration is less than 50% by volume. In one embodiment of the method, the second germanium concentration is 100% by volume.

[0126] In another embodiment, a method includes placing a wafer in a deposition chamber, the wafer including a fin; introducing a first precursor into the deposition chamber at a first flow rate; introducing a second precursor into the deposition chamber at a second flow rate, the first flow rate ratio being a ratio of the second flow rate to the first flow rate; using the first flow rate ratio for a first process time to form a source / drain region over the fin, the source / drain region including a first germanium concentration level; adjusting the first flow rate to a third flow rate and adjusting the second flow rate to a fourth flow rate, the second flow rate ratio being a ratio of the fourth flow rate to the third flow rate, the second flow rate ratio being greater than the first flow rate ratio; and using the second flow rate ratio for a second process time to form a contact landing region over the source / drain region to a first thickness, the first thickness being at least 1 nm, the contact landing region including a second germanium concentration level greater than the first germanium concentration level. In one embodiment, the first precursor includes a high-order silane precursor and the second precursor includes a germanium precursor. In one embodiment, the first germanium concentration level is less than 50% by volume of germanium. In one embodiment, the second germanium concentration level is at least 50% by volume of germanium. In one embodiment, the third flow rate is less than the first flow rate. In one embodiment, the fourth flow rate is greater than the second flow rate. In one embodiment, a third precursor is introduced into the deposition chamber, the third precursor comprising an n-type dopant. In one embodiment, the n-type dopant is diborane.

[0127] According to yet another embodiment, a semiconductor device includes: a first fin within a substrate; a second fin within the substrate and adjacent to the first fin; a first source / drain region above the first fin, wherein the first source / drain region includes a low germanium concentration; a second source / drain region above the second fin, wherein the second source / drain region includes a low germanium concentration; a contact landing region above the first source / drain region and the second source / drain region, the contact landing region including a high germanium concentration and having a first height of at least 1 nm above a top surface of the first source / drain region and the second source / drain region; and a source / drain contact, wherein at least a portion of the source / drain contact is embedded in the contact landing region. In one embodiment of the device, the low germanium concentration is less than 50% by volume of germanium. In one embodiment of the device, the high germanium concentration is greater than 50% by volume of germanium. In one embodiment of the device, the contact landing region includes an extension region located between sidewalls of the first source / drain region and the second source / drain region. In one embodiment of the device, the first source / drain region is at least partially merged with the second source / drain region.

[0128] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0129] Example 1 is a method for forming a semiconductor device, comprising: forming a first fin in a substrate; forming a first source / drain region to a first height above the first fin, the first source / drain region comprising a first germanium concentration; and forming a top layer to a second height above the first source / drain region, the top layer comprising a second germanium concentration, the second germanium concentration being greater than the first germanium concentration, and the second height being greater than 1 nm.

[0130] Example 2 is the method described in Example 1, further including: forming a second fin in the substrate; forming a second source / drain region above the second fin to the first height, the second source / drain region including the first germanium concentration; and wherein forming the top layer further includes: forming the top layer above the second source / drain region to the second height.

[0131] Example 3 is the method of Example 2, wherein forming the top layer further comprises: filling a gap between the first source / drain region and the second source / drain region with the top layer.

[0132] Example 4 is the method of Example 3, wherein the second source / drain region is at least partially merged with the first source / drain region.

[0133] Example 5 is the method of Example 3, wherein the second source / drain region is not merged with the first source / drain region.

[0134] Example 6 is the method of Example 1, wherein the first germanium concentration is less than 50%.

[0135] Example 7 is the method of Example 6, wherein the second germanium concentration is 100%.

[0136] Example 8 is a method for forming a semiconductor device, comprising: placing a wafer in a deposition chamber, the wafer comprising a fin; introducing a first precursor into the deposition chamber at a first flow rate; introducing a second precursor into the deposition chamber at a second flow rate, a first flow rate ratio being a ratio of the second flow rate to the first flow rate; using the first flow rate ratio for a first process time to form a source / drain region above the fin, the source / drain region comprising a first germanium concentration level; adjusting the first flow rate to a third flow rate and adjusting the second flow rate to a fourth flow rate, a second flow rate ratio being a ratio of the fourth flow rate to the third flow rate, the second flow rate ratio being greater than the first flow rate ratio; and using the second flow rate ratio for a second process time to form a contact landing area above the source / drain region to a first thickness, the first thickness being at least 1 nm, the contact landing area comprising a second germanium concentration level greater than the first germanium concentration level.

[0137] Example 9 is the method of Example 8, wherein the first precursor comprises a high-order silane precursor and the second precursor comprises a germanium precursor.

[0138] Example 10 is the method of Example 9, wherein the first germanium concentration level is less than 50% germanium by volume.

[0139] Example 11 is the method of Example 10, wherein the second germanium concentration level is at least 50% germanium by volume.

[0140] Example 12 is the method of Example 10, wherein the third flow rate is less than the first flow rate.

[0141] Example 13 is the method of Example 10, wherein the fourth flow rate is higher than the second flow rate.

[0142] Example 14 is the method of Example 8, further comprising: introducing a third precursor into the deposition chamber, the third precursor comprising an n-type dopant.

[0143] Example 15 is the method of Example 14, wherein the n-type dopant is diborane.

[0144] Example 16 is a semiconductor device comprising: a first fin within a substrate; a second fin within the substrate and adjacent to the first fin; a first source / drain region above the first fin, wherein the first source / drain region comprises a low germanium concentration; a second source / drain region above the second fin, wherein the second source / drain region comprises the low germanium concentration; a contact landing area above the first source / drain region and the second source / drain region, the contact landing area comprising a high germanium concentration and having a first height of at least 1 nm above a top surface of the first source / drain region and the second source / drain region; and a source / drain contact, wherein at least a portion of the source / drain contact contacts the contact landing area.

[0145] Example 17 is the semiconductor device of Example 16, wherein the low germanium concentration is less than 50% by volume of germanium.

[0146] Example 18 is the semiconductor device of Example 17, wherein the high germanium concentration is greater than 50% by volume of germanium.

[0147] Example 19 is the semiconductor device of Example 16, wherein the contact landing area includes an extension region between sidewalls of the first source / drain region and the second source / drain region.

[0148] Example 20 is the semiconductor device of Example 16, wherein the first source / drain region is at least partially merged with the second source / drain region.

Claims

1. A method for forming a semiconductor device, comprising: forming a first fin and a second fin in a substrate; forming a first source / drain region on the first fin to a first height, the first source / drain region comprising a first germanium concentration; forming a second source / drain region on the second fin to the first height, the second source / drain region comprising the first germanium concentration; and A top layer is formed over the first source / drain region and the second source / drain region to a second height, the top layer extending continuously from over the first fin to over the second fin, the top layer including a second germanium concentration greater than the first germanium concentration, and the second height greater than 1 nm.

2. The method according to claim 1, wherein: Forming the top layer further includes filling a gap between the first source / drain region and the second source / drain region with the top layer.

3. The method according to claim 2, wherein: The second source / drain region at least partially merges with the first source / drain region.

4. The method according to claim 2, wherein: The second source / drain region is not merged with the first source / drain region.

5. The method according to claim 1, wherein: The first germanium concentration is less than 50% by volume of germanium.

6. The method according to claim 5, wherein: The second germanium concentration is 100% by volume of germanium.

7. A method of forming a semiconductor device, comprising: placing a wafer in a deposition chamber, the wafer comprising a first fin and a second fin; introducing a first precursor into the deposition chamber at a first flow rate; introducing a second precursor into the deposition chamber at a second flow rate, the first flow rate ratio being a ratio of the second flow rate to the first flow rate; using the first flow rate ratio for a first process time to form a first source / drain region over the first fin and a second source / drain region over the second fin, the first source / drain region and the second source / drain region comprising a first germanium concentration level; adjusting the first flow rate to a third flow rate and adjusting the second flow rate to a fourth flow rate, a second flow rate ratio being a ratio of the fourth flow rate to the third flow rate, the second flow rate ratio being greater than the first flow rate ratio; and The second flow rate ratio is used for a second process time to form a contact landing area over the first source / drain region and the second source / drain region to a first thickness, the contact landing area extending continuously from over the first fin to over the second fin, the first thickness being at least 1 nm, the contact landing area including a second germanium concentration level greater than the first germanium concentration level.

8. The method according to claim 7, wherein: The first precursor includes a high-order silane precursor, and the second precursor includes a germanium precursor.

9. The method according to claim 8, wherein: The first germanium concentration level is less than 50% germanium by volume.

10. The method according to claim 9, wherein: The second germanium concentration level is at least 50% germanium by volume.

11. The method according to claim 9, wherein: The third flow rate is less than the first flow rate.

12. The method according to claim 9, wherein: The fourth flow rate is higher than the second flow rate.

13. The method according to claim 7, further comprising: A third precursor is introduced into the deposition chamber, the third precursor comprising an n-type dopant.

14. The method according to claim 13, wherein: The n-type dopant is diborane.

15. A semiconductor device comprising: a first fin, within the substrate; a second fin within the substrate and adjacent to the first fin; a first source / drain region overlying the first fin, wherein the first source / drain region comprises a low germanium concentration; a second source / drain region on the second fin, wherein the second source / drain region comprises the low germanium concentration; a contact landing region over the first source / drain region and the second source / drain region, the contact landing region extending continuously from over the first fin to over the second fin, the contact landing region comprising a high germanium concentration and having a first height of at least 1 nm over top surfaces of the first source / drain region and the second source / drain region; and A source / drain contact, wherein at least a portion of the source / drain contact contacts the contact landing area.

16. The semiconductor device according to claim 15, wherein: The low germanium concentration is less than 50% by volume of germanium.

17. The semiconductor device according to claim 16, wherein: The high germanium concentration is greater than 50% by volume of germanium.

18. The semiconductor device according to claim 15, wherein: The contact landing area includes an extension region between sidewalls of the first source / drain region and the second source / drain region.

19. The semiconductor device according to claim 15, wherein: The first source / drain region at least partially merges with the second source / drain region.

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