Semiconductor package including semiconductor chip having point-symmetric chip pads

Abstract

A semiconductor package including a semiconductor chip having point-symmetric chip pads. A semiconductor package according to one aspect of the present disclosure includes a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each of the semiconductor chips includes: a chip body; at least one first side power pad and at least one first side grounding pad arranged on a first side portion on one surface of the chip body; and at least one second side power pad and at least one second side grounding pad arranged on a second side portion opposite to the first side portion on one surface of the chip body. One of the second side power pads may be arranged point-symmetrically with respect to a reference point on the one surface and a corresponding one of the first side power pads, and one of the second side grounding pads may be arranged point-symmetrically with respect to a reference point on the one surface and a corresponding one of the first side grounding pads.

Description

Technical Field

[0001] The present disclosure relates generally to a semiconductor package, and more particularly, to a semiconductor chip having a chip pad with a point-symmetric structure and a semiconductor package including the semiconductor chip. Background Art

[0002] The semiconductor industry has developed to manufacture semiconductor products with light weight, small size, high speed, multi-function, high performance and high reliability at low cost, and one of the important technologies to achieve these requirements is semiconductor packaging technology. Semiconductor packaging technology is a technology for mounting a semiconductor chip having a circuit part formed by a wafer process on a packaging substrate, a technology for ensuring electrical connection between the semiconductor chip and external electronic devices through the packaging substrate, and a technology for protecting the semiconductor chip from the external environment.

[0003] As package products become lighter and shorter, research is being conducted on connection pads for electrically connecting a semiconductor chip to a package substrate. The research on the connection pads includes research on the design of the package substrate and the pads provided on the semiconductor chip. Summary of the invention

[0004] A semiconductor package according to one aspect of the present disclosure may include a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each semiconductor chip may include: a chip body; at least one first side power supply pad and at least one first side grounding pad disposed at a first side portion on one surface of the chip body; and at least one second side power supply pad and at least one second side grounding pad disposed at a second side portion opposite to the first side portion on the one surface of the chip body. One of the at least one second side power supply pad may be arranged point-symmetrically with respect to a reference point on the one surface of the chip body and a corresponding one of the at least one first side power supply pad, and one of the at least one second side grounding pad may be arranged point-symmetrically with respect to the reference point on the one surface of the chip body and a corresponding one of the at least one first side grounding pad.

[0005] According to another aspect of the present disclosure, a semiconductor package may include a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each semiconductor chip may include: a chip body; at least one first side power supply pad, at least one first side grounding pad, and at least one signal pad disposed at a first side portion on one surface of the chip body; and at least one second side power supply pad and at least one second side grounding pad disposed at a second side portion opposite to the first side portion on the one surface of the chip body. One of the at least one second side power supply pad may be arranged point-symmetrically with respect to a reference point on the one surface of the chip body and a corresponding one of the at least one first side power supply pad, and one of the at least one second side grounding pad may be arranged point-symmetrically with respect to a reference point on the one surface of the chip body and a corresponding one of the at least one first side grounding pad.

[0006] A semiconductor package according to another aspect of the present disclosure may include a package substrate, the package substrate including a first bonding finger array and a second bonding finger array spaced apart from each other and arranged in a row, respectively. In addition, the semiconductor package may include a lower semiconductor chip disposed between the first bonding finger array and the second bonding finger array, and an upper semiconductor chip disposed on the lower semiconductor chip. The lower semiconductor chip and the upper semiconductor chip have pad arrangements that are substantially the same as each other. Each semiconductor chip may include: a chip body; at least one first side power supply pad, at least one first side grounding pad, and at least one signal pad disposed at a first side portion on one surface of the chip body; and at least one second side power supply pad and at least one second side grounding pad disposed at a second side portion opposite to the first side portion on the one surface of the chip body. One of the at least one second side power supply pad may be arranged point-symmetrically with respect to a reference point on the one surface of the chip body and a corresponding one of the at least one first side power supply pad, and one of the at least one second side grounding pad may be arranged point-symmetrically with respect to the reference point on the one surface of the chip body and a corresponding one of the at least one first side grounding pad. The at least one first side power supply pad of the lower semiconductor chip and the at least one second side power supply pad of the upper semiconductor chip may be arranged to overlap each other, and the at least one first side grounding pad of the lower semiconductor chip and the at least one second side grounding pad of the upper semiconductor chip may be arranged to overlap each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1is a cross-sectional view schematically showing a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 2 is a plan view schematically showing a package substrate according to an embodiment of the present disclosure.

[0009] Figure 3 is a view schematically showing a first semiconductor chip according to an embodiment of the present disclosure.

[0010] Figure 4 is a view schematically showing a second semiconductor chip according to an embodiment of the present disclosure.

[0011] Figure 5 and Figure 6 is a view schematically showing electrical connection between a package substrate and a semiconductor chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The terms used herein may correspond to words selected in consideration of their functions in the presented embodiments, and the meaning of the terms may be interpreted as different meanings according to the ordinary technicians in the field of the embodiment. If specifically defined, these terms can be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meanings as those generally understood by the ordinary technicians in the field of the associated embodiment. In the description of the present disclosure, words such as "first" and "second" and "upper" and "lower" are used to distinguish components, and are not used to limit the components themselves by implying a specific number or order of elements.

[0013] Throughout the specification, the same reference numerals refer to the same elements. Even if a reference numeral is not indicated or described with reference to one figure, it may be indicated or described with reference to another figure. In addition, even if a reference numeral is not shown in one figure, it may be indicated or described with reference to another figure.

[0014] In the specification of the present disclosure, the semiconductor package is described using the orthogonal axes xyz of the right-handed Cartesian coordinate system. In this case, the x direction may refer to the direction parallel to the x axis. Similarly, the y direction and the z direction may refer to the direction parallel to the y axis and the direction parallel to the z axis, respectively.

[0015] Figure 1 Schematically shows a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. Figure 1, the semiconductor package 1 may include a package substrate 100 and a plurality of semiconductor chips 200 and 300 stacked on the package substrate 100. The plurality of semiconductor chips 200 and 300 may have substantially the same pad arrangement. As an example, the arrangement of the power pads, ground pads, and signal pads of the plurality of semiconductor chips 200 and 300 may be substantially the same. In one embodiment, the plurality of semiconductor chips 200 and 300 may be chips of the same type. The package substrate 100 and the semiconductor chips 200 and 300 may be electrically connected by bonding wires 401, 402, 403, and 404.

[0016] The package substrate 100 may have a substrate body 110. The substrate body 110 may have a first surface 110S1 and a second surface 110S2 opposite to the first surface 110S1.

[0017] The first bonding finger array 120a and the second bonding finger array 120b can be arranged on the first surface 110S1 of the substrate body 110. The first bonding finger array 120a and the second bonding finger array 120b can each include a plurality of bonding fingers (not shown) for wire bonding with the semiconductor chips 200 and 300. The plurality of bonding fingers can include power fingers, ground fingers, and signal fingers. The first bonding finger array 120a can be arranged on the first side 110E1 of the substrate body 110. The second bonding finger array 120b can be arranged on the second side 110E2 of the substrate body 110. The following will use Figure 2 The arrangement of the plurality of bonding fingers of the first bonding finger array 120a and the second bonding finger array 120b is described with reference to a plan view of FIG.

[0018] The first connection structure 130a and the second connection structure 130b may be disposed on the second surface 110S2 of the substrate body 110. The first connection structure 130a and the second connection structure 130b may be connected to an external printed circuit board or an external electronic system. Through the first connection structure 130a and the second connection structure 130b, power may be provided from the external printed circuit board or the electronic system to the package substrate 100, or the package substrate 100 may exchange electrical signals with the external printed circuit board or the electronic system. Figure 1 , the numbers of the first connection structures 130a and the second connection structures 130b are respectively shown as four, but are not limited thereto, and various other modifications are possible.

[0019] The first connection structure 130a and the second connection structure 130b may receive electrical signals distinguished from each other from an external printed circuit board or an electronic system. That is, an electrical signal received through any one of the first connection structures 130a may be sent to a corresponding one of the signal fingers of the first bonding finger array 120a through the first internal wirings 112a1, 112a2, and 112a3. In addition, an electrical signal received through any one of the second connection structures 130b may be sent to a corresponding one of the signal fingers of the second bonding finger array 120b through the second internal wirings 112b1, 112b2, and 112b3. That is, the electrical signal path from the first connection structure 130a to the signal fingers of the first bonding finger array 120a and the electrical signal path from the second connection structure 130b to the signal fingers of the second bonding finger array 120b may be independent of each other. The first internal wirings 112a1, 112a2, 112a3 and the second internal wirings 112b1, 112b2 and 112b3 may include first blind vias 112a1 and 112b1, internal circuit layers 11a2 and 112b2, and second blind vias 112a3 and 112b3.

[0020] Reference Figure 1 , discloses a plurality of semiconductor chips 200 and 300, wherein a lower semiconductor chip 220 is disposed on a package substrate 100, and an upper semiconductor chip 300 is disposed on the lower semiconductor chip 200. The package substrate 100 and the lower semiconductor chip 200 may be combined by a first adhesive layer 510. The lower semiconductor chip 200 and the upper semiconductor chip 300 may be combined by a second adhesive layer 520. The first adhesive layer 510 and the second adhesive layer 520 may each include, for example, a non-conductive paste or a non-conductive film.

[0021] The lower semiconductor chip 200 may have a chip body 210. The chip body 210 may have a first surface 210S1 and a second surface 210S2 opposite to the first surface 210S1. A first chip pad 220a and a second chip pad 220b may be disposed on the first surface 210S1 of the chip body 210. The first chip pad 220a and the second chip pad 220b may be used as connection pads for wire bonding with the package substrate 100. The first chip pad 220a may be disposed on the first side 210E1 of the chip body 210. The second chip pad 220b may be disposed on the second side 210E2 of the chip body 210. In one embodiment, the first chip pad 220a and the second chip pad 220b may each include, for example, a power pad and a ground pad. In addition, any one of the first chip pad 220a and the second chip pad 220b may also include a signal pad. As an example, Figure 3As shown in the plan view in FIG. 1 , the first chip pad 220a may have a power pad, a ground pad and a signal pad, and the second chip pad 220b may have a power pad and a ground pad. Figure 3 The plan view of FIG. 1 describes in detail the pad arrangement of the first chip pad 220 a and the second chip pad 220 b.

[0022] Meanwhile, the first chip pad 220 a and the second chip pad 220 b may be connected to corresponding fingers of the first bonding finger array 120 a and the second bonding finger array 120 b through the first bonding wire 401 and the second bonding wire 402 , respectively.

[0023] Reference Figure 1 , the upper semiconductor chip 300 may be stacked on the lower semiconductor chip 200. The upper semiconductor chip 300 and the lower semiconductor chip 200 may have substantially the same pad arrangement. As an example, the arrangement of the power pads, ground pads, and signal pads of the upper semiconductor chip 300 and the lower semiconductor chip 200 may be substantially the same as each other. In one embodiment, the upper semiconductor chip 300 may be the same type of chip as the lower semiconductor chip 200. As an example, the configuration of the upper semiconductor chip 300 may be substantially the same as the configuration of the lower semiconductor chip 200. In one embodiment, the upper semiconductor chip 300 may be arranged to overlap with the lower semiconductor chip 200. At this time, the first side 310E1 of the upper semiconductor chip 300 and the second side 210E2 of the lower semiconductor chip 200 may overlap, and the second side 310E2 of the upper semiconductor chip 300 and the first side 210E1 of the lower semiconductor chip 200 may overlap. In other words, as described later in conjunction with Figure 6 As described, when the upper semiconductor chip 300 is stacked on the lower semiconductor chip 200 , the upper semiconductor chip 300 may be stacked while being rotated 180° with respect to the center point C200 of the lower semiconductor chip 200 .

[0024] The upper semiconductor chip 300 may have a chip body 310. The chip body 310 may have a first surface 310S1 and a second surface 310S2 opposite to the first surface 310S1. A first chip pad 320a and a second chip pad 320b may be disposed on the first surface 310S1 of the chip body 310. The first chip pad 320a and the second chip pad 320b may be used as connection pads for wire bonding with the package substrate 100. The first chip pad 320a may be disposed on the first side 310E1 of the chip body 310. The second chip pad 320b may be disposed on the second side 310E2. In one embodiment, the first chip pad 320a and the second chip pad 320b may each include, for example, a power pad and a ground pad. In addition, any one of the first chip pad 320a and the second chip pad 320b may also include a signal pad. As an example, Figure 4 As shown in the plan view in FIG. 1 , the first chip pad 320a may have a power pad, a ground pad and a signal pad, and the second chip pad 320b may have a power pad and a ground pad. Figure 4 The plan view of FIG. 1 describes in detail the pad arrangement of the first chip pad 320 a and the second chip pad 320 b.

[0025] The first chip pad 320a may be connected to a corresponding finger in the second bonding finger array 120b via a fourth bonding wire 404. Similarly, the second chip pad 320b may be connected to a corresponding finger in the first bonding finger array 120a via a third bonding wire 403.

[0026] Figure 2 is a plan view schematically showing a package substrate according to an embodiment of the present disclosure. Figure 2 The package substrate 100 shown may be Figure 1 The semiconductor package 1 is provided with a package substrate 100. Figure 1 and Figure 2 , the package substrate 100 may include a substrate body 110 having a first surface 110S1 and a second surface 110S2 opposite to the first surface 110S1. The substrate body 110 may have a length L1 along the x direction and a width W1 along the y direction. In addition, the package substrate 100 may have a central axis CX extending at 1 / 2 of the length L1 in the y direction.

[0027] The first bonding finger array 120a and the second bonding finger array 120b may be disposed on the first surface 110S1 of the substrate body 110. The first bonding finger array 120a may be disposed on the first side 110E1 of the substrate body 110, and the second bonding finger array 120b may be disposed on the second side 110E2 of the substrate body 110. The first side 110E1 and the second side 110E2 may be located outside the semiconductor chip mounting region 100A, in which the lower semiconductor chip 200 is disposed. The positions of the first side 110E1 and the second side 110E2 may be opposite to each other based on the semiconductor chip mounting region 100A. As shown in the following combination Figure 3 and Figure 5 As described, the first side 110E1 of the substrate body 110 may be disposed adjacent to the first side 210E1 of the lower semiconductor chip 200 , and the second side 110E2 of the substrate body 110 may be disposed adjacent to the second side 210E2 of the lower semiconductor chip 200 .

[0028] In one embodiment, the first bonding finger array 120a may include two power fingers 120aP1 and 120aP2, two ground fingers 120aG1 and 120aG2, and four signal fingers 120aS1, 120aS2, 120aS3, and 120aS4. The power fingers 120aP1 and 120aP2, the ground fingers 120aG1 and 120aG2, and the signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 may be arranged in a row LR110 along one direction (i.e., the y direction) at the first side 110E1. When the power fingers 120aP1 and 120aP2, the ground fingers 120aG1 and 120aG2, and the signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 are arranged in a row LR110, the fingers adjacent to each other may be spaced apart from each other by a predetermined distance d1 with respect to the y direction.

[0029] As a specific example, the first bonding finger array 120a may include a first side first power finger 120aP1, a first side first signal finger 120aS1, a first side first grounding finger 120aG1, a first side second signal finger 120aS2, a first side second power finger 120aP2, a first side third signal finger 120aS3, a first side second grounding finger 120aG2, and a first side fourth signal finger 120aS4 arranged sequentially along the y direction.

[0030] Meanwhile, the number of power fingers, the number of ground fingers, and the number of signal fingers of the first bonding finger array 120a may not necessarily be limited to the above numbers. In one embodiment, the number of power fingers, the number of ground fingers, and the number of signal fingers of the first bonding finger array 120a may be determined corresponding to the number of power pads, the number of ground pads, and the number of signal pads disposed on the lower semiconductor chip 200 and the upper semiconductor chip 300, as described below with reference to Figure 3 and Figure 4 described.

[0031] In addition, the arrangement order of the power fingers, ground fingers, and signal fingers of the first bonding finger array 120a may not necessarily be limited to the above order. The arrangement order of the power fingers, ground fingers, and signal fingers of the first bonding finger array 120a may be determined corresponding to the arrangement order of the power pads, ground pads, and signal pads disposed on the lower semiconductor chip 200 and the upper semiconductor chip 300, as described below with reference to Figures 3 to 6 described.

[0032] Meanwhile, the second bonding finger array 120b may include two power fingers 120bP1 and 120bP2, two ground fingers 120bG1 and 120bG2, and four signal fingers 120bS1, 120bS2, 120bS3, and 120bS4. The power fingers 120bP1 and 120bP2, the ground fingers 120bG1 and 120bG2, and the signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 may be arranged in a row RR110 along one direction (i.e., the y direction) at the second side 110E2. When the power fingers 120bP1 and 120bP2 , the ground fingers 120bG1 and 120bG2 , and the signal fingers 120bS1 , 120bS2 , 120bS3 , and 120bS4 are arranged in a row RR110 , the fingers adjacent to each other may be spaced apart from each other by a predetermined distance d1 with respect to the y direction.

[0033] As a specific example, the second bonding finger array 120b may include a second side fourth signal finger 120bS4, a second side second grounding finger 120bG2, a third side third signal finger 120bS3, a second side second power finger 120bP2, a second side second signal finger 120bS2, a second side first grounding finger 120bG1, a second side first signal finger 120bS1, and a second side first power finger 120bP1 arranged sequentially along the y direction.

[0034] Meanwhile, the number of power fingers, the number of ground fingers, and the number of signal fingers of the second bonding finger array 120b may not necessarily be limited to the above numbers. In one embodiment, the number of power fingers, the number of ground fingers, and the number of signal fingers of the second bonding finger array 120b may be determined corresponding to the number of power pads, the number of ground pads, and the number of signal pads disposed on the lower semiconductor chip 200 and the upper semiconductor chip 300, as described below with reference to Figure 3 and Figure 4 described.

[0035] In addition, the arrangement order of the power fingers, ground fingers, and signal fingers of the second bonding finger array 120b may not necessarily be limited to the above order. The arrangement order of the power fingers, ground fingers, and signal fingers of the second bonding finger array 120b may be determined corresponding to the arrangement order of the power pads, ground pads, and signal pads disposed on the lower semiconductor chip 200 and the upper semiconductor chip 300, as described below with reference to Figures 3 to 6 described.

[0036] In one embodiment, the positions of the fingers aligned in the y-direction of the first bonding finger array 120 a and the positions of the fingers aligned in the y-direction of the second bonding finger array 120 b may be symmetrical to each other about the central axis CX.

[0037] In one embodiment, the signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 of the first bonding finger array 120a may be electrically separated from the signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 of the second bonding finger array 120b. In other words, the signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 of the first bonding finger array 120a and the signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 of the second bonding finger array 120b may constitute independent signal paths that are distinguishable from each other. In one embodiment, referring back to FIG. Figure 1 The signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 of the first bonding finger array 120a may be connected to the first connection structure 130a through the first internal wirings 112a1, 112a2, and 112a3. The signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 of the second bonding finger array 120b may be connected to the second connection structure 130b through the second internal wirings 112b1, 112b2, and 112b3.

[0038] As referenced later Figure 5 and Figure 6As described, the signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 of the first bonding finger array 120a may be connected to the signal pads 220aS1, 220aS2, 220aS3, and 220aS4 of the lower semiconductor chip 200. On the other hand, the signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 of the second bonding finger array 120b may be connected to the signal pads 320aS1, 320aS2, 320aS3, and 320aS4 of the upper semiconductor chip 300. That is, the data signal and the address command signal for the lower semiconductor chip 200 may be transmitted through the signal fingers 120aS1, 120aS2, 120asS3, and 120aS4 of the first bonding finger array 120a. In addition, data signals and address command signals for the upper semiconductor chip 300 may be transmitted through the signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 of the second bonding finger array 120b. As a result, each of the lower semiconductor chip 200 and the upper semiconductor chip 300 may exchange electrical signals with the package substrate 100 through independent signal paths, respectively.

[0039] On the other hand, the power fingers 120aP1 and 120aP2 and the ground fingers 120aG1 and 120aG2 of the first bonding finger array 120a and the power fingers 120bP1 and 120bP2 and the ground fingers 120bG1 and 120bG2 of the second bonding finger array 120b may be shared by the lower semiconductor chip 200 and the upper semiconductor chip 300, as shown in the following combination. Figure 6 described.

[0040] Figure 3 Schematically illustrates a first semiconductor chip according to an embodiment of the present disclosure. Figure 3 The first semiconductor chip 200 may be the one described above with reference to Figure 1 The lower semiconductor chip 200 is described.

[0041] Reference Figure 1 and Figure 3 The first semiconductor chip 200 may include a chip body 210 , a first chip pad 220 a disposed at a first side 210E1 on a first surface 210S1 of the chip body 210 , and a second chip pad 220 b disposed at a second side 210E2 on the first surface 210S1 of the chip body 210 .

[0042] In one embodiment, the first chip pad 220a may include two power pads 220aP1 and 220aP2, two ground pads 220aG1 and 220aG2, and four signal pads 220aS1, 220aS2, 220aS3, and 220aS4. The power pads 220aP1 and 220aP2, the ground pads 220aG1 and 220aG2, and the signal pads 220aS1, 220aS2, 220aS3, and 220aS4 may be arranged in a row LR210 along one direction (i.e., the y direction) at the first side portion 210E1.

[0043] As a specific example, the first chip pad 220a may include a first side first power pad 220aP1, a first side first signal pad 220aS1, a first side first ground pad 220aG1, a first side second signal pad 220aS2, a first side second power pad 220aP2, a first side third signal pad 22aS3, a first side second ground pad 220aG2, and a first side fourth signal pad 220aS4 arranged sequentially along the y direction.

[0044] Meanwhile, the number of the first side power pads, the number of the first side ground pads, and the number of the first side signal pads of the first chip pad 220a may not necessarily be limited to the above numbers. In addition, the arrangement order of the first side power pads, the first side ground pads, and the first side signal pads of the first chip pad 220a may not necessarily be limited to the above order, and various modifications are possible.

[0045] In one embodiment, the second chip pad 220b may include two power pads 220bP1 and 220bP2 and two ground pads 220bG1 and 220bG2. The power pads 220bP1 and 220bP2 and the ground pads 220bG1 and 220bG2 may be arranged in a row RR210 along one direction (ie, y direction) at the second side 210E2.

[0046] As a specific example, the second chip pad 220b may include a second side second grounding pad 220bG2, a second side second power pad 220bP2, a second side first grounding pad 220bG1, and a second side first power pad 220bP1 sequentially arranged along the y direction. At the same time, the number of the second side power pads and the number of the second side grounding pads of the second chip pad 220b may be substantially the same as the number of the first side power pads and the number of the first side grounding pads of the first chip pad 220a. In addition, the second side power pad and the second side grounding pad may be arranged to correspond to the first side power pad and the first side grounding pad of the first chip pad 220a. When compared with the first chip pad 220a, the second chip pad 220b may not include a signal pad.

[0047] In one embodiment, any one of the second side power pads 220bP1 and 220bP2 may be arranged point-symmetrically with respect to a reference point C210 on the first surface 210S1 and a corresponding one of the first side power pads 220aP1 and 220aP2. Any one of the second side ground pads 220bG1 and 220bG2 may be arranged point-symmetrically with respect to a reference point C210 on the first surface 210S1 and a corresponding one of the first side ground pads 220aG1 and 220aG2. Here, the reference point C210 on the first surface 210S1 may be a center point of a shape of the chip body 210 projected onto the first surface 210S1. As an example, when the chip body 210 has a rectangular shape on the first surface 210S1, the center point may be an intersection of two diagonal lines connecting vertices facing each other in the rectangle.

[0048] As a specific example, the first side first power pad 220aP1 and the second side first power pad 220bP1 may be arranged point-symmetrically with respect to the reference point C210. ​​The first side second power pad 220aP2 and the second side second power pad 220bP2 may be arranged point-symmetrically with respect to the reference point C210. ​​The first side first ground pad 220aG1 and the second side first ground pad 220bG1 may be arranged point-symmetrically with respect to the reference point C210. ​​The first side second ground pad 220aG2 and the second side second ground pad 220bG2 may be arranged point-symmetrically with respect to the reference point C210.

[0049] In one embodiment, the first side first power pad 220aP1 and the second side first power pad 220bP1 may have the same shape. The first side second power pad 220aP2 and the second side second power pad 220bP2 may have the same shape. The first side first ground pad 220aG1 and the second side first ground pad 220bG1 may have the same shape. The first side second ground pad 220aG2 and the second side second ground pad 220bG2 may have the same shape.

[0050] In one embodiment, when the first side first power pad 220aP1 and the first side second power pad 220aP2, the first side first ground pad 220aG1 and the first side second ground pad 220aG2, and the first side first signal pad to the first side fourth signal pad 220aS1, 220aS2, 220aS3 and 220aS4 are arranged in a row LR210 to have Figure 3When the first power pad 220bP1 and the second power pad 220bP2 on the second side, and the first ground pad 220bG1 and the second ground pad 220bG2 on the second side are arranged in a row RR210 to have a predetermined distance d2, the power pads and the ground pads adjacent to each other can be spaced apart from each other by a predetermined distance d2 in the y direction. Figure 3 In the arrangement order shown, the power pads and ground pads adjacent to each other may be spaced apart from each other by a predetermined distance d2 in the y direction.

[0051] Figure 4 Schematically illustrates a second semiconductor chip according to an embodiment of the present disclosure. Figure 4 The second semiconductor chip 300 may be a Figure 1 The upper semiconductor chip 300 of the semiconductor package 1 is described. Figure 4 The second semiconductor chip 300 may be Figure 3 The first semiconductor chip 200 of the second semiconductor chip 300 may have substantially the same pad arrangement. That is, the arrangement of the power pads, ground pads, and signal pads of the second semiconductor chip 300 may be substantially the same as the arrangement of the first semiconductor chip 200. In one embodiment, the second semiconductor chip 300 may be the same type of chip as the first semiconductor chip 200. The configuration of the second semiconductor chip 300 may be substantially the same as the configuration of the first semiconductor chip 200.

[0052] The second semiconductor chip 300 may include a chip body 310 , a first chip pad 320 a disposed at a first side 310E1 on a first surface 310S1 of the chip body 310 , and a second chip pad 320 b disposed at a second side 310E2 on the first surface 310S1 of the chip body 310 .

[0053] In one embodiment, the first chip pad 320a may include a first side first power pad 320aP1 and a first side second power pad 320aP2, a first side first ground pad 320aG1 and a first side second ground pad 320aG2, and a first side first signal pad to a first side fourth signal pad 320aS1, 320aS2, 320aS3, and 320aS4. The first side first power pad 320aP1 and the first side second power pad 320aP2, the first side first ground pad 320aG1 and the first side second ground pad 320aG2, and the first side first signal pad to the first side fourth signal pad 320aS1, 320aS2, 320aS3, and 320aS4 may be arranged in a row LR310 along one direction (i.e., y direction) at the first side portion 310E1.

[0054] In one embodiment, the second chip pad 320b may include a second side first power pad 320bP1 and a second side second power pad 320bP2, and a second side first ground pad 320bG1 and a second side second ground pad 320bG2. The second side first power pad 320bP1 and the second side second power pad 320bP2 and the second side first ground pad 320bG1 and the second side second ground pad 320bG2 may be arranged in a row RR310 along one direction (i.e., y direction) at the second side portion 310E2. When compared with the first chip pad 320a, the second chip pad 320b may not have a signal pad.

[0055] In one embodiment, any one of the second side power pads 320bP1 and 320bP2 may be arranged point-symmetrically with respect to a reference point C310 on the first surface 310S1 and a corresponding one of the first side power pads 320aP1 and 320aP2. Any one of the second side grounding pads 320bG1 and 320bG2 may be arranged point-symmetrically with respect to a reference point C310 on the first surface 310S1 and a corresponding one of the first side grounding pads 320aG1 and 320aG2. Here, the reference point C310 on the first surface 310S1 may be the center point of the shape of the chip body 310 projected onto the first surface 310S1. As an example, when the chip body 310 has a rectangular shape on the first surface 310S1, the center point may be the intersection of two diagonal lines connecting vertices facing each other in the rectangle.

[0056] As a specific example, the first side first power pad 320aP1 and the second side first power pad 320bP1 may be arranged point-symmetrically with respect to the reference point C310. The first side second power pad 320aP2 and the second side second power pad 320bP2 may be arranged point-symmetrically with respect to the reference point C310. The first side first ground pad 320aG1 and the second side first ground pad 320bG1 may be arranged point-symmetrically with respect to the reference point C310. The first side second ground pad 320aG2 and the second side second ground pad 320bG2 may be arranged point-symmetrically with respect to the reference point C310.

[0057] In one embodiment, when the first side first power pad 320aP1 and the first side second power pad 320aP2, the first side first ground pad 320aG1 and the first side second ground pad 320aG2, and the first side first signal pad to the first side fourth signal pad 320aS1, 320aS2, 320aS3 and 320aS4 are arranged in a row LR310 to have Figure 4When the first power pad 320bP1 and the second power pad 320bP2 on the second side, and the first ground pad 320bG1 and the second ground pad 320bG2 on the second side are arranged in a row RR310 to have a predetermined distance d3, the power pads and the ground pads adjacent to each other can be spaced apart from each other by a predetermined distance d3 in the y direction. Figure 4 In the arrangement order shown, the power pads and ground pads adjacent to each other may be spaced apart from each other by a predetermined distance d3 in the y direction.

[0058] Figure 5 and Figure 6 is a view schematically illustrating electrical connection between a package substrate and a semiconductor chip according to an embodiment of the present disclosure. Figure 5 It is used to illustrate the above reference Figure 1 A view describing a form in which the lower semiconductor chip 200 is mounted on the package substrate 100 in the semiconductor package 1. Here, the lower semiconductor chip 200 may be combined with the above Figure 3 The described first semiconductor chips 200 have the same configuration. Figure 6 It is used to illustrate the above reference Figure 1 FIG. 1 is a view of a semiconductor package 1 in which an upper semiconductor chip 300 is stacked on a lower semiconductor chip 200. Here, the upper semiconductor chip 300 may be combined with the above Figure 4 The described second semiconductor chip 300 has the same configuration.

[0059] Reference Figure 5 , the lower semiconductor chip 200 may be disposed in the semiconductor chip mounting region 110A of the substrate body 110. The lower semiconductor chip 200 may be disposed in the semiconductor chip mounting region 110A of the substrate body 110. Figure 1 The first adhesive layer 510 is bonded to the substrate body 110. The pads of the first chip pad 220a on the lower semiconductor chip 200 may be wire-bonded to corresponding fingers of the first bonding finger array 120a on the package substrate 100, respectively. As a specific example, for the lower semiconductor chip 200, the power pads 220aP1 and 220aP2, the ground pads 220aG1 and 220aG2, and the signal pads 220aS1, 220aS2, 220aS3, and 220aS4 of the first chip pad 220a may be connected to corresponding power fingers 120aP1 and 120aP2, ground fingers 120aG1 and 120aG2, and signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 of the first bonding finger array 120a, respectively. Figure 5As shown in , the pads of the first die pad 220a can be wire bonded to the fingers of the first bonding finger array 120a in a one-to-one (1:1) ratio. In addition, the pads of the first die pad 220a can be arranged adjacent to the wire bonded fingers of the first bonding finger array 120a along the x direction.

[0060] In addition, the pads of the second chip pad 220b on the lower semiconductor chip 200 may be wire-bonded to corresponding fingers of the second bonding finger array 120b on the package substrate 100. Specifically, the power pads 220bP1 and 220bP2 and the ground pads 220bG1 and 220bG2 of the second chip pad 220b may be connected to the corresponding power fingers 120bP1 and 120bP2 and the ground fingers 120bG1 and 120bG2 of the second bonding finger array 120b, respectively. Figure 5 As shown in , the pads of the second chip pad 220b can be wire-bonded to the fingers of the second bonding finger array 120b at a ratio of 1:1. In addition, the pads of the second chip pad 220b can be arranged adjacent to the wire-bonded fingers of the second bonding finger array 120b along the x-direction. However, because the second chip pad 220b does not have a signal pad, there may be no pads connected to the signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 of the second bonding finger array 120b among the pads of the second chip pad 220b.

[0061] Reference Figure 6 as well as Figure 5 , the upper semiconductor chip 300 may be stacked on the lower semiconductor chip 200. As described above with reference to Figure 1 As described above, the second adhesive layer 520 may combine the lower semiconductor chip 200 and the upper semiconductor chip 300. Figure 6 , for ease of description, it is shown that the upper semiconductor chip 300 is stacked by offsetting a predetermined distance from the lower semiconductor chip 200, but in practice, the upper semiconductor chip 300 may be arranged to overlap with the lower semiconductor chip 200 without offset. In one embodiment, the lower semiconductor chip 200 and the upper semiconductor chip 300 may have substantially the same pad arrangement. That is, the arrangement of the power pads, ground pads, and signal pads of the upper semiconductor chip 300 and the lower semiconductor chip 200 may be substantially the same. In one embodiment, the lower semiconductor chip 200 and the upper semiconductor chip 300 may be chips of the same type. The configuration of the lower semiconductor chip 200 and the configuration of the upper semiconductor chip 300 may be substantially the same.

[0062] When the upper semiconductor chip 300 is stacked on the lower semiconductor chip 200, the upper semiconductor chip 300 may be disposed to overlap the lower semiconductor chip 200 while being rotated 180° about the center point C310 relative to the lower semiconductor chip 200. Respectively, the lower semiconductor chip 200 may have signal pads 220aS1, 220aS2, 220aS3, and 220aS4 only at the first side 210E1 of the chip body 210 of the lower semiconductor chip 200, and the upper semiconductor chip 300 may have signal pads 320aS1, 320aS2, 320aS3, and 320aS4 only at the first side 310E1 of the chip body 310 of the upper semiconductor chip 300. Therefore, by setting the upper semiconductor chip 300 to overlap with the lower semiconductor chip 200 after rotating the upper semiconductor chip 300 180° relative to the lower semiconductor chip 200, the signal pads 220aS1, 220aS2, 220aS3 and 220aS4 of the lower semiconductor chip 200 can be connected to the signal fingers 120aS1, 120aS2, 120asS3 and 120aS4 of the first bonding finger array 120a of the packaging substrate 100, and the signal pads 320aS1, 320aS2, 320aS3 and 320aS4 of the upper semiconductor chip 300 can be connected to the signal fingers 120bS1, 120bS2, 120bS3 and 120bS4 of the second bonding finger array 120b. As described above, the signal fingers 120aS1, 120aS2, 120aS3, and 120aS4 of the first bonding finger array 120a and the signal fingers 120bS1, 120bS2, 120bS3, and 120bS4 of the second bonding finger array 120b may be respectively connected to different signal paths of the package substrate 100. Therefore, the lower semiconductor chip 200 and the upper semiconductor chip 300 may exchange data signals and address command signals via independent signal paths of the package substrate 100, respectively.

[0063] In addition, as described above, according to an embodiment of the present disclosure, the lower semiconductor chip 200 and the upper semiconductor chip 300 may have substantially the same pad arrangement. That is, the arrangement of the power pads, ground pads, and signal pads of the lower semiconductor chip 200 and the upper semiconductor chip 300 may be substantially the same. In one embodiment, the lower semiconductor chip 200 and the upper semiconductor chip 300 may be chips of the same type. In addition, in each semiconductor chip, any one of the second side power pads may be arranged point-symmetrically with respect to a center point on one surface and a corresponding one of the first side power pads. In addition, any one of the second side ground pads may be arranged point-symmetrically with respect to a center point on the one surface and a corresponding one of the first side ground pads.

[0064] Therefore, when the lower semiconductor chip 200 and the upper semiconductor chip 300 are sequentially stacked on the packaging substrate 100 in a direction perpendicular to the packaging substrate 100, the first side first power pad 220aP1 and the first side second power pad 220aP2 of the lower semiconductor chip 200 and the second side first power pad 320bP1 and the second side second power pad 320bP2 of the upper semiconductor chip 300 can overlap with each other, and the first side first grounding pad 220aG1 and the first side second grounding pad 220aG2 of the lower semiconductor chip 200 and the second side first grounding pad 320bG1 and the second side second grounding pad 320bG2 of the upper semiconductor chip 300 can overlap with each other. In addition, the second side first power pad 220bP1 and the second side second power pad 220bP2 of the lower semiconductor chip 200 can overlap with the first side first power pad 320aP1 and the first side second power pad 320aP2 of the upper semiconductor chip 300, and the second side first grounding pad 220bG1 and the second side second grounding pad 220bG2 of the lower semiconductor chip 200 can overlap with the first side first grounding pad 320aG1 and the first side second grounding pad 320aG2 of the upper semiconductor chip 300.

[0065] As a result, the same type of power pads and ground pads of the lower semiconductor chip 200 and the upper semiconductor chip 300 that overlap each other can be respectively commonly connected to the corresponding power fingers and ground fingers of the package substrate 100. As an example, the first side first power pads 220aP1 of the lower semiconductor chip 200 and the second side first power pads 320bP1 of the upper semiconductor chip 300 can be commonly wire-bonded to the first side first power finger 120aP1 of the first bonding finger array 120a of the package substrate 100. The first side second power pads 220aP2 of the lower semiconductor chip 200 and the second side second power pads 320bP2 of the upper semiconductor chip 300 can be commonly wire-bonded to the first side second power finger 120aP2 of the first bonding finger array 120a of the package substrate 100. Similarly, the first side first grounding pad 220aG1 of the lower semiconductor chip 200 and the second side first grounding pad 320bG1 of the upper semiconductor chip 300 may be wire-bonded together to the first side first grounding finger portion 120aG1 of the first bonding finger array 120a of the package substrate 100. The first side second grounding pad 220aG2 of the lower semiconductor chip 200 and the second side second grounding pad 320bG2 of the upper semiconductor chip 300 may be wire-bonded together to the first side second grounding finger portion 120aG2 of the first bonding finger array 120a of the package substrate 100.

[0066] In the same manner, the second side first power pad 220bP1 of the lower semiconductor chip 200 and the first side first power pad 320aP1 of the upper semiconductor chip 300 may be wire-bonded together to the second side first power finger 120bP1 of the second bonding finger array 120b of the package substrate 100. The second side second power pad 220bP2 of the lower semiconductor chip 200 and the first side second power pad 320aP2 of the upper semiconductor chip 300 may be wire-bonded together to the second side second power finger 120bP2 of the second bonding finger array 120b of the package substrate 100. Similarly, the second side first grounding pad 220bG1 of the lower semiconductor chip 200 and the first side first grounding pad 320aG1 of the upper semiconductor chip 300 may be wire-bonded together to the second side first grounding finger 120bG1 of the second bonding finger array 120b of the package substrate 100. The second side second grounding pads 220 bG2 of the lower semiconductor chip 200 and the first side second grounding pads 320 aG2 of the upper semiconductor chip 300 may be commonly wire-bonded to the second side second grounding fingers 120 bG2 of the second bonding finger array 120 b of the package substrate 100 .

[0067] As described above, according to an embodiment of the present disclosure, a semiconductor package includes a package substrate and a plurality of semiconductor chips stacked on the package substrate. The plurality of semiconductor chips may each have the same pad arrangement. The semiconductor chip includes a chip body, a first chip pad disposed at a first side portion on one surface of the chip body, and a second chip pad disposed at a second side portion on the one surface.

[0068] The first chip pad may have at least one first side power pad and at least one first side ground pad. The second chip pad may have at least one second side power pad and at least one second side ground pad. In this case, any one of the second side power pads may be arranged point-symmetrically with respect to a reference point on one surface and a corresponding one of the first side power pads, and any one of the second side ground pads may be arranged point-symmetrically with respect to a reference point on the one surface and a corresponding one of the first side ground pads.

[0069] When a pair of semiconductor chips having the above configuration are stacked to overlap each other in a direction perpendicular to the package substrate, the first side power pad of the lower semiconductor chip and the second side power pad of the upper semiconductor chip may be arranged to overlap each other, and the first side grounding pad of the lower semiconductor chip and the second side grounding pad of the upper semiconductor chip may be arranged to overlap each other. The second side power pad of the lower semiconductor chip and the first side power pad of the upper semiconductor chip may be arranged to overlap each other, and the second side grounding pad of the lower semiconductor chip and the first side grounding pad of the upper semiconductor chip may be arranged to overlap each other.

[0070] As a result, the overlapping power pads of the lower and upper semiconductor chips can be wire-bonded together to a power finger of the package substrate. Similarly, the overlapping ground pads of the lower and upper semiconductor chips can be wire-bonded together to a ground finger of the package substrate.

[0071] As described above, in an embodiment of the present disclosure, the power pads and ground pads of the upper semiconductor chip and the lower semiconductor chip can share the power fingers and ground fingers of the package substrate. Therefore, the number of power fingers and ground fingers provided on the package substrate can be reduced according to the number of shared ones. Therefore, the integration of the power fingers and ground fingers on the package substrate can be improved. Therefore, the space for arranging the power fingers and ground fingers on the package substrate can be reduced, thereby obtaining an effect of reducing the planar size of the entire package. In addition, by reducing the arrangement space of the power fingers and ground fingers on the package substrate, additional space for pattern design on the package substrate can be ensured. That is, the design freedom of various other patterns implemented on the package substrate can be improved.

[0072] The embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure and the accompanying claims.

[0073] CROSS-REFERENCE TO RELATED APPLICATIONS

[0074] This application claims priority to Korean Application No. 10-2020-0017892, filed on February 13, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: Package substrate; as well as a lower semiconductor chip, wherein the lower semiconductor chip is stacked on the packaging substrate; as well as an upper semiconductor chip, the upper semiconductor chip being stacked on the lower semiconductor chip, Wherein, each of the upper semiconductor chip and the lower semiconductor chip comprises: Chip body; at least one first-side power supply pad and at least one first-side grounding pad provided at a first side portion on one surface of the chip body; and at least one second side power pad and at least one second side ground pad provided at a second side opposite to the first side on the one surface of the chip body, wherein one of the at least one second side power pads is point-symmetrically arranged with respect to a reference point on the one surface of the chip body and a corresponding one of the at least one first side power pads, and wherein one of the at least one second side grounding pads is point-symmetrically arranged with respect to the reference point on the one surface of the chip body and a corresponding one of the at least one first side grounding pads, Wherein, the packaging substrate further includes: a first bonding finger array, the first bonding finger array being arranged in a row on the package substrate adjacent to the first side of the lower semiconductor chip, and a second bonding finger array, the second bonding finger array being arranged in a row on the package substrate adjacent to the second side of the lower semiconductor chip, wherein the at least one first-side power pad of the lower semiconductor chip and the at least one second-side power pad of the upper semiconductor chip overlap each other to share a bonding finger of the first bonding finger array of the package substrate through electrical connection with each of the bonding wires, and Wherein, the at least one second side power pad of the lower semiconductor chip and the at least one first side power pad of the upper semiconductor chip overlap each other to share the bonding fingers of the second bonding finger array of the packaging substrate through electrical connection with each of the bonding wires.

2. The semiconductor package according to claim 1, wherein Each of the upper semiconductor chip and the lower semiconductor chip has the same pad arrangement.

3. The semiconductor package according to claim 1, wherein: The reference point on the one surface of the chip body is a center point of a shape of the chip body projected onto the one surface.

4. The semiconductor package according to claim 1, wherein: The at least one first-side power pad and the at least one first-side ground pad are arranged in a row at the first side portion, and The at least one second-side power pad and the at least one second-side ground pad are arranged in a row at the second side portion. 5 . The semiconductor package according to claim 4 , further comprising at least one signal pad disposed at the first side.

6. The semiconductor package according to claim 5, wherein: The at least one signal pad is arranged in the same row as the at least one first-side power pad and the at least one first-side ground pad.

7. The semiconductor package according to claim 1, in, The upper semiconductor chip and the lower semiconductor chip are sequentially stacked in a direction perpendicular to the package substrate and have the same pad arrangement as each other, wherein the at least one first side grounding pad of the lower semiconductor chip and the at least one second side grounding pad of the upper semiconductor chip overlap each other, and Wherein, the at least one second side grounding pad of the lower semiconductor chip and the at least one first side grounding pad of the upper semiconductor chip overlap each other.

8. The semiconductor package according to claim 7, in, The first bonding finger array includes at least one first side power finger and at least one first side ground finger, and the second bonding finger array includes at least one second side power finger and at least one second side ground finger, wherein one of the at least one first-side power finger is wire-bonded to a corresponding pad of the at least one first-side power pad of the lower semiconductor chip and a corresponding pad of the at least one second-side power pad of the upper semiconductor chip, wherein one of the at least one first side grounding finger is wire-bonded to a corresponding pad of the at least one first side grounding pad of the lower semiconductor chip and a corresponding pad of the at least one second side grounding pad of the upper semiconductor chip, wherein one of the at least one second-side power finger is wire-bonded to a corresponding pad of the at least one second-side power pad of the lower semiconductor chip and a corresponding pad of the at least one first-side power pad of the upper semiconductor chip, and Among them, one of the at least one second side grounding finger is wire-bonded to a corresponding pad of the at least one second side grounding pad of the lower semiconductor chip and a corresponding pad of the at least one first side grounding pad of the upper semiconductor chip.

9. The semiconductor package according to claim 8, in, The first bond finger array further comprises at least one first side signal finger, and the second bond finger array further comprises at least one second side signal finger, and wherein one of the at least one first side signal finger is connected to a signal pad disposed on a surface of one of the lower semiconductor chip and the upper semiconductor chip, and one of the at least one second side signal finger is connected to a signal pad disposed on a surface of the other of the lower semiconductor chip and the upper semiconductor chip.

10. The semiconductor package according to claim 1, wherein Each of the upper semiconductor chip and the lower semiconductor chip is configured to exchange electrical signals with the package substrate through an independent signal path.

11. A semiconductor package, comprising: Package substrate; as well as a lower semiconductor chip, wherein the lower semiconductor chip is stacked on the packaging substrate; as well as an upper semiconductor chip, the upper semiconductor chip being stacked on the lower semiconductor chip, Wherein, each of the upper semiconductor chip and the lower semiconductor chip comprises: Chip body; at least one first-side power pad, at least one first-side ground pad, and at least one signal pad disposed at a first side portion on one surface of the chip body; and at least one second side power pad and at least one second side ground pad provided at a second side opposite to the first side on the one surface of the chip body, wherein one of the at least one second side power pads is point-symmetrically arranged with respect to a reference point on the one surface of the chip body and a corresponding one of the at least one first side power pads, and wherein one of the at least one second side grounding pads is point-symmetrically arranged with respect to the reference point on the one surface of the chip body and a corresponding one of the at least one first side grounding pads, Wherein, the packaging substrate further includes: a first bonding finger array arranged in a row on the package substrate adjacent to the first side of the lower semiconductor chip; and a second bonding finger array, the second bonding finger array being arranged in a row on the package substrate adjacent to the second side of the lower semiconductor chip, wherein the at least one first-side power pad of the lower semiconductor chip and the at least one second-side power pad of the upper semiconductor chip overlap each other to share a bonding finger of the first bonding finger array of the package substrate through electrical connection with each of the bonding wires, and Wherein, the at least one second side power pad of the lower semiconductor chip and the at least one first side power pad of the upper semiconductor chip overlap each other to share the bonding fingers of the second bonding finger array of the packaging substrate through electrical connection with each of the bonding wires.

12. The semiconductor package according to claim 11, wherein Each of the upper semiconductor chip and the lower semiconductor chip has the same pad arrangement.

13. The semiconductor package according to claim 11, wherein The reference point on the one surface of the chip body is a center point of a shape of the chip body projected onto the one surface.

14. The semiconductor package according to claim 11, in, The at least one first-side power pad, the at least one first-side ground pad, and the at least one signal pad are arranged in a row at the first side portion, and The at least one second-side power pad and the at least one second-side ground pad are arranged in a row at the second side portion.

15. The semiconductor package according to claim 11, in, The lower semiconductor chip and the upper semiconductor chip are sequentially stacked in a direction perpendicular to the package substrate and have the same pad arrangement as each other, wherein the at least one first side grounding pad of the lower semiconductor chip and the at least one second side grounding pad of the upper semiconductor chip overlap each other, and Wherein, the at least one second side grounding pad of the lower semiconductor chip and the at least one first side grounding pad of the upper semiconductor chip overlap each other.

16. The semiconductor package according to claim 15, wherein: The at least one signal pad of the lower semiconductor chip and the at least one signal pad of the upper semiconductor chip do not overlap each other.

17. The semiconductor package according to claim 15, wherein: The first bonding finger array includes at least one first-side power finger, at least one first-side ground finger, and at least one first-side signal finger, and The second bonding finger array includes at least one second-side power finger, at least one second-side ground finger and at least one second-side signal finger.

18. The semiconductor package according to claim 17, in, One of the at least one first-side power finger is wire-bonded to a corresponding pad of the at least one first-side power pad of the lower semiconductor chip and a corresponding pad of the at least one second-side power pad of the upper semiconductor chip, wherein one of the at least one first side grounding finger is wire-bonded to a corresponding pad of the at least one first side grounding pad of the lower semiconductor chip and a corresponding pad of the at least one second side grounding pad of the upper semiconductor chip, wherein one of the at least one first-side signal finger is wire-bonded to a corresponding pad of the at least one signal pad of the lower semiconductor chip, wherein one of the at least one second-side power finger is wire-bonded to a corresponding pad of the at least one second-side power pad of the lower semiconductor chip and a corresponding pad of the at least one first-side power pad of the upper semiconductor chip, wherein one of the at least one second side grounding finger portions is wire-bonded to a corresponding pad of the at least one second side grounding pad of the lower semiconductor chip and a corresponding pad of the at least one first side grounding pad of the upper semiconductor chip, and Among them, one of the at least one second-side signal finger is wire-bonded to a corresponding pad of the at least one signal pad of the upper semiconductor chip.

19. A semiconductor package, comprising: A packaging substrate, the packaging substrate comprising a first bonding finger array and a second bonding finger array that are spaced apart from each other and are respectively arranged in a row; a lower semiconductor chip disposed between the first bonding finger array and the second bonding finger array; as well as an upper semiconductor chip, the upper semiconductor chip being disposed on the lower semiconductor chip, wherein the lower semiconductor chip and the upper semiconductor chip have the same pad arrangement as each other, Wherein, each of the lower semiconductor chip and the upper semiconductor chip comprises: Chip body; at least one first-side power pad, at least one first-side ground pad, and at least one signal pad disposed at a first side portion on one surface of the chip body; and at least one second side power pad and at least one second side ground pad provided at a second side opposite to the first side on the one surface of the chip body, Among them, one of the at least one second side power supply pads is point-symmetrically arranged with respect to a reference point on the one surface of the chip body and a corresponding one of the at least one first side power supply pads, and one of the at least one second side grounding pads is point-symmetrically arranged with respect to the reference point on the one surface of the chip body and a corresponding one of the at least one first side grounding pads, and wherein the at least one first side power pad of the lower semiconductor chip and the at least one second side power pad of the upper semiconductor chip are arranged to overlap each other to share a bonding finger of the first bonding finger array of the package substrate through electrical connection with each of the bonding wires, and Wherein, the at least one second side power pad of the lower semiconductor chip and the at least one first side power pad of the upper semiconductor chip are arranged to overlap each other to share the bonding fingers of the second bonding finger array of the packaging substrate through electrical connection with each of the bonding wires.

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