Semiconductor device package and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device package and a method for manufacturing the same. The semiconductor device package includes a first circuit layer, a first emitter, and a second emitter. The first circuit layer has a first surface and a second surface opposite the first surface. The first emitter is disposed on the second surface of the first circuit layer. The first emitter has a first surface facing the first circuit layer and a second surface opposite the first surface. The first emitter has a first conductive pattern disposed on the first surface of the first emitter. The second emitter is disposed on the second surface of the first emitter. The second emitter has a first surface facing the second surface of the first emitter and a second surface opposite the first surface. The second emitter has a second conductive pattern disposed on the second surface of the emitter. The coefficient of thermal expansion (CTE) of the first emitter is greater than the CTE of the second emitter.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly to a semiconductor device package including an antenna and a method of manufacturing the same. Background Art

[0002] Wireless communication devices such as cellular phones typically include an antenna for transmitting and receiving radio frequency (RF) signals. Comparatively, a wireless communication device includes an antenna and a communication module, each of which is placed on different parts of a circuit board. Under a comparable method, the antenna and the communication module are manufactured separately and electrically connected together after being placed on the circuit board. Therefore, both components may incur separate manufacturing costs. In addition, it may be difficult to reduce the size of the wireless communication device to obtain a suitably compact product design. In order to reduce costs and reduce the package size, an antenna-in-package (AiP) method is provided. Typically, organic substrates are commonly used in AiP systems. However, due to the process limitations of organic substrates, it is difficult to achieve fine pitch (less than 15 / 15 μm), and the organic substrate is relatively thick, which will hinder the miniaturization of the AiP system. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a semiconductor device package includes a first circuit layer, a first emitting device, and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device. The coefficient of thermal expansion (CTE) of the first emitting device is greater than the CTE of the second emitting device. In some embodiments, the CTE may be an equivalent CTE.

[0004] According to some embodiments of the present disclosure, a semiconductor device package includes a stacked circuit, a first emitting device, and a second emitting device. The stacked circuit has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the stacked circuit. The first emitting device has a first surface facing the stacked circuit and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device. The thickness of the second emitting device is greater than that of the first emitting device.

[0005] According to some embodiments of the present disclosure, a method for manufacturing an optical module includes: (a) providing a first transmitting device having a first conductive pattern; (b) providing a plurality of second transmitting devices, each second transmitting device having a second conductive pattern; and (c) attaching the second transmitting device to the first transmitting device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0007] Figure 1B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 2A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0009] Figure 2B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0012] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E Semiconductor manufacturing methods according to some embodiments of the present disclosure are presented.

[0013] Throughout the drawings and detailed description, common reference numerals are used to refer to the same or similar components.The present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0014] Figure 1A A cross-sectional view of a semiconductor device package 1A according to some embodiments of the present disclosure is shown. The semiconductor device package 1A includes carriers 10a, 10b, circuit layers 11, 13, 14, interconnect structures 12a, 12b, electronic components 15, electrical contacts 16, and package bodies 17, 18, and 19.

[0015] In some embodiments, the carrier 10a may be or include a glass substrate. In some embodiments, the carrier 10a may be or include a transmitting device having one or more transmitting components (e.g., an antenna, a light emitting device, a sensor, etc.) disposed thereon. The carrier 10a may include one or more conductive pads, one or more traces, and one or more interconnects (e.g., one or more through-holes). In some embodiments, the carrier 10a may include a transparent material. In some embodiments, the carrier 10a may include an opaque material. The carrier 10a includes a material having a dielectric constant (Dk) of less than approximately 5. The carrier 10a includes a material having a Dk of less than approximately 3. The carrier 10a includes a material having a loss tangent or dissipation factor (Df) of less than approximately 0.005. The carrier 10a includes a material having a loss tangent or Df of less than approximately 0.003.

[0016] The carrier 10a has a surface 101a, a surface 102a opposite to the surface 101a, and a side surface 103a extending between the surface 101a and the surface 102a. Compared to an organic substrate, the thickness of the glass carrier is easier to control, which can promote the miniaturization of the semiconductor device package 1A. In some embodiments, the thickness of the carrier 10a is equal to or less than about 400 μm. For example, the thickness of the carrier 10a is in the range of about 50 μm to about 400 μm. For example, the thickness of the carrier 10a is in the range of about 100 μm to about 300 μm. In some embodiments, the coefficient of thermal expansion (CTE) of the carrier 10a is in the range of about 0.5 to about 13. In some embodiments, the CTE of the carrier 10a is in the range of about 3.6 to about 8.5.

[0017] The conductive layer 10p is disposed on the surface 102a of the carrier 10a. In some embodiments, the conductive layer 10p defines a patterned antenna, such as a directional antenna, an omnidirectional antenna, or an antenna array. For example, the conductive layer 10p defines a patch antenna. The conductive layer 10p is or includes a conductive material such as a metal or a metal alloy. Examples of conductive materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), one or more other metals, one or more alloys, or a combination of two or more thereof. In some embodiments, the conductive layer 10p can be replaced by one or more light-emitting devices or sensors.

[0018] The carrier 10b is placed on the surface 101a of the carrier 10a. The carrier 10b has a surface 101b facing away from the carrier 10a, a surface 102b opposite to the surface 101b, and a side 103b extending between the surface 101b and the surface 102b. The surface 102b of the carrier 10b is connected to the surface 101a of the carrier 10a by an adhesive layer 10h (e.g., tape, glue, or die attach film (DAF)). The carrier 10b is spaced apart from the carrier 10a. For example, there is a distance (e.g., the thickness of the adhesive layer 10a) between the surface 101a of the carrier 10a and the surface 102b of the carrier 10b. In some embodiments, the side 103a of the carrier 10a and the side 103b of the carrier 10b are non-coplanar or discontinuous. For example, the side 103a of the carrier 10a is recessed from the side 103b of the carrier 10b. For example, the width of the carrier 10a is less than the width of the carrier 10b. In some embodiments, the roughness of side surface 103a of carrier 10a is less than the roughness of side surface 103b of carrier 10b. In some embodiments, carrier 10b and a portion of circuit layer 11 (eg, a conductive layer of the circuit layer adjacent to carrier 10b) may also be referred to as a first emitting device.

[0019] In some embodiments, the thickness of the carrier 10b and the carrier 10a may be the same. Alternatively, the thickness of the carrier 10b and the carrier 10a may be different. For example, the thickness of the carrier 10a may be equal to, greater than, or less than the thickness of the carrier 10b. In some embodiments, the sum of the thickness of the carrier 10a and the thickness of the carrier 10b may be equal to or less than about 400 μm. For example, the thickness of the carrier 10a may be about 350 μm and the thickness of the carrier 10b may be about 50 μm. For example, the thickness of the carrier 10a may be about 300 μm and the thickness of the carrier 10b may be about 100 μm. For example, the thickness of the carrier 10a may be about 250 μm and the thickness of the carrier 10b may be about 150 μm.

[0020] In some embodiments, the carrier 10b and the carrier 10a may comprise the same material. Alternatively, the carrier 10b and the carrier 10a may comprise different materials. In some embodiments, the CTE of the carrier 10b is higher than the CTE of the carrier 10a. In some embodiments, the hardness of the carrier 10b is higher than the hardness of the carrier 10a. By placing the carrier 10b having relatively high CTE and hardness between the carrier 10a and the circuit layer 11, the warping problem caused by the CTE mismatch between the carrier 10b and the package 17 (or package 18) can be alleviated. In some embodiments, the Dk of the carrier 10a is lower than the Dk of the carrier 10b. By selecting a carrier 10a with a relatively low Dk, the electrical performance of the antenna pattern (e.g., the conductive layer 10p) can be improved. This will increase the flexibility in designing the semiconductor device package 1A.

[0021] Encapsulation body 17 is disposed on surface 102b of carrier 10b. Encapsulation body 17 covers carrier 10a and conductive layer 10p. Encapsulation body 17 covers surface 102a and side 103a of carrier 10a, as well as the side of adhesive layer 10h. In some embodiments, encapsulation body 17 has side 173 that is substantially coplanar with side 103b of carrier 10b. Side 103a of carrier 10a is recessed from side 173 of encapsulation body 17. For example, there is a distance between side 103a of carrier 10a and side 173 of encapsulation body 17. In some embodiments, encapsulation body 17 comprises an epoxy resin containing a filler, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material containing silicone dispersed therein, or a combination thereof.

[0022] Circuit layer 11 (or built-up circuit) has a surface 111 facing away from carrier 10b, a surface 112 opposite to surface 111, and a side 113 extending between surface 111 and surface 112. Circuit layer 11 is placed on surface 101b of carrier 10b. In some embodiments, circuit layer 11 is in contact with carrier 10b. Alternatively, circuit layer 11 can be connected to carrier 10b by an adhesive layer (e.g., DAF). In some embodiments, side 113 of circuit layer 11 is substantially coplanar with side 103b of carrier 10b.

[0023] Circuit layer 11 includes one or more conductive layers (e.g., redistribution layers (RDLs)) 11c and one or more dielectric layers 11d. A portion of conductive layer 11c is covered or encapsulated by dielectric layer 11d, while another portion of conductive layer 11c is exposed from dielectric layer 11d to provide electrical connections. In some embodiments, the exposed portion of conductive layer 11c has a surface facing carrier 10b and in contact with surface 101b of carrier 10b. In some embodiments, conductive layer 11c may include or contain one or more antenna patterns, light emitting devices, sensors, and the like.

[0024] In some embodiments, dielectric layer 11d may include pre-impregnated composite fibers (e.g., prepreg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), or any combination of two or more thereof. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating multiple prepreg materials / sheets. In some embodiments, any number of conductive layers 11c and dielectric layers 11d may be present, depending on design specifications. In some embodiments, conductive layer 11c is formed of or includes Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0025] One or more interconnect structures 12a (e.g., conductive pillars or conductive elements) are disposed on surface 111 of circuit layer 11. Interconnect structures 12a are electrically connected to circuit layer 11 (i.e., electrically connected to conductive layer 11c exposed from dielectric layer 11d). In some embodiments, interconnect structures 12a define antenna structures. Interconnect structures 12a are or include a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0026] Encapsulation body 18 is disposed on surface 111 of circuit layer 11. Encapsulation body 18 covers interconnect structure 12a. In some embodiments, encapsulation body 18 has side 183 that is substantially coplanar with side 113 of circuit layer 11. In some embodiments, encapsulation body 18 comprises an epoxy resin containing a filler, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material containing a silicone resin dispersed therein, or a combination thereof.

[0027] Circuit layer 13 (or built-up circuit) is disposed on package body 18. Circuit layer 13 includes a dielectric layer 13d and a conductive layer 13c. In some embodiments, dielectric layer 13d and dielectric layer 11d may comprise the same material. Alternatively, dielectric layer 13d and dielectric layer 11d may comprise different materials. Circuit layer 13 is electrically connected to interconnect structure 12a. For example, conductive layer 13c of circuit layer 13 contacts interconnect structure 12a. Alternatively, a seed layer is disposed between conductive layer 13c and interconnect structure 12a. In some embodiments, any number of conductive layers 13c and dielectric layers 13d may be present, depending on design specifications.

[0028] One or more interconnect structures 12b (e.g., conductive pillars or conductive elements) are disposed on a surface of circuit layer 13 facing away from circuit layer 11. Interconnect structures 12b are electrically connected to circuit layer 13. Interconnect structures 12b are or include a conductive material such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0029] Encapsulation body 19 is disposed on a surface of circuit layer 13 facing away from circuit layer 11. Encapsulation body 19 covers interconnect structure 12b and electronic component 15. In some embodiments, encapsulation body 19 has sides that are substantially coplanar with sides of circuit layer 13. In some embodiments, encapsulation body 19 comprises an epoxy resin containing a filler, a molding material (e.g., an epoxy molding material or other molding material), a polyimide, a phenolic compound or material, a material containing a silicone resin dispersed therein, or a combination thereof.

[0030] Circuit layer 14 (or built-up circuit) is disposed on package body 19. Circuit layer 14 includes a dielectric layer 14d and a conductive layer 14c. In some embodiments, dielectric layer 14d and dielectric layer 11d may comprise the same material. Alternatively, dielectric layer 14d and dielectric layer 11d may comprise different materials. Conductive layer 14c is electrically connected to interconnect structure 12b. For example, conductive layer 14c of circuit layer 14 contacts interconnect structure 12b. Alternatively, a seed layer is disposed between conductive layer 14c and interconnect structure 12b. In some embodiments, any number of conductive layers 14c and dielectric layers 14d may be present, depending on design specifications.

[0031] Electronic component 15 is placed on the surface of circuit layer 13 facing away from circuit layer 11. The active surface of electronic component 15 faces circuit layer 13. Electronic component 15 is electrically connected to circuit layer 13 (e.g., electrically connected to conductive layer 13c) through electrical contacts (e.g., solder balls), and the electrical connection can be achieved, for example, by flip-chip technology. Electronic component 15 can be an active electronic component such as an integrated circuit (IC) chip or die.

[0032] Electrical contacts 16 are disposed on conductive layer 14c exposed from dielectric layer 14d. In some embodiments, electrical contacts 16 may comprise solder or one or more other suitable materials.

[0033] In some embodiments, side 103a of carrier 10a can be coplanar with side 103b of carrier 10b. For example, side 103a of carrier 10a is exposed from package 17. Such a structure can be formed by: (i) providing a glass wafer; (ii) forming circuit layers 11, 13, 14, interconnect structures 12a, 12b, packages 17, 18, 19, and electronic component 15 on the glass wafer; and (iii) performing singulation through circuit layers 11, 13, 14, packages 17, 18, 19, and the carrier wafer. To meet the performance requirements of the antenna structure, the glass wafer should be selected from a material with a relatively low Dk (e.g., less than 5). However, a glass wafer with a relatively low Dk will also have a relatively low CTE (e.g., less than 13). Due to the CTE mismatch between the glass wafer and package 17 (e.g., the CTE of the package is typically greater than 20), warping issues may occur. As the size of the glass wafer increases, the warping issue becomes more severe, potentially causing the glass wafer to crack or damage.

[0034] according to Figure 1A In the embodiment shown in FIG, the side surface 103a of the carrier 10a is recessed from the side surface 103b of the carrier 10b. Such a structure can be formed by the following (detailed operations will be described later): (i) singulating the glass wafer to separate the glass wafer into a plurality of glass carriers (e.g., Figure 1A ); (ii) forming a carrier 10b, circuit layers 11, 13, 14, interconnect structures 12a, 12b, and packages 17, 18, 19, and electronic components 15; and (iii) attaching the carrier 10a to the carrier 10b via an adhesive layer 10h. Because the size of the divided glass carrier is much smaller than the size of the glass wafer, the warping problem can be significantly alleviated. In addition, because it is not necessary to select a material for the carrier 10a with a higher CTE to approach the CTE of the package 17, a material with a lower CTE (and lower Dk) can be selected as the carrier 10a. This will enhance the performance of the antenna structure of the semiconductor device package 1A. In addition, the thickness of the carrier 10a can also be reduced, which will promote the miniaturization of the semiconductor device package 1A.

[0035] Figure 1B FIG1 shows a cross-sectional view of a semiconductor device package 1B according to some embodiments of the present disclosure. The semiconductor device package 1B is similar to Figure 1A The semiconductor device package 1A shown in FIG. 1 is different from the semiconductor device package 1A shown in FIG. 1 in FIG. Figure 1B In the embodiment, the width of the adhesive layer 10h is greater than the width of the carrier 10a. For example, the side surface of the adhesive layer 10h is substantially coplanar with the side surface 103b of the carrier 10b. For example, the side surface 103a of the carrier 10a is recessed from the side surface of the adhesive layer 10h. This improves the accuracy of aligning the carriers 10a and 10b during the manufacturing process.

[0036] Figure 2A FIG2 shows a cross-sectional view of a semiconductor device package 2A according to some embodiments of the present disclosure. The semiconductor device package 2A is similar to Figure 1A The semiconductor device package 1A shown in FIG. 1 is shown in FIG. 2 , and the differences therebetween are described below.

[0037] Electronic component 15 is placed on the surface of circuit layer 13 facing away from circuit layer 11. The back surface of electronic component 15 is connected to circuit layer 13 via adhesive layer 15a (e.g., DAF). Electronic component 15 is electrically connected to circuit layer 14 (e.g., electrically connected to conductive layer 14c) via interconnect structure 15c (e.g., Cu pillar).

[0038] Figure 2B FIG2 shows a cross-sectional view of a semiconductor device package 2B according to some embodiments of the present disclosure. The semiconductor device package 2B is similar to Figure 2A The semiconductor device package 2A shown in FIG, and one of the differences therebetween is that in Figure 2B In the embodiment, the width of the adhesive layer 10h is greater than the width of the carrier 10a. For example, the side surface of the adhesive layer 10h is substantially coplanar with the side surface 103b of the carrier 10b. For example, the side surface 103a of the carrier 10a is recessed from the side surface of the adhesive layer 10h. This improves the accuracy of aligning the carriers 10a and 10b during the manufacturing process.

[0039] Figure 3 FIG2 shows a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to Figure 1B The semiconductor device package 1B shown in FIG. 1 is shown in FIG. 2 , and the differences therebetween are described below.

[0040] The semiconductor device package 3 may include two parts 3A and 3B. Part 3A includes a dielectric layer 13d1, a package body 19, an electronic component 15, a circuit layer 14, an interconnect structure 12b, and electrical contacts 16. Part 3B includes a dielectric layer 13d2, package bodies 17, 18, a circuit layer 11, carriers 10a and 10b. Part 3A and part 3B may be manufactured separately and then connected to each other via electrical contacts 31s (e.g., solder balls). This will improve the yield of the semiconductor device package 3. In some embodiments, a bottom filler 31h may be placed between part 3A and part 3B to cover the electrical contacts 31s. In some embodiments, the width of part 3A is the same as the width of part 3B. Alternatively, depending on the design specifications, the width of part 3A may be greater than or less than the width of part 3B.

[0041] Figure 4 FIG2 shows a cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure. The semiconductor device package 4 is similar to Figure 3 The semiconductor device package 3 shown in FIG. 1 is shown in FIG. 2 , and the differences therebetween are described below.

[0042] The semiconductor device package 4 may include two parts 4A and 4B. Part 4B is similar to Figure 3 Part 3B of the semiconductor device package 3. Part 4A is similar to Figure 3 Part 3A of the semiconductor device package 3, except in Figure 4 In portion 4A of the semiconductor device package 4, electronic component 15 is positioned on the surface of circuit layer 14 facing dielectric layer 13d2. The back surface of electronic component 15 is connected to the surface of circuit layer 14 via adhesive layer 15a. The active surface of electronic component 15 is electrically connected to conductive layer 13c via interconnect structure 15c (e.g., Cu pillar). In some embodiments, the width of portion 4A is the same as the width of portion 4B. Alternatively, the width of portion 4A may be greater than or less than the width of portion 4B, depending on design specifications.

[0043] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E A semiconductor manufacturing method according to some embodiments of the present disclosure is presented. In some embodiments, a semiconductor manufacturing method may be used. Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E Methods in making Figure 1A The semiconductor device package 1A is shown in FIG.

[0044] Reference Figure 5A , providing a carrier 10b. The substrate 10b can be of wafer type, panel type, or strip type. A circuit layer 11 comprising one or more conductive layers 11c and one or more dielectric layers 11d is formed on the carrier 10b. An interconnect structure 12a is formed on the circuit layer 11 to electrically connect to the circuit layer 11 (e.g., connected to the portion of the conductive layer 11c exposed from the dielectric layer 11d). The dielectric layer 11d is formed using, for example, but not limited to, photolithography techniques. In some embodiments, the interconnect structure 12a can be formed using, for example, but not limited to, electroplating techniques.

[0045] Then, a package body 18 is formed on the circuit layer 11 to cover the interconnection structure 12a. In some embodiments, the package body 18 can be formed to completely cover the interconnection structure 12a. In some embodiments, the package body 18 is formed by, for example, transfer molding, compression, or any other suitable technique.

[0046] Reference Figure 5B, a portion of the carrier 10b is removed by, for example, grinding or any other suitable process to reduce the thickness of the carrier 10b. In some embodiments, the thinning operation is performed on a surface of the carrier 10b facing away from the circuit layer 11. In some embodiments, after the thinning operation, the thickness of the carrier 10b is equal to or less than 200 μm. For example, the thickness of the carrier 10b is equal to or less than 100 μm. For example, the thickness of the carrier 10b is equal to or less than 50 μm.

[0047] Reference Figure 5C , the package 18 is placed on the carrier 59. The package 18 can be attached to the carrier 59 by an adhesive layer (e.g., tape or glue). The carrier 10a having the conductive layer 10p thereon is placed on the carrier 10b. In some embodiments, the carrier 10a is attached to the carrier 10b by an adhesive layer 10h. In some embodiments, the carrier 10a can be formed by performing singulation to separate the glass wafer into a plurality of glass carriers containing the carrier 10a. In some embodiments, the thickness of the carrier 10a is equal to or greater than 200 μm. For example, the thickness of the carrier 10a is equal to or greater than 300 μm. For example, the thickness of the carrier 10a is equal to or greater than 350 μm.

[0048] Then, a package body 17 is formed on the carrier 10b to cover the carrier 10a and the conductive layer 10p. In some embodiments, the package body 17 is formed by, for example, a transfer molding technique, a compression technique, or any other suitable technique. Because the carrier 10b is relatively thin (compared to the carrier 10a), even if the carrier 10b may be a wafer type, a panel type, or a strip type, the warpage problem caused by the CTE mismatch between the carrier 10b and the package body 17 can be reduced. In addition, because the carrier 10a is connected to the carrier 10b after the carrier wafer is divided into a plurality of carriers including the carrier 10a, the size of the divided carriers is much smaller than the size of the carrier wafer. Therefore, the warpage problem caused by the CTE mismatch between the package body 17 and the carrier 10a can be significantly reduced.

[0049] Reference Figure 5D , carrier 59 is removed from package body 18. A portion of package body 18 is removed, for example, by grinding or any other suitable process, to expose interconnect structure 12a. Circuit layer 13, comprising one or more conductive layers 13c and one or more dielectric layers 13d, is formed on package body 18 and electrically connected to interconnect structure 12a exposed from package body 18. Electronic component 15 is then placed on circuit layer 13. In some embodiments, the active surface of electronic component 15 is connected to circuit layer 13 by, for example, flip-chip bonding or any other suitable process.

[0050] Reference Figure 5E, an interconnect structure 12b is formed on the circuit layer 13 and electrically connected to the circuit layer 13. In some embodiments, the interconnect structure 12b can be formed by, for example, but not limited to, electroplating technology. A package body 19 is formed on the circuit layer 13 to cover the interconnect structure 12b and the electronic component 15. In some embodiments, the package body 19 can be formed to completely cover the interconnect structure 12b, and then a portion of the package body 19 can be removed by, for example, grinding or any other suitable technology to expose the top portion of the interconnect structure 12b to achieve electrical connection. In some embodiments, the package body 19 is formed by, for example, transfer molding technology, compression technology, or any other suitable technology.

[0051] A circuit layer 14 including one or more conductive layers 14c and one or more dielectric layers 14d is formed on the package body 18 and electrically connected to the interconnect structure 12b exposed from the package body 18. The dielectric layer 14d is formed by, for example, but not limited to, photolithography. Then, electrical contacts 16 are placed on the conductive layer 14c exposed from the dielectric layer 14d.

[0052] As used herein, the terms "substantially," "essentially," "approximately," and "about" are used to indicate and account for small variations. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a thickness of a film or layer that is "substantially uniform" may refer to a standard deviation less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces that are positioned along the same plane within a few microns of each other, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm of each other. Two surfaces or components may be considered "substantially perpendicular" if the angle between them is, for example, 90° ± 10°, such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°. When used in conjunction with an event or circumstance, the terms "substantially," "essentially," "approximately," and "about" may refer to both situations where the event or circumstance occurs exactly and situations where the event or circumstance is close to occurring.

[0053] As used herein, the singular terms "a / an" and "the" may include plural referents unless the context clearly indicates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass both the case where the former component is directly located on (e.g., physically in contact with) the latter component and the case where one or more intermediate components are positioned between the former and the latter component.

[0054] As used herein, the terms "conductive," "electrically conductive," and "electrical conductivity" refer to the ability to carry an electric current. Conductive materials generally refer to those materials that offer little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has an electrical conductivity greater than about 10 4 S / m, such as at least 10 5 S / m or at least 10 6 S / m for conductive materials. The conductivity of a material can sometimes vary with temperature. Unless otherwise stated, the conductivity of a material is measured at room temperature.

[0055] In addition, amounts, ratios and other numerical values are sometimes presented herein in a range format. It should be understood that such range format is used for convenience and brevity and should be construed flexibly to include not only the values explicitly designated as the limits of the range, but also all individual values or subranges encompassed within the range, as if each value and subrange were explicitly designated.

[0056] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these depictions and illustrations do not limit the present disclosure. It will be understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the spirit and scope of the present disclosure as defined by the claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically shown. The description and drawings should be regarded as illustrative and not restrictive. Modifications may be made to adapt specific circumstances, materials, material compositions, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it will be understood that these operations may be combined, subdivided or rearranged to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A semiconductor device package, comprising: a first circuit layer having a first surface and a second surface opposite to the first surface; a first emitting device, the first emitting device being disposed on the second surface of the first circuit layer, the first emitting device having a first surface facing the first circuit layer and a second surface opposite to the first surface, the first emitting device having a first conductive pattern disposed on the first surface of the first emitting device; as well as a second emitting device, the second emitting device being disposed on the second surface of the first emitting device, the second emitting device having a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface, the second emitting device having a second conductive pattern disposed on the second surface of the emitting device, The coefficient of thermal expansion (CTE) of the first emitting device is greater than the CTE of the second emitting device. 2 . The semiconductor device package according to claim 1 , wherein a side surface of the first circuit layer is substantially coplanar with a side surface of the first emitting device. 3 . The semiconductor device package according to claim 1 , wherein a side surface of the emitting device is recessed from a side surface of the first emitting device. 4 . The semiconductor device package according to claim 1 , wherein a width of the first emission device is smaller than a width of the second emission device. 5 . The semiconductor device package according to claim 1 , wherein a thickness of the second emission device is greater than a thickness of the first emission device. 6 . The semiconductor device package according to claim 1 , wherein a roughness of a side surface of the second emitting device is smaller than a roughness of a side surface of the first emitting device. 7 . The semiconductor device package of claim 1 , further comprising an adhesive layer disposed between the second surface of the first emitting device and the first surface of the second emitting device. 8 . The semiconductor device package according to claim 7 , wherein a side surface of the adhesive layer is substantially coplanar with a side surface of the second emitting device. 9 . The semiconductor device package according to claim 7 , wherein a side surface of the adhesive layer is substantially coplanar with a side surface of the first emitting device. 10 . The semiconductor device package of claim 1 , wherein the first emission device comprises a first glass carrier and the second emission device comprises a second glass carrier. The semiconductor device package of claim 10 , wherein a CTE of the first glass carrier is greater than a CTE of the second glass carrier.

12. The semiconductor device package according to claim 1, further comprising: a first group of conductive pillars, the first group of conductive pillars being disposed on the first surface of the first circuit layer; as well as A first package body is disposed on the first surface of the first circuit layer and covers the first group of conductive pillars.

13. The semiconductor device package according to claim 12, further comprising: a second circuit layer, the second circuit layer being disposed on the first package body; a second group of conductive pillars, the second group of conductive pillars being disposed on the second circuit layer; as well as A second package body is disposed on the second circuit layer and covers the second group of conductive pillars. 14 . The semiconductor device package according to claim 13 , further comprising an electronic component disposed on the second circuit layer, the electronic component having an active surface facing the second circuit layer and electrically connected to the second circuit layer.

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