Memory device and method of manufacturing the same

Abstract

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets formed on the substrate and spaced vertically from each other. The semiconductor device includes a first source / drain (S / D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S / D region electrically coupled to both a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S / D region electrically coupled to the second end of the plurality of first nanosheets. The fin-based structure has a first lattice direction, and the plurality of first nanosheets have a second lattice direction different from the first lattice direction. Embodiments of the present invention also relate to a memory device and a method for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present invention also relate to a memory device and a method for manufacturing the same. Background Art

[0002] The present disclosure relates generally to semiconductor devices and, in some embodiments, to memory devices including different lattice orientations.

[0003] Integrated circuits (ICs) sometimes include one-time programmable (OTP) memory to provide non-volatile memory (NVM) in which data is not lost when the IC is powered off. One type of OTP device includes an anti-fuse memory. The anti-fuse memory includes a plurality of anti-fuse memory cells (or bit cells) whose terminals are disconnected before programming and shorted (e.g., connected) after programming. The anti-fuse memory can be based on metal oxide semiconductor (MOS) technology. For example, an anti-fuse memory cell can include a programming MOS transistor (or MOS capacitor) and at least one reading MOS transistor. The gate dielectric of the programming MOS transistor can be broken down to interconnect the gate of the programming MOS transistor with the source or drain region. Depending on whether the gate dielectric of the programming MOS transistor is broken down, the anti-fuse memory cell can present different data bits by reading the resulting current flowing through the programming MOS transistor and reading the MOS transistor. Since the programming state of the anti-fuse cell cannot be determined by reverse engineering, the anti-fuse memory has the advantageous feature of reverse engineering verification. Summary of the invention

[0004] According to one aspect of the present invention, a semiconductor device is provided, comprising: a fin-based structure formed on a substrate; a plurality of first nanosheets vertically spaced apart from each other and formed on the substrate; a first source / drain (S / D) region coupled to a first end of the fin-based structure; a second S / D region coupled to both a second end of the fin-based structure and a first end of the plurality of first nanosheets; and a third S / D region coupled to a second end of the plurality of first nanosheets; wherein the fin-based structure has a first lattice direction, and the plurality of first nanosheets have a second lattice direction different from the first lattice direction.

[0005] According to another aspect of the present invention, a semiconductor device is provided, comprising: a fin-based structure formed on a substrate, the fin-based structure extending along a first direction; one or more first nanosheets arranged on the substrate, each of the one or more first nanosheets being spaced apart from each other along a second direction perpendicular to the first direction; and a first source / drain (S / D) region arranged between the fin-based structure and the one or more first nanosheets along the first direction; wherein the sidewalls of the fin-based structure each have a first crystal plane direction along a third direction perpendicular to the first direction and the second direction, and the top boundary and the bottom boundary of each of the first nanosheets have different second crystal plane directions.

[0006] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a fin-based structure extending from a top boundary of a substrate, wherein the fin-based structure is made of a first semiconductor material; forming a nanosheet-based structure protruding from a top boundary of the substrate, wherein the nanosheet-based structure includes one or more first nanosheets made of a second semiconductor material and one or more second nanosheets made of the first semiconductor material, and the one or more first nanosheets and the one or more second nanosheets are alternately arranged; and epitaxially growing a first source / drain (S / D) region, a second S / D region, and a third S / D region, wherein the first S / D region is arranged between the fin-based structure and the nanosheet-based structure, the second S / D region and the first S / D region are arranged relative to the fin-based structure, and the third S / D region and the first S / D region are arranged relative to the nanosheet-based structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An exemplary circuit diagram of a memory cell according to some embodiments is shown.

[0009] Figure 2 An exemplary circuit diagram of another memory cell according to some embodiments is shown.

[0010] Figure 3 A perspective view illustrating a memory device according to some embodiments.

[0011] Figure 4 A flow chart illustrating an exemplary method of manufacturing a memory device according to some embodiments.

[0012] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 According to some embodiments, Figure 4 A cross-sectional view of a memory device fabricated by a method at various fabrication stages.

[0013] Fig.23 A cross-sectional view of another memory device according to some embodiments is shown.

[0014] Fig.24 Shown is a graph comparing breakdown times between different lattice directions in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0017] In the manufacturing process of contemporary semiconductor devices, a large number of semiconductor devices (such as silicon channel n-type field effect transistors (nFETs) and silicon germanium channel p-type field effect transistors (pFETs)) are manufactured on a single wafer. Non-planar transistor device architectures (such as fin-based transistors) can provide higher device density and higher performance than planar transistors. Some advanced non-planar transistor device architectures (such as nanosheet (or nanowire) transistors) can further improve performance relative to fin-based transistors. Compared to fin-based transistors in which the channel is partially surrounded by a gate stack, nanosheet transistors typically include a gate stack that surrounds the entire periphery of one or more nanosheet channels to improve control of the channel current, for example, for similar sizes of fin-based transistors and nanosheet transistors, the drive current is relatively large.

[0018] Considering that nanosheet transistors outperform fin-based transistors, some existing memory devices have configured corresponding memory cells as nanosheet transistor configurations. For example, an anti-fuse memory cell may include a programming transistor and a reading transistor, each of which is configured as a nanosheet transistor. However, the corresponding active planes (e.g., one or more planes of the conductive channel) of the programming transistor and the reading transistor of the existing anti-fuse memory cell generally share the same or substantially similar lattice directions (crystallographic directions, directions of the crystal, or crystal directions), e.g. <110> Lattice direction. When the active plane of the programming transistor has <110> When the lattice direction is set, the programming transistor can provide good programming performance (for example, low breakdown voltage (V BD ), fast breakdown time (t BD ) etc.). However, when the active plane of the read transistor has <110> The performance of the read transistor may be impaired when the lattice direction Fig.24 Weibull plot (where the X axis represents t BD , the Y axis represents the probability), since the active plane is along <110> lattice direction, so with the <100> The active plane of the read transistor is extended in the lattice direction compared to the gate dielectric t BD can be relatively short, which is generally undesirable because the read transistor is designed not to break down. Therefore, existing anti-fuse memory devices are not entirely satisfactory.

[0019] The present disclosure provides various embodiments of memory cells. In some embodiments, the disclosed memory cell includes an anti-fuse memory cell, which includes a programming transistor and one or more read transistors. The programming transistor is configured as a fin-based transistor, and the one or more read transistors are each configured as a nanosheet transistor. The fin-based transistor and the one or more read transistors are electrically coupled to each other via one or more shared source / drain regions. In addition, the active plane of the programming transistor and the active plane of the one or more read transistors are different from each other. For example, the active plane of the fin-based programming transistor can be configured to have <110> lattice direction, and the active plane of the nanosheet read transistor can be configured to have <100> Lattice direction. Typically, when the active plane has <110> When the lattice direction is adjusted, the nanosheet transistor can show a significantly extended t BD In this way, the reliability of the reading transistor can be improved while maintaining the good programming performance of the programming transistor.

[0020] Figure 1 An exemplary circuit diagram of a memory cell 100 according to some embodiments is shown. As shown, the memory cell (or sometimes referred to as a memory bit cell, memory bit or bit) 100 includes a first transistor 110 and a second transistor 120. Each of the first and second transistors 110 and 120 may include an n-type metal oxide semiconductor field effect transistor (MOSFET). Transistors 110 and 120 may each include another type of MOSFET, for example, a p-type MOSFET. In some other embodiments, at least one of transistors 110 or 120 may be replaced by another type of electronic device (e.g., a MOS capacitor) while still within the scope of the present disclosure. The first transistor 110 and the second transistor 120 are electrically coupled to each other in series. For example, the source 110S of the first transistor is connected to the drain 120D of the second transistor.

[0021] The memory cell 100 may be configured as a one-time programmable (OTP) memory cell, such as an anti-fuse cell. It should be understood that the memory cell 100 may be configured as any type of memory cell including two transistors electrically coupled in series with each other (e.g., a NOR-type non-volatile memory cell, a dynamic random access memory (DRAM) cell, a two-transistor static random access memory (SRMA) cell, etc.).

[0022] When the memory cell 100 is configured as an anti-fuse cell, the first transistor 110 can be used as a programming transistor and the second transistor 120 can be used as a reading transistor. Thus, the drain 110D of the first transistor is floating (e.g., uncoupled), the gate 110G of the first transistor is coupled to a programming word line (WLP) 130; and the gate 120G of the second transistor is coupled to a reading word line (WLR) 132, and the source 120S of the second transistor is coupled to a bit line (BL) 134.

[0023] To program the memory cell 100, the read transistor 120 is turned on by providing a high voltage (e.g., a positive voltage corresponding to a logic high state) to the gate 120G via the WLR 132. Before, simultaneously with, or after the read transistor 120 is turned on, a sufficiently high voltage (e.g., a breakdown voltage (V BD )) is applied to WLP 130, and a low voltage (e.g., a positive voltage corresponding to a logic low state) is applied to BL 134. The low voltage (applied on BL 134) can be transferred to source 110S, so that V is created on source 110S and gate 110G. BD , to cause breakdown of a portion of the gate dielectric of the programming transistor 110 (e.g., the portion between the source 110S and the gate 110G). After programming the gate dielectric of the transistor 110, the portion interconnecting the gate 110G and the source 110S behaves equivalently as resistive. For example, such a portion may function as the resistor 136. Before programming (before the gate dielectric of the programming transistor 110 is broken down), when the read transistor 120 is turned on, there is no conductive path between the BL 134 and the WLP 130; after programming, when the read transistor 120 is turned on, there is a conductive path between the BL 134 and the WLP 130 (e.g., via the resistor 136).

[0024] To read the memory cell 100, similar to programming, the read transistor 120 is turned on and the BL 134 is coupled to a voltage corresponding to a logic low state. In response, a positive voltage is applied to the gate 110G of the programming transistor. As described above, if the gate dielectric of the programming transistor 110 is not broken down, there is no conductive path between the BL 134 and the WLP 130. Therefore, a relatively low current is conducted from the WLP 130 through the transistors 110 and 120 to the BL 134. If the gate dielectric of the programming transistor 110 is broken down, there is a conductive path between the BL 134 and the WLP 130. Therefore, a relatively high current is conducted from the WLP 130 through the transistor 110 (now equivalent to the resistor 136) and the transistor 120 to the BL 134. Such a low current and a high current may sometimes be referred to as the I of the memory cell 110, respectively. off and Ion Circuit components (eg, sense amplifiers) coupled to BL 134 may be configured to off with I on 1 (or vice versa), thereby determining whether the memory cell 100 presents a logic high (“1”) or a logic low (“0”). For example, when reading I on When 1 is read, the memory cell 100 may present a 1; and when 1 is read off , memory cell 100 may present a 0.

[0025] Figure 2 FIG. 2 shows an exemplary circuit diagram of another memory cell 200 according to some embodiments. The memory cell 200 is similar to Figure 1 The memory cell 100 is a memory cell 200, except that the memory cell 200 includes an additional read transistor. As shown, the memory cell 200 includes a first transistor 202, a second transistor 204, and a third transistor 206. Each of the first, second, and third transistors 202-206 may include an n-type MOSFET. In some other embodiments, each of the transistors 202-206 may include a p-type MOSFET while still within the scope of the present disclosure. The first transistor 202, the second transistor 204, and the third transistor 206 are electrically coupled in series with each other. For example, the source 202S of the first transistor is connected to the drain 204D of the second transistor, and the source 204S of the second transistor is connected to the drain 206D of the third transistor. The memory cell 200 can be used as an anti-fuse cell (as described above), wherein the first transistor 202 is used as a programming transistor for the anti-fuse cell, and the second and third transistors 204 and 206 are used together as read transistors for the anti-fuse cell. Similar to memory cell 100, gate 202G of the programming transistor is coupled to WLP 208, gates 204G and 206G of the read transistor are coupled to WLR0 210 and WLR1 212, respectively, and source 206S of the read transistor is coupled to BL 214. The operation of memory cell 200 is substantially similar to the operation of memory cell 100, and therefore, discussion will not be repeated.

[0026] refer to Figure 3 , shows a perspective view of an exemplary memory device 300 including a fin-based transistor and a nanosheet transistor. According to some embodiments, the memory device 300 may be part of an anti-fuse memory cell including a programming transistor and a reading transistor, such as the memory cell 100. Figure 3 The perspective view is an overview of the memory device 300, and thus, Figure 3 Certain features of the memory device 300 may not be identified in the following. Figure 5-Figure 22 More detailed features of the memory device 300 are shown and discussed in detail in the cross-sectional view of FIG.

[0027] The memory device 300 includes a programming transistor 302 and a reading transistor 304. In some embodiments, the programming transistor 302 is configured as a fin-based transistor, and the reading transistor is configured as a nanosheet transistor. The programming transistor 302 and the reading transistor 304 may be formed on (or include) a semiconductor structure (e.g., a substrate) 306. For example, above the semiconductor structure 306, the memory device 300 includes a first gate structure 308 and a second gate structure 310. The first gate structure 308 and the second gate structure 310, which are parallel to each other, may be oriented and elongated along a first lateral direction (e.g., a Y direction). On the respective sides of the first gate structure 308, a drain / source region 316 and a drain / source region 318 are formed. On the respective sides of the second gate structure 310, a drain / source region 318 and a drain / source region 320 are formed. The first gate structure 308 is formed to span the fin-based structure 312, which is coupled to the drain / source regions 316 and 318 at the respective ends. The second gate structure 310 is formed to surround a plurality of nanosheets 314a, 314b, 314c, and 314d, which are coupled to drain / source regions 318 and 320 at respective ends. In some embodiments, the fin-based structure 312 and the nanosheets 314a-d may be oriented and elongated along a second lateral direction (e.g., the X direction), which is the same direction along which the drain / source regions 316-320 are aligned with each other. In this way, the drain / source regions 316-320, the fin-based structure 312, and the nanosheets 314a-d may be formed within the same active region (sometimes referred to as an "oxide-defined (OD) region") on the semiconductor structure 306 (e.g., a semiconductor substrate / wafer). As shown, the nanosheets 314a-d may be characterized by a width (along the Y direction) W1, and the fin-based structure 312 may be characterized by a width (along the Y direction) W2, where W1 is substantially greater than W2. In some other embodiments, W1 may be equal to or substantially similar to W2.

[0028] Program transistor 302 may be formed of gate structure 308 (which serves as a gate of transistor 302), fin structure 312 (which serves as a conductive channel of transistor 302), drain / source region 316 (which serves as a drain of transistor 302), and source 318 (which serves as a source of transistor 302). Read transistor 304 may be formed of gate structure 310 (which serves as a gate of transistor 304), nanosheets 314a-d (which collectively serve as a conductive channel of transistor 304), drain / source region 318 (which serves as a source of transistor 304), and drain / source region 320 (which serves as a drain of transistor 304). Program transistor 302 and read transistor 304 are electrically coupled in series with each other via drain / source region 318.

[0029] According to various embodiments of the present disclosure, the respective conductive channels (fin-based structures 312) (nanosheets 314a-d) of the programming transistor 302 and the reading transistor 304 may be characterized by respective different lattice orientations. For example, the fin-shaped structures 312 may have <110> lattice direction, and the nanosheets 314a-d may have <100> Lattice direction. Specifically, the corresponding "active planes" of the conductive channels of the programming transistor 302 and the reading transistor 304 can be characterized by different crystal planes. The term "active plane" can refer to the plane along which the corresponding transistor conducts most of the current. For example, the programming transistor 302 can have an active plane along the sidewall 302a of the fin-based structure 302, and the reading transistor 304 can have an active plane along the top boundary and bottom boundary of each nanosheet (e.g., the top boundary 314a1 and the bottom boundary 314a2 of the nanosheet 314a). In some embodiments, the active plane of the programming transistor 302 (e.g., 312a) can be characterized by a {110} crystal plane (e.g., a (110) crystal plane), and the active plane of the reading transistor 304 (e.g., 314a1, 314a2) can be characterized by a {100} crystal plane (e.g., a (100) crystal plane).

[0030] In the following, crystallography will be briefly explained to facilitate understanding of the embodiments of the present disclosure. When dealing with crystal structures, it is useful to refer to lattice planes or lattice directions. In the symbols used to describe planes or directions, a set of three integers is used to indicate the position of a plane in the lattice or the direction of a vector. The three integers used to describe a certain plane in the lattice can be determined as follows.

[0031] First, find the intersection points where a certain plane intersects the three crystal axes and express them as integer multiples of the basis vectors. In this case, the plane can be moved while keeping its direction unchanged until the intersection between the plane and the crystal axis is found. Find the reciprocal of the intersection point and obtain the set of three integers h, k, and l with the minimum integer ratio while maintaining the same relationship. You can use parentheses () to represent the three integers h, k, and l.

[0032] The set of three integers h, k and l is called the Miller index, which is used to define parallel planes in the lattice. From a crystallographic point of view, many planes in the lattice are equivalent. In other words, a specific plane with a given Miller index can be moved in the lattice only according to the method of selecting the position and orientation of the unit cell. That is, the planes symmetrical with respect to the lattice axis are called equivalent planes in crystallography. Crystallographically equivalent planes are represented by curly braces {} instead of parentheses (). For example, the crystal plane {100} includes multiple equivalent crystal planes: (100), (010) and (001). In another example, the crystal plane {110} includes multiple equivalent crystal planes: (110), (011) and (101).

[0033] Meanwhile, directions in the lattice are represented as sets of three integers that have the same relationship to the components of the vector with that direction. The three components of the vector are represented as the product of the basis vectors, converted to the lowest integer ratio, and represented using square brackets []. Like the lattice planes, many directions in the lattice are equivalent, and equivalent directions are represented using angle brackets <>. For example, the lattice direction <100> Includes multiple equivalent lattice directions:

[100] ,

[010] ,

[001] , and In another example, the lattice direction <110> Includes multiple equivalent lattice directions:

[110] ,

[101] ,

[011] , and

[0034] From the previous overview of crystallography, it can be seen that for a cubic crystal (e.g., silicon), the crystal plane (001) is at right angles to the crystal plane (110) corresponding to the lattice direction

[110] . In other words, the crystal plane {100} is at right angles to the crystal plane corresponding to the lattice direction {100}. <110> The crystal plane {110} is at right angles. Therefore, when the <110> When etching a substrate having a crystal plane {100}, the etched portion of the substrate has a crystal plane {110}. <100> When a substrate having a crystal plane {111} is cut, the cut portion of the substrate has a crystal plane {100}. <110> When a substrate having a crystal plane {111} is cut, the cut portion of the substrate has a crystal plane {110}.

[0035] Reference again Figure 3 , and in more detail, the gate structure 310 may include a plurality of gate stacks. Each gate stack may include one or more gate dielectrics and one or more gate metals (for clarity in Figure 3 ). Two of the gate stacks are configured to jointly surround a corresponding one of the one or more nanosheets. For example, the gate structure 310 includes gate stacks 311a, 311b, 311c, 311d, and 311e. The gate stacks 311a-e may have a width (along the Y direction) substantially similar to the width (along the Y direction) of the gate structure 310, and the nanosheets 314a-d are characterized by a width W1 (along the Y direction) that is less than the width of the gate stacks 311a-e. Each of the gate stacks 311a-e may further include a portion extending along the Z direction to contact an adjacent gate stack. In this way, two adjacent ones of the gate stacks 311a-e may surround the entire perimeter of a corresponding one of the nanosheets 314a-d.

[0036] For example, gate stacks 311a and 311b may together surround at least four sides of nanosheet 314a, and two sides of nanosheet 314a are respectively coupled to drain / source region 318 and drain / source region 320; gate stacks 311b and 311c may together surround at least four sides of nanosheet 314b, and two sides of nanosheet 314b are respectively coupled to drain / source region 318 and drain / source region 320; gate stacks 311c and 311d may together surround at least four sides of nanosheet 314c, and two sides of nanosheet 314c are respectively coupled to drain / source region 318 and drain / source region 320; and gate stacks 311d and 311e may together surround at least four sides of nanosheet 314d, and two sides of nanosheet 314d are respectively coupled to drain / source region 318 and drain / source region 320.

[0037] Figure 4 A flow chart of a method 400 of forming a memory device according to one or more embodiments of the present disclosure is shown. The method 400 may be used to form an anti-fuse memory cell that includes a fin-based programming transistor and a nanosheet read transistor coupled in series. For example, at least some of the operations described in the method 400 may be used to form the memory device 300. It is noted that the method 400 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 400 may be used in the present disclosure. Figure 4 Additional operations are provided before, during, and after method 400, and only some of the other operations are briefly described here.

[0038] The operations of method 400 may be performed in the Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 The cross-sectional view of the memory device 300 taken along the line AA' at the corresponding manufacturing stage shown is related. In some embodiments, the memory device 300 may be included in or coupled with a microprocessor, another memory device, and / or other integrated circuit (IC). In addition, in order to better understand the concepts of the present disclosure, the Figure 5-Figure 22Although the figures show a memory device 300, it should be understood that the IC may include many other devices, such as inductors, resistors, capacitors, transistors, etc., which are not shown in the figure for the sake of clarity. Figure 5-Figure 22 Not shown.

[0039] First reference Figure 4 In brief overview, method 400 begins with operation 402, wherein a semiconductor structure is provided. Method 400 proceeds to operation 406, wherein a patterned mask is formed to cover a first region of a semiconductor substrate and expose a second region of the semiconductor structure. Method 400 proceeds to operation 408, wherein a recess is formed by etching the semiconductor structure in the second region. Method 400 proceeds to operation 410, wherein a dielectric layer is deposited to cover the semiconductor structure. Method 400 proceeds to operation 412, wherein a portion of the dielectric layer is etched to expose a bottom boundary of the recess. Method 400 proceeds to operation 414, wherein a plurality of first and second semiconductor layers alternately stacked in the recess are epitaxially grown. Method 400 proceeds to operation 416, wherein a polishing process is performed. Method 400 proceeds to operation 418, wherein a dummy gate stack is formed. Method 400 proceeds to operation 420, wherein a fin-based structure is covered. Method 400 proceeds to operation 422, wherein ends of the first semiconductor layer of the alternating nanosheet pillars are removed. The method 400 proceeds to operation 424, wherein internal spacers in the alternating nanosheet pillars are formed. The method 400 proceeds to operation 426, wherein drain / source regions are formed. The method 400 proceeds to operation 428, wherein an interlayer dielectric (ILD) material is deposited. The method 400 proceeds to operation 430, wherein the dummy gate stack is removed. The method 400 proceeds to operation 432, wherein the first semiconductor layer of the alternating nanosheet pillars is removed. The method 400 proceeds to operation 434, wherein a gate dielectric is deposited. The method 400 proceeds to operation 436, wherein a gate metal is deposited.

[0040] Corresponding to operation 402, Figure 5 is a memory device 300 including a semiconductor structure 306 along line AA′ ( Figure 3). The semiconductor structure 306 includes a semiconductor material substrate, such as silicon. In the present embodiment, based on the above crystallographic overview, the crystal structure of such a silicon substrate has a top boundary 306a in a {100} crystal plane (e.g., a (100) crystal plane). Alternatively, the semiconductor structure 306 may include other elemental semiconductor materials, such as germanium. The semiconductor structure 306 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The semiconductor structure 306 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and gallium indium phosphide. In one embodiment, the semiconductor structure 306 includes an epitaxial layer. For example, the semiconductor structure 306 may have an epitaxial layer located above a bulk semiconductor. In addition, the semiconductor structure 306 may include a semiconductor on an insulator (SOI) structure. For example, the semiconductor structure 306 may include a buried oxide (BOX) layer, wherein the buried oxide layer is formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0041] Corresponding to operation 404, Figure 6 The memory device 300 includes a patterned mask located on the top boundary 306a of the semiconductor structure 306 along the line AA' ( Figure 3 ). The patterned mask covers the first region 321a and includes an opening that exposes the second region 321b of the semiconductor structure 306. In one embodiment, the first region 321a is a portion of the semiconductor structure 306 that is configured as one or more programming transistors (e.g., Figure 3 301) as shown, and the second region 321b is a region of the semiconductor structure 306 for one or more read transistors (eg, Figure 3 It should be understood that the semiconductor device 300 may alternatively have p-type transistors in the regions 321a-b.

[0042] The patterned mask may be a soft mask such as a patterned resist layer, or a hard mask such as a dielectric material layer, or a combination thereof. In one embodiment, the patterned mask includes a hard mask 322 disposed on the region 321a and a patterned resist layer 323 formed on the hard mask 322 by a photolithography process. The hard mask 322 is etched to transfer the opening from the patterned resist layer 323 to the hard mask 322. For example, the hard mask 322 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxynitride, other semiconductor materials and / or other dielectric materials. In an embodiment, the thickness of the hard mask 322 is in the range of about 1nm to about 40nm. The hard mask 322 may be formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other appropriate method. An exemplary photolithography process may include forming a resist layer, exposing the resist by a photolithography exposure process, performing a post-exposure baking process, and developing the photoresist layer to form a patterned photoresist layer. The photolithography process may alternatively be replaced with other techniques such as electron beam writing, ion beam writing, maskless patterning or molecular printing. In some embodiments, the patterned resist layer 323 may be directly used as an etching mask for a subsequent etching process. After patterning of the hard mask 322, the patterned resist layer 323 may be removed by an appropriate process such as wet stripping or plasma ashing.

[0043] Corresponding to operation 406, Figure 7 The memory device 300 is a device in which the semiconductor structure 306 is etched to form the recess 324 in one of the various stages of manufacturing along the line AA' ( Figure 3 ). The semiconductor structure 306 in the second region 321b is etched to form a recess 324. The etching process is designed to selectively remove the semiconductor structure 306 in the second region 321b using the hard mask 322 as an etching mask. The etching process may be continued to ensure that the boundary 325 of the semiconductor structure 306 is exposed in the recess 324. The sidewall 326 of the semiconductor structure 306 in the first region 321a is also exposed, thereby defining the edge of the recess 324. The etching process may include dry etching, wet etching, or a combination thereof. The patterned mask 322 protects the semiconductor structure 306 in the first region 321a from etching. In various examples, the etching process may include dry etching using a suitable etchant, such as a fluorine-containing etching gas or a chlorine-containing etching gas, such as Cl2, CCl2F2, CF4, SF6, NF3, CH2F2, or other suitable etching gases. In some other examples, the etching process may include wet etching using a suitable etchant, such as a hydrofluoric acid (HF)-based solution, a sulfuric acid (H2SO4)-based solution, a hydrochloric acid (HCl)-based solution, an ammonium hydroxide (NH4OH)-based solution, other suitable etching solutions, or combinations thereof. The etching process may include more than one step.

[0044] Corresponding to operation 408, Figure 8 is a memory device 300 including a dielectric layer 327 along line AA' ( Figure 3 ) is a cross-sectional view taken from FIG. The dielectric layer 327 may conformally cover the memory device 300 in the two regions 321a-b. The dielectric layer 327 is deposited as a blanket layer. In an embodiment, the thickness of the dielectric layer 327 is in the range of about 1nm to about 40nm. The dielectric layer 327 may include semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbon nitrides, semiconductor carbon oxynitrides, and metal oxides, such as hafnium oxide, zirconium oxide, and aluminum oxide, other dielectrics, and / or other suitable materials. The dielectric layer 327 may be selected to have an etching selectivity different from that of the hard mask 322. In an example, the hard mask 322 includes silicon oxide, and the dielectric layer 327 includes silicon nitride. In another example, the hard mask 322 includes silicon oxynitride, and the dielectric layer 327 includes aluminum oxide. In yet another example, the hard mask 322 includes silicon oxynitride, and the dielectric layer 327 includes zirconium oxide. Dielectric layer 327 may be deposited over hard mask 322, sidewalls 326 and boundaries 325 of semiconductor structure 306 by any suitable process including atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or other suitable deposition techniques. Conformal deposition techniques may be used.

[0045] Corresponding to operation 410, Fig. 9 The memory device 300 is a device in which one or more portions of the dielectric layer 327 are removed during one of the various stages of manufacturing along the line AA' ( Figure 3 ). In some embodiments, portions of the dielectric layer 327 deposited on horizontal boundaries of the memory device 300 are removed (e.g., portions of the dielectric layer 327 covering the hard mask 322, portions of the dielectric layer 327 covering the boundary 308), while the sidewalls 326 of the semiconductor structure 306 in the first region 321 a remain covered by the remaining portions of the dielectric layer 327.

[0046] To perform the removal, an anisotropic etch, such as dry etching or plasma etching, may be performed to etch back and remove those portions of the dielectric layer 327 deposited on the horizontal surface of the hard mask 322 and the boundary 308 of the semiconductor structure 306. In this way, only those portions of the dielectric layer 327 deposited on the sidewalls 306 remain. Since the etching sensitivity of each component is different, portions of the dielectric layer 327 can be selectively etched without etching (or without significant etching) the hard mask 322. Various etching parameters may be adjusted to etch the dielectric layer 327, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters or combinations thereof. In some embodiments, after the anisotropic etching, the thickness of the hard mask 322 is reduced by about 5% to 15%, such as from a thickness of about 40nm to about 35nm. The dielectric layer 327 deposited on the sidewalls 306 may also suffer some material loss due to the anisotropic etching. In some embodiments, the thickness of dielectric layer 327 is reduced by about 8% to 20%, such as from a thickness of about 40 nm to about 35 nm.

[0047] Corresponding to operation 412, Fig.10 A memory device 300 including a plurality of first semiconductor layers 328 (eg, 328a, 328b, 328c, and 328d) and a plurality of second semiconductor layers 330 (eg, 330a, 330b, 330c, and 330d) in one of the various stages of manufacturing is shown along line AA' ( Figure 3 ) is a cross-sectional view taken from FIG. 3 . In some embodiments, the first semiconductor layer 328a-d and the second semiconductor layer 330a-d are formed in the recess 324 ( Fig. 9 ) are alternately arranged with each other (e.g., along the Z direction) to form a stack. For example, one of the second semiconductor layers 330a is arranged on one of the first semiconductor layers 328a, and then another one of the second semiconductor layers 328b is arranged on the second semiconductor layer 330a, and so on.

[0048] In various embodiments, the stack may include any number of alternating semiconductor layers 328 and 330. The semiconductor layers 328 and 330 may have different thicknesses. The semiconductor layer 328 may have different thicknesses from each other. The semiconductor layer 330 may have different thicknesses from each other. The thickness of each of the semiconductor layers 328 and 330 may be in the range of several nanometers to tens of nanometers. The first layer of the stack may be thicker than the other semiconductor layers 328 and 330. For example, layer 328a may be thicker than the other layers 328b-d and 330a-d. In an embodiment, each of the first semiconductor layers 228a-d has a thickness in the range of about 5nm to about 20nm, and each of the second semiconductor layers 330a-d has a thickness in the range of about 5nm to about 20nm.

[0049] The two semiconductor layers 328 and 330 have different compositions. In various embodiments, the two semiconductor layers 328 and 330 have compositions that provide different oxidation rates and / or different etching selectivities between the layers. In an embodiment, the semiconductor layer 328 includes silicon germanium (Si 1-x Ge x ), and the semiconductor layer 330 includes silicon (Si). In an embodiment, each semiconductor layer 330 is silicon, which may be undoped or substantially free of dopants (ie, having a thickness from about 0 cm -3 to about 1×10 17 cm -3 The concentration of non-intrinsic dopants is determined by the semiconductor layer 330. For example, when forming the layer 328 (e.g., silicon), unintentional doping is performed. Alternatively, the semiconductor layers 330 may be intentionally doped. For example, each semiconductor layer 330 may be silicon doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga) to form a p-type channel, or an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb) to form an n-type channel. In some embodiments, each semiconductor layer 328 is Si 1-x Ge x , which includes Ge in a molar ratio of less than 50% (x < 0.5). For example, Ge may account for Si in a molar ratio of 1-x Ge x The semiconductor layer 328 may include about 15% to 35% of the semiconductor layer 328. In addition, the semiconductor layers 328 may include different compositions therebetween, and the semiconductor layers 330 may include different compositions therebetween.

[0050] In various embodiments, any of the semiconductor layers 328 and 330 may include other materials, for example: a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or a combination thereof. The materials of the semiconductor layers 328 and 330 may be selected based on providing different oxidation rates and / or etching selectivities. As described above, the semiconductor layers 328 and 330 may be doped or undoped.

[0051] In various embodiments, the semiconductor layers 328 and 330 are epitaxially grown from the boundary 308 of the semiconductor structure 306 in the second region 321 b. For example, each of the semiconductor layers 328 and 330 may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and / or other suitable epitaxial growth processes. During the epitaxial growth, the crystal structure of the semiconductor structure 306 is extended upward (e.g., in the Z direction), resulting in the semiconductor layers 328 and 330 having the same crystal orientation as the semiconductor structure 306.

[0052] In the first region 321a, the hard mask 322 acts as a capping layer on the top boundary 306a of the semiconductor structure 306, thereby preventing epitaxial growth from occurring in the first region 321a. When in the second region 321b, the dielectric layer 327 covers the sidewall 306, thereby preventing epitaxial growth from originating from the sidewall 306, so that epitaxial growth does not occur in the lateral direction from the sidewall 306 to the second region 321b. Therefore, in some embodiments, the epitaxial growth of the semiconductor layers 328 and 330 is confined to the recess 324 ( Fig. 9 )middle.

[0053] In various embodiments of the present disclosure, the crystal structure of semiconductor structure 306 has a top boundary 306a in a {100} crystal plane. Therefore, each of the epitaxially grown semiconductor layers 328 and 330 has a corresponding top / bottom boundary in the same {100) crystal plane. In some other embodiments, semiconductor structure 306 may have a top boundary in one of the crystal planes different from the {100} crystal plane, such as in a {110} crystal plane. Therefore, the epitaxially grown semiconductor layers 328 and 330 maintain the same crystal structure and present the same {110} crystal plane in the corresponding top / bottom boundaries.

[0054] Corresponding to operation 414, Fig.11 The memory device 300 is subjected to a polishing process in one of the various stages of manufacturing along the line AA' ( Figure 3). A polishing process (eg, a chemical mechanical polishing (CMP) process) is configured to planarize the top boundary of the semiconductor structure 306 after the epitaxial growth of the semiconductor layers 328 and 330. Fig.10 The hard mask layer 322 may be used as a CMP stop layer in operation 414. Operation 414 may also remove the hard mask layer 322. As a result, the semiconductor structure 306 in the first region 321a is exposed again to form a portion of a top boundary of the semiconductor structure 306.

[0055] Corresponding to operation 416, Fig.12 The memory device 300 including the first dummy gate stack 332a and the second dummy gate stack 332b in one of the various stages of manufacturing is shown along the line AA′ ( Figure 3 ) is a cross-sectional view taken from FIG. Each of the dummy gate stacks 332a-b includes a dummy gate and a hard mask. Fig.12 In the present invention, the first dummy gate stack 332a includes a dummy gate 333a formed above the semiconductor structure 306 in the first region 321a and a hard mask 334a formed above the dummy gate 333a; and the second dummy gate stack 332b includes a dummy gate 333a formed above the semiconductor layer 330d in the second region 321b and a hard mask 334b ​​formed above the dummy gate 333b.

[0056] In some embodiments, a dummy gate stack 332a may be formed over and around the sidewalls of the semiconductor structure 306 in the first region 321a, and a dummy gate 332b may be formed over and around the sidewalls of the semiconductor layers 328 and 330 in the second region 321b. Dummy gates 333a and 333b may be formed by depositing amorphous silicon (a-Si) over and around the semiconductor structure 306 in the first region 321a and the semiconductor layers 328 and 330 in the second region 321b, respectively. The a-Si is then flattened to a desired level. A hard mask (not shown) is deposited over the flattened a-Si and patterned to form hard masks 334a and 334b. The hard masks 334a and 334b ​​may be formed of a nitride or oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form dummy gate stacks 332a and 332b.

[0057] After forming the dummy gate stacks 332a and 332b, offset gate spacers 335a and 335b may be formed to extend along respective sidewalls of the dummy gate stacks 332a and 332b, as shown in FIG. Fig.12As shown. The offset gate spacers 335a-b may be formed using a spacer pull-down formation process. The offset gate spacers 335a-b may also be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials) followed by directional etching (e.g., RIE).

[0058] Corresponding to operation 418, Fig.13 is one of the various stages of manufacturing including a fin-based structure 312 (eg Figure 3 ) and the memory device 300 having alternating nanosheet pillars 338 along line AA′ ( Figure 3 ). The fin-based structure 312 and the alternating nanosheet pillars 338 are both formed to protrude from the rest of the semiconductor structure 306. Specifically, the fin-based structure 312 is an integrally continuous structure extending from the semiconductor structure 306. The fin-based structure 312 can be elongated in a lateral direction (e.g., X direction). The alternating nanosheet pillars 338 include nanosheets 314a-d ( Figure 3 314a-d) and a stack of nanosheets 339a, 339b, 339c and 339d interlaced with nanosheets 314a-d. In the formation of the fin-based structure 312 and the alternating nanosheet pillars 338, the dummy gate stack 332a-b together with the corresponding offset gate spacers 335a-b can be used as a mask to define the occupied area of ​​the fin-based structure 312 and the alternating nanosheet pillars 338, and one or more etching processes can be applied to the semiconductor structure 306 in the first region 321a and the semiconductor layers 328 and 330 in the second region 321b (enclosed by dashed lines), respectively, to form the fin-based structure 312 and the alternating nanosheet pillars 338. As such, nanosheets 339a, 314a, 339b, 314b, 339c, 314c, 339d, and 314d may be the remainder of semiconductor layers 328a, 330a, 328b, 330b, 328c, 330c, 328d, and 330d, respectively.

[0059] One or more etching processes may include one or more dry etching processes, wet etching processes, and other suitable etching techniques. For example, the dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in the following etchants: diluted hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; aqueous ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants.

[0060] In some embodiments, the orientation of the dummy gate stack 332a can be set so that the top boundary 312b of the etched fin-based structure 312 has a {100} crystal plane and the sidewall 312a ( Figure 3 In the above example, where the crystal structure of the semiconductor structure 306 (e.g., Si wafer) has a top boundary in the {100} crystal plane, the semiconductor structure 306 can have a flat region in the {110} crystal plane, as manufactured. The orientation of the pseudo gate stack 332a can be parallel or perpendicular to the flat region. Therefore, through one or more etching processes (e.g., anisotropic etching processes), each sidewall 312a of the fin-based structure 312 can be characterized as having the same {110} crystal plane as the flat region. Based on the aforementioned crystallographic overview, the fin-based structure 312 can sometimes be referred to as having <110> Lattice directions, including lattice directions:

[110] ,

[101] ,

[011] , and As described above, the respective top / bottom boundaries of the epitaxially grown semiconductor layers 328 and 330 each have the same {100} crystal plane. After the etching process, the respective top / bottom boundaries of the nanosheets 339a-d and 314a-d (e.g., Figure 3 The nanosheets 314a1 and 314a2 in FIG. 314a-d may inherit the same {100} crystal plane. Nanosheets 314a-d are sometimes referred to as having <100> Lattice directions, including lattice directions:

[100] ,

[010] ,

[001] , or

[0061] Corresponding to operation 420, Fig.14 The memory device 300 is shown with the fin-based structure 312 covered by the blocking mask 340 along the line AA′ ( Figure 3). In some embodiments, the blocking mask 340 is formed to cover the fin-based structure 312 in the first region 321a while exposing the alternating nanosheet pillars 338 in the second region 321b. The blocking mask 340 can be formed to have a sufficiently large thickness (or height) so that the sidewalls 312a of the fin-based structure 312 are completely covered. The formation of the blocking mask 340 can allow one or more processes to be performed only on the alternating nanosheet pillars 338, which will be discussed below. The blocking mask 340 can be formed of a material that is relatively resistant to etchants that can etch SiGe, such as silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials.

[0062] Corresponding to operation 422, Fig.15 is the removal of nanosheets 339a-d ( Fig.14 ) of each of the memory devices 300 at the corresponding ends along line AA'( Figure 3 ) is a cross-sectional view taken from FIG. 3 . During the removal of the respective ends of the nanosheets 339a-d in the alternating nanosheet column 338, the fin-based structure 312 is covered by a blocking mask 340. In this way, the fin-based structure 312 can remain intact. The remaining nanosheets 339a', 339b', 339c', and 339d' can be replaced by multiple gate stacks later. Therefore, the remaining nanosheets 339a'-d' can be referred to as sacrificial nanosheets 339a'-d' in this article. For the alternating nanosheet column 338.

[0063] In some embodiments of the present disclosure, the ends of the nanosheets 339a-d may be removed using a first application, a so-called "pull-back" process to pull the nanosheets 339a-d back to the initial pull-back distance, such that the ends of the sacrificial nanosheets 339a'-d' terminate underneath (e.g., aligned with) the offset gate spacer 335b. Fig.15 In the illustrated embodiment, the end of each of the sacrificial nanosheets 339a'-d' is substantially aligned with the sidewall of the offset gate spacer 335b, but it should be understood that the pullback distance (i.e., the degree to which each of the sacrificial nanosheets 339a'-d' is etched or pulled back) can be increased or decreased arbitrarily. According to various embodiments of the present disclosure, the nanosheets 314a-d include Si, and the nanosheets 339a-d include Si 1-x Ge x Thus, the pull-back process may include a hydrogen chloride (HCL) gas isotropic etching process that etches SiGe without corroding Si.

[0064] Corresponding to operation 424, Fig.16is a memory device 300 including internal spacers 342, 344, 346, and 348 along line AA' ( Figure 3 ) is a cross-sectional view taken from FIG. 3 . During the formation of the internal spacers 342-348, the fin-based structure 312 is still covered by the blocking mask 340. In this way, only the alternating nanosheet pillars 338 have internal spacers 342-348 set along the corresponding sidewalls of the sacrificial nanosheets 339a'-d'. In some embodiments, the internal spacers 342-348 can be conformally formed by chemical vapor deposition (CVD) or by single-layer doping (MLD) of nitride and subsequent spacer RIE. In some other embodiments, the internal spacers 342-348 can be deposited using, for example, a conformal deposition process and subsequent isotropic or anisotropic etching back to remove excess spacer material on the vertical sidewalls of the alternating nanosheet pillars 338 and on the surface of the semiconductor structure 306. The material of the internal spacers 342-348 can be formed of the same or different material as the offset gate spacers 335a-b (e.g., silicon nitride). For example, the inner spacers 342 - 348 may be formed of silicon nitride, silicon carbon boron nitride, silicon carbon nitride, silicon carbon oxynitride, or any other type of dielectric material suitable for forming insulating gate sidewall spacers for transistors (eg, a dielectric material having a dielectric constant k less than about 5).

[0065] Corresponding to operation 426, Fig.17 The drain / source regions 316, 318 and 320 ( Figure 3 The memory device 300 shown in FIG. 1 is arranged along line AA′ ( Figure 3 ) is a cross-sectional view taken from FIG. The blocking mask 340 ( Fig.16 338). Drain / source regions 316-320 are formed after the fin-based structure 312 is formed (as shown). In some embodiments, the drain / source region 316 can be formed on one exposed end of the fin-based structure 312 (e.g., the left side of the fin-based structure 312) using an epitaxial layer growth process. The drain / source region 318 can be formed on the other exposed end of the fin-based structure 312 (e.g., the right side of the fin-based structure 312) and one exposed end of each of the nanosheets 314a-d (e.g., the left side of the alternating nanosheet pillars 338) using the same epitaxial layer growth process. The drain / source region 320 is formed on the other exposed end of each of the nanosheets 314a-d (e.g., the right side of the alternating nanosheet pillars 338) using the same epitaxial layer growth process. In some embodiments, the bottom boundary of the drain / source region 318 can be in full contact with the semiconductor structure 306 (e.g., no additional features are formed between the drain / source region 318 and the semiconductor structure 306).

[0066] According to some embodiments, drain / source region 316 and drain / source region 318 are electrically coupled to fin-based structure 312; drain / source region 318 and drain / source region 320 are electrically coupled to nanosheets 314a-d. Fin-based structure 312 can serve as a conductive channel for programming transistor 302; and nanosheets 314a-d can collectively serve as a conductive channel for reading transistor 304. In addition, programming transistor 302 can be electrically coupled in series to reading transistor 304 via drain / source region 318.

[0067] In-situ doping (ISD) may be applied to form doped drain / source regions 316-320 to create the necessary junctions for programming transistor 302 and reading transistor 304. N-type and p-type FETs are formed by implanting different types of dopants into selected regions of the device (e.g., drain / source regions 316-320) to form the necessary junctions. N-type devices may be formed by implanting arsenic (As) or phosphorus (P), while p-type devices may be formed by implanting boron (B).

[0068] Corresponding to operation 428, Fig.18 is a memory device 300 including an interlayer dielectric (ILD) material 350 along line AA′ ( Figure 3 ). The ILD material 350 may be formed by depositing a bulk oxide material (eg, silicon dioxide) and then back-polishing the bulk oxide (eg, using CMP) to the level of the offset gate spacers 335a-b and the hard masks 334a-b.

[0069] Corresponding to operation 430, Fig.19 The dummy gate stack 332a-b is removed during one of the various stages of manufacturing. Fig.18 ) of the memory device 300 along line AA'( Figure 3 ) is a cross-sectional view taken from FIG. After forming the protective ILD material 350, as shown in FIG. Fig.18 Dummy gate stacks 332a (including dummy gate 333a and hard mask 334a) and 332b (including dummy gate 333b and hard mask 334b) are shown removed. The dummy gate stacks 332a-b may be removed by a known etching process such as RIE or chemical oxide removal (COR).

[0070] After removing the dummy gate stack 332a, the top boundary of the fin-based structure 312 may be exposed. Fig.19, but it should be understood that in addition to the top boundary, the corresponding sidewall 312a of the fin-based structure 312 may also be exposed. Similarly, after removing the dummy gate stack 332b, the top boundary of the alternating nanosheet pillars 338 may be exposed. Specifically, the top boundary 314d2 of the nanosheet 314d may be exposed. Although in Fig.19 Not shown in the cross-sectional view of , it is understood that in addition to the top boundaries, the sidewalls of the alternating nanosheet pillars 338 (eg, the corresponding sidewalls of the nanosheets 314a-d) may also be exposed.

[0071] Corresponding to operation 432, Fig. 20 is a sacrificial nanosheet 339a'-d' ( Fig.19 ) of the memory device 300 along line AA'( Figure 3 ). The sacrificial nanosheets 339a'-d' can be removed by applying a selective etch (e.g., hydrochloric acid (HCl)). After removing the sacrificial nanosheets 339a'-d', the corresponding bottom boundaries (314a1, 314b1, 314c1, and 314d1) of the nanosheets 314a-d and the corresponding top boundaries (314a2, 314b2, and 314c2) of the nanosheets 314a-c can be exposed.

[0072] As described above, the fin-based structure 312 can be used as a conductive channel of the programming transistor 302 to conduct current flowing therethrough, and the nanosheets 314a-d can be used together as a conductive channel of the reading transistor 304 to conduct current flowing therethrough. In addition, the active plane of the conductive channel of the programming transistor 302 can include the sidewall 312a, and the active plane of the conductive channel of the reading transistor 304 can include the respective top boundaries 314a2, 314b2, 314c2, and 314d2 of the nanosheets 314a-d and the respective bottom boundaries 314a1, 314b1, 314c1, and 314d1 of the nanosheets 314a-d. By using the manufacturing methods disclosed herein, the programming transistor 302 can be characterized with an active plane having a {110} crystal plane, and the reading transistor 304 can be characterized with an active plane having a {100} crystal plane. In this way, the excellent programming performance of the programming transistor 302 and the improved reliability of the reading transistor 304 can be achieved simultaneously.

[0073] Corresponding to operation 434, Fig.21 is a memory device 300 including gate dielectrics 354a and 354b along line AA′ ( Figure 3) is a cross-sectional view taken from FIG. As shown, gate dielectric 354a is in direct contact with fin-based structure 312; and gate dielectric 354b surrounds each of nanosheets 314a-d. Fig.21 , but it should be understood that the gate dielectric 354a is formed across the top boundary and sidewalls 312a of the fin-based structure 312, and the gate dielectric 354b is formed around each of the nanosheets 314a-d (e.g., the top / bottom boundaries and the sidewalls perpendicular to the Y direction). The gate dielectrics 354a and 354b can be formed of different high-k dielectric materials or the same high-k dielectric material. The gate dielectrics 354a and 354b can include stacks of multiple high-k dielectric materials. The gate dielectrics 354a and 354b can be deposited simultaneously or separately using any suitable method including, for example, atomic layer deposition (ALD). In some embodiments, the gate dielectrics 354a and 354b can optionally include a substantially thin oxide (e.g., SiO x )layer.

[0074] Corresponding to operation 436, Fig. 22 is a memory device 300 including gate metals 356a and 356b along line AA′ ( Figure 3 ) is a cross-sectional view taken from FIG. 3. In some embodiments, gate metal 356a may span the top boundary and sidewall 312a of fin-based structure 312, with gate dielectric 354a disposed therebetween. Gate metal 356b may surround each of nanosheets 314a-d, with gate dielectric 354b disposed therebetween. In some embodiments, gate structure 308( Figure 3 ) includes a gate metal 356a, a corresponding gate dielectric 354a and an offset gate spacer 335a; and the gate structure 308 ( Figure 3 ) includes a gate metal 356b, a corresponding gate dielectric 354b and an offset gate spacer 335b. The gate metals 356a-b can be formed of different metal materials or the same metal material. The gate metals 356a-b can each include a stack of multiple metal materials. It should be understood that the gate metals 356a-b can each include any of other types of conductor materials while still within the scope of the present disclosure. Any suitable method including, for example, CVD can be used to deposit the gate metals 356a-b.

[0075] Although gate metals 356a-b are each Fig. 22356a-b are shown as a two-dimensional structure, but it should be understood that the gate metals 356a-b are formed as three-dimensional structures. Specifically, the gate metals 356a-b can each include a plurality of gate metal portions spaced apart from each other along the Z direction. Each gate metal portion can extend not only along a horizontal plane (e.g., a plane extending along the X direction and the Y direction), but also along a vertical direction (e.g., the Z direction). In this way, two adjacent gate metal portions can be adjacent to each other to surround the corresponding nanosheet, and the gate dielectric is disposed therebetween.

[0076] For example, Fig. 22 In the embodiment of the present invention, the gate metal 356b may include multiple gate metal portions. Two adjacent gate metal portions may be adjacent to each other to surround one of the nanosheets 314a-d, and a portion of the gate dielectric 354b is disposed therebetween. In some embodiments, such a gate metal portion that at least partially surrounds one of the Si nanosheets and a corresponding portion of the gate dielectric may be collectively referred to as a gate stack. The gate stack is operably associated with the surrounding Si nanosheet (e.g., modulating the current conducted in the nanosheet). The gate stack may sometimes be referred to as a full-ring gate stack.

[0077] Fig.23 A cross-sectional view of another exemplary memory device 500 is shown. According to some embodiments, the memory device 500 may be part of an anti-fuse memory cell that includes a programming transistor and a plurality of read transistors, such as the memory cell 200. The memory device 500 is substantially similar to the memory device 300, except that the memory device 500 includes an additional read transistor. Therefore, the following discussion will focus on the differences between the memory devices 300 and 500.

[0078] As shown, the memory device 500 includes a programming transistor 502, a first reading transistor 504, and a second reading transistor 506 formed on a substrate 508. The programming transistor 502 is formed as a fin-based transistor, and the reading transistors 504 and 506 are both formed as nanosheet transistors. For example, the programming transistor 502 includes: a fin-based structure 509 extending from the substrate 508, a gate structure 510 across the fin-based structure 509, and drain / source regions 512 and 514 formed on respective sides of the fin-based structure 509; the reading transistor 504 includes: a plurality of nanosheets 516 spaced vertically apart from each other, a gate structure 518 surrounding each nanosheet 516, and drain / source regions 514 and 520 formed on respective sides of the nanosheet 516; and the reading transistor 506 includes: a plurality of nanosheets 522 spaced vertically apart from each other, a gate structure 524 surrounding each nanosheet 522, and drain / source regions 520 and 526 formed on respective sides of the nanosheet 522. The read transistor 504 may also include a plurality of internal spacers 517 disposed between a portion of a gate structure 518 and the drain / source region 514 and between a portion of the gate structure 518 and the drain / source region 520. The read transistor 506 may also include a plurality of internal spacers 523 disposed between a portion of a gate structure 524 and the drain / source region 520 and between a portion of the gate structure 524 and the drain / source region 526. The transistors 502-506 may be at least partially embedded in the ILD material 530.

[0079] In some embodiments, the fin-based structure 509 of the programming transistor 502 can have a first lattice orientation, and the corresponding nanosheets 516 and 522 of the reading transistors 504 and 506 can have a different second lattice orientation. For example, the fin-based structure 509 has a {110} lattice orientation, and the nanosheets 516 and 522 have a {100} lattice orientation. Specifically, the sidewall 408a of the fin-based structure 509 can be characterized by a {110} crystal plane, the top boundary and the bottom boundary (e.g., 516a, 516b) of each nanosheet 516 can be characterized by a {100} crystal plane, and the top boundary and the bottom boundary (e.g., 522a, 522b) of each nanosheet 522 can be characterized by the same {100} crystal plane.

[0080] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets formed on the substrate and spaced vertically apart from each other. The semiconductor device includes a first source / drain (S / D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S / D region electrically coupled to both a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S / D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first lattice direction, and the plurality of first nanosheets have a second lattice direction different from the first lattice direction.

[0081] In the above semiconductor device, the first lattice direction includes <110> A lattice direction, and the different second lattice direction includes a

[100] lattice direction.

[0082] In the semiconductor device, the first lattice direction includes at least one of the following lattice directions:

[110] ,

[101] ,

[011] , or The different second lattice directions include at least one of the following lattice directions:

[100] ,

[010] ,

[001] , or

[0083] In the above semiconductor device, sidewalls of the fin-based structure each have a {110} crystal plane, and a top boundary of each of the plurality of first nanosheets has a {100} crystal plane.

[0084] In the above-mentioned semiconductor device, the fin-based structure, the first S / D region and the second S / D region are configured as at least a part of the programming transistor of the anti-fuse memory cell, and the multiple first nanosheets, the second S / D region and the third S / D region are configured as at least a part of the reading transistor of the anti-fuse memory cell.

[0085] In the above semiconductor device, the read transistor is electrically coupled to the programming transistor in series via a second shared S / D region.

[0086] In the above-mentioned semiconductor device, it also includes: a plurality of second nanosheets vertically spaced apart from each other, formed on the substrate, the third S / D region coupled to the first ends of the plurality of first nanosheets; a fourth S / D region electrically coupled to the second ends of the plurality of second nanosheets, wherein the plurality of second nanosheets have the second lattice direction.

[0087] In the above semiconductor device, sidewalls of the fin-based structure each have a {110} crystal plane, and a top boundary of each of the plurality of first nanosheets and the plurality of second nanosheets each have a {100} crystal plane.

[0088] In the above-mentioned semiconductor device, the fin-based structure, the first S / D region and the second S / D region are configured as at least a part of the programming transistor of the anti-fuse memory cell, the multiple first nanosheets, the second S / D region and the third S / D region are configured as at least a part of the first read transistor of the anti-fuse memory cell, and the multiple second nanosheets, the third S / D region and the fourth S / D region are configured as at least a part of the second read transistor of the anti-fuse memory cell.

[0089] In the above semiconductor device, it further comprises: a plurality of full-ring gate stacks operably associated with the plurality of first nanosheets, each of the plurality of gate stacks comprising a metal gate and a gate dielectric.

[0090] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes. The semiconductor device includes a fin-based structure formed on a substrate. The fin-based structure extends along a first direction. The semiconductor device includes one or more first nanosheets disposed on the substrate. Each of the one or more first nanosheets is spaced apart from each other along a second direction perpendicular to the first direction. The semiconductor device includes a first source / drain (S / D) region disposed between the fin-based structure and the one or more first nanosheets along the first direction. The sidewalls of the fin-based structure each have a first crystal plane direction along a third direction perpendicular to the first direction and the second direction, and the top boundary and the bottom boundary of each first nanosheet have different second crystal plane directions.

[0091] In the above semiconductor device, the first crystal plane direction includes (110), and the different second crystal plane direction includes (100).

[0092] In the above semiconductor device, it also includes: a second S / D region, which is arranged with the first S / D region relative to the fin-based structure; and a third S / D region, which is arranged with the first S / D region relative to the one or more first nanosheets.

[0093] In the above-mentioned semiconductor device, the fin-based structure, the first S / D region and the second S / D region are configured as at least a part of the programming transistor of the anti-fuse memory cell, and the one or more first nanosheets, the first S / D region and the third S / D region are configured as at least a part of the reading transistor of the anti-fuse memory cell.

[0094] In the above semiconductor device, the programming transistor is electrically coupled to the reading transistor via the first S / D region.

[0095] In the above-mentioned semiconductor device, it also includes: one or more second nanosheets arranged on the substrate, each of the one or more second nanosheets is spaced apart from each other along the second direction, wherein the third S / D region is arranged between the one or more second nanosheets and the one or more first nanosheets along the first direction; and a fourth source / drain (S / D) region, which is arranged relative to the one or more second nanosheets and the third S / D region.

[0096] In the above-mentioned semiconductor device, the fin-based structure, the first S / D region and the second S / D region are configured as at least a part of the programming transistor of the anti-fuse memory cell, the one or more first nanosheets, the first S / D region and the third S / D region are configured as at least a part of the first read transistor of the anti-fuse memory cell, and the one or more second nanosheets, the third S / D region and the fourth S / D region are configured as at least a part of the second read transistor of the anti-fuse memory cell.

[0097] In the above semiconductor device, the programming transistor is electrically coupled to the first reading transistor via the first S / D region, and the first reading transistor is electrically coupled to the second reading transistor via the third S / D region.

[0098] In another aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes forming a fin-based structure extending from the top boundary of a substrate, wherein the fin-based structure is made of a first semiconductor material. The method includes forming a nanosheet-based structure protruding from the top boundary of the substrate. The nanosheet-based structure includes one or more first nanosheets made of a second semiconductor material and one or more second nanosheets made of a first semiconductor material, and the one or more first nanosheets and the one or more second nanosheets are alternately arranged. The method includes epitaxially growing a first source / drain (S / D) region, a second S / D region, and a third S / D region. The first S / D region is arranged between the fin-based structure and the nanosheet-based structure, the second S / D region and the first S / D region are arranged relative to the fin-based structure, and the third S / D region and the first S / D region are arranged relative to the nanosheet-based structure.

[0099] In the above method, sidewalls of the fin-based structure each have a {110} crystal plane, and a top boundary and a bottom boundary of each of the one or more first nanosheets have a {100} crystal plane.

[0100] The components of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. It should also be recognized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can be variously changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A fin-based structure formed on a substrate; a plurality of first nanosheets, vertically spaced apart from each other and formed on the substrate; a first S / D (source / drain) region coupled to a first end of the fin-based structure; a second S / D region coupled to both the second end of the fin-based structure and the first ends of the plurality of first nanosheets; and a third S / D region coupled to the second ends of the plurality of first nanosheets; wherein the fin-based structure has a first lattice direction, and the plurality of first nanosheets have a second lattice direction different from the first lattice direction, The fin-based structure, the first S / D region, and the second S / D region are configured as at least a portion of a programming transistor of an anti-fuse memory cell, and the plurality of first nanosheets, the second S / D region, and the third S / D region are configured as at least a portion of a read transistor of the anti-fuse memory cell.

2. The semiconductor device according to claim 1, wherein The first lattice direction includes <110> A lattice direction, and the different second lattice direction includes a [100] lattice direction.

3. The semiconductor device according to claim 1, wherein The first lattice direction includes at least one of the following lattice directions: [110], [101], [011], or The different second lattice directions include at least one of the following lattice directions: [100], [010], [001], or 4. The semiconductor device according to claim 1, wherein: Sidewalls of the fin-based structure each have a {110} crystal plane, and a top surface of each of the plurality of first nanosheets has a {100} crystal plane.

5. The semiconductor device according to claim 1, wherein The first nanosheet comprises silicon.

6. The semiconductor device according to claim 1, wherein The read transistor is electrically coupled in series to the programming transistor via a second shared S / D region.

7. The semiconductor device according to claim 1, further comprising: A plurality of second nanosheets vertically spaced apart from each other are formed on the substrate, the third S / D region being coupled to first ends of the plurality of second nanosheets; a fourth S / D region electrically coupled to the second ends of the plurality of second nanosheets, Wherein, the plurality of second nanosheets have the second lattice direction.

8. The semiconductor device according to claim 7, wherein: Sidewalls of the fin-based structure each have a {110} crystal plane, and a top surface of each of the plurality of first nanosheets and the plurality of second nanosheets each have a {100} crystal plane.

9. The semiconductor device according to claim 7, wherein: The fin-based structure, the first S / D region, and the second S / D region are configured as at least a portion of a programming transistor of an anti-fuse memory cell, the plurality of first nanosheets, the second S / D region, and the third S / D region are configured as at least a portion of a first read transistor of the anti-fuse memory cell, and the plurality of second nanosheets, the third S / D region, and the fourth S / D region are configured as at least a portion of a second read transistor of the anti-fuse memory cell.

10. The semiconductor device according to claim 1, further comprising: A plurality of full-all-around gate stacks are associated with the plurality of first nanosheets, each of the plurality of full-all-around gate stacks comprising a metal gate and a gate dielectric.

11. A semiconductor device comprising: A fin-based structure is formed on a substrate, wherein the fin-based structure extends along a first direction; One or more first nanosheets are disposed on the substrate, each of the one or more first nanosheets being spaced apart from each other along a second direction perpendicular to the first direction; a first S / D (source / drain) region disposed between the fin-based structure and the one or more first nanosheets along the first direction; a second S / D region disposed relative to the fin-based structure from the first S / D region; as well as a third S / D region disposed relative to the first S / D region and relative to the one or more first nanosheets; wherein the sidewalls of the fin-based structure each have a first crystal plane direction along a third direction perpendicular to the first direction and the second direction, and the top surface and the bottom surface of each of the first nanosheets have different second crystal plane directions, The fin-based structure, the first S / D region, and the second S / D region are configured as at least a portion of a programming transistor of an anti-fuse memory cell, and the one or more first nanosheets, the first S / D region, and the third S / D region are configured as at least a portion of a read transistor of the anti-fuse memory cell.

12. The semiconductor device according to claim 11, wherein The first crystal plane direction includes (110), and the different second crystal plane direction includes (100).

13. The semiconductor device according to claim 11, further comprising: A plurality of full-all-around gate stacks are associated with the one or more first nanosheets, each of the plurality of full-all-around gate stacks comprising a metal gate and a gate dielectric.

14. The semiconductor device according to claim 11, wherein The first nanosheet comprises silicon.

15. The semiconductor device according to claim 11, wherein The programming transistor is electrically coupled to the reading transistor via the first S / D region.

16. The semiconductor device according to claim 11, further comprising: One or more second nanosheets disposed on the substrate, each of the one or more second nanosheets being spaced apart from each other along the second direction, wherein the third S / D region is disposed between the one or more second nanosheets and the one or more first nanosheets along the first direction; and A fourth S / D region is disposed relative to the one or more second nanosheets together with the third S / D region.

17. The semiconductor device according to claim 16, wherein: The fin-based structure, the first S / D region, and the second S / D region are configured as at least a portion of a programming transistor of an anti-fuse memory cell, the one or more first nanosheets, the first S / D region, and the third S / D region are configured as at least a portion of a first read transistor of the anti-fuse memory cell, and the one or more second nanosheets, the third S / D region, and the fourth S / D region are configured as at least a portion of a second read transistor of the anti-fuse memory cell.

18. The semiconductor device according to claim 17, wherein: The programming transistor is electrically coupled to the first read transistor via the first S / D region, and the first read transistor is electrically coupled to the second read transistor via the third S / D region.

19. A method for manufacturing a semiconductor device, comprising: forming a fin-based structure extending from a top surface of the substrate, wherein the fin-based structure is made of a first semiconductor material; forming a nanosheet-based structure protruding from a top surface of the substrate, wherein the nanosheet-based structure comprises one or more first nanosheets made of a second semiconductor material and one or more second nanosheets made of the first semiconductor material, the one or more first nanosheets and the one or more second nanosheets being alternately arranged; and epitaxially growing a first S / D (source / drain) region, a second S / D region, and a third S / D region, wherein the first S / D region is disposed between the fin-based structure and the nanosheet-based structure, the second S / D region and the first S / D region are disposed relative to the fin-based structure, and the third S / D region and the first S / D region are disposed relative to the nanosheet-based structure, wherein the fin-based structure, the first S / D region, and the second S / D region are configured as at least a portion of a programming transistor of an anti-fuse memory cell, and the nanosheet-based structure, the first S / D region, and the third S / D region are configured as at least a portion of a reading transistor of the anti-fuse memory cell.

20. The method according to claim 19, wherein: Sidewalls of the fin-based structure each have a {110} crystal plane, and top and bottom surfaces of each of the one or more first nanosheets have a {100} crystal plane.

Images