High electron mobility transistor with doped semiconductor region in gate structure

Abstract

A high electron mobility transistor having a doped semiconductor region in a gate structure is disclosed. The transistor device includes: a gate fin, which is a segment of the semiconductor body deployed between pairs of gate trenches formed in the upper surface of the semiconductor body; a plurality of two-dimensional charge carrier gas channels deployed at different vertical depths within the gate fin; source contacts and drain contacts arranged on either side of the gate fin in the current flow direction of the gate fin, each of the source and drain contacts being electrically connected to each of the two-dimensional charge carrier gas channels; and a gate structure configured to control the conductive connection between the source and drain contacts. The gate structure includes: a region of doped group III nitride-type semiconductor material covering the gate fin and extending into the gate trench; and a conductive gate electrode formed on the region of the doped group III nitride-type semiconductor material.

Description

Background Technology

[0001] Semiconductor transistors—particularly field-effect controlled switching devices, such as MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) (also referred to below as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors)) and HEMTs (High Electron Mobility Field-Effect Transistors) (also known as Heterojunction FETs (HFETs) and Modulation-Doped FETs (MODFETs))—are used in a variety of applications. HEMTs are transistors having a junction between two materials with different band gaps, such as GaN and AlGaN. In GaN / AlGaN-based HEMTs, a two-dimensional electron gas (2DEG) is generated near the interface between the AlGaN barrier layer and the GaN channel layer. In HEMTs, the 2DEG forms the channel of the device. A similar principle can be used to select and form a two-dimensional hole gas (2DHG) as the channel layer and barrier layer of the device. 2DEG or 2DHG is generally referred to as a two-dimensional charge carrier gas. Without further measures, the heterojunction configuration results in a self-conducting, i.e., normally conducting transistor. Typically, more desirable, normally disconnected configurations of devices must include additional features to deplete the channel region of the HEMT without gate-source bias.

[0002] Due to the high electron mobility of the two-dimensional charge carrier gas in the heterojunction configuration, HEMTs offer high conduction and low loss compared to many conventional semiconductor transistor designs. These advantageous conduction characteristics make HEMTs desirable for applications including, but not limited to, their use as switches in power supplies and converters, electric vehicles, air conditioning, and consumer electronics.

[0003] Designers are constantly seeking ways to improve the performance of HEMTs (e.g., power consumption and voltage blocking capability). Examples of device parameters designers seek to improve include leakage current, threshold voltage (V... TH ), drain-source on-state resistance (R) DSON ) and maximum voltage switching capability. Summary of the Invention

[0004] A transistor device is disclosed. According to an embodiment, the transistor device includes: a gate fin, which is a segment of a semiconductor body deployed between pairs of gate trenches, each of the pairs of gate trenches being formed in an upper surface of the semiconductor body; a plurality of two-dimensional charge carrier gas channels deployed at different vertical depths within the gate fin, each of the plurality of two-dimensional charge carrier gas channels being formed by a heterojunction between two regions of a semiconductor material of a group III nitride type with different band gaps; source contacts and drain contacts disposed on either side of the gate fin in the current flow direction of the gate fin, each of the source contacts and drain contacts being electrically connected to each of the two-dimensional charge carrier gas channels; and a gate structure configured to control the conductive connection between the source contacts and drain contacts by controlling the conductive state of each of the two-dimensional charge carrier gas channels within the gate fin. The gate structure includes: a region of doped group III nitride type semiconductor material covering the gate fins and extending into the gate trench; and a conductive gate electrode formed on the region of doped group III nitride type semiconductor material.

[0005] Separately or in combination, the gate structure further includes one or more current blocking devices configured to prevent carriers from flowing into or out of regions of the doped group III nitride type semiconductor material.

[0006] Separately or in combination, the gate fin includes a first sidewall and a second sidewall defined by a pair of gate trenches, each of the two-dimensional charge carrier gas channels extending to the first and second sidewalls of the gate fin, and one or more current blocking devices are configured to prevent charge carriers from flowing between the region of the doped group III nitride type semiconductor material and each of the two-dimensional charge carrier gas channels at the first and second sidewalls of the gate fin.

[0007] Separately or in combination, one or more current blocking devices include a layer of group III nitride type semiconductor material that covers a gate fin and is formed along a first sidewall and a second sidewall of the gate fin.

[0008] Separately or in combination, the gate fin comprises a layered stack of GaN-based layer pairs with different aluminum contents, each of the two-dimensional charge carrier gas channels appearing near the heterojunction between the GaN-based layers in each layer pair, and the layer of group III nitride type semiconductor material is an AlGaN layer having a different bandgap from the channel layers from the GaN-based layer pairs.

[0009] Separately or in combination, the gate structure further includes a conductive Schottky contact material deployed between the gate electrode and a region of doped Group III nitride type semiconductor material, and one or more current blocking devices include a Schottky diode formed by a Schottky junction between the Schottky contact material and the doped Group III nitride type semiconductor material.

[0010] In discrete or combined configurations, conductive Schottky contact material extends into the gate trench.

[0011] Separately or in combination, the gate fin includes multiple pairs of semiconductor nitride layers, wherein each pair includes a barrier layer of a group III nitride-type semiconductor alloy and a channel layer of a group III nitride-type semiconductor, and wherein at least one of the barrier layer or channel layer from one of the layer pairs has a different thickness and / or alloy concentration compared to the corresponding barrier layer or channel layer from other pair within the gate fin.

[0012] Separately or in combination, the uppermost barrier layer of the gate fin has a greater thickness than each of the barrier layers below it within the gate fin.

[0013] Separately or in combination, each of the semiconductor nitride layers within the gate fin has a thickness between 5 nm and 80 nm.

[0014] In both discrete and combined configurations, the separation distance between pairs of gate trenches is 100 nm or less.

[0015] Separately or in combination, the gate fins comprise a channel layer of a group III nitride-type semiconductor material, and the region of the doped group III nitride-type semiconductor material has a different band gap than the channel layer.

[0016] In either a discrete or combined configuration, the channel layer is a GaN layer, and the region of the doped group III nitride type semiconductor material is a p-type AlGaN region.

[0017] In both discrete and combined grounding, the gate trench gradually tapers along the current flow direction, causing the width of the gate fins to increase as the gate fins approach the drain contact.

[0018] In either a separate or combined configuration, both gate trenches have a triangular shape, having a first side facing the source electrode and substantially orthogonal to the current flow direction, and a second side extending from the first side to a point facing the drain electrode.

[0019] Separately or in combination, both gate trenches include rectangular segments and tapering segments, the gate fins have substantially uniform width between the rectangular segments of the gate trenches, and the width of the gate fins increases between the tapering segments of the gate trenches as the gate fins approach the drain contact.

[0020] In both separate or combined configurations, the two gate trenches gradually taper in the vertical direction perpendicular to the upper surface of the semiconductor body, causing the width of the gate trench to decrease as it moves toward the bottom of the gate trench.

[0021] Separately or in combination, the gate electrode includes a first outer edge side and a second outer edge side extending across the current flow direction, and both gate trenches are completely contained within the first outer edge side and the second outer edge side of the gate electrode.

[0022] Separately or in combination, the gate electrode includes a first outer edge side and a second outer edge side extending across the current flow direction, and both gate trenches extend through one or both of the first outer edge side and the second outer edge side of the gate electrode.

[0023] According to another embodiment, the transistor device includes: a gate fin, which is a segment of a semiconductor body deployed between pairs of gate trenches, each of the pairs of gate trenches being formed in the upper surface of the semiconductor body; a plurality of two-dimensional charge carrier gas channels deployed at different vertical depths within the gate fin, each of the plurality of two-dimensional charge carrier gas channels being formed by a heterojunction between two regions of a group III nitride type semiconductor material with different band gaps; and a gate structure formed on top of the gate fin and extending into the two gate trenches. The gate structure is configured to apply a vertical electric field from above the gate fin and a lateral electric field from the outside of the first and second sidewalls of the gate fin facing opposite sides, the vertical and lateral electric fields jointly controlling the conductivity state of each two-dimensional charge carrier gas channel within the gate fin. The gate structure includes regions of doped group III nitride type semiconductor material configured to apply the lateral field and the vertical electric field.

[0024] Separately or in combination, the gate structure further includes one or more current blocking devices configured to prevent carriers from flowing into or out of regions of the doped group III nitride type semiconductor material.

[0025] A method for forming a transistor device is disclosed. According to an embodiment, the method includes: providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths below an upper surface of the semiconductor body; forming a gate fin in the semiconductor body by forming paired gate trenches in the upper surface of the semiconductor body, the paired gate trenches exposing each of the plurality of two-dimensional charge carrier gas channels at a first sidewall and a second sidewall of the gate fin; providing source contacts and drain contacts arranged such that the gate fin is between the source contacts and the drain contacts in the current flow direction of the gate fin, and such that each of the source contacts and the drain contacts is electrically connected to each of the two-dimensional charge carrier gas channels; and providing a gate structure configured to control the conductive connection between the source contacts and the drain contacts by controlling the conductive state of each two-dimensional charge carrier gas channel. The gate structure includes: forming a layer of doped group III nitride-type semiconductor material covering the gate fins and extending into the gate trench; and forming a conductive gate electrode on top of the layer of doped group III nitride-type semiconductor material.

[0026] Separately or in combination, the gate structure includes: depositing a blanket layer of doped group III nitride type semiconductor material; depositing a conductive Schottky contact material on top of the blanket layer of doped group III nitride type semiconductor material; and using the conductive Schottky contact material as an etch mask to form a self-aligned edge side of the gate structure.

[0027] Separately or in combination, a gate structure is provided comprising: depositing a blanket layer of doped group III nitride-type semiconductor material; structuring the blanket layer of doped group III nitride-type semiconductor material to include an edge side facing the drain electrode; forming a passivation layer covering the upper surface of the semiconductor body and extending on the edge side of the doped group III nitride-type semiconductor material; and depositing a conductive Schottky contact material such that the Schottky contact material contacts the doped group III nitride-type semiconductor material and extends on the passivation layer.

[0028] Separately or in combination, a Schottky contact material is formed to extend through the edge side of a doped group III nitride type semiconductor material, and the method further includes configuring the Schottky contact material extending through the edge side of the doped group III nitride type semiconductor material as a field plate. Attached Figure Description

[0029] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0030] Figure 1 includes Figure 1A and Figure 1B The illustration shows a transistor device according to an embodiment. Figure 1B A transistor device is shown in perspective from a plan view. Figure 1A According to along in Figure 1B The cross-sectional perspective of the cross-section line I-I' shown in the figure reveals the transistor device.

[0031] Figure 2 includes Figure 2A and Figure 2B The illustration shows a transistor device according to an embodiment. Figure 2B A transistor device is shown in perspective from a plan view. Figure 2A According to along in Figure 2B The cross-sectional perspective of the cross-section line I-I' shown in the figure reveals the transistor device.

[0032] Figure 3 includes Figure 3A and Figure 3B The illustration shows a transistor device according to an embodiment. Figure 3B A transistor device is shown in perspective from a plan view. Figure 3A According to along in Figure 3B The cross-sectional perspective of the cross-section line I-I' shown in the figure reveals the transistor device.

[0033] Figure 4 includes Figure 4A and Figure 4B The illustration shows a transistor device according to an embodiment. Figure 4B A transistor device is shown in perspective from a plan view. Figure 4A According to along in Figure 4B The cross-sectional perspective of the cross-section line I-I' shown in the figure reveals the transistor device.

[0034] Figure 5 includes Figure 5A and Figure 5B The illustration shows a transistor device according to an embodiment. Figure 5B A transistor device is shown in perspective from a plan view. Figure 5A According to along in Figure 5B The cross-sectional perspective of the cross-section line I-I' shown in the figure reveals the transistor device.

[0035] Figure 6 includes Figure 6A and Figure 6B The illustration shows a transistor device according to an embodiment. Figure 6B A transistor device is shown in perspective from a plan view. Figure 6A According to along in Figure 6B The cross-sectional perspective of the cross-section line I-I' shown in the figure reveals the transistor device.

[0036] Figure 7 includes Figure 7A and Figure 7B The illustration shows a transistor device according to an embodiment. Figure 7B A transistor device is shown in perspective from a plan view. Figure 7A According to along in Figure 7B The cross-sectional perspective of the cross-section line I-I' shown in the figure reveals the transistor device.

[0037] Figure 8 includes Figure 8A , Figure 8B and Figure 8C The diagram illustrates three embodiments of a transistor device based on a plan view perspective illustration.

[0038] Figure 9 includes Figure 9A , Figure 9B and Figure 9C The diagram illustrates three embodiments of a transistor device based on a plan view perspective illustration.

[0039] Figure 10 includes Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E The illustrations depict transistor devices according to different embodiments. Figure 10A A transistor device is shown in perspective from a plan view. Figure 10B According to along in Figure 10A The cross-sectional perspective of the cross-sectional line II-II' shown in the figure illustrates a transistor device according to an embodiment. Figure 10C According to along in Figure 10A The cross-sectional perspective of the cross-sectional line II-II' shown in the figure illustrates a transistor device according to an embodiment. Figure 10D According to along in Figure 10A The cross-sectional perspective of the cross-sectional line II-II' shown in the figure illustrates a transistor device according to an embodiment. Figure 10E According to along in Figure 10A The cross-sectional perspective of the cross-sectional line II-II' shown in the figure illustrates a transistor device according to an embodiment. Detailed Implementation

[0040] An embodiment of a high electron mobility field-effect transistor (HEMT) having a gate configuration configured as fins is described herein. In this device configuration, the gate of the transistor is provided by a segment of the semiconductor body configured as a fin (i.e., a mesa structure with vertical semiconductor sidewalls). The segment configured as a fin includes a two-dimensional charge carrier gas that appears near a heterojunction within the semiconductor body and provides the channel for the device. The gate structure of the transistor surrounds the segment configured as a fin. This allows the gate structure to control the two-dimensional charge carrier gas in the vertical direction (i.e., from above the fins) and in the horizontal direction (i.e., across the sidewalls of the fins). Examples of these devices are described in the following documents, the contents of which are incorporated herein by reference in their entirety: U.S. Patent Nos. 9,035,355, 9,647,104, and 9,837,520, belonging to Ostermaier.

[0041] The embodiments disclosed herein provide a high electron mobility field-effect transistor (HEMT) with an improved electrical characteristic in a finned gate configuration. According to the embodiments, the transistor's gate structure includes a region of doped group III nitride-type semiconductor material (e.g., p-type GaN) that surrounds a finned segment of the semiconductor body on all three sides (i.e., from above and on either side of the fin). This structure is highly efficient in depleting the two-dimensional charge carrier gas in all three directions and results in beneficial on-off control. This is particularly advantageous when the gate fin has a multi-channel configuration—where multiple two-dimensional charge carrier gas channels are deployed within the gate fin. However, the doped material in the gate structure can contribute to gate leakage by creating leakage paths at the sidewalls of the gate fin. The embodiments described herein include current blocking devices incorporated into the transistor's gate structure and mitigating this gate leakage problem. In one example, the gate structure includes a Schottky diode integrated into the gate metal. This Schottky diode prevents charge carriers (e.g., holes) from entering the doped Group III nitride-type semiconductor material and ultimately prevents charge carriers from contributing to gate leakage. In another example, the gate structure includes a layer of a Group III nitride-type semiconductor alloy material (e.g., AlGaN) formed along the sidewalls of the gate fins. This layer creates a PIN diode between the two-dimensional charge carrier gas channel and the doped Group III nitride-type semiconductor material, thereby suppressing carrier flow in both directions.

[0042] Referring to FIG1, a transistor device 100 according to an embodiment is depicted. The transistor device 100 includes a gate fin 102. The gate fin 102 is a segment of a semiconductor body 101 disposed between pairs of gate trenches 104. The gate trenches 104 are formed in the upper surface 103 of the semiconductor body 101. A two-dimensional charge carrier gas channel 106 is disposed within the gate fin 102. The two-dimensional charge carrier gas channel 106 is formed by a heterojunction between two regions of a group III nitride type semiconductor material with different band gaps. These regions include a channel layer 108 and a barrier layer 110. The band gap difference between the regions can be created by a difference in alloy concentration. For example, in one embodiment, the channel layer 108 is a GaN (gallium nitride) region, and the barrier layer 110 is an AlGaN (aluminum gallium nitride) region. In this case, a 2DEG (two-dimensional electron gas) appears in the channel layer 108 near the heterojunction. A similar principle can be used to provide 2DHG (two-dimensional cavitation gas) as the channel of transistor device 100.

[0043] As in Figure 1B As shown, the transistor device 100 includes a source contact 112 and a drain contact 114. The source contact 112 and drain contact 114 are arranged on either side of the gate fin 102 in the current flow direction 116 of the gate fin 102. The current flow direction 116 refers to the direction of electron flow during the forward-biased on-state of the transistor device 100. A gate trench 104 is formed such that a continuous two-dimensional charge carrier gas region extending between the source contact 112 and drain contact 114 enters and exits the gate fin 102. The source contact 112 and drain contact 114 may be formed of a conductive material (e.g., copper, aluminum, tungsten, etc., and alloys thereof). The source contact 112 and drain contact 114 are in ohmic contact with the two-dimensional charge carrier gas channel. For example, the source contact 112 and the drain contact 114 can be ohmic contacts with the two-dimensional charge carrier gas channel 106 in the semiconductor body 101 at a location outside the gate fin 102 by a combination of electrical conductors, doped regions, trench structures, etc.

[0044] The transistor device 100 includes a gate structure 118 configured to control a conductive connection between a source contact 112 and a drain contact 114. This is accomplished by controlling the conductive state of a two-dimensional charge carrier gas channel 106 within a gate fin 102. When properly biased, the gate structure 118 can completely deplete the two-dimensional charge carrier gas channel 106 within the gate fin 102, thereby turning off the device. Similarly, when properly biased, the gate structure 118 can place the two-dimensional charge carrier gas channel 106 into a conductive state, thereby turning on the device. The gate structure 118 includes a gate electrode 120 that receives gate bias. The gate electrode 120 may be formed of a conductive material (e.g., copper, aluminum, tungsten, etc., and alloys thereof).

[0045] According to an embodiment, the gate structure 118 includes a region 122 of a doped Group III nitride-type semiconductor material. The doped Group III nitride-type semiconductor material region 122 covers the gate fin 102 and extends into a pair of gate trenches 104 on either side of the gate fin 102. That is, the doped Group III nitride-type semiconductor material region 122 is positioned above the gate fin 102 and is laterally adjacent to the first sidewall 124 and second sidewall 126 of the gate fin 102 defined by the gate trenches 104. In this manner, the doped Group III nitride-type semiconductor material region 122 is configured to apply a vertical electric field from above the gate fin 102 and a lateral electric field from outside the first sidewall 124 and second sidewall 126 of the gate fin 102. The vertical and lateral electric fields can jointly and completely deplete the two-dimensional charge carrier gas, thereby providing on / off control of the device. According to an embodiment, region 122 of the doped group III nitride-type semiconductor material is configured to completely deplete the two-dimensional charge carrier gas channel 106 under zero bias applied to the gate electrode 120. This provides a normally disconnected configuration. An exemplary dopant concentration value for region 122 of the doped group III nitride-type semiconductor material can be 10... 17 dopant atoms / cm -3 Up to 5×10 20 dopant atoms / cm -3 Within the range. In a preferred embodiment, this value is approximately 5 × 10⁻⁶. 19 Up to 1×10 20 dopant atoms / cm -3 In the embodiment, it is sufficient to completely deplete the two-dimensional charge carrier gas channel 106 under zero gate bias.

[0046] Several performance improvements are achieved in the transistor device 100 by providing regions 122 of doped Group III nitride-type semiconductor material around the three sides of the finned gate of the HEMT. For example, the device has reduced IV curve hysteresis (characterizing on-off operation across the gate voltage range) compared to a metal-insulator-semiconductor (MIS) configuration. However, a disadvantage of the finned configuration of the doped semiconductor is increased gate leakage current compared to other device configurations including MIS configurations. The gate leakage current mechanism of this device is as follows. When the gate electrode 120 is forward biased, charge carriers can be injected from the gate electrode 120 into the regions 122 of the doped Group III nitride-type semiconductor material. The regions 122 of the doped Group III nitride-type semiconductor material form a pn junction with the semiconductor material of the gate fin 102. This PN junction creates a diode 128 such that, when forward biased, it allows charge carriers to flow into the two-dimensional charge carrier gas present within the gate fin 102 and to the source / drain of the device. If the device is reverse biased, a similar reverse leakage phenomenon may occur in the opposite direction. In this case, the charge carriers must overcome the reverse blocking voltage of the diode 128. Without measures to reduce this gate leakage, the power consumption of the device increases adversely.

[0047] According to an embodiment, the gate structure 118 further includes one or more current blocking devices configured to prevent carriers from flowing into or out of the region 122 of the doped Group III nitride-type semiconductor material. The current blocking devices advantageously mitigate the gate leakage current described above by preventing or suppressing current flow between the region 122 of the doped Group III nitride-type semiconductor material and the gate fin 102. As will be detailed below, the current blocking devices can prevent carriers from entering the doped Group III nitride-type semiconductor material at the gate electrode 120 side, thereby causing the region 122 of the doped Group III nitride-type semiconductor material to lose carriers. Furthermore, or alternatively, the current blocking devices can prevent carrier flow between the region 122 of the doped Group III nitride-type semiconductor material and the plurality of two-dimensional charge carrier gas channels 106 within the gate fin 102, thereby blocking leakage current at this interface. Generally, the current blocking devices can be implemented by any of a wide variety of structures that suppress carrier flow in at least one direction. Examples of these structures include electrical insulators, lightly doped or intrinsically doped regions of semiconductor materials, and pn junctions.

[0048] In the embodiment of FIG1, transistor device 100 includes a Schottky diode 130 provided with a current blocking device incorporated into gate structure 118. Schottky diode 130 is provided by a conductive Schottky contact material 132 disposed between gate electrode 120 and region 122 of a doped Group III nitride-type semiconductor material. Schottky diode 130 is reverse biased when gate electrode 120 is forward biased relative to source contact 112. Therefore, Schottky diode 130 prevents the injection of charge carriers (e.g., holes) from gate electrode 120 into region 122 of the doped Group III nitride-type semiconductor material under positive gate bias. Schottky contact material 132 is a conductive material that creates an energy barrier at the metal-semiconductor interface. Examples of Schottky contact materials 132 include titanium, gold, platinum, tungsten, molybdenum, nickel, tantalum, etc., as well as their nitrides and alloys.

[0049] Exemplary device parameters for transistor device 100 are as follows. Channel layer 108 may be provided by a GaN UID (unintentionally doped) region, and barrier layer 110 may be an AlGaN layer deposited on top of the GaN UID region. The GaN UID region may have a thickness between 50 nm and 1000 nm. In a preferred embodiment, this thickness is in the range of 100 nm to 500 nm. Barrier layer 110 may have a thickness between 5 nm and 100 nm. In a preferred embodiment, for the single-channel gate fin 102 embodiment of FIG1, this thickness is in the range of 5 nm to 20 nm. The thickness of the GaN UID region and the thickness of channel layer 108 are measured in a direction perpendicular to the upper surface 103 of semiconductor body 101. The width of gate trench 104 may be between 200 nm and 500 nm. In a preferred embodiment, this width is in the range of 100 nm to 200 nm. The width is measured between the sidewalls defining the gate fin 102 of the gate trench 104 and the opposing sidewalls of the same gate trench 104. The separation distance between a pair of gate trenches 104 defining one of the gate fins 102 can be between 30 nm and 1000 nm. In a preferred embodiment, the separation distance is greater than about 100 nm. The separation distance is measured in a direction parallel to the upper surface 103 of the semiconductor body 101. The length of the gate trench 104 can be between 50 nm and 2 μm. In a preferred embodiment, the length is in the range of 20 nm to 150 nm. The length is measured between the opposing ends of the gate trench 104 that are spaced apart from each other in the current flow direction 116.

[0050] The transistor device 100 may be formed according to the following techniques. Initially, a semiconductor wafer is provided to include a seed region 134. Generally, the seed region 134 may include any semiconductor material suitable for epitaxial growth of a group III nitride type material thereon. For example, the seed region 134 may include silicon (Si), sapphire, group IV compound semiconductor materials (such as silicon carbide (SiC) or silicon germanium (SiGe)), group III-V type semiconductors (including gallium nitride, gallium arsenide (GaAs), aluminum nitride (AlN), aluminum arsenide (AlAs), indium nitride (InN), indium arsenide (InAs), etc.). For example, the seed region 134 may be provided using a commercially available semiconductor wafer. Additionally or alternatively, the seed region 134 may have an SOI (silicon-on-insulator) configuration. A thin nucleation layer (not shown) may be provided on the seed region 134, which is beneficial for growing group III-V type semiconductors (e.g., an aluminum nitride layer of 100 nm to 200 nm) thereon. Then, for example, an epitaxial deposition technique is used to form a region of a group III nitride-type semiconductor material (e.g., GaN) providing the channel layer 108 on the seed region 134. Then, for example, an epitaxial deposition technique is used to form a region of a group III nitride-type semiconductor material (e.g., AlGaN) providing the barrier layer 110 on the channel layer 108. Then, for example, an etching technique such as plasma etching, wet chemical etching, etc., is used to form the gate trench 104 with a desired geometry. Then, a region 122 of doped group III nitride-type semiconductor material (e.g., p-type GaN) is formed on the semiconductor body 101. The region 122 of doped group III nitride-type semiconductor material can be formed as a blanket layer covering the entire upper surface 103 of the semiconductor body 101. Subsequently, a structuring technique (e.g., mask etching) can be performed to remove the doped group III nitride-type semiconductor material outside the regions of the gate structure 118. A conductive Schottky contact material 132 can then be deposited on top of the doped group III nitride type semiconductor material, followed by the deposition of a gate electrode 120 material on top of the Schottky contact material 132.

[0051] According to an embodiment, region 122 of the doped Group III nitride-type semiconductor material has a different bandgap than the channel layer 108. This can be achieved by alloying region 122 of the doped Group III nitride-type semiconductor material to create a bandgap difference between the two materials. For example, region 122 of the doped Group III nitride-type semiconductor material can be a p-type AlGaN region, while the channel layer 108 is an unintentionally doped GaN or AlGaN layer with a lower aluminum content compared to region 122 of the doped Group III nitride-type semiconductor material. The band shift between the two regions creates an energy barrier that prevents charge carriers in the two-dimensional charge carrier gas 106 from entering the doped Group III nitride-type semiconductor material 122. As a result, the reverse leakage characteristics of the device are advantageously improved.

[0052] Referring to FIG2, a transistor device 100 according to another embodiment is depicted. In this embodiment, the transistor device 100 additionally includes a layer 136 of a group III nitride-type semiconductor material covering a gate fin 102 and formed along a first sidewall 124 and a second sidewall 126 of the gate fin 102. The layer 136 of the group III nitride-type semiconductor material may be a doped or unintentionally doped material layer. An exemplary dopant value for the layer 136 of the group III nitride-type semiconductor material may be 10. 15 One dopant atom cm -3 Up to 10 19 One dopant atom cm -3 Within the range. The layer 136 of the group III nitride-type semiconductor material separates the region 122 of the doped group III nitride-type semiconductor material from the plurality of two-dimensional charge carrier gas channels 106 present at the first sidewall 124 and the second sidewall 126 of the gate fin 102. In an embodiment, the layer 136 of the group III nitride-type semiconductor material is an AlGaN layer. This layer may be conformally deposited (e.g., by epitaxy) after the gate trench etching step and before the deposition of the doped group III nitride-type semiconductor material.

[0053] Layer 136 of the group III nitride-type semiconductor material provides an additional current blocking device in the gate structure 118. This current blocking device is configured to prevent carrier flow in both directions between the multiple two-dimensional charge carrier gas channels 106 present at the first sidewall 124 and the second sidewall 126 of the gate fin 102 and the region 122 of the doped group III nitride-type semiconductor material. Layer 136 of the group III nitride-type semiconductor material has the effect of converting the diode 128 discussed above into a so-called PIN diode (i.e., a diode with an intrinsic region sandwiched between a p-type region and an n-type region). As is known, PIN diodes have higher characteristic voltages in both the forward and reverse directions compared to their corresponding PN junction diodes. Therefore, this structure reduces both forward and reverse leakage currents. In particular, the 2DHG hole leakage path from the region 122 of the doped group III nitride-type semiconductor material into the gate fin 102, as discussed above, is blocked by layer 136 of the group III nitride-type semiconductor material.

[0054] Gate structure 118 may include one or both of a Schottky diode 130 and a layer 136 of group III nitride-type semiconductor material as a current blocking device. For example, instead of the Schottky gate configuration shown in FIG2, transistor device 100 may include an ohmic connection between a doped group III nitride-type semiconductor material 122 and a gate electrode 120, wherein the layer 136 of the group III nitride-type semiconductor material is provided in a similar manner. In this case, the characteristics (e.g., thickness or alloy concentration) of the layer 136 of the group III nitride-type semiconductor material can be suitably adapted to provide desired electrical isolation.

[0055] Referring to FIG3, a transistor device 100 according to another embodiment is depicted. In this embodiment, the gate fin 102 has a multi-channel configuration. More specifically, the gate fin 102 includes a plurality of two-dimensional charge carrier gas channels 106 deployed at different vertical depths within the gate fin 102. Each two-dimensional charge carrier gas channel 106 is formed by a heterojunction between two regions of a group III nitride type semiconductor material with different band gaps. Although the depicted embodiment shows a device with three two-dimensional charge carrier gas channels 106, any number of two-dimensional charge carrier gas channels 106, such as 2, 3, 4, 5, etc., can be provided using the concepts described herein.

[0056] The multi-channel gate fin configuration 102 can be obtained by initially providing a semiconductor body 101 to include a layered stack of heterojunction forming layers. The layered stack includes pairs 138 of group III nitride semiconductor materials forming heterojunctions within each other. Each pair 138 includes a barrier layer 110 and a channel layer 108. The barrier layer 110 and channel layer 108 of each pair 138 can be semiconductors of group III nitride types with different alloy concentrations. For example, the semiconductor body 101 can be formed to include a plurality of GaN layers arranged alternately with AlGaN layers, wherein the GaN layers form the channel layer 108 and the AlGaN layers form the barrier layer 110. In another example, the semiconductor body 101 can be formed to include layers with AlGaN layers arranged alternately with AlGaN layers. y Ga 1-y Al layers arranged alternately in N layers x Ga 1-x N layers, wherein the layer with lower aluminum content forms the channel layer 108 and the layer with higher aluminum content forms the barrier layer 108. In either case, the heterojunction formation layer can be formed by successive epitaxial deposition steps, wherein the alloy concentration (e.g., aluminum in the example above) varies for each layer. After providing the semiconductor body 101 with the layered stack of heterojunction formation layers, the etching steps described above can be performed to form paired gate trenches 104. The gate trenches 104 are formed such that each two-dimensional charge carrier gas channel 106 is exposed at the first sidewall 124 and the second sidewall 126 of the gate fin 102.

[0057] Exemplary device parameters for a transistor device 100 having a multi-channel gate fin 102 are as follows. Each semiconductor nitride layer within the gate fin 102 may have a thickness between 5 nm and 80 nm. In a preferred embodiment, each barrier layer 110 has a thickness between 40 nm and 80 nm. This thickness is measured in a vertical direction perpendicular to the upper surface 103 of the semiconductor body 101. The separation distance between the gate trenches 104 defining the width of the gate fin 102 may be 100 nm or less. In a preferred embodiment, this separation distance is 65 nm or less. The vertical distance between the deepest two-dimensional charge carrier gas channel 106 and the seed region 134 of the semiconductor body 101 is between 50 nm and 1000 nm. In a preferred embodiment, this distance is between 100 nm and 500 nm.

[0058] According to an embodiment, at least one layer from one of the layer pairs 138 has a different thickness and / or alloy concentration compared to a corresponding layer from the other layer pair 138 within the gate fin 102. For example, the gate fin 102 can be configured such that the barrier layers 110 moving from the top to the bottom (or vice versa) of the gate fin 102 exhibit a gradual change in thickness and / or alloy concentration. Alternatively, the gate fin 102 can be configured such that the barrier layer 110 located at the vertical midpoint of the gate fin 102 has a maximum or minimum thickness and / or alloy concentration, wherein the barrier layers 110 above and below this barrier layer have a lower thickness and / or alloy concentration (in the case of the maximum value) or a higher thickness and / or alloy concentration (in the case of the minimum value). For example, the thickness of the barrier layer 110 and / or channel layer 108 within each gate fin 102 can vary relative to each other to optimize R ON Performance and electric field distribution.

[0059] According to an embodiment, the uppermost barrier layer 110 of the gate fin 102 (i.e., the barrier layer 110 extending to the top surface of the gate fin 102) has a greater thickness than each of the lower barrier layers 110 within the gate fin 102. For example, the uppermost barrier layer 110 may be an AlGaN layer with a thickness of approximately 300 nm, while each of the lower barrier layers 110 may have a thickness of no more than 100 nm, and specifically no more than 80 nm. Generally, by forming the uppermost barrier layer 110 with a greater thickness, beneficial electrical properties are obtained due to interface charge behavior. Techniques for forming the uppermost barrier layer 110 with a greater thickness may include the following: After providing the semiconductor body 101 with a layered stack including a heterojunction formation layer and etching the gate trench 104, an AlGaN regrowth process is performed.

[0060] Compared to the previously described single-channel embodiments, the multi-channel gate fin 102 configuration of FIG3 advantageously provides a low Ri due to the provision of multiple parallel channels. ON(On-resistance). However, as the number of two-dimensional charge carrier gas channels 106 increases, it becomes difficult and, at certain points, impossible to completely and exclusively control the two-dimensional charge carrier gas channels 106 from above. For this purpose, a finned configuration provides an efficient structure for depleting the lower two-dimensional channels by applying a lateral electric field to the sidewalls. In particular, the region 122 of the doped group III nitride-type semiconductor material is highly efficient in generating the lateral electric field for depleting the lower two-dimensional channels in a multi-fin device, and thus provides predictable on-off control. However, in a multi-channel configuration, the gate leakage problem is amplified because multiple two-dimensional charge carrier gas channels 106 represent multiple leakage paths at the first sidewall 124 and the second sidewall 126 of the gate fin 102. Furthermore, a multilayer configuration generates parasitic two-dimensional charge gas regions opposite the channels of the device. In the GaN / AlGaN example described above, for each channel layer 108 sandwiched between barrier layers, a naturally occurring two-dimensional hole gas (2DHG) is formed on the side of the channel layer opposite to the two-dimensional hole gas (2DHG). This naturally occurring 2DHG represents an additional leakage path for holes injected from the gate electrode 120 into region 122 of the doped Group III nitride-type semiconductor material, entering the 2DHG and flowing to the source of the device. Therefore, the current blocking device incorporated into the gate structure 118 as described herein is particularly advantageous for performance in multi-channel cases. In the depicted embodiment, the transistor device 100 includes a Schottky diode 130 as described above. Thus, under positive gate bias, carriers are prevented from entering the doped Group III nitride-type semiconductor material, and the leakage mechanism described above is substantially mitigated.

[0061] Referring to FIG4, a transistor device 100 according to another embodiment is depicted. In this embodiment, the transistor device 100 is the same as the transistor device of FIG3, except that it additionally includes a layer 136 of a group III nitride-type semiconductor material covering the gate fin 102 and formed along the first sidewall 124 and the second sidewall 126 of the gate fin 102 (e.g., in the same manner as described with reference to FIG2). Thus, the same beneficial effects regarding gate leakage are achieved. That is, the layer 136 of the group III nitride-type semiconductor material forms a PIN diode at the first sidewall 124 and the second sidewall 126 of the gate fin 102, which mitigates the forward gate leakage current and the reverse gate leakage current between the doped group III nitride-type semiconductor material region 122 and the gate fin 102.

[0062] Referring to FIG5, a transistor device 100 according to another embodiment is depicted. In this embodiment, conductive Schottky contact material 132 extends into each gate trench 104. This configuration can be achieved, for example, by etching regions 122 of a doped group III nitride-type semiconductor material prior to depositing the Schottky contact material 132. This configuration can provide lower gate resistance, which advantageously improves the device's power consumption and switching performance.

[0063] Referring to FIG6, a transistor device 100 according to another embodiment is depicted. In this embodiment, the transistor device 100 includes the previously described multi-channel fin configuration combined with a configuration of conductive Schottky contact material 132 extending into the gate trench 104 (as described above with reference to the embodiment in FIG5). A similar benefit of lower gate resistance can be obtained in this device.

[0064] Referring to FIG7, a transistor device 100 according to another embodiment is depicted. In this embodiment, the gate trench 104 tapers gradually in a vertical direction perpendicular to the upper surface 103 of the semiconductor body 101, such that the width of the gate trench 104 decreases as it moves toward the bottom of the gate trench 104. As a result, the gate fins 102 are narrowest at the top of the gate fins 102. This configuration allows for adjustment of the width and thickness of the channel layer 108 and the barrier layer 110 for each gate fin 102. For example, by adjusting the thickness of the channel layer 108 and the barrier layer 110, the depletion behavior as a function of the vertical taper in the gate trench 104 can be controlled to achieve an optimized device. An exemplary value for the first width 135 of the gate trench 104 at the upper surface 103 of the semiconductor body 101 can be between 30 nm and 1000 nm, and more preferably between 100 nm and 300 nm. The gate trench 104 can be tapered vertically, such that the sidewalls are oriented at any position between 45 degrees and less than 90 degrees relative to the upper surface 103. A negative tapering of the gate trench 104, becoming wider as it moves toward the bottom of the trench, is also possible.

[0065] Referring to Figure 8, three embodiments of the transistor device 100 are depicted. In each embodiment, the gate trench 104 tapers gradually along the current flow direction 116, such that the width of the gate fin 102 increases as the gate fin 102 approaches the drain contact 114. Since the gate fin 102 has a geometry opposite to that of the first and gate trench 104, this means that the gate trench 104 tapers inwards as it approaches the drain contact 114. One benefit of this configuration is that the electric field is reduced at critical locations, thus providing an effect similar to a field plate. This allows for a given on-resistance R... ON Higher breakdown voltage V BR .

[0066] exist Figure 8A In one embodiment, the gate trench 104 has a triangular shape. Each triangle includes a first side 140 facing the source contact 112 and substantially orthogonal to the current flow direction 116, and a second side 142 extending from the first side 140 to a point facing the drain contact 114. The second side 142, and therefore the sidewall of the gate fin 102, is inclined relative to the current flow direction 116.

[0067] exist Figure 8B In one embodiment, the gate trench 104 includes rectangular segments 144 and tapering segments 146. Gate fins 102 have a substantially uniform width between the rectangular segments 144 of the gate trench 104. In this region, the sidewalls of the gate fins 102 travel parallel to the current flow direction 116. The width of the gate fins 102 increases between the tapering segments 146 as the gate fins 102 approach the drain contact 114. In this region, the sidewalls of the gate fins 102 are inclined relative to the current flow direction 116.

[0068] exist Figure 8C In one embodiment, the gate trench 104 includes a plurality of rectangular segments arranged adjacent to each other in the current flow direction 116. The width of each rectangular segment varies in a direction perpendicular to the current flow direction 116. The width of the gate fin 102 increases between each successively narrowing rectangular segment as the gate fin 102 approaches the drain contact 114.

[0069] In each of the examples depicted in Figure 8, the gate trench 104 tapers gradually along the current flow direction 116, such that the narrowest portion of the gate fin 102 is located at the end of the gate fin 102 facing the source contact 112. Alternatively, the gate trench 104 may taper gradually along the current flow direction 116, such that the narrowest portion of the gate fin 102 appears between the two ends of the gate fin 102 facing the source contact 112 and the drain contact 114. That is, the minimum spacing between two adjacent gate trenches 104 may not necessarily be located at the end of the gate trench 104.

[0070] Referring to FIG9, three different embodiments of the transistor device 100 are depicted. These embodiments differ from each other in the placement of the gate trench 104 relative to the gate electrode 120. In each figure, the gate electrode 120 includes a first outer edge side 148 and a second outer edge side 150 extending across the current flow direction 116. Figure 9A In this embodiment, the gate trench 104 is completely contained within the first outer edge side 148 and the second outer edge side 160 of the gate electrode 120. Figure 9B and Figure 9CIn one embodiment, the gate trench 104 extends through at least one of the first outer edge side 148 and the second outer edge side 150 of the gate electrode 120. More specifically, in Figure 9B In one embodiment, the gate trench 104 extends through both the first outer edge side 148 and the second outer edge side 150. Figure 9C In some embodiments, the gate trench 104 extends only through the second outer edge side 150 facing the drain electrode 114. These examples illustrate the advantageous flexibility of forming a device by forming pairs of spaced-apart trenches in the semiconductor body 101, since precise alignment between the trenches and the gate metallization is not required.

[0071] Figure 9 additionally depicts an exemplary arrangement of the region 122 of the doped Group III nitride-type semiconductor material relative to the gate trench 104 and the gate electrode 120. Generally, the position of the region 122 of the doped Group III nitride-type semiconductor material within the gate structure 118 can be flexibly adjusted relative to the gate trench 104. In each of the depicted embodiments, the region 122 of the doped Group III nitride-type semiconductor material is formed to be wider than the gate trench 104. This maintains a flat surface above the trench 104 for depositing the gate metal 134 thereon.

[0072] Referring to FIG10, four different embodiments of transistor device 100 are depicted. These embodiments differ from one another in the structuring of the Schottky contact material 132 and the region 122 of the doped group III nitride type semiconductor material at the edge of the gate structure 118. In each case, transistor device 100 is shown along cross-sectional line II-II' of semiconductor body 101, which is taken at the outer edge of the gate structure 118 facing the drain contact 114.

[0073] exist Figure 10BIn one embodiment, a region 122 of conductive Schottky contact material 132 and doped Group III nitride-type semiconductor material forms a self-aligned edge side of the gate structure 118. This structure can be obtained by depositing a doped Group III nitride-type semiconductor material as a blanket layer (e.g., via epitaxy) on the semiconductor body 101 and forming the Schottky contact material 132 on top of the blanket layer. The Schottky contact material 132 can be structured, for example, by deposition and / or mask etching techniques. The edge side of the gate structure 118 traveling across (e.g., perpendicular to) the current flow direction 116 is formed by structuring the Schottky contact material 132 and the blanket layer of doped Group III nitride-type semiconductor material using a common mask. In one example, the conductive Schottky contact material 132 itself is used as an etching mask. Alternatively, a common photomask can be used to structure both layers. Although the depicted embodiment shows the edge of the gate structure 118 between the gate fin 102 and the drain contact 114, the same technique can be applied to the edge of the gate structure 118 between the gate fin 102 and the source contact 112.

[0074] exist Figure 10C In this embodiment, the Schottky contact material 132 and the doped Group III nitride-type semiconductor material are not formed using a self-aligned technique. Instead, the region 122 of the doped Group III nitride-type semiconductor material is initially formed and structured, for example, using a mask etching technique. Subsequently, a passivation layer 152 is formed to overlap with the edge side of the doped Group III nitride-type semiconductor material. The passivation layer 152 can be a protective and electrically insulating layer (e.g., silicon nitride, silicon oxynitride, etc.) formed, for example, by known deposition and structuring techniques. Subsequently, the Schottky contact material 132 is deposited on top of the region 122 of the doped Group III nitride-type semiconductor material such that the Schottky contact material 132 overlaps with the passivation layer 152. This technique mitigates any misalignment issues between the formation of the Schottky contact material 132 and the doped Group III nitride-type semiconductor material.

[0075] Figure 10D The embodiments are substantially the same as Figure 10B The embodiment is similar, except that the Schottky contact material 132 is intentionally formed to extend through the edge side of the gate structure 118. The extended portion of the Schottky contact material 132 forms a field plate structure on the drift region of the device, thereby improving the performance for a given on-resistance R. ON Breakdown voltage V BR In this case, the potential of the field plate is connected to the gate potential of the device.

[0076] Figure 10E The embodiments are substantially the same as Figure 10DThe embodiment is the same, except that the Schottky contact material 132 is interrupted between the gate structure 118 and the drift region of the device. This allows the field plate connected to the potential source to be independent of the gate potential (e.g., the source potential).

[0077] In the embodiments described above, the heterojunction forming layers (i.e., channel layer and barrier layer) of the semiconductor body are disclosed as GaN-based semiconductor layers. GaN is used for illustrative purposes only. More generally, any of a wide variety of combinations of group III nitride type semiconductor materials can be used to provide the device concepts described herein. Examples of these materials include, among others, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). In a broader sense, the compound semiconductor transistors described herein can be formed from any binary, ternary, or quaternary group III nitride type semiconductor material, where the piezoelectric effect is the origin of the device concept.

[0078] The term HEMT is also commonly referred to as HFET (Heterostructure Field-Effect Transistor), MODFET (Modulation-Doped FET), and MESFET (Metal-Semiconductor Field-Effect Transistor). The terms HEMT, HFET, MESFET, and MODFET are used interchangeably herein to refer to any group III nitride-based compound semiconductor transistor incorporating a junction (i.e., a heterojunction) between two materials with different band gaps as a channel.

[0079] The term "electrical connection" is intended to describe a low-ohmic electrical connection between components that are electrically connected together, such as a connection via a metal and / or a highly doped semiconductor.

[0080] As used herein, the terms “having,” “containing,” “including,” and “including” are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “one,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0081] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0082] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various substitutions and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A transistor device, comprising: Gate fins are segments of the semiconductor body deployed between pairs of gate trenches, each of which is formed in the upper surface of the semiconductor body. Multiple two-dimensional charge carrier gas channels are deployed at different vertical depths within a gate fin, each of the multiple two-dimensional charge carrier gas channels being formed by a heterojunction between two regions of a group III nitride type semiconductor material with different band gaps. Source and drain contacts are arranged on either side of the gate fin in the direction of current flow in the gate fin, and each of the source and drain contacts is electrically connected to each channel in the two-dimensional charge carrier gas channel. as well as A gate structure configured to control the conductive connection between the source and drain contacts by controlling the conductivity state of each of the two-dimensional charge carrier gas channels within the gate fins. The gate structure includes: A region of doped group III nitride type semiconductor material that covers the gate fins and extends into the gate trench; A conductive gate electrode is formed on a region of a doped group III nitride-type semiconductor material; and One or more current blocking devices are configured to prevent charge carriers from flowing into or out of regions of a doped group III nitride type semiconductor material.

2. The transistor device according to claim 1, wherein, The gate fin includes a first sidewall and a second sidewall defined by a pair of gate trenches, wherein each of the two-dimensional charge carrier gas channels extends to the first and second sidewalls of the gate fin, and wherein the one or more current blocking devices are configured to prevent charge carriers from flowing between the region of the doped group III nitride type semiconductor material and each of the two-dimensional charge carrier gas channels at the first and second sidewalls of the gate fin.

3. The transistor device according to claim 2, wherein, The one or more current blocking devices include a layer of group III nitride type semiconductor material that covers the gate fin and is formed along the first and second sidewalls of the gate fin.

4. The transistor device according to claim 3, wherein, The gate fin comprises a layered stack of GaN-based layer pairs with different aluminum contents, wherein each of the two-dimensional charge carrier gas channels appears near the heterojunction between the GaN-based layers in each layer pair, and wherein the layer of the group III nitride type semiconductor material is an AlGaN layer having a different bandgap from the channel layers of the GaN-based layer pair.

5. The transistor device according to claim 1, wherein, The gate structure further includes a conductive Schottky contact material deployed between the gate electrode and a region of the doped group III nitride type semiconductor material, and wherein the one or more current blocking devices comprise a Schottky diode formed by a Schottky junction between the Schottky contact material and the doped group III nitride type semiconductor material.

6. The transistor device according to claim 5, wherein, Conductive Schottky contact material extends into the gate trench.

7. The transistor device according to claim 1, wherein, The gate fin includes multiple pairs of semiconductor nitride layers, wherein each pair includes a barrier layer of a group III nitride-type semiconductor alloy and a channel layer of a group III nitride-type semiconductor, and wherein at least one of the barrier layer or channel layer from one of the layer pairs has a different thickness and / or alloy concentration compared to the corresponding barrier layer or channel layer from other pair within the gate fin.

8. The transistor device according to claim 7, wherein, The topmost barrier layer of the gate fin has a greater thickness than each of the barrier layers below it within the gate fin.

9. The transistor device according to claim 7, wherein, Each semiconductor nitride layer in the gate fin has a thickness between 5 nm and 100 nm.

10. The transistor device according to claim 7, wherein, The separation distance between pairs of gate trenches is 200 nm or less.

11. The transistor device according to claim 1, wherein, The gate fin includes a channel layer of a group III nitride type semiconductor material, wherein the region of the doped group III nitride type semiconductor material has a different band gap than the channel layer.

12. The transistor device according to claim 11, wherein, The channel layer is a GaN layer, and the region of the doped group III nitride type semiconductor material is a p-type AlGaN region.

13. The transistor device according to claim 1, wherein, The gate trench gradually tapers along the direction of current flow, causing the width of the gate fins to increase as the gate fins approach the drain contact.

14. The transistor device according to claim 13, wherein, Both gate trenches have a triangular shape, with a first side facing the source electrode and substantially orthogonal to the current flow direction, and a second side extending from the first side to a point facing the drain electrode.

15. The transistor device according to claim 13, wherein, Both gate trenches include rectangular sections and tapering sections, wherein the gate fins have substantially uniform width between the rectangular sections of the gate trenches, and wherein the width of the gate fins increases between the tapering sections of the gate trenches as the gate fins approach the drain contact.

16. The transistor device according to claim 1, wherein, Both gate trenches gradually taper in the vertical direction perpendicular to the upper surface of the semiconductor body, causing the width of the gate trench to decrease as it moves toward the bottom of the gate trench.

17. The transistor device according to claim 1, wherein, The gate electrode includes a first outer edge side and a second outer edge side extending across the current flow direction, wherein both gate trenches are completely contained within the first outer edge side and the second outer edge side of the gate electrode.

18. The transistor device according to claim 1, wherein, The gate electrode includes a first outer edge side and a second outer edge side extending across the current flow direction, and wherein two gate trenches extend through one or both of the first outer edge side and the second outer edge side of the gate electrode.

19. A transistor device, comprising: Gate fins are segments of the semiconductor body deployed between pairs of gate trenches, each of which is formed in the upper surface of the semiconductor body. Multiple two-dimensional charge carrier gas channels are deployed at different vertical depths within a gate fin, each of the multiple two-dimensional charge carrier gas channels being formed by a heterojunction between two regions of a group III nitride type semiconductor material with different band gaps. as well as A gate structure is formed on top of the gate fins and extends into two gate trenches. The gate structure is configured to apply a vertical electric field from above the gate fins and a transverse electric field from the outside of the first and second sidewalls relative to the ground surface of the gate fins. The vertical and transverse electric fields jointly control the conductivity state of each two-dimensional charge carrier gas channel within the gate fins. The gate structure includes a region of doped Group III nitride type semiconductor material, which is configured to apply a transverse electric field and a vertical electric field, and one or more current blocking devices configured to prevent charge carriers from flowing into or out of the region of the doped Group III nitride type semiconductor material.

20. A method of forming a transistor device, comprising: A semiconductor body is provided, comprising multiple two-dimensional charge carrier gas channels deployed at different vertical depths below the upper surface of the semiconductor body; A gate fin is formed in the semiconductor body by forming a pair of gate trenches in the upper surface of the semiconductor body. The pair of gate trenches expose each of a plurality of two-dimensional charge carrier gas channels at the first sidewall and the second sidewall of the gate fin. Source contacts and drain contacts are provided, and the source contacts and drain contacts are arranged such that the gate fin is between the source contacts and drain contacts in the current flow direction of the gate fin, and such that each of the source contacts and drain contacts is electrically connected to each of the plurality of two-dimensional charge carrier gas channels. A gate structure is provided, configured to control the conductive connection between the source contact and the drain contact by controlling the conductivity state of each of the plurality of two-dimensional charge carrier gas channels. The gate structure includes: A layer of doped group III nitride-type semiconductor material is formed, covering the gate fins and extending into the gate trench; a conductive gate electrode is formed on top of the layer of doped group III nitride-type semiconductor material; and One or more current blocking devices are formed to prevent charge carriers from flowing into or out of regions of the doped group III nitride type semiconductor material.

21. The method according to claim 20, wherein, The gate structure includes: A blanket coating of deposited group III nitride type semiconductor material; A conductive Schottky contact material is deposited on top of a blanket coating of a doped group III nitride semiconductor material; and By utilizing a common mask to structure a blanket layer of Schottky contact material and a doped group III nitride type semiconductor material, a self-aligned edge side of the gate structure is formed.

22. The method according to claim 20, wherein, The gate structure includes: a deposited blanket layer of doped group III nitride type semiconductor material; The blanket coating of a doped group III nitride type semiconductor material is structured to include edge sides extending across the current flow direction. A passivation layer is formed, covering the upper surface of the semiconductor body and extending along the edge side of the doped group III nitride type semiconductor material; and Deposit conductive Schottky contact material so that the Schottky contact material contacts the doped group III nitride type semiconductor material and extends on the passivation layer.

23. The method according to claim 22, wherein, The Schottky contact material is formed to extend through the edge side of a doped group III nitride type semiconductor material, and the method further includes configuring the Schottky contact material extending through the edge side of the doped group III nitride type semiconductor material as a field plate.

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