Semiconductor structure and method of forming a semiconductor device

Abstract

A method for forming a semiconductor device includes: forming a bottom electrode; forming a dielectric layer; forming a phase change random access memory (PCRAM) region in contact with the dielectric layer; and forming a top electrode. The dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode. A filament is formed in the dielectric layer. The filament is in contact with the dielectric layer. According to other embodiments of the present application, a semiconductor structure is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming a semiconductor device. Background Art

[0002] Phase change memory can use chalcogenide semiconductors to store states. Chalcogenide semiconductors have a crystalline state and an amorphous state. In the crystalline state, phase change materials have a low resistivity, while in the amorphous state, they have a high resistivity. The ratio of the resistance of phase change materials in the amorphous and crystalline states is typically greater than 1,000, so phase change memory devices are less likely to have erroneous readings. Chalcogenide materials are stable in both the crystalline and amorphous states over a certain temperature range, and can be switched back and forth between the two states by electrical pulses.

[0003] Phase change memory has several operational and engineering advantages, including high speed, low power, non-volatility, high density, and low cost. For example, phase change memory is non-volatile and can be written quickly, for example, in less than about 50 nanoseconds. Phase change memory cells can have high density. In addition, phase change memory is compatible with CMOS logic and can generally be manufactured at low cost compared to other types of memory cells. Summary of the invention

[0004] In some embodiments, a method of forming a semiconductor device includes: forming a bottom electrode; forming a dielectric layer; forming a phase change random access memory (PCRAM) region in contact with the dielectric layer; forming a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode; and forming a filament in the dielectric layer, wherein the filament is in contact with the dielectric layer.

[0005] In some embodiments, a semiconductor structure includes: an array of memory cells, wherein each memory cell in the array of memory cells includes: a bottom electrode; a dielectric layer; a filament located in the dielectric layer; a phase change random access memory (PCRAM) region in contact with the dielectric layer and the filament; and a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode.

[0006] In some embodiments, a semiconductor structure includes: a plurality of bottom electrodes; a dielectric layer located above and in contact with the plurality of bottom electrodes; a plurality of filaments located in the dielectric layer, wherein each of the plurality of filaments overlaps with a corresponding one of the plurality of bottom electrodes; a plurality of chalcogenide semiconductor regions, wherein each of the plurality of chalcogenide semiconductor regions overlaps with and in contact with a corresponding one of the plurality of filaments; and a plurality of top electrodes covering the plurality of chalcogenide semiconductor regions.

[0007] According to other embodiments of the present application, a method for generating a self-aligned heater for a PCRAM is also provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figures 1 to 8 A cross-sectional view illustrates an intermediate stage in the formation of a phase change random access memory (PCRAM) cell including a self-aligned heater in accordance with some embodiments.

[0010] Fig. 9 Operations performed on a PCRAM cell according to some embodiments are shown.

[0011] Figures 10 to 12 Cross-sectional views illustrating intermediate stages in the formation and operation of a PCRAM cell according to some embodiments.

[0012] Figures 13 to 15 Cross-sectional views illustrating intermediate stages in the formation and operation of a PCRAM cell according to some embodiments.

[0013] Figures 16 to 18 Cross-sectional views illustrating intermediate stages in the formation and operation of a PCRAM cell according to some embodiments.

[0014] Fig.19 A perspective view of a PCRAM array is shown in accordance with some embodiments.

[0015] Fig. 20 A process flow for forming a PCRAM cell according to some embodiments is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides a variety of different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to facilitate description of the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0018] According to some embodiments, a phase change random access memory (PCRAM) cell with a self-aligned resistive random access memory (ReRAM) heater and a method for forming the same are provided. According to some embodiments, intermediate stages in the formation of a memory cell are shown. Some variations of some embodiments are discussed. The embodiments discussed herein will provide examples to enable the subject matter of the present disclosure to be performed or used, and those of ordinary skill in the art will readily understand the modifications that may be made while remaining within the intended scope of the different embodiments. Throughout the various views and exemplary embodiments, the same reference numerals are used to designate the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may also be implemented in any reasonable order.

[0019] According to some embodiments of the present disclosure, a PCRAM cell is formed adjacent to a dielectric layer configured to function as a resistive random access memory (ReRAM) cell. Before or after forming a die or wafer on which the PCRAM cell is located, a filament formation process is performed to form a filament in the dielectric layer. The filament is connected in series with the PCRAM cell. The filament has a relatively high resistance and functions as a heater for the PCRAM cell. The filament is self-aligned with the corresponding PCRAM cell.

[0020] Figures 1 to 9 A cross-sectional view showing an intermediate stage in the formation of a PCRAM cell according to some embodiments of the present disclosure and a read / write operation of the PCRAM cell. The corresponding process is also schematically shown in Fig. 20 The process flow shown.

[0021] Figure 1A cross-sectional view of a wafer 10 is shown, which includes a plurality of device dies 12. A substrate 20 is included in the wafer 10. The substrate 20 may be a doped (e.g., doped with a p-type or n-type dopant) or undoped semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc. According to some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; a compound semiconductor including silicon carbide, SiPC, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0022] The transistor is formed on the front surface of the semiconductor substrate 20. According to some embodiments, the transistor includes a selector 22, which includes a gate dielectric 25, a gate electrode 26, source / drain regions 24A and 24B, and contact plugs (vias) 30 and 32. The corresponding process is shown as Fig. 20 202 in the process flow 200 shown in . The source / drain regions 24A and 24B may extend into the semiconductor substrate 20. The gate electrode 26 and the contact plugs 30 and 32 may be formed in the dielectric layer 31, which may include an interlayer dielectric (ILD) and may or may not include an intermetallic dielectric (ILD). According to some embodiments of the present disclosure, the dielectric layer 31 is formed of a low-k dielectric material having a dielectric constant (k value) of less than about 3.0 or less. The dielectric layer 31 may be formed of Black Diamond (a registered trademark of Applied Materials, Inc.), a carbon-containing low-k dielectric material such as SiOC (having pores therein), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present invention, the formation of the dielectric layer 31 includes depositing a dielectric material containing a porogen and then performing a curing process to drive off the porogen, and thus the remaining dielectric layer 31 is porous. The dielectric layer 31 may also be formed of silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like.

[0023] Metal lines 34 are formed in the dielectric layer 31. According to some embodiments, each metal line 34 includes a diffusion barrier layer and a copper-containing material located above the corresponding diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and has the function of preventing copper in the copper-containing material from diffusing into the dielectric layer 31. The metal line 34 may have a single damascene structure, a dual damascene structure, etc. The formation of the metal line 34 may include: etching the corresponding dielectric layer 31 to form a trench; depositing a blanket diffusion barrier layer extending into the trench; depositing a conductive material to completely fill the trench; and performing a planarization process. Part of the conductive material and the blanket diffusion barrier layer outside the trench are removed by the planarization process, thereby leaving the metal line 34 in the corresponding dielectric layer 31. The copper-containing material may include substantially pure copper (e.g., copper with an atomic percentage greater than 90%) or a copper alloy.

[0024] Figure 2 The formation of more dielectric layers and metal lines, vias, and pads above and electrically connected to the selector 22 is shown. According to some embodiments, the dielectric layer includes a dielectric layer 36, which may be an intermetallic dielectric (IMD). According to some embodiments, the dielectric layer 36 may be formed of a low-k dielectric material. Metal lines 40 and vias 38 may be formed in the dielectric layer 36. The metal lines 40 and vias 38 may be formed using a single damascene or dual damascene process. It will be appreciated that although one metal layer (metal lines 40 in the same plane are collectively referred to as metal layers) is described as an example, more than one metal layer may be formed. Additionally, a via 44 ( Figure 3 ).

[0025] Figure 3 The formation of dielectric layer 42 is shown. The corresponding process is shown as Fig. 20 204 in the process flow 200 shown in FIG. According to some embodiments of the present disclosure, the dielectric layer 42 is formed of silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, etc. Alternatively, the dielectric layer 42 may be formed of a low-k dielectric material, which may be a low-k dielectric material containing oxygen and carbon, HSQ, MSQ, etc.

[0026] Further references Figure 3 , a conductive via 44 is formed in the dielectric layer 42. The corresponding process is shown as Fig. 20206 in the process flow 200 shown in FIG. According to some embodiments, the conductive via 44 is formed of or includes a metal, which may include tungsten, cobalt, copper, nickel, etc. or their alloys. The conductive via 44 may also include a conductive barrier and a metal region (such as a copper region) located on the conductive barrier. The formation of the conductive via 44 may include: forming an opening in the dielectric layer 42; filling the opening with a conductive material; and performing a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process to flatten the top surface of the via 44 and the dielectric layer 42. According to some embodiments, the via 44 has a top view shape of a circle or a rectangle (such as a square). The size of the via 44 is small enough to limit the location where the filament (heater) is formed, and the via 44 is preferably small. On the other hand, the size of the heater is independent of the size of the via 44, so the via 44 can be formed large enough so that there is no process difficulty. According to some embodiments, the lateral dimension L1 (which may be a length or a diameter, for example) of the via 44 may be in a range between about 20nm and about 100nm.

[0027] Figure 4 4 shows the deposition of the ReRAM layer 46 according to some embodiments. The corresponding process is shown as Fig. 20 208 in the process flow 200 shown in FIG. 20. The ReRAM layer 46 is formed of a dielectric material configured to form conductive filaments therein by applying an appropriate electric field. For example, the ReRAM layer 46 may be formed of or include a metal-containing high-k dielectric material that may be a metal oxide. The metal may be a transition metal. According to some embodiments of the present disclosure, the ReRAM layer 46 includes HfO x 、ZrO x 、TaO x 、TiO x , VO x 、NiO x 、NbO x 、LaO x or a combination thereof. The thickness T1 of the ReRAM layer 46 is small, so that a voltage required to form filaments in the ReRAM 46 is low. For example, the thickness T1 may be in a range between about 3 nm and about 10 nm. The ReRAM layer 46 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.

[0028] Above the ReRAM layer 46, a PCRAM layer 48 is deposited over and in contact with the ReRAM layer 46. The corresponding process is shown as Fig. 20 The PCRAM layer 48 may be formed of or include a chalcogenide material, which may be Ge x Sby Te z , wherein x, y, and z represent the ratio of each element. According to some embodiments, x is approximately 2, y is approximately 2, and z is approximately 5. The thickness T2 of the PCRAM layer 48 may be in a range between about 5 nm and about 150 nm. According to some embodiments, the formation process (such as temperature and deposition rate) of the PCRAM layer 48 is controlled so that the PCRAM layer 48 is in a crystalline state. Therefore, the PCRAM layer 48 has a lower resistivity (compared to the resistivity in the amorphous state). For example, the resistivity of the PCRAM layer 48 in the crystalline state may be in a range between about 1E-5Ω·cm and about 5E-3Ω·cm. According to an alternative embodiment, the phase change material of the PCRAM layer 48 may be represented as Ge x Sb y Te z X, where X is a material selected from Ag, Sn, In, Si, N, and combinations thereof. PCRAM layer 48 may also be formed using physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), CVD, etc. The temperature for forming PCRAM layer 48 may range between about -40°C and about 400°C.

[0029] Above the PCRAM layer 48, a conductive layer 50 (also referred to as a top electrode layer) is deposited. The corresponding process is shown as Fig. 20 212 in the process flow 200 shown in FIG. According to some embodiments, the top electrode layer 50 is formed of a conductive material, which may include tungsten, nickel, cobalt, aluminum, etc. The top electrode layer 50 may also include an adhesion layer such as a titanium layer and an aluminum copper layer located above the titanium layer. The formation method may include physical vapor deposition (PVD), CVD, metal organic chemical vapor deposition (MOCVD), etc.

[0030] Figure 5 The patterning of the top electrode layer 50 and the PCRAM layer 48 is shown to form the top electrode 50' and the phase change element 48', respectively. The corresponding process is shown as Fig. 20 214 in the process flow 200 shown in FIG. According to some embodiments, the patterning process includes forming a patterned etching mask 52, which may be formed of a photoresist and may or may not include a hard mask, such as a titanium nitride layer, and then etching the top electrode layer 50 and the PCRAM layer 48 using the patterned etching mask 52 to define a pattern. After the etching process, the etching mask 52 is removed. The obtained top electrode 50' and phase change element 48' can form an array, such as Fig.19As shown. Patterning can be performed using the ReRAM layer 46 as an etch stop layer. It should be understood that over-etching may occur when patterning the phase change element 48'. As a result, the exposed portion of the ReRAM layer 46 exposed after removing the overlying portion of the PCRAM layer 48 in the patterning may be thinned. As a result, the portion of the ReRAM layer 46 directly below the phase change element 48' may be thicker than the thinned portion of the ReRAM layer 46. After the patterning process, the ReRAM layer 46 remains a blanket layer covering the entire PCRAM array. According to some embodiments, the lateral dimension L2 (e.g., which may be a length, width, or diameter) of the top electrode 50' and the phase change element 48' may be in a range between and about 110nm. The lateral dimension L2 may be greater than the lateral dimension L1 by a difference of approximately 10nm.

[0031] refer to Figure 6 , depositing dielectric layer 54. The corresponding process is shown as Fig. 20 216 in the process flow 200 shown in FIG. 216. According to some embodiments, dielectric layer 54 is formed of a low-k dielectric material, such as a dielectric material containing carbon and oxygen. The k value of dielectric layer 54 may be, for example, less than about 3.0. The top surface of dielectric layer 54 may be higher than the top surface of top electrode 50'. A planarization process may be performed to planarize the top surface of dielectric layer 54.

[0032] Next, if Figure 7 As shown, a via 56 is formed to contact the top electrode 50'. A metal line 58 is also formed over and bonded to the via 56. The corresponding process is shown as Fig. 20 218 in the process flow 200 shown in FIG. According to some embodiments, the metal line 58 and the via 56 are formed in a dual damascene process, which includes: etching into the dielectric layer 54 to form a via opening and a trench combined with the via opening; and filling the trench and the via opening with a conductive material, and then performing a planarization process such as a CMP process or a mechanical grinding process. The metal line 58 can be used as a bit line of the corresponding PCRAM array. In a subsequent process, features covering the metal line 58 and the dielectric layer 54 are formed to complete the formation of the wafer 10 and the corresponding tube core 12. A sawing process is then performed to saw the wafer 10 into individual tube cores 12.

[0033] According to some embodiments, at a time after metal line 58 is formed, since the entirety of ReRAM layer 46 is a dielectric, the corresponding PCRAM array does not have a heater contacting phase change element 48'. Figure 8As shown, at a time after the metal line 58 is formed, a filament formation process is performed to form a filament 62 as a heater for the PCRAM array 60. The PCRAM array 60 includes PCRAM cells 61 arranged in an array. The filament formation process can be performed at any time after the metal line 58 is formed, as long as a filament can be formed for each cell in the PCRAM array 60. According to some embodiments of the present disclosure, the filament formation process is performed at the wafer level. For example, the filament formation process can be performed immediately after the metal line 58 is formed and before any overlying features are formed. The filament formation process can also be performed after the formation of the wafer 10 is completed and before the cutting process of sawing the wafer 10 into the tube core 12. The filament formation process can also be performed at the tube core level, for example, after the tube core 12 is packaged, and the filament formation process can be performed through the external connectors of the tube core 12 (such as, pins, solder areas, metal pads, etc.).

[0034] Figure 8 An exemplary filament formation process according to some embodiments of the present disclosure is shown. The corresponding process is shown as Fig. 20 200 in the process flow 200 shown in . According to some embodiments, the filament formation process (also referred to as a formation operation) is performed by applying a bias voltage V1 on the metal line 58 (which may be a bit line) and grounding the source line 34A (which is connected to the source / drain region 24A of the selector 22). The gate electrode 26 of the corresponding selector 22 is connected to the word line, which is applied with an appropriate voltage V3 to turn on the corresponding selector. Therefore, an electric field E is applied to a portion of the ReRAM layer 46, which is between the corresponding phase change element 48' and the through hole 44. The electric field E is high enough to form a filament 62 in the corresponding portion of the ReRAM layer 46. According to some embodiments of the present disclosure, the voltage V1 is in a range between about 2 volts and about 5 volts. It should be understood that the voltage V1 is related to the thickness of the ReRAM layer 46, and the thicker the ReRAM layer 46, the higher the voltage V1 is used. The filament formation process is performed for each phase change region 48' so that each phase change region 48' has a filament 62 located thereunder and in contact therewith. The formation of filaments 62 for the entire PCRAM array 60 is performed by applying a voltage V1 to each pair of bit line BL and word line WL and grounding the corresponding source line SL.

[0035] As a result of applying the electric field E, filaments 62 are generated in ReRAM 46 to connect vias 44 to corresponding phase change elements 48' thereon. Filaments 62 may be formed due to oxygen vacancies generated in metal-containing ReRAM layer 46, and portions of ReRAM layer 46 having oxygen vacancies are interconnected to form a conductive path. Thus, filaments 62 include the same metal as the dielectric portion of ReRAM 46, which may include Hf, Zr, Ta, Ti, V, Ni, Nb, La, or a combination thereof.

[0036] According to some embodiments, Figure 8 As shown, PCRAM cells 61 form an array, which includes an array of phase change elements 48' and an array of filaments 62 in contact with the array of phase change elements. Each PCRAM cell 61 may include a via 44 as a bottom electrode, a filament 62 as a heater, a phase change element 48', and a top electrode 50'. This means that the array of PCRAM cells 61 includes a ReRAM array, which is formed by filaments 62 and corresponding dielectric layers 46.

[0037] According to some embodiments, the lateral dimension L3 of the filament 62 is less than about 10 nm, and the lateral dimension may be in a range between about 0.5 nm and about 10 nm. Since the formation of the filament 62 may be affected by random factors, unlike conventional heaters formed by through holes, the size, shape, relative position, etc. of the filament 62 of different PCRAM cells 61 may be different from each other. For example, Figure 8 An example is shown in which the filament 62 on the left has a different shape than the filament 62 on the right. In addition, the bottom end of the filament 62 contacts the corresponding through hole 44, and the top end contacts the corresponding phase change element 48'. However, the contact points of the filament 62 with the corresponding through hole 44 below and the corresponding phase change element 48' above can vary between PCRAM cells, and the relative contact positions are random. For example, Figure 8 The left filament 62 contacts the left portion of the through hole 44 below, and Figure 8The filament 62 on the right contacts the middle of the through hole 44 below. The filament 62 may also be generated when contacting the top corner of the through hole 44 below. In addition, the shape of the filament 62 (in the cross-sectional view) may be similar to the shape of another filament, or different from the shape of another filament. For example, the cross-sectional shape of the filament 62 may be straight, curved, zigzag, etc. The lateral dimensions of the filament 62 may also vary from filament to filament, for example, the ratio of the width of the wide filament to the width of the narrow filament is greater than about 0.2, and the ratio may be in a range between 1.0 and about 1.4. According to some embodiments, different shapes, different sizes, different relative positions, etc. of the filament 62 may be found in any combination in the same PCRAM array 60. In general, the filament 62 is different from a conventionally formed heater due to its irregular shape, size, position, etc.

[0038] Fig. 9 Shown in Fig. 9 An example of a read operation or a write operation performed on the PCRAM cell 61 on the left. The corresponding process is shown as Fig. 20 Process 222 in the process flow 200 shown in . The write operation includes: a reset operation, which resets the phase change element 48' to an amorphous phase; and a set operation, which sets the phase change element 48' to a crystalline phase. In order to reset the phase change element 48', a voltage V2 is applied so that a large current pulse flows through the filament 62 for a short time. The temperature of the filament 62 increases due to its relatively high resistivity, causing the programming region 48α of the phase change element 48' to melt. The voltage V2 is then rapidly reduced to zero, and the temperature of the filament 62 and the programming region 48α in the phase change element 48' drops rapidly. Therefore, the molten region 48α becomes amorphous and has a high resistivity. The amorphous region 48α is connected in series with any remaining crystalline region of the phase change element 48', and the amorphous region 48α determines the high resistance of the corresponding PCRAM cell 61. To set the PCRAM cell 61 to a crystalline phase, a moderate current pulse is applied at a temperature between the crystallization temperature and the melting temperature to anneal the amorphous region 48α for a period of time long enough to crystallize the amorphous region 48α. To read the state of the PCRAM cell 61, the resistance of the cell is measured by flowing a current small enough not to disturb the current state. The voltage V3 is used to select a corresponding row of the array for a read or write operation. According to some embodiments, the voltage V2 for a write operation may be in a range between about 1.0 volts and about 3.0 volts, and the voltage V2 for a read operation may be in a range between about 0.3 volts and about 0.9 volts.

[0039] After forming the filaments 62 for all PCRAM cells 61 of the entire PCRAM array 60, and throughout the life of the corresponding die 12, the filaments 62 will remain to maintain the functionality of the PCRAM cells 61. In other words, once the filaments 62 are formed, they will not be dissolved and formed again as in conventional ReRAM cells. This makes the filaments 62 always available for heating the phase change element 48' during read and write operations. Therefore, the read and write operations are designed not to dissolve the filaments 62, and the bias direction during the read and write operations is always the same as the bias direction used to form the filaments 62. For example, assuming that the formation of the filaments 62 is performed with a voltage applied to the bit line 58 higher than the voltage applied to the source line 34A, the voltage applied to the bit line 58 will also be higher than the voltage applied to the source line 34A during the read and write operations. In other words, the current direction of the filament formation process, the read operation, and the write operation is the same. Otherwise, filaments 62 receiving the reverse bias voltage will dissolve and PCRAM array 60 will malfunction. According to some embodiments, the current for the filament formation process, read operations, and write operations are all in the same direction, ie, from bit line 58 to source line 34A.

[0040] According to some embodiments, control circuit 64 is formed to be electrically and signally connected to PCRAM array 60. Control circuit 64 is connected to and configured to control voltage and current sources and measurement circuits for filament formation process, read operation and write operation. Control circuit 64 is also configured to control filament formation process, read operation and write operation so that the bias direction for filament formation process is the same as the bias direction for read and write operation.

[0041] In such Figure 8 In the above exemplary filament formation process shown, a higher voltage is applied to bit line 58 than source line 34A. According to alternative embodiments, a source loading scheme is employed, and the voltage applied to source line 34A is higher than the voltage applied to bit line 58. For example, by grounding bit line 58 and applying a positive voltage to source line 34A. According to these embodiments, during write and read operations, the voltage applied to source line 34A is also higher than the voltage applied to bit line 58. In other words, the direction of current flow for the filament formation process, read operations, and write operations is the same, i.e., from source line 34A to bit line 58.

[0042] The filament 62 has a smaller lateral dimension L3, for example, less than about 10 nm. In comparison, the lateral dimension of a conventional heater formed using a damascene process or a deposition and patterning process is typically greater than 20 nm. The smaller lateral dimension of the filament 62 means that a smaller current can be used for a write operation. For example, assume that the lateral dimension L3 of the filament 62 is 10 nm, while the lateral dimension of a conventional heater is 20 nm. The write current of a PCRAM cell according to an embodiment of the present disclosure can be as low as 25% of the write current used to write a conventional PCRAM cell. When the lateral dimension L3 of the filament 62 is smaller, even a smaller write current can be used.

[0043] Figures 10 to 12 1 and 2 illustrate cross-sectional views of intermediate stages in the formation and operation of a PCRAM array according to other embodiments of the present disclosure. Unless otherwise indicated, these embodiments (and Figures 13 to 18 The materials, forming process and operation of the components in the embodiment shown in FIG. Figures 1 to 9 Similar components denoted by similar reference numerals in the embodiments shown in FIG. 1 are substantially the same. Therefore, the discussion of the previous embodiments can be found in detail. Figures 12 to 18 Details of the formation process, operations and materials of the components shown.

[0044] Figures 10 to 12 The embodiment shown is Figures 1 to 9 The illustrated embodiment is similar, except that the ReRAM layer 46 is patterned into an array of ReRAM 46' (each covering a via 44) rather than leaving it as a blanket layer. Fig.10 , by executing Figures 1 to 7 The process shown is similar to the process used to form the structure, except that the formation of the via 44 and the ReRAM 46 is similar to the process shown in FIG. Figures 3 to 5 44 and ReRAM 46', respectively. Dielectric layer 42 is then deposited. If ReRAM 46' is covered by dielectric layer 42, a patterning process may be performed to etch through the top of dielectric layer 42 covering ReRAM 46', thereby exposing ReRAM 46'. Next, a process similar to Figures 4 to 7 The process shown in the figure is used to form the remaining PCRAM array 60, and in Fig.10 The resulting structure is shown in . According to these embodiments, dielectric layer 42 may or may not include a top portion covering ReRAM 46 ′, and if a top portion is present, phase change element 48 ′ will extend into the opening in the top portion of dielectric layer 42 .

[0045] Fig.11 FIG. 4 shows the formation of filaments 62 according to some embodiments. The formation details of filaments 62 are substantially the same as those of reference 1. Figure 8 The discussion is the same and will not be repeated here. Fig.12 An exemplary writing or reading process according to some embodiments is shown. Fig. 9 The details were discussed and will not be repeated here.

[0046] Figures 13 to 15 1 shows a cross-sectional view of an intermediate stage in the formation and operation of a PCRAM array according to some embodiments of the present disclosure. Figures 1 to 9 The embodiment shown is similar except that the ReRAM 46' has edges that are flush with corresponding edges of the upper phase change element 48'. Fig.13 , by executing Figures 1 to 4 Next, the same etching mask is used to pattern the structure in an etching process. Figure 4 The ReRAM layer 46, PCRAM layer 48 and top electrode layer 50 shown in FIG. The etching process can be performed using the dielectric layer 42 as an etch stop layer. The top electrode layer 50, the PCRAM layer 48 and the remaining portion of the ReRAM layer 46 are the top electrode 50', the phase change element 48' and the ReRAM 46', respectively. Then the dielectric layer 54 is formed. In the subsequent process, the Figure 6 and Figure 7 The process shown in the figure, the obtained structure is as follows Fig.13 shown.

[0047] Fig.14 FIG. 4 shows the formation of filaments 62 according to some embodiments. The formation details of filaments 62 are substantially the same as those of reference 1. Figure 8 The discussion is the same and will not be repeated here. Fig.15 illustrative write operations or read operations according to some embodiments are shown. Fig. 9 The details were discussed and will not be repeated here.

[0048] Figures 16 to 18 1 shows a cross-sectional view of an intermediate stage in the formation and operation of a PCRAM array according to some embodiments of the present disclosure. Fig.13 The embodiment shown in FIG. 1 is similar to that shown in FIG. 1 , except that ReRAM 46 ′ is formed above phase change element 48 ′ instead of below. The initial formation process is shown in FIG. Figures 1 to 3 Next, a PCRAM layer 48, a top electrode layer 50, and a ReRAM layer 46 are formed. Figure 4The structure shown in FIG. 4 is similar to that shown in FIG. 4 , except that the ReRAM layer 46 is above the PCRAM layer 48 instead of below. Next, the top electrode layer 50, the ReRAM layer 46, and the PCRAM layer 48 are patterned in an etching process using the same etching mask. The etching process may be performed using the dielectric layer 42 as an etching stop layer. Fig.16 As shown, the top electrode layer 50, the remaining portions of the ReRAM layer 46 and the PCRAM layer 48 are the top electrode 50', the ReRAM 46' and the phase change element 48', respectively. Then, a dielectric layer 54 is formed. In a subsequent process, Figure 6 and Figure 7 The process shown in the figure, the obtained structure is as follows Fig.16 shown.

[0049] Fig.17 FIG. 4 shows the formation of filament 62 according to some embodiments. Fig.17 As shown, filament 62 may be formed by source loading, wherein a positive voltage V1 is applied to source line 34A, and bit line 58 is electrically grounded. According to an alternative embodiment, formation of filament 62 may be performed by applying a positive voltage V1 to bit line 58, and source line 34A is electrically grounded. The formation details of filament 62 are substantially the same as those of reference 1. Figure 8 The discussion is the same and will not be repeated here.

[0050] Fig.18 illustratively shows an exemplary write or read operation. According to some embodiments of the present disclosure, Fig.18 As shown, a write operation or a read operation is performed by source loading, wherein a positive voltage V2 is applied to the source line 34A, and the bit line 58 is electrically grounded. According to an alternative embodiment, a write operation or a read operation is performed by applying a positive voltage V2 to the bit line 58, and the source line 34A is electrically grounded. Fig. 9 The details are discussed and will not be repeated here. It should be understood that the bias direction for write and read operations remains the same as the bias direction used to form the filament 62. Otherwise, the filament will be dissolved.

[0051] Fig.19 A perspective view of a PCRAM array 60 including bit lines 58 is schematically shown. ReRAM 46' is formed below and connected to bit lines 58. It is understood that although ReRAMs 46' are shown as discrete elements of the array, ReRAM 46' can also be part of a continuous and blanket dielectric layer. Top electrode 50' and phase change element 48' are also schematically shown. Vias 44 ( Fig. 9 , Fig.12 , Fig.15 and Fig.18 ) is not in Fig.19 Shown in.

[0052] Embodiments of the present invention have several advantageous features. By forming filaments for ReRAM and using these filaments as heaters for PCRAM, the heaters can be made much narrower than conventional heaters formed using conventional heater formation processes. The write current required for write operations is greatly reduced.

[0053] According to some embodiments of the present disclosure, a method includes: forming a bottom electrode; forming a dielectric layer; forming a PCRAM region in contact with the dielectric layer; forming a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode; and forming a filament in the dielectric layer, wherein the filament is in contact with the dielectric layer. In an embodiment, forming the PCRAM region includes depositing a chalcogenide semiconductor material. In an embodiment, forming the filament includes applying an electric field on the dielectric layer to generate the filament. In an embodiment, the method further includes: writing to the PCRAM region or reading the state of the PCRAM by conducting a current through the PCRAM region, wherein a first direction of the current is the same as a second direction of the electric field. In an embodiment, forming the dielectric layer includes depositing a selected from HfO x 、ZrO x 、TaO x 、TiO x , VO x 、NiO x 、NbO x 、LaO x and combinations thereof. In an embodiment, the method further comprises: forming a memory array, comprising forming a first array of PCRAM regions, wherein the PCRAM region is an array element in the array of PCRAM regions; and forming an array of filaments in contact with the array of PCRAM regions, wherein the filaments are additional array elements in the array of filaments. In an embodiment, the PCRAM region is located above the dielectric layer, and wherein, when the filaments are formed, the dielectric layer extends laterally beyond the PCRAM region. In an embodiment, the PCRAM region is located above the dielectric layer, and the method further comprises: depositing a blanket PCRAM layer; and patterning the blanket PCRAM layer and the dielectric layer using the same etch mask, wherein the blanket PCRAM layer is patterned into a plurality of PCRAM regions including the PCRAM region.

[0054] According to some embodiments of the present disclosure, a structure includes: an array of memory cells, wherein each memory cell in the array of memory cells includes: a bottom electrode; a dielectric layer; a filament in the dielectric layer; a PCRAM region in contact with the dielectric layer and the filament; and a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode. In an embodiment, the dielectric layer and the filament include the same metal. In an embodiment, the PCRAM region includes a chalcogenide semiconductor material. In an embodiment, the filaments of different memory cells in the array of memory cells have different shapes. In an embodiment, the filaments of different memory cells in the array of memory cells have different relative positions relative to the bottom electrode in the corresponding memory cell. In an embodiment, the dielectric layer of the array of memory cells is part of a continuous dielectric layer that extends throughout the array of memory cells. In an embodiment, the dielectric layers of the array of memory cells are spaced apart from each other by additional dielectric regions.

[0055] According to some embodiments of the present disclosure, a structure includes: a plurality of bottom electrodes; a dielectric layer located above and in contact with the plurality of bottom electrodes; a plurality of filaments in the dielectric layer, wherein each of the plurality of filaments overlaps with a corresponding one of the plurality of bottom electrodes; a plurality of chalcogenide semiconductor regions, wherein each of the plurality of chalcogenide semiconductor regions overlaps with and contacts a corresponding one of the plurality of filaments; and a plurality of top electrodes covering the plurality of chalcogenide semiconductor regions. In an embodiment, the plurality of filaments penetrate the dielectric layer. In an embodiment, the plurality of filaments have different relative positions relative to corresponding underlying bottom electrodes of the plurality of bottom electrodes. In an embodiment, the lateral dimensions of the plurality of filaments are less than about 10 nm. In an embodiment, the thickness of the dielectric layer is in a range between about 3 nm and about 10 nm.

[0056] In some embodiments, a method of forming a semiconductor device includes: forming a bottom electrode; forming a dielectric layer; forming a phase change random access memory (PCRAM) region in contact with the dielectric layer; forming a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode; and forming a filament in the dielectric layer, wherein the filament is in contact with the dielectric layer. In some embodiments, forming the PCRAM region includes depositing a chalcogenide semiconductor material. In some embodiments, forming the filament includes applying an electric field to the dielectric layer to generate the filament. In some embodiments, further comprising: writing to the PCRAM region or reading the state of the PCRAM by conducting a current through the PCRAM region, wherein a first direction of the current is the same as a second direction of the electric field. In some embodiments, forming the dielectric layer includes depositing a selected from HfO x 、ZrO x 、TaO x 、TiO x , VOx 、NiO x 、NbO x 、LaO x and combinations thereof. In some embodiments, a memory array is formed, comprising: forming a first array of PCRAM regions, wherein the PCRAM region is an array element in the first array of PCRAM regions; and forming an array of filaments in contact with the array of PCRAM regions, wherein the filaments are additional array elements in the array of filaments. In some embodiments, the PCRAM region is located above a dielectric layer, and wherein, when the filaments are formed, the dielectric layer extends laterally beyond the PCRAM region. In some embodiments, the PCRAM region is located above a dielectric layer, and the method of forming a semiconductor device further comprises: depositing a blanket PCRAM layer; and patterning the blanket PCRAM layer and the dielectric layer using the same etch mask, wherein the blanket PCRAM layer is patterned into a plurality of PCRAM regions including the PCRAM region.

[0057] In some embodiments, a semiconductor structure includes: an array of memory cells, wherein each memory cell in the array of memory cells includes: a bottom electrode; a dielectric layer; a filament located in the dielectric layer; a phase change random access memory (PCRAM) region in contact with the dielectric layer and the filament; and a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode. In some embodiments, the dielectric layer and the filament include the same metal. In some embodiments, the PCRAM region includes a chalcogenide semiconductor material. In some embodiments, the filaments of different memory cells in the array of memory cells have different shapes. In some embodiments, the filaments of different memory cells in the array of memory cells have different relative positions relative to the bottom electrode in the corresponding memory cell. In some embodiments, the dielectric layer of the array of memory cells is part of a continuous dielectric layer that extends through the array of memory cells. In some embodiments, the dielectric layers of the array of memory cells are spaced apart from each other by additional dielectric regions.

[0058] In some embodiments, a semiconductor structure includes: a plurality of bottom electrodes; a dielectric layer located above and in contact with the plurality of bottom electrodes; a plurality of filaments located in the dielectric layer, wherein each of the plurality of filaments overlaps with a corresponding one of the plurality of bottom electrodes; a plurality of chalcogenide semiconductor regions, wherein each of the plurality of chalcogenide semiconductor regions overlaps with and contacts a corresponding one of the plurality of filaments; and a plurality of top electrodes covering the plurality of chalcogenide semiconductor regions. In some embodiments, the plurality of filaments penetrates the dielectric layer. In some embodiments, the plurality of filaments have different relative positions relative to corresponding underlying bottom electrodes of the plurality of bottom electrodes. In some embodiments, the lateral dimensions of the plurality of filaments are less than about 10 nm. In some embodiments, the thickness of the dielectric layer is in a range between about 3 nm and about 10 nm.

[0059] The components of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. It should also be appreciated by those skilled in the art that these equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: forming a bottom electrode; forming a dielectric layer; forming a phase change random access memory region in contact with the dielectric layer; forming a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode; forming a filament in the dielectric layer, wherein the filament contacts the dielectric layer, the filament also contacts the PCRAM region and serves as a heater for the PCRAM region; and The state of the phase change random access memory region is written to or read from by conducting a first current or a second current through the phase change random access memory region, wherein a first direction of the first current is the same as a second direction of the second current to maintain the filament for heating the phase change random access memory region during both the read operation and the write operation.

2. The method according to claim 1, wherein: Forming the PCRAM region includes depositing a chalcogenide semiconductor material.

3. The method according to claim 1, wherein: The lateral dimension of the filaments is formed to be less than 10 nm.

4. The method according to claim 1, further comprising: A bit line connected to the top electrode is formed over the top electrode, wherein the first current and the second current are formed by applying different voltages to the bit line.

5. The method according to claim 1, wherein: Forming the dielectric layer includes depositing a selected from HfO x 、ZrO x 、TaO x 、TiO x , VO x 、NiO x 、NbO x 、LaO x and their combinations to form the group of materials.

6. The method of claim 1, comprising forming a memory array, comprising: forming a first array of PCRAM regions, wherein the PCRAM region is an array element in the first array of PCRAM regions; as well as An array of filaments is formed in contact with the array of phase change random access memory regions, wherein the filaments are additional array elements in the array of filaments.

7. The method according to claim 1, wherein: The phase change random access memory region is located above the dielectric layer, and wherein, when the filaments are formed, the dielectric layer extends laterally beyond the phase change random access memory region.

8. The method according to claim 1, wherein: The phase change random access memory region is located above the dielectric layer, and the method further comprises: depositing a blanket PCRAM layer; and The blanket PCRAM layer and the dielectric layer are patterned using a same etching mask, wherein the blanket PCRAM layer is patterned into a plurality of PCRAM regions including the PCRAM region.

9. A semiconductor structure comprising: An array of memory cells, wherein each memory cell in the array of memory cells comprises: bottom electrode; Dielectric layer; a filament in the dielectric layer; a phase change random access memory region in contact with the dielectric layer and the filament, and the filament serves as a heater for the phase change random access memory region; and a top electrode, wherein the dielectric layer and the PCRAM region are located between the bottom electrode and the top electrode; Wherein, the state of the phase change random access memory region is written or read by conducting a first current or a second current through the phase change random access memory region, wherein a first direction of the first current is the same as a second direction of the second current, so as to maintain the filament for heating the phase change random access memory region during both the read operation and the write operation.

10. The semiconductor structure according to claim 9, wherein: The dielectric layer and the filaments include the same metal.

11. The semiconductor structure according to claim 9, wherein: The PCRAM region includes a chalcogenide semiconductor material.

12. The semiconductor structure according to claim 9, wherein: The filaments of different memory cells in the array of memory cells have different shapes.

13. The semiconductor structure according to claim 9, wherein: The filaments of different memory cells in the array of memory cells have different relative positions with respect to the bottom electrode in the corresponding memory cell.

14. The semiconductor structure according to claim 9, wherein: The dielectric layer of the array of memory cells is the portion of a continuous dielectric layer that extends throughout the array of memory cells.

15. The semiconductor structure according to claim 9, wherein: The dielectric layers of the array of memory cells are spaced apart from each other by additional dielectric regions.

16. A semiconductor structure comprising: a plurality of bottom electrodes; a dielectric layer over and in contact with the plurality of bottom electrodes; a plurality of filaments in the dielectric layer, wherein each of the plurality of filaments overlaps a corresponding one of the plurality of bottom electrodes; a plurality of chalcogenide semiconductor regions, wherein each of the plurality of chalcogenide semiconductor regions overlaps and contacts a corresponding one of the plurality of filaments, and each of the plurality of filaments serves as a heater for the corresponding one of the plurality of chalcogenide semiconductor regions; and a plurality of top electrodes covering the plurality of chalcogenide semiconductor regions; wherein the state of the chalcogenide semiconductor region is written or read by conducting a first current or a second current through the chalcogenide semiconductor region, wherein a first direction of the first current is the same as a second direction of the second current so as to maintain the filament for heating the chalcogenide semiconductor region during both the read operation and the write operation.

17. The semiconductor structure according to claim 16, wherein: The plurality of filaments penetrate the dielectric layer.

18. The semiconductor structure according to claim 16, wherein: The plurality of filaments have different relative positions with respect to corresponding underlying bottom electrodes of the plurality of bottom electrodes.

19. The semiconductor structure according to claim 16, wherein: The lateral dimensions of the plurality of filaments are less than 10 nm.

20. The semiconductor structure of claim 16, wherein: The thickness of the dielectric layer is in the range between 3 nm and 10 nm.

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