Secure device for generating a key based on a physically unclonable function and method of operation thereof

Abstract

A security device generates a key based on a physical unclonable function (PUF). The security device includes a physical unclonable function (PUF) block, an integrity detector, and a post-processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals, each of the plurality of corresponding first inverted random signals having a logic level opposite to a logic level of each of the plurality of first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post-processor generates a first row of keys including a validity signal satisfying the data integrity.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0017145, filed on February 12, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The inventive concept(s) described herein relate to a secure device generating a key by using a physically unclonable function (PUF) and an operating method thereof. BACKGROUND

[0004] As wired and wireless communication technologies and smart device related technologies are rapidly developing, the demand for establishing a secure system capable of safely using these technologies is also increasing. One basic method for providing security for communication systems and smart devices is to install a secure device implemented by hardware logic (as compared to logic implemented using a memory) in the communication systems and smart devices. When a secure chip having hardware logic is first driven, and then software such as an operating system (OS) is driven, authentication or checking of malicious code is performed. A security technology based on a physically unclonable function (PUF) has recently been developed. The PUF can be a physical object having a unique characteristic for creating a unique identity for use by a secure device. When a PUF is used, copying of important keys such as authentication keys stored in a secure device can be prevented. SUMMARY

[0005] The inventive concept(s) described herein relate to a secure device and an operating method thereof, which generates a valid and correct key by using a validity map when a key is generated by using a physically unclonable function (PUF).

[0006] According to an aspect of the disclosure, a security device includes a physically unclonable function (PUF) block, an integrity detector, and a post-processor. The PUF block includes a plurality of PUF cells that generate a plurality of first random signals, and outputs the plurality of first random signals and a plurality of corresponding first inverted random signals each of which has a logic level opposite to that of each of the plurality of first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post-processor generates a first row key including a validity signal satisfying the data integrity. The validity signal satisfying the data integrity is selected from the plurality of first random signals. The post-processor also generates helper data including parity data corresponding to the first row key based on a predetermined error correction algorithm, and generates a PUF-applied key by using the helper data.

[0007] According to an aspect of the disclosure, a security device includes a physically unclonable function (PUF) block, a validity detector, an enrollment module, and a memory block. The PUF block includes a plurality of PUF cells that generate a plurality of first random signals, and outputs the plurality of first random signals. The validity detector generates a plurality of validity signals respectively corresponding to the plurality of PUF cells based on the plurality of first random signals in a first mode. The enrollment module generates a validity map for the PUF block based on the plurality of validity signals, and selects a first valid random signal from the plurality of first random signals based on the validity map. The enrollment module also generates a first row key including the first valid random signal, and generates helper data including parity data corresponding to the first row key based on a predetermined error correction algorithm. The memory block stores the validity map and the helper data to be used when generating a PUF-applied key.

[0008] According to an aspect of the disclosure, a security device includes a physically unclonable function (PUF) block, an enrollment block, an encoding module, and a memory block. The PUF block includes a plurality of PUF cells that generate a plurality of first random signals, and outputs the plurality of first random signals. The enrollment block generates a first row key by using the plurality of first random signals in a first mode. The encoding module receives the first row key, obtains parity data by performing error correction on the first row key, and generates helper data including the parity data. The memory block stores the helper data.

[0009] According to an aspect of the disclosure, a security device includes a physically unclonable function (PUF) block, a memory block, a key generator, and a decoding module. The PUF block includes a plurality of PUF cells that generate a plurality of first random signals and outputs the plurality of first random signals. The memory block stores a validity map including information about validity of the plurality of first random signals and helper data including parity data. The key generator receives the plurality of first random signals, receives the validity map from the memory block, and selects a first valid random signal from the plurality of first random signals based on the validity map. The key generator also generates a first row key by using the first valid random signal. The decoding module receives the first row key, receives the helper data from the memory block, and generates a key by performing error correction on the first row key based on the helper data. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments of the inventive concept(s) described herein will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a security device according to an exemplary embodiment of the disclosure;

[0012] Figure 2 is a block diagram illustrating a security device according to an exemplary embodiment of the disclosure;

[0013] Figure 3 is a block diagram illustrating a security device according to an exemplary embodiment of the disclosure;

[0014] Figure 4A is a diagram illustrating an operation of a registration block according to an exemplary embodiment of the disclosure;

[0015] Figure 4B is a diagram illustrating an operation of a registration block according to an exemplary embodiment of the disclosure;

[0016] Figure 5A is a diagram illustrating an operation of an encoding block according to an exemplary embodiment of the disclosure;

[0017] Figure 5B is a diagram illustrating an operation of an encoding block according to an exemplary embodiment of the disclosure;

[0018] Figure 6 is a block diagram illustrating a security device according to an exemplary embodiment of the disclosure;

[0019] Figure 7 is a diagram illustrating an operation of a key generator according to an exemplary embodiment of the disclosure;

[0020] Figure 8 is a diagram illustrating an operation of a decoding block according to an exemplary embodiment of the present disclosure;

[0021] Figure 9 is a block diagram of a post-processor according to an exemplary embodiment of the present disclosure;

[0022] Figure 10A and Figure 10B is a circuit diagram of an attack detector according to an exemplary embodiment of the present disclosure;

[0023] Figure 11 is a block diagram of a security device according to an exemplary embodiment of the present disclosure;

[0024] Figure 12 is a diagram illustrating an operation of an integrity detector according to an exemplary embodiment of the present disclosure;

[0025] Figure 13 is a block diagram of an integrated circuit according to an exemplary embodiment of the present disclosure;

[0026] Figure 14A and Figure 14B is a block diagram of an environment in which a security device according to an exemplary embodiment of the present disclosure is used; and

[0027] Figure 15 is a block diagram of a computing device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a block diagram of a security device 10 according to an exemplary embodiment of the present disclosure.

[0030] Referring to Figure 1 , the security device 10 can generate a unique key KEY for security, and can perform a security operation such as encryption / decryption by using the generated key KEY. The security device 10 can include a PUF circuit 100 (Physical Unclonable Function (PUF) circuit) and a post-processor 200.

[0031] The security device 10 can operate in one of a registration mode and a use mode. In the registration mode, the security device 10 can select a valid random signal from among the plurality of random signals RS generated by the PUF circuit 100, and can register a key generated by using the selected valid random signal. In the use mode, the security device 10 can generate a key by using a random signal generated by the PUF circuit 100 in response to a request of a host, and can output the generated key to the host. In an embodiment, the registration mode can be performed once at a manufacturing time point when the security device 10 is manufactured. The use mode can be performed at a plurality of time points at which a key is to be generated by using the security device 10.

[0032] The PUF circuit 100 can include a PUF block 110. The PUF block 110 can generate a plurality of random signals RS. To this end, the PUF block 110 can include a plurality of PUF source circuits. Each of the plurality of PUF source circuits can generate a signal having a unique value according to a PUF, and can be referred to as a PUF cell in the present specification. The PUF can refer to a function that provides a unique value corresponding to hardware based on an inherent characteristic of the hardware. For example, although a plurality of hardware components such as semiconductor chips are manufactured by the same process, the plurality of hardware components can not be physically and completely identical to each other, and slight variations can occur in the plurality of hardware components. Based on these variations, a unique value of the plurality of hardware components can be extracted. The extracted value can be used for an application requiring security. Examples of the application requiring security in which the extracted value can be used include, for example, secure communication, secure data processing, user identification, and firmware update.

[0033] In some embodiments, each of the plurality of PUF source circuits included in the PUF block 110 can have an arbitrary structure in which a bit signal having a unique value is generated. As a non-limiting example, each of the plurality of PUF source circuits can have an SRAM type PUF structure based on a value stored in a static random access memory (SRAM) cell, a ring oscillator structure based on a frequency variation, a PUF structure based on a leakage current, or an arbiter PUF structure in which a path of an arbitrary determination signal. In addition, each of the plurality of PUF source circuits can generate a bit signal having a unique value based on a difference between threshold levels of logic gates.

[0034] In an example, the PUF block 110 can include at least one of a transistor threshold voltage-based PUF cell, an arbiter-based PUF cell, a ring oscillator-based PUF cell, a memory-based PUF cell, and a reconfigurable PUF cell according to a laser beam or thermal change. The arbiter-based PUF cell can be, for example, a feed-forward PUF cell, an XOR PUF cell obtained by arranging arbiter PUF cells in parallel, or a lightweight PUF cell. The memory-based PUF cell can be, for example, an SRAM PUF cell, a latch PUF cell, a flash PUF cell, or a storage resistor PUF cell.

[0035] The PUF block 110 can generate a plurality of random signals RS based on signals generated by a plurality of PUF source circuits. Accordingly, the plurality of random signals RS can be different from random signals generated by a PUF block included in another security device having the same structure. In some embodiments, the PUF block 110 can generate n-bit random signals RS (n is an integer greater than 1). For example, the PUF block 110 can include n PUF source circuits, and each PUF source circuit can generate a 1-bit random signal RS.

[0036] The post-processor 200 can include a key generator 230. The key generator 230 can generate a key KEY by receiving the plurality of random signals RS and performing post-processing on the plurality of random signals RS. Since the integrity of the key is guaranteed, the key KEY, which is an encryption key uniquely generated by the security device 10 for security, can be used as an encryption and decryption key or a key such as an authentication code.

[0037] The key generator 230 can determine whether the plurality of random signals RS are valid, and can generate a row key by using only valid random signals. In addition, the post-processor 200 can generate the key KEY by performing an error correction operation on the row key. That is, the key KEY can be generated based on the row key. For example, the row key can be generated in an enrollment mode, and the key KEY can be generated based on the row key in a use mode. The key KEY can be a key for use, for example, a key provided to the outside for encryption or decryption. The key KEY is based on a PUF, and the key KEY is generated by using helper data.

[0038] According to an embodiment of the present disclosure, the post-processor 200 can generate a validity map including information about each valid random signal, and can store the generated validity map in the registration mode of registering the key KEY. Also, in an embodiment, the post-processor 200 can store the parity bits generated by the error correction operation as the side data in the registration mode. The key generator 230 can generate the key KEY by using the stored validity map and / or the side data in the generation mode of generating the key KEY in response to a request of a user, so that the key generation process can be efficiently performed.

[0039] In Figure 1 , the PUF circuit 100 and the post-processor 200 are shown as being separated from each other, which is merely an example. The PUF circuit 100 and the post-processor 200 can be implemented by one construction. In an example, the PUF circuit 100 can be implemented by hardware including the PUF block 110. The post-processor 200 can be implemented by software and / or hardware.

[0040] Figure 2 is a block diagram showing a security device 10 according to an exemplary embodiment of the present disclosure.

[0041] Before proceeding, it should be made clear that the figures herein including Figure 2 utilize notations such as "blocks" or "modules" to show and refer to circuitry. As is conventional in the art(s) of the inventive concepts described herein, examples can be described and shown in terms of blocks and modules that perform described function(s). These blocks and modules can be referred to herein as PUF blocks, registration blocks, registration modules, encoding blocks, encoding modules, decoding blocks, decoding modules, interface blocks, interface modules, memory modules, and the like, and are physically implemented by analog and / or digital circuitry such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, and the like, and can optionally be driven by firmware and / or software. For example, circuitry can be presented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. Circuitry making up a block or module can be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and related circuitry), or by a combination of dedicated hardware to perform some functions of the block, and a processor to perform other functions of the block. Each block or module of an example can be physically separated into two or more interacting and discrete blocks, without departing from the scope of the present disclosure. Likewise, blocks and / or modules of an example can be physically combined into more complex blocks, without departing from the scope of the present disclosure.

[0042] Referring to Figure 2The security device 10 can include a PUF circuit 100, a post-processor 200, and a memory module 300. The PUF circuit 100 can include a PUF block 110 and a validity detector 120. Since the PUF block 110 is described in detail in Figure 1

[0043] The validity detector 120 can generate a plurality of validity signals respectively corresponding to a plurality of random signals (and thus to a plurality of PUF cells) by detecting validity of the plurality of random signals. The plurality of random signals can be used to generate a password that can be used as an authentication key. In this case, the password must have a time-invariant property that a value of the password does not change depending on circumstances. The validity detector 120 can determine the time-invariant property of the digital random signal, and can generate the plurality of validity signals based on the determined time-invariant property. The validity detector 120 can generate the plurality of validity signals based on validity of the plurality of validity signals as determined based on and with respect to the time-invariant property.

[0044] In an example, the validity detector 120 can generate a validity signal based on whether random signals output from PUF cells included in the PUF block 110 at different time points are identical. In another example, the validity detector 120 can generate a validity signal based on whether random signals output from PUF cells included in the PUF block 110 under different external conditions (e.g., temperature, pressure, humidity, etc.) are identical.

[0045] The post-processor 200 can include an enrollment block 210, an encoding block 220, a key generator 230, a decoding block 240, and an interface block 250. The enrollment block 210, the encoding block 220, the key generator 230, the decoding block 240, and the interface block 250 can be connected to communicate with each other. In an example, the enrollment block 210, the encoding block 220, the key generator 230, the decoding block 240, and the interface block 250 can be connected through a bus. In another example, at least part of the enrollment block 210, the encoding block 220, the key generator 230, the decoding block 240, and the interface block 250 can be formed of software executed by one processor. The operation of the enrollment block 210, the encoding block 220, the key generator 230, the decoding block 240, and the interface block 250 to transmit data to each other can mean that the operations of the respective components are continuously performed by one processor.

[0046] The enrollment block 210 can receive the plurality of random signals and the plurality of validity signals, and can select a valid random signal based on the plurality of random signals and the plurality of validity signals in an enrollment mode. The enrollment block 210 can generate a row key by using the valid random signal, and can output the generated row key to the encoding block 220.

[0047] ​According to embodiments of the present disclosure, the enrollment block 210 can generate an effectiveness map indicating whether the plurality of random signals are effective based on the plurality of effectiveness signals. The enrollment block 210 can store the generated effectiveness map in the memory module 300 through the interface block 250.

[0048] The encoding block 220 can receive the row key from the enrollment block 210 and can perform an error correction operation on the row key by using an error correction code in the enrollment mode. The error correction code can include at least one of a low-density parity-check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon code, a convolutional code, a recursive systematic code, and an encoding modulation such as a trellis coded modulation (TCM), a block coded modulation (BCM), and a majority vote.

[0049] According to embodiments of the present disclosure, the encoding block 220 can generate the helper data by using a parity code generated by performing the error correction operation on the row key. The encoding block 220 can store the generated helper data in the memory module 300 through the interface block 250.

[0050] The key generator 230 can receive the effectiveness map from the memory module 300 through the interface block 250 and can receive the plurality of random signals from the PUF block 110. The key generator 230 can select an effective random signal from the plurality of random signals based on the effectiveness map and can generate the row key by using the selected effective random signal.

[0051] The decoding block 240 can receive the helper data from the memory module 300 through the interface block 250 and can perform an error correction operation on the row key received from the key generator 230 by using the helper data. The decoding block 240 can output the key generated by performing the error correction operation to the outside (e.g., a host). The key output by the decoding block 240 can be a key for use and is a key based on the PUF from the PUF block 110 and thus is a key to which the PUF is applied

[0052] The memory module 300 can include a system memory and a non-volatile memory. In the following embodiments, the system memory of the memory module 300 can be a system memory 310 and the non-volatile memory of the memory module 300 can be a non-volatile memory 320. The system memory can be used as a working memory required for operating the security device 10. In embodiments, the interface module 250 can store the effectiveness map and the helper data generated in the enrollment mode in the system memory. When the enrollment mode is completed, the interface module 250 can store the effectiveness map and the helper data stored in the system memory in the non-volatile memory.

[0053] In an example, the system memory can include a high-speed volatile memory, such as a latch, a register, a static random access memory (SRAM), or a dynamic random access memory (DRAM). The non-volatile memory in the memory module 300 is a memory that does not lose data even if a power supply such as an electronic fuse is blocked, and can include a NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), a phase change random access memory (PRAM), a thyristor random access memory (TRAM), a magnetic random access memory (MRAM), or a one-time programmable (OTP) memory.

[0054] Figure 3 is a block diagram illustrating a security device 10 according to an example embodiment of the present disclosure. In detail, Figure 3 The operation of the security device 10 in the enrollment mode is illustrated. The description given previously with reference to Figure 1 is omitted.

[0055] Referring to Figure 3 , the security device 10 can include a PUF block 110, a validity detector 120, an enrollment block 210, an encoding block 220, an interface block 250, a system memory 310, and a non-volatile memory 320. In the enrollment mode, a key generator 230 and a decoding block 240 can be disabled.

[0056] Upon entering the enrollment mode, the PUF block 110 can output a plurality of random signals RS generated by a plurality of PUF units included in the PUF block 110 to the validity detector 120 and the enrollment block 210. The validity detector 120 can generate a plurality of validity signals VS based on whether the plurality of random signals RS change according to time or conditions. In an embodiment, the plurality of validity signals VS can be matched one-to-one with the plurality of random signals RS, respectively.

[0057] The enrollment block 210 can generate a validity map VM representing whether the plurality of random signals RS are valid based on the plurality of validity signals VS, and can store the generated validity map VM in the system memory 310 through the interface block 250. In addition, the enrollment block 210 can select a valid random signal from the plurality of random signals RS based on the generated validity map VM, and can generate a row key RKEY by using the selected valid random signal. The enrollment block 210 can output the generated row key RKEY to the encoding block 220.

[0058] The encoding block 220 can generate the parity check code by performing an error correction operation on the received row key RKEY based on the previously determined error correction code. The encoding block 220 can store the generated parity check code as the helper data HD in the system memory 310 through the interface block 250.

[0059] The interface block 250 can store the validity map VM and the helper data HD in the system memory 310 in the registration mode. When the registration mode is completed, the interface block 250 can store the validity map VM and the helper data HD stored in the system memory 310 in the non-volatile memory 320.

[0060] Figure 4A is a diagram illustrating an operation of the registration block 210 according to an exemplary embodiment of the present disclosure. In detail, Figure 4A A method of operating the registration block 210 in the registration mode is illustrated. The description given previously with reference to Figure 3 is omitted.

[0061] With reference to Figure 3 and Figure 4A , the registration block 210 can receive a plurality of random signals RS including the first to sixth random signals RS1 to RS6, and can receive a plurality of validity signals VS corresponding to the first to sixth random signals RS1 to RS6. In an example, each of the plurality of random signals RS can have a first bit (e.g., '1') or a second bit (e.g., '0'). Each of the plurality of validity signals VS can have a first value (e.g., 'O' or a bit '1' corresponding to 'O') representing that each of the plurality of validity signals VS is valid or a second value (e.g., 'X' or a bit '0' corresponding to 'X') representing that each of the plurality of validity signals VS is invalid. 'O' and 'X' are merely examples of the first value and the second value, respectively, and in other examples, the first value and the second value can be represented by other characters or values.

[0062] The registration block 210 can generate a validity bit VB based on each of the plurality of validity signals VS, and can generate a validity map VM by using the validity bit VB. In an embodiment, when any one of the plurality of validity signals VS has a first value representing that the validity signal VS is valid, the registration block 210 can assign a first bit (e.g., '1') as the validity bit VB, and when any one of the plurality of validity signals VS has a second value representing that the validity signal VS is invalid, the registration block 210 can assign a second bit (e.g., '0') as the validity bit VB. In another embodiment, the registration block 210 can assign the plurality of validity signals VS as the validity bit VB. The registration block 210 can generate the validity map VM by using the validity bit VB, and can output the generated validity map VM to the interface block 250. In Figure 4A In an example, the validity map VM can include '101101'. In an embodiment, the validity map VM can include a validity bit for all random signals that can be generated by the PUF block 110.

[0063] The registration block 210 can select a valid random signal from the plurality of random signals RS by using the generated validity bit VB. In Figure 4A In an example, because the validity bit VB corresponding to each of the first random signal RS1, the third random signal RS3, the fourth random signal RS4, and the sixth random signal RS6 is the first bit '1', the registration block 210 can select the first random signal RS1, the third random signal RS3, the fourth random signal RS4, and the sixth random signal RS6 from the plurality of random signals RS, and can output the row key RKEY by using the first random signal RS1, the third random signal RS3, the fourth random signal RS4, and the sixth random signal RS6.

[0064] Figure 4B is a diagram illustrating an operation of the registration block 210 according to an exemplary embodiment of the present disclosure. In detail, Figure 4B a method of operating the registration block 210 in the registration mode is illustrated. The description given previously with reference to Figure 3 and Figure 4A is omitted.

[0065] With reference to Figure 3 and Figure 4B , unlike Figure 4A , the registration block 210 can receive a plurality of first validity signals VS1 and a plurality of second validity signals VS2. In an example, the plurality of first validity signals VS1 can be obtained as a result of detecting validity under a first condition or at a first time point, and the plurality of second validity signals VS2 can be obtained as a result of detecting validity under a second condition or at a second time point.

[0066] The registration block 210 can generate the validity bit VB based on the plurality of first validity signals VS1 and the plurality of second validity signals VS2, and can generate the validity map VM by using the validity bit VB. In an embodiment, when each of the first validity signal VS1 and the second validity signal VS2 corresponding to any one of the random signals has a first value representing that each of the first validity signal VS1 and the second validity signal VS2 is valid, the registration block 210 can assign a first bit (e.g., '1') as the validity bit VB, and when any one of the first validity signal VS1 or the second validity signal VS2 has a second value representing that the first validity signal VS1 or the second validity signal VS2 is invalid, the registration block 210 can assign a second bit (e.g., '0') as the validity bit VB. In an embodiment, the registration block 210 can generate a result value obtained by performing an AND operation on the first validity signal VS1 and the second validity signal VS2 as the validity bit VB. The registration block 210 can generate the validity map VM by using the validity bit VB, and can output the generated validity map VM to the interface block 250. In Figure 4B an example, the validity map VM can include '100100'. As illustrated, for any one of the random signals, when both the first validity signal VS1 and the second validity signal VS2 have a first value representing that the first validity signal VS1 and the second validity signal VS2 are valid, a first bit (e.g., '1') is assigned as the validity bit VB. Otherwise, a second bit (e.g., '0') is assigned as the validity bit VB.

[0067] The registration block 210 can select valid random signals from the plurality of random signals RS by using the generated validity bit VB. In Figure 4B an example, because the validity bit VB corresponding to each of the first random signal RS1 and the fourth random signal RS4 is a first bit '1', the registration block 210 can select the first random signal RS1 and the fourth random signal RS4 from the plurality of random signals RS. The registration module 210 can output the row key RKEY by using the first random signal RS1 and the fourth random signal RS4.

[0068] Figure 5A is a diagram illustrating an operation of the encoding block 220 according to an exemplary embodiment of the present disclosure. In detail, Figure 5A a method of operating the encoding block 220 in the registration mode is illustrated. The description given previously with reference to Figure 3 is omitted.

[0069] Reference is made to Figure 3 and Figure 5AThe encoding block 220 can generate the parity data PDAT by receiving the row key RKEY and applying the row key RKEY to the error correction code ECC. The generation of the parity data PDAT is indicated by a plus (+) sign in Figure 5A As described above, the error correction code ECC can include at least one of an LDPC code, a BCH code, a turbo code, a Reed-Solomon code, a convolutional code, RSC, TCM, BCM, and majority voting.

[0070] The encoding block 220 can generate the parity data PDAT as the helper data HD, and can store the helper data HD in the memory module 300. In an embodiment, when the security device 10 generates a plurality of keys, the helper data HD can include the parity data PDAT for each of the plurality of keys. The helper data HD including the parity data PDAT is indicated by an arrow symbol pointing downward and to the right in Figure 5A

[0071] Figure 5B is a diagram illustrating an operation of the encoding block 220 according to an exemplary embodiment of the present disclosure. In detail, Figure 5B a method of operating the encoding block 220 in the enrollment mode is illustrated. The descriptions given previously with reference to Figure 3 and Figure 5A are omitted.

[0072] With reference to Figure 3 and Figure 5B , the encoding block 220 can generate the first parity data PDAT1 by receiving the row key RKEY and applying the row key RKEY to the first error correction code ECC1. The generation of the first parity data PDAT1 is indicated by a first arrow symbol pointing downward in Figure 5B The encoding block 220 can generate the second parity data PDAT2 by applying the row key RKEY to the first error correction code ECC1 and then applying the row key RKEY to the second error correction code ECC2. The generation of the second parity data PDAT2 is indicated by a second arrow symbol pointing downward in Figure 5B In an embodiment, the first error correction code ECC1 can be majority voting, and the second error correction code ECC2 can be a BCH code.

[0073] The encoding block 220 can generate the first parity data PDAT1 and the second parity data PDAT2 as the helper data HD, and can store the helper data HD in the memory module 300. The helper data HD including the first parity data PDAT1 and the second parity data PDAT2 is indicated by both a plus (+) sign and an arrow symbol pointing to the right in Figure 5B ​​

[0074] Figure 6 is a block diagram illustrating a security device 10 according to an example embodiment of the disclosure. In detail, Figure 6 Operation of the security device 10 according to the usage mode is illustrated. The descriptions given previously with reference to Figure 2 are omitted.

[0075] Referring to Figure 6 , the security device 10 can include a PUF block 110, a key generator 230, a decoding block 240, an interface block 250, a system memory 310, and a non-volatile memory 320. In the usage mode, the validity detector 120, the enrollment block 210, and the encoding block 220 can be disabled.

[0076] Upon entering the usage mode, the PUF block 110 can output a plurality of random signals RS generated by a plurality of PUF units included in the PUF block 110 to the key generator 230.

[0077] The key generator 230 can read a validity map VM from the non-volatile memory 320 through the interface block 250, and can select a valid random signal from the plurality of random signals RS based on the read validity map VM. In an embodiment, the key generator 230 can select the valid random signal by using the validity map VM loaded onto the system memory 310 from the non-volatile memory 320. The key generator 230 can generate a row key RKEY by using the selected valid random signal. In an embodiment, the key generator 230 can generate the row key RKEY by concatenating the selected valid random signal.

[0078] According to an embodiment of the disclosure, the key generator 230 can select the valid random signal by using the validity map VM without an additional validity signal. Since the validity detector 120 is disabled in the usage mode, power efficiency can be improved, and resources required to generate a key can be reduced.

[0079] The decoding block 240 can read the helper data HD from the memory module 300 through the interface block 250, and can perform error correction on the row key RKEY by using the read helper data HD. In an embodiment, the decoding block 240 can perform error correction by using the helper data HD loaded onto the system memory 310 from the non-volatile memory 320. The decoding block 240 can obtain one or more parity data segments from the helper data HD, and can perform error correction on the row key RKEY by using the obtained parity data segments. The decoding block 240 can output the key KEY generated as a result of performing error correction to the outside (e.g., a host). In an embodiment, the decoding block 240 can output the key KEY through the interface block 250. The interface block 250 can be connected with or can control an interface connected with the outside. In an embodiment, the decoding block 240 can output the row key RKEY on which error correction is performed as the key KEY.

[0080] According to an embodiment of the present disclosure, the decoding block 240 can effectively perform error correction with increased accuracy by performing error correction on the row key RKEY by using the previously generated helper data HD.

[0081] In the usage mode, the interface block 250 can load the validity map VM and the helper data HD from the non-volatile memory 320 included in the memory module 300 onto the system memory 310. The key generator 230 and the decoding block 240 can perform the above-described operations by using the validity map VM and the helper data HD loaded on the system memory 310.

[0082] Figure 7 is a diagram illustrating an operation of the key generator 230 according to an exemplary embodiment of the present disclosure. In detail, Figure 7 A method of operating the key generator 230 in the usage mode is illustrated. The description given previously with reference to Figure 6 is omitted.

[0083] Referring to Figure 6 and Figure 7 , the key generator 230 can receive the validity map VM and a plurality of random signals RS including the first to sixth random signals RS1 to RS6. The validity map VM can include a plurality of validity bits respectively corresponding to the plurality of random signals RS.

[0084] The key generator 230 can determine a random signal corresponding to a first bit (e.g., '1') representing validity as a validity bit VB as a valid random signal, and can determine a random signal corresponding to a second bit (e.g., '0') representing invalidity as a validity bit VB as an invalid random signal. In Figure 7In the example of FIG. 2, the key generator 230 can determine that each of the first random signal RS1, the third random signal RS3, the fourth random signal RS4, and the sixth random signal RS6 having the validity bit VB '1' is valid, and can generate the row key RKEY by concatenating the first random signal RS1, the third random signal RS3, the fourth random signal RS4, and the sixth random signal RS6.

[0085] Figure 8 is a diagram illustrating an operation of the decoding block 240 according to an example embodiment of the present disclosure. In detail, Figure 8 a method of operating the decoding block 240 in a use mode is illustrated. The description given previously with reference to Figure 6 is omitted.

[0086] With reference to Figure 6 and Figure 8 , the decoding block 240 can receive the row key RKEY and the helper data HD, and can generate the parity data PDAT from the helper data HD. The decoding block 240 can perform error correction on the row key RKEY by using the parity data PDAT.

[0087] In an embodiment, the decoding block 240 can obtain a plurality of parity data segments PDAT from the helper data HD. The decoding block 240 can perform error correction on the row key RKEY according to a first error correction algorithm by using first parity data of the plurality of parity data segments PDAT, and then can perform error correction on the row key RKEY according to a second error correction algorithm by using second parity data of the plurality of parity data segments PDAT.

[0088] In an embodiment, the decoding block 240 can obtain a result value as first parity data from the helper data HD according to a majority vote, and can perform error correction on the row key RKEY by using the majority vote. After performing error correction by using the majority vote, the decoding block 240 can obtain a result value as second parity data from the helper data HD according to a BCH code, and can finally generate the key KEY by performing error correction on the row key RKEY using the BCH code.

[0089] Figure 9 is a block diagram illustrating the post-processor 200a according to an example embodiment of the present disclosure. The description given previously with reference to Figure 2 is omitted.

[0090] With reference to Figure 9The post-processor 200a can include a registration block 210a, an encoding block 220a, a key generator 230a, a decoding block 240a, and an interface block 250a. The interface block 250a can include an attack detector 252a. Since the registration block 210a, the encoding block 220a, the key generator 230a, and the decoding block 240a can perform the same or similar operations as those described with reference to the registration block 210, the encoding block 220, the key generator 230, and the decoding block 240 of FIG. 2, a description thereof will be omitted. Figure 2 The detailed description of the operations of the registration block 210, the encoding block 220, the key generator 230, and the decoding block 240 is the same or similar to the operations of the registration block 210a, the encoding block 220a, the key generator 230a, and the decoding block 240a, and thus a description thereof will be omitted.

[0091] The attack detector 252a can include a register that receives a key generated in a use mode or a registration mode and stores the key before outputting the key to the outside. The attack detector 252a can determine whether the register storing the key is attacked from the outside. In an embodiment, the attack detector 252a can generate an inverted key by inverting one or more bits of the key, and can determine whether the register is attacked from the outside by comparing the inverted key with the key obtained from the register.

[0092] According to an embodiment of the disclosure, the attack detector 252a can guarantee the integrity of the key by determining whether the register storing the key is attacked using the inverted key.

[0093] In Figure 9 , the attack detector 252a is illustrated as being included in the interface block 250a, which is only one example. Embodiments of the disclosure can also be applied to a case in which the attack detector 252a is included in a configuration from which the key is output.

[0094] Figure 10A and Figure 10B are circuit diagrams illustrating an attack detector according to an exemplary embodiment of the disclosure. A description given previously with reference to Figure 9 is omitted.

[0095] Referring to Figure 10A , the attack detector 252a can include a first register Rg1, a second register Rg2, an inverter INV, a comparator Cmp, and a key switch KS. The first register Rg1 can receive and store a key KEY. The inverter INV can receive the key KEY, and can generate an inverted key KEYb by inverting a bit(s) of the key KEY. In an example, the inverter INV can generate the inverted key KEYb by converting '1' to '0' and '0' to '1' in data included in the key KEY.

[0096] The NOT gate INV can store the negated key KEYb in the second register Rg2, and the comparator Cmp can generate the attack detection signal AD by receiving the key KEY from the first register Rg1, receiving the negated key KEYb from the second register Rg2, and comparing the key KEY with the negated key KEYb. In an example, the comparator Cmp can compare the key KEY with the negated key KEYb bit by bit, can output '0' as the attack detection signal AD when all bits of the key KEY are different from all bits of the negated key KEYb, and can output '1' as the attack detection signal AD when any bit of the key KEY is identical to the corresponding bit of the negated key KEYb.

[0097] The key switch KS can receive the key KEY and can output the key KEY based on the attack detection signal AD. In an example, based on the attack detection signal AD, the key switch KS can output the key when all bits of the key KEY are different from all bits of the negated key KEYb, and can not output the key KEY when any bit of the key KEY is identical to the corresponding bit of the negated key KEYb. In an example, the key switch KS can inform the key generator 230a Figure 9 ) that an attack is detected, and the key generator 230a can generate a new key KEY in response to the notification.

[0098] The first register Rg1 can be exposed to the outside as a physical device. Accordingly, an attacker can confirm the key KEY stored in the first register Rg1 by de-packaging. According to an embodiment of the disclosure, an attack by an attacker can be detected based on whether the key KEY included in the first register Rg1 is transformed. As a result, when the key KEY is transformed, the integrity of the key KEY can be guaranteed by generating a new key KEY without using the transformed key KEY.

[0099] Referring to Figure 10B , the attack detector 253a can include the first register Rg1, the NOT gate INV, the comparator Cmp, and the key switch KS. When the negated key KEYb is received from the NOT gate INV, the comparator Cmp can generate the attack detection signal AD by receiving the key KEY stored in the first register Rg1 and comparing the key KEY with the negated key KEYb. Because the operations of Figure 10B are the same as or similar to those of Figure 10A , the previously given description is omitted.

[0100] Figure 11 is a block diagram illustrating a security device 10b according to an exemplary embodiment of the disclosure. The previously given description with reference to Figure 2 is omitted.

[0101] Referring to Figure 11 , the security device 10b can include a PUF circuit 100b, an integrity detector 400b, and a post-processor 200b. The PUF circuit 100b can include a PUF block 110b and a complemented signal generator 130b. Since the PUF block 110b can be the same as or similar to the PUF block 110 described in detail above, a description thereof is omitted. Figure 2 The PUF block 110b can generate a random signal RS and can output the generated random signal RS to the integrity detector 400b. The complemented signal generator 130b can generate a complemented random signal RSb by complementing the random signal RS generated by the PUF block 110b. The complemented signal generator 130b can output the generated complemented random signal RSb to the integrity detector 400b. To this end, in an embodiment, the complemented signal generator 130b can include at least one NOT gate.

[0102] The PUF block 110b can generate a random signal RS and can output the generated random signal RS to the integrity detector 400b. The complemented signal generator 130b can generate a complemented random signal RSb by complementing the random signal RS generated by the PUF block 110b. The complemented signal generator 130b can output the generated complemented random signal RSb to the integrity detector 400b. To this end, in an embodiment, the complemented signal generator 130b can include at least one NOT gate.

[0103] The integrity detector 400b can detect the integrity of the random signal RS by receiving the random signal RS and the complemented random signal RSb and comparing the random signal RS with the complemented random signal RSb. The integrity detector 400b can output the integrity detection result of the random signal RS as an integrity bit IB to the post-processor 200b. In an embodiment, the integrity detector 400b can include at least one comparator that compares the random signal RS with the complemented random signal RSb, and the comparator can compare the bits of the random signal RS with the bits of the complemented random signal RSb.

[0104] When it is determined that all the bits of the random signal RS are different from all the bits of the complemented random signal RSb, the integrity detector 400b can output a first value (e.g., '1') indicating integrity as the integrity bit IB. When it is determined that any bit of the random signal RS is the same as the corresponding bit of the complemented random signal RSb, the integrity detector 400b can output a second value (e.g., '0') indicating incompleteness as the integrity bit IB.

[0105] In an embodiment, after the PUF circuit 100b generates the random signal RS, the random signal RS can be transformed by an external attacker. In this case, at least one bit of the complemented random signal RSb generated by the PUF circuit 100b can not be different from at least one corresponding bit of the random signal RS. That is, based on the integrity bit, the post-processor 200b can determine whether the random signal RS has integrity.

[0106] The post-processor 200b may include a registration block 210b and a key generator 230b. In registration mode, when a first value indicating completeness is received as an integrity bit, the registration block 210b may generate a row key based on the random signal RS, and may generate information about the valid random signal as a validity mapping, as described above. When a second value indicating incompleteness is received as an integrity bit IB, the registration block 210b may discard the random signal RS and may request the PUF circuit 100b to provide a new random signal. In another embodiment, the registration block 210b may discard the random signal corresponding to the second value as the integrity bit IB, and may perform the registration process by using only the random signal corresponding to the first value as the integrity bit IB. That is, the incomplete bits of the random signal may be discarded, and the complete bits of the random signal may be registered as the random signal. Then, the key KEY can be generated using only the random signal registered with the complete bits.

[0107] When receiving a first value representing completeness as the integrity bit IB in the usage mode, the key generator 230b can generate a row key based on the random signal RS, and the post-processor 200b can output the key KEY generated using the row key to the outside. When receiving a second value representing incompleteness as the integrity bit IB, the key generator 230b can discard the random signal RS and can request the PUF circuit 100b to provide a new random signal. Furthermore, in another embodiment, the key generator 230b can discard the random signal corresponding to the second value as the integrity bit IB, and can generate the key KEY by using only the random signal corresponding to the first value as the integrity bit IB. According to at least... Figure 11 In one embodiment, the key generator 230b can determine whether to generate a second row of keys from a plurality of first random signals including the random signal RS based on the determination of data integrity by the integrity detector 400b of the random signal RS. That is, the first row of keys KEY may not be generated or may be discarded, and the second row of keys KEY may be generated by using new random signals or by using only the random signals corresponding to the first value as the integrity bit IB.

[0108] According to embodiments of this disclosure, the integrity detector 400b can determine whether the random signal RS has been attacked by using the random signal RS and the inverted random signal RSb, and can help ensure the integrity of the random signal RS.

[0109] Figure 12 This is a diagram illustrating the operation of the integrity detector 400b according to an exemplary embodiment of the present disclosure. Previous references are omitted. Figure 11 The given description.

[0110] ReferenceFigure 11 and Figure 12 The integrity detector 400b can generate the integrity bit IB by receiving the random signal RS and the inverted random signal RSb and comparing the random signal RS with the inverted random signal RSb. In an example of Figure 12 , the integrity detector 400b can receive '110110' as the random signal RS, and can receive '001100' as the inverted random signal RSb.

[0111] When some bits of the random signal RS are different from some bits of the inverted random signal RSb, the integrity detector 400b can assign a first value (e.g., '1') as the integrity bit IB, and when some bits of the random signal RS are not different from some bits of the inverted random signal RSb, the integrity detector 400b can assign a second value (e.g., '0') as the integrity bit IB. For example, for any bit of the random signal RS that is different from a corresponding bit of the inverted random signal RSb, the integrity detector 400b can assign a first value (e.g., '1') as the integrity bit IB. For any bit of the random signal RS that is not different from a corresponding bit of the inverted random signal RSb, the integrity detector 400b can assign a second value (e.g., '0') as the integrity bit IB.

[0112] In an example of Figure 12 , the integrity detector 400b can compare the bits '110110' of the random signal RS with the bits '001100' of the inverted random signal RSb bit by bit. Because the first bit, the second bit, the third bit, and the fifth bit of the random signal RS are different from the first bit, the second bit, the third bit, and the fifth bit of the inverted random signal RSb, the integrity detector 400b can assign '1' as the integrity bit IB, and because the fourth bit and the sixth bit of the random signal RS are not different from the fourth bit and the sixth bit of the inverted random signal RSb, the integrity detector 400b can assign '0' as the integrity bit IB. As a result, the integrity detector 400b can output '111010' as the integrity bit IB.

[0113] Because the post-processor 200b receives '111010' as the integrity bit IB, which means that there is at least one bit of the random signal RS that is not complete, the random signal RS can be discarded, and a new random signal can be requested from the PUF circuit 100b. Also, in another embodiment, because the post-processor 200b receives '111010' as the integrity bit IB, the fourth bit and the sixth bit of the random signal RS that are not complete are discarded, and the enrollment process or the generation of a key can be performed by using only the first bit, the second bit, the third bit, and the fifth bit of the random signal RS.

[0114] Figure 13 is a block diagram illustrating a security device 10c according to an exemplary embodiment of the present disclosure. Descriptions given previously with reference to Figures 1 to 12 are omitted.

[0115] Referring to Figure 13 , the security device 10c can include functional blocks performing a trial authentication method PUF and another function. For example, the security device 10c can further include a processor 400c and the PUF circuit 100c, the post-processor 200c, and the memory module 300c as a system on chip (SoC). The processor 400c can include any processing unit that executes a set of instructions, and can include a field-programmable gate array (FPGA) and a hardware accelerator. In an embodiment, the processor 400c can output various control signals that control the PUF circuit 100c, the post-processor 200c, and the memory module 300c to the PUF circuit 100c, the post-processor 200c, and the memory module 300c.

[0116] The processor 400c can communicate with another device through a communication channel CH, and can transmit a key KEY. The communication channel CH can include a cable channel and / or a radio channel.

[0117] Figure 14A and Figure 14B is a block diagram illustrating an environment in which a security device according to an exemplary embodiment of the present disclosure is used. In detail, Figure 14A an environment in which the security device is used in a registration process is illustrated, Figure 14B an environment in which the security device is used in a use process is illustrated.

[0118] Referring to Figure 14A , a host (for example, a computing system 20d operated by a manufacturer of the first through m-th integrated circuits IC1-ICm, m being an integer greater than 1) can communicate with each of the first through m-th integrated circuits IC1-ICm. For example, the computing system 20d can generate a validity map and helper data by controlling the first integrated circuit IC1, and can store the generated validity map and helper data in the first integrated circuit IC1. In an embodiment, each of the first through m-th integrated circuits IC1-ICm can operate in a registration mode by the method described in detail with reference to Figures 1 to 13

[0119] Referring to Figure 14B ​, the computing system 20e can communicate with the devices 10_1 to 10_m through the network 30, the computing system 20e can represent a specific system that is desired to communicate with the devices 10_1 to 10_m through the network 30 by using encryption. The network 30 can include any network, and as non-limiting examples can include a cellular network, a local area network (LAN), or a wireless local area network (WLAN). In addition, the computing system 20e can communicate with the devices 10_1 to 10_m through wired communication and / or wireless communication.

[0120] The devices 10_1 to 10_m can provide a key to the computing system 20e through the network 30 based on the validity map and the auxiliary data generated in the registration process, and the computing system 20e can communicate with the devices 10_1 to 10_m by using the key to perform encryption. In an embodiment, each of the first to m integrated circuits IC1 to ICm included in the devices 10_1 to 10_m can communicate with the computing system 20e through the network 30 by referring to Figures 1 to 13 The method described in detail operates in a use mode.

[0121] Figure 15 is a block diagram illustrating a computing device 3000 according to an exemplary embodiment of the present disclosure. In detail, Figure 15 The computing device 3000 is illustrated as including a reference Figures 1 to 13 The computing device 3000 of the security device described in detail.

[0122] Referring to Figure 15 , the computing device 3000 can include a processor 3100, a working memory 3200, a PUF device 3300, a cryptographic processor 3400, a non-volatile memory (NVM) interface 3500, an NVM 3600, and a user interface 3700.

[0123] The processor 3100 can control the overall operation of the computing device 3000. The processor 3100, which is a central processing unit (CPU), can perform various operations. For example, the processor 3100 can include one or more processor cores.

[0124] The working memory 3200 can exchange data with the processor 3100. The working memory 3200 can arbitrarily store data for the operation of the computing device 3000. For example, the working memory 3200 can include a high-speed memory such as a dynamic random access memory (DRAM) or a static RAM (SRAM).

[0125] The PUF device 3300 can be a reference Figures 1 to 13Detailed description of PUF circuit. The PUF device 3300 can generate a key required for security. The PUF device 3300 can be implemented by hardware, software, or firmware. The cryptographic processor 3400 can perform encryption and decryption operations by using the key output from the PUF device 3300.

[0126] The NVM interface 3500 can exchange data with the NVM 3600 according to the control of the processor 3100, the PUF device 3300, or the cryptographic processor 3400. The NVM 3600 can store data that needs to be maintained regardless of power. In an embodiment, in the NVM 3600, the validity map and the auxiliary data described above with reference to FIG. 2 can be stored, and the PUF device 3300 can not include the NVM therein. Figures 1 to 13

[0127] The user interface 3700 can relay communication between a user and the computing device 3000 according to the control of the processor 3100. The user interface 3700 can include an input interface such as a keypad, a key pad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, or a vibration sensor. Also, the user interface 3700 can include an output interface such as a liquid crystal display (LCD), a light emitting diode (LED), an organic LED (OLED), an active matrix OLED (AMOLED), a speaker, or a motor.

[0128] The bus 3800 can provide a communication path between the components of the computing device 3000. The components of the computing device 3000 can transmit data to and receive data from each other according to a bus format. In an embodiment, the bus format can include a universal serial bus (USB), a small computer system interface (SCSI), a peripheral component interconnect express (PCIe), an advanced technology attachment (ATA), a parallel ATA (PATA), a serial ATA (SATA), a serial attached SCSI (SAS), or an integrated drive electronics (IDE).

[0129] While the (one or more) inventive concepts described herein have been particularly shown and described with reference to embodiments of the (one or more) inventive concepts, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.​

Claims

1. A security device comprising: a physically unclonable function block including a plurality of physically unclonable function units, the plurality of physically unclonable function units generating a plurality of first random signals, and the physically unclonable function block outputting the plurality of first random signals and a plurality of corresponding first inverted random signals, each of the plurality of corresponding first inverted random signals having a logic level opposite to that of each of the plurality of first random signals; an integrity detector determining data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals; and a post-processor generating a first line key including a validity signal satisfying the data integrity and selected from the plurality of first random signals, the post-processor generating auxiliary data including parity data corresponding to the first line key based on a predetermined error correction algorithm, and the post-processor generating a key for use by using the auxiliary data, the key for use being based on a physically unclonable function from one of the plurality of physically unclonable function units. 2.The security device of claim 1, further comprising: a validity detector generating a plurality of validity signals respectively corresponding to the plurality of physically unclonable function units based on validity of the plurality of first random signals in a first mode; and a memory block storing a validity map, wherein the post-processor further includes a registration module generating the validity map for the physically unclonable function block based on the plurality of validity signals, selecting a first valid random signal from the plurality of first random signals based on the validity map, and generating the first line key including the first valid random signal. 3.The security device of claim 2, the post-processor further comprising: a key generator receiving a plurality of second random signals in a second mode, receiving the plurality of second random signals from the physically unclonable function block, receiving the validity map from the memory block, selecting a second valid random signal from the plurality of second random signals based on the validity map, and generating a second line key including the second valid random signal in the second mode. 4.The security device of claim 3, wherein the physically unclonable function block further generates the plurality of second random signals and a plurality of corresponding second inverted random signals in the second mode, each of the plurality of corresponding second inverted random signals having a logic level opposite to that of each of the plurality of second random signals, and the integrity detector determines data integrity of the plurality of second random signals by using the plurality of second random signals and the plurality of corresponding second inverted random signals in the second mode. wherein 5.The security device of claim 3, the post-processor further comprising: an encoding module generating the auxiliary data in the first mode, ​ The memory block further stores the auxiliary data.

6. The security apparatus of claim 5, wherein, The post-processor further includes: a decoding module that, in the second mode, receives the second row key from the key generator, receives the auxiliary data from the memory block, and generates the key for use by performing error correction on the second row key based on the auxiliary data.

7. The security apparatus of claim 6, wherein, The first mode is performed once at a point in time at which the security device is manufactured, and The second mode is performed when the key for use is to be generated by using the security device.

8. The security device of claim 5, the memory block further including: a non-volatile memory that stores at least one of the auxiliary data and the validity map generated in the first mode.

9. The security device of claim 8, the post-processor further including: a decoding module that, in the second mode, receives the second row key from the key generator, receives the auxiliary data from the memory block, and generates the key for use by performing error correction on the second row key based on the auxiliary data, wherein the key generator reads the validity map from the non-volatile memory when entering the second mode, and wherein the decoding module reads the auxiliary data from the non-volatile memory when entering the second mode.

10. The security device of claim 1, the post-processor further including: an interface block that communicates with an outside of the security device and outputs the key for use to the outside of the security device.

11. The security device of claim 10, the interface block further including: an attack detector that includes a first register that stores the first row key and determines whether the first register is attacked.

12. The security apparatus of claim 11, wherein, The attack detector further includes: a NOT gate that generates an inverted key by inverting the key for use; a second register that stores the inverted key; a comparator that determines whether the first register and the second register are attacked by comparing the key for use and the inverted key; and a key switch that outputs the key for use to the outside based on a result of the determination by the comparator whether the first register and the second register are attacked.

13. A security device, comprising: a physically unclonable function block that includes a plurality of physically unclonable function units that generate a plurality of first random signals and that outputs the plurality of first random signals and a plurality of corresponding first inverted random signals, each of the plurality of corresponding first inverted random signals having a logic level opposite to a logic level of each of the plurality of first random signals; an integrity detector that determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals; and a key generator that generates a second row key by using the plurality of first random signals and the plurality of corresponding first inverted random signals, and that outputs the second row key to the post-processor. an effectiveness detector that generates a plurality of effectiveness signals respectively corresponding to the plurality of physically unclonable function units based on the plurality of first random signals in the first mode; a registration module that generates an effectiveness map for the physically unclonable function block based on the plurality of effectiveness signals, selects a first effective random signal from the plurality of first random signals satisfying the data integrity based on the effectiveness map, and generates a first row key including the first effective random signal; and a memory block that stores the effectiveness map and helper data to be used when generating a key based on a physically unclonable function from one of the plurality of physically unclonable function units.

14. The security device of claim 13, further comprising: an encoding module that generates the helper data including parity data corresponding to the first row key based on a predetermined error correction algorithm in the first mode.

15. The security device of claim 13, further comprising: a key generator that receives a plurality of second random signals from the physically unclonable function block in a second mode, receives the effectiveness map from the memory block, selects a second effective random signal from the plurality of second random signals based on the effectiveness map, and generates a second row key including the second effective random signal in the second mode.

16. The security device of claim 15, further comprising: a decoding module that receives the second row key from the key generator, receives the helper data from the memory block, and generates a key for use by performing error correction on the second row key based on the helper data in the second mode, the key for use being based on a physically unclonable function from one of the plurality of physically unclonable function units.

17. The security device of claim 16, further comprising: an interface block that communicates with an outside of the security device and outputs the key for use to the outside of the security device.

18. The security apparatus of claim 17, wherein, the interface block further comprising: a first register that stores the key for use; a NOT gate that generates an inverted key by inverting the key for use; a second register that stores the inverted key; a comparator that determines whether the first register and the second register are attacked by comparing the key for use and the inverted key; and a key switch that outputs the key for use to the outside based on a result of the determination by the comparator whether the first register and the second register are attacked.

19. A security device comprising: a physically unclonable function block including a plurality of physically unclonable function units, the plurality of physically unclonable function units generating a plurality of first random signals, and the physically unclonable function block outputting the plurality of first random signals and a plurality of corresponding first inverted random signals, each of the plurality of corresponding first inverted random signals having a logic level opposite to a logic level of each of the plurality of first random signals; an integrity checker that determines data integrity of the first plurality of random signals by using the first plurality of random signals and the corresponding first plurality of inverted random signals; a registration block that generates, in a first mode, a first line key by using the first plurality of random signals that satisfy the data integrity; an encoding module that receives the first line key, obtains parity data by performing error correction on the first line key, and generates helper data including the parity data; and a memory block that stores the helper data.

20. The security apparatus of claim 19, further comprising: a key generator that receives, in a second mode, a second plurality of random signals from the physically unclonable function block and generates a second line key by using the second plurality of random signals; and a decoding module that receives the second line key from the key generator, receives the helper data from the memory block, and generates a key for use by performing error correction on the second line key based on the helper data.

21. The security apparatus of claim 20, wherein the key generator comprises: a second registration block that generates, in the second mode, the second line key by using the second plurality of random signals that satisfy the data integrity.

22. The security apparatus of claim 21, wherein the decoding module comprises: a second encoding module that receives the second line key from the second registration block, obtains the parity data by performing error correction on the second line key, and generates the helper data including the parity data.

23. The security apparatus of claim 22, wherein the decoding module comprises: a second memory block that stores the helper data.

24. The security apparatus of claim 23, wherein the decoding module comprises: a second decoding module that receives the second line key from the second memory block, receives the helper data from the second memory block, and generates the key for use by performing error correction on the second line key based on the helper data.

25. The security apparatus of claim 24, wherein the decoding module comprises: a second error correction decoder that receives the second line key from the second memory block, receives the helper data from the second memory block, and generates the key for use by performing error correction on the second line key based on the helper data.

26. The security apparatus of claim 25, wherein the decoding module comprises: a second error correction encoder that receives the second line key from the second memory block, receives the helper data from the second memory block, and generates the key for use by performing error correction on the second line key based on the helper data.

27. The security apparatus of claim 26, wherein the decoding module comprises: a second error correction decoder that receives the second line key from the second memory

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