Semiconductor chip with stacked conductor lines and air gap

Abstract

Various semiconductor chip metallization layers and methods of making the same are disclosed. In one aspect, a semiconductor chip (15) is provided that includes a substrate (50), a plurality of metallization layers (75, 80) on the substrate, a first conductor line (175b) in one of the metallization layers and a second conductor line (175c) in the one of the metallization layers, the second conductor line being spaced apart from the first conductor line, each of the first and second conductor lines having a first line portion (190) and a second line portion (200) stacked on the first line portion, and a dielectric layer (187) having a portion positioned between the first and second conductor lines, the portion having an air gap (185a).

Description

Background Technology

[0001] Currently available integrated circuits typically contain millions of individual transistors and other electronic components. Much of the interconnection of these numerous components in such circuits is provided via one or more metallization layers that serve as global interconnect layers. In a conventional subtractive process, each metallization layer is typically deposited as a single, continuous layer on the substrate of the integrated circuit, which is then photolithographically patterned and etched to remove metal from areas where metal lines are not needed. In another process, a dual damascene process is used.

[0002] In multilayer metallized circuits, individual metal layers are typically vertically separated by one or more interlayer dielectric (ILD) layers. Electrical contacts between adjacent metal layers are provided by openings or vias in the ILD. Vias are typically formed by masking selected portions of the ILD and subsequently etching them. The vias are then filled with a conductive material or sometimes a combination of conductive materials. The term "via" used in semiconductor manufacturing refers not only to the opening itself but also to the opening filled with a conductive material.

[0003] As the spacing between conductor lines in metallization decreases, the capacitance between such adjacent lines increases, accompanied by performance loss due to capacitive delay. A common technique to combat the increased capacitance caused by reduced line spacing is to use air gaps between adjacent lines. A single layer of conductor lines consists of gaps filled with a dielectric material. Since the dielectric material is deposited via chemical vapor deposition, the opposing walls of adjacent lines are coated with the dielectric. Finally, the dielectric material bridges, leaving air gaps in the dielectric between the lines. Attached Figure Description

[0004] The foregoing and other advantages of the invention will become apparent from the following detailed description and with reference to the accompanying drawings, in which:

[0005] Figure 1 This is an exploded view of an exemplary semiconductor chip device arrangement;

[0006] Figure 2 yes Figure 1 A side-view orthogonal diagram of a semiconductor chip;

[0007] Figure 3 yes Figure 1 A sectional view taken at section 3-3;

[0008] Figure 4 These are diagrams illustrating some exemplary conductor lines decomposed from a metallization layer;

[0009] Figure 5 yes Figure 3 A sectional view taken at section 5-5;

[0010] Figure 6 This is a cross-sectional view depicting the initial processing of several exemplary metallization layers;

[0011] Figure 7 It is similar to Figure 6 However, a cross-sectional view is depicted of the additional processing used to create the additional metallization layer;

[0012] Figure 8 It is similar to Figure 7 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0013] Figure 9 It is similar to Figure 8 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0014] Figure 10 It is similar to Figure 9 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0015] Figure 11 It is similar to Figure 10 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0016] Figure 12 It is similar to Figure 11 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0017] Figure 13 It is similar to Figure 12 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0018] Figure 14 It is similar to Figure 13 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0019] Figure 15 It is similar to Figure 14 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0020] Figure 16 It is similar to Figure 15 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0021] Figure 17 It is similar to Figure 16 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0022] Figure 18 It is similar to Figure 17However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0023] Figure 19 It is similar to Figure 18 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0024] Figure 20 It is similar to Figure 19 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0025] Figure 21 It is similar to Figure 20 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0026] Figure 22 It is similar to Figure 21 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0027] Figure 23 It is similar to Figure 22 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0028] Figure 24 It is similar to Figure 23 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0029] Figure 25 It is similar to Figure 24 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0030] Figure 26 It is similar to Figure 25 However, a cross-sectional view is depicted of the additional treatment used to construct the additional metallization layer;

[0031] Figure 27 It is similar to Figure 3 However, a cross-sectional view of an alternative exemplary semiconductor chip metallization layer arrangement is depicted;

[0032] Figure 28 It is similar to Figure 3 However, a cross-sectional view of an alternative exemplary semiconductor chip metallization layer arrangement is depicted;

[0033] Figure 29 It is a diagram of an electronic device having a semiconductor chip device from which it is decomposed. Detailed Implementation

[0034] The disclosed arrangement provides semiconductor chip metallization by utilizing air gaps in the interlayer dielectric layer between adjacent conductor lines to offset the increase in capacitance associated with reduced line spacing. However, to further improve electrical performance with even tighter line spacing, the disclosed technique utilizes conductor lines composed of stacked lines. Each adjacent line separated by the air gap consists of a first line and a second line stacked on the first line. This process can be directly integrated into well-known dual damascene metallization processes to provide via interconnects. In this way, conductor lines with a higher aspect ratio than allowed by conventional techniques can be constructed without resorting to extremely difficult deep trench etching techniques with very high aspect ratios. Existing types of barrier layers and materials can be used. Significant resistance reduction and a trade-off with capacitance can be achieved. With lower resistance, the number of lines required for routing other things can be reduced, and this can improve routing congestion time and consumed chip area. The disclosed arrangement provides better electromigration and power drop performance and can reduce the sensitivity of the output driver to conductor line resistance.

[0035] According to one aspect of the present invention, a semiconductor chip is provided, the semiconductor chip comprising: a substrate; a plurality of metallization layers on the substrate; a first conductor line in one of the metallization layers and a second conductor line in the same metallization layer, the second conductor line being spaced apart from the first conductor line, each of the first conductor line and the second conductor line having a first line portion and a second line portion stacked on the first line portion; and a dielectric layer having a portion located between the first conductor line and the second line, the portion having an air gap.

[0036] The semiconductor chip, wherein the third conductor line of one of the metallization layers includes a first line portion and a second line portion stacked on the first line portion, the one of the metallization layers has a conductive via, the first line portion and the conductive via having a shared continuous block conductor portion and a shared continuous barrier layer.

[0037] The semiconductor chip, wherein the second line portion has a first thickness, and the air gap has a second thickness greater than the first thickness.

[0038] The semiconductor chip includes multiple conductor lines in another of the metallization layers, each of the multiple conductor lines having a first thickness, and the first conductor line of the metallization layer having a second thickness greater than the first thickness.

[0039] The semiconductor chip includes a plurality of conductive vias in another of the metallization layers, each of the plurality of conductive vias having a first thickness, the third conductor line of the metallization layer including a first line portion and a second line portion stacked on the first line portion, the metallization layer having a conductive via connected to the first line portion, the conductive via having a second thickness greater than the first thickness.

[0040] The semiconductor chip, wherein one of the metallization layers includes a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, and each of the first conductor line and the second conductor line is partially located in the first dielectric layer and partially located in the second dielectric layer.

[0041] The semiconductor chip includes multiple conductor lines in another of the metallization layers, the multiple conductor lines having a first lateral spacing, and the first conductor line and the second conductor line of the metallization layer having a second lateral spacing smaller than the first lateral spacing.

[0042] The semiconductor chip includes a circuit board, and the semiconductor chip is mounted on the circuit board.

[0043] According to another aspect of the present invention, a semiconductor chip is provided, the semiconductor chip comprising: a substrate; a first metallization layer on the substrate and a second metallization layer on the first metallization layer; a plurality of conductor lines in the first metallization layer, each of the conductor lines having an aspect ratio; a first conductor line in the second metallization layer and a second conductor line in the second metallization layer, the second conductor line being spaced apart from the first conductor line, each of the first conductor line and the second conductor line having a first line portion and a second line portion stacked on the first line portion, the aspect ratio of each of the first conductor line and the second conductor line being greater than the aspect ratio of the plurality of conductor lines; and a dielectric layer having a portion positioned between the first conductor line and the second line, the portion having an air gap.

[0044] The semiconductor chip, wherein the third conductor line of the second metallization layer includes a first line portion and a second line portion stacked on the first line portion, the second metallization layer has a conductive via, and the first line portion and the conductive via have a shared continuous block conductor portion and a shared continuous barrier layer.

[0045] The semiconductor chip includes a plurality of conductive vias in a first metallization layer, each of the plurality of conductive vias having a first thickness. The third conductor line of the second metallization layer includes a first line portion and a second line portion stacked on the first line portion. The second metallization layer has a conductive via connected to the first line portion, and the conductive via has a second thickness greater than the first thickness.

[0046] The semiconductor chip, wherein the second metallization layer includes a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, each of the first conductor line and the second conductor line being partially located in the first dielectric layer and partially located in the second dielectric layer.

[0047] The semiconductor chip, wherein the plurality of conductor lines have a first lateral spacing, and the first conductor line and the second conductor line of the second metallization layer have a second lateral spacing smaller than the first lateral spacing.

[0048] The semiconductor chip includes a circuit board, and the semiconductor chip is mounted on the circuit board.

[0049] According to another aspect of the present invention, a method for manufacturing a semiconductor chip is provided. The method includes: manufacturing a plurality of metallization layers on a substrate; manufacturing a first conductor line in one of the metallization layers and manufacturing a second conductor line in the same metallization layer, the second conductor line being spaced apart from the first conductor line, each of the first and second conductor lines having a first line portion and a second line portion stacked on the first line portion; and manufacturing a dielectric layer having a portion located between the first and second conductor lines, the portion having an air gap.

[0050] The method includes fabricating a third conductor line in one of the metallization layers, the third conductor line having a first line portion and a second line portion stacked on the first line portion, and fabricating a conductive via in one of the metallization layers, the first line portion and the conductive via having a shared continuous block conductor portion and a shared continuous barrier layer.

[0051] The method wherein the second line portion has a first thickness, and the air gap has a second thickness greater than the first thickness.

[0052] The method includes fabricating a plurality of conductor lines in another of the metallization layers, each of the plurality of conductor lines having a first thickness, and the first conductor line of the metallization layer having a second thickness greater than the first thickness.

[0053] The method includes fabricating a plurality of conductive vias in another of the metallization layers, each of the plurality of conductive vias having a first thickness, and fabricating a third conductor line in one of the metallization layers, the third conductor line having a first line portion and a second line portion stacked on the first line portion, the one of the metallization layers having a conductive via connected to the first line portion, the conductive via having a second thickness greater than the first thickness.

[0054] The method, wherein one of the metallization layers includes a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, each of the first conductor line and the second conductor line being partially located in the first dielectric layer and partially located in the second dielectric layer.

[0055] The method includes fabricating a plurality of conductor lines in another of the metallization layers, the plurality of conductor lines having a first lateral spacing, and the first conductor line and the second conductor line of the first metallization layer having a second lateral spacing smaller than the first lateral spacing.

[0056] The method includes mounting the semiconductor chip on a circuit board.

[0057] In the accompanying drawings described below, reference numerals are often repeated, and the same elements appear in more than one drawing. Turning now to the drawings and referring in particular to… Figure 1 The diagram shows a partially exploded view of an exemplary embodiment of a semiconductor chip device 10, which includes a semiconductor chip 15 that can be mounted on a circuit board 20. The semiconductor chip 15 is shown exploded from the circuit board. The semiconductor chip 15 includes a plurality of interconnect structures 25, which are designed to be metallurgically bonded to the circuit board 20 and form a plurality of connectors or other types of solder connections when the semiconductor chip 15 is mounted to the circuit board 20. The two edges 30 and 40 of the semiconductor chip 15 are at... Figure 1 It is visible in the middle.

[0058] The exemplary arrangements disclosed herein do not depend on the specific functionality of the semiconductor chip 15 or the circuit board 20. Therefore, the semiconductor chip 15 can be any of a variety of different types of circuit devices used in electronic devices, such as interpolators, microprocessors, graphics processors, combined microprocessors / graphics processors, application-specific integrated circuits, memory devices, etc., and can be single-core or multi-core. The semiconductor chip 15 can be made of bulk semiconductors (such as silicon or germanium) or semiconductor-on-insulator materials (such as silicon-on-insulator or even insulating materials). Therefore, the term "semiconductor chip" can even imply insulating materials. Stacked dies can be used if desired.

[0059] Circuit board 20 can be another semiconductor chip of the type described above, a semiconductor chip packaging substrate, a circuit card, or virtually any other type of printed circuit board. Monolithic or laminated structures can be used. A build-up design is an example of a laminate. In this respect, circuit board 20 can consist of a central core on which one or more stacked layers are formed and below it, one or more additional stacked layers are formed. The core itself can consist of one or more stacks. A so-called "coreless" design can also be used. The layers of circuit board 20 can be composed of insulating materials, such as various well-known epoxy resins or other resins with dispersed metal interconnects. Multilayer configurations other than stacking can be used. Optionally, circuit board 20 can be made of well-known ceramics or other materials suitable for packaging substrates or other printed circuit boards.

[0060] Additional details about semiconductor chip 15 can now be found by referring to Figure 2 To understand, Figure 2 This is an enlarged orthographic view of the side 30 of the semiconductor chip 15. (Example) Figure 2 As shown, the semiconductor chip 15 includes a substrate or bulk semiconductor layer 50, a device layer 55 positioned on the bulk layer 50, and a plurality of metallization layers 60, 65, 70, 75, 80, 85, and 90. As described in more detail below, each of the metallization layers includes a layer of metallization traces distributed within an interlayer dielectric (ILD) and vertically interconnected with adjacent metallization layers via conductive vias. In this illustrative arrangement, seven metallization layers 60, 65, 70, 75, 80, 85, and 90 are depicted. However, those skilled in the art will understand that the number of metallization layers may not be seven.

[0061] You can still refer to it now. Figure 3 and Figure 4 To understand the additional details of semiconductor chip 15, Figure 3 yes Figure 1 The sectional view taken at section 3-3. Figure 4 This is a partial schematic diagram of some conductors in the metallization layer 70. Note the position and size of the cutting plane in section 3-3, therefore... Figure 3 Only a very small portion of the semiconductor chip 15 is depicted, and in fact... Figure 3 The focus will be solely on metallization layers 60, 65, 70, 75, 80, 85, and 90, and especially on a subset of metallization layers 70, 75, 80, and 85. Note that... Figure 3Only a portion of metallization layer 85 is depicted. Focus first on metallization layer 70. Metallization layer 70 comprises multiple conductor lines 95a, 95b, 95c, 95d, and 95e (and other invisible conductor lines) scattered throughout ILD 97. Although only a few conductor lines 95a, 95b, 95c, 95d, and 95e are depicted, it should be understood that the number of metallization layers 70 and any of the other metallization layers 60, 75, 80, 85, and 90 can be much greater than the number shown. Each of conductor lines 95a, 95b, 95c, 95d, and 95e consists of a barrier layer 100 and a bulk conductor 105, and is manufactured with a typical linewidth x1 and a typical spacing x2. The barrier layer 100 is designed to prevent the movement of metal ions and other impurities. Some or all of conductor lines 95a, 95b, 95c, 95d, and 95e pass through multiple vias to the next metallization layer below (in this case, a via). Figure 2 The layers 65 shown are interconnected, with two vias in... Figure 3 and Figure 4 The two holes are visible and are labeled 110a and 110b respectively, and another through hole 110c is in... Figure 4 The vias 110a, 110b, and 110c are visible. There can be many more vias than shown in the figure. Visors 110a, 110b, and 110c are preferably constructed using a dual damascene process, such that, in practice, the barrier layer 100 and block conductor of via 110a are adjacent to the barrier layer 100 and block conductor 105 of line 95a, and for via 110b relative to line 95d and via 110c relative to line 95e, etc. Visors 110a, 110b, and 110c can be cylindrical, square, or other covering areas. Visors 110a and 110b are in... Figure 4 The diagram is shown as an assumption that the lines 95a and 95d are decomposed from their lower sides 112a and 112d, respectively, to illustrate the decomposition. Figure 4 This cylindrical arrangement is shown in the image. Note the lower sides 112a and 112d. Figure 3The middle layer is invisible and is therefore shown as a dashed line. The barrier layer 100 can be composed of Ti, TiN, Ta, TaN, Ta, Ru, Co, and laminates thereof. The bulk conductor 105 can be composed of copper, silver, aluminum, platinum, gold, palladium, Co, Ru, combinations thereof, laminates thereof, or other conductor materials, as needed. Well-known material deposition processes such as electroplating, chemical vapor deposition, and physical vapor deposition can be used. The ILD 97 can be composed of various interlayer dielectric materials, such as tetraethyl orthosilicate, various other glasses, or so-called "low-K" materials with a K value less than about 3.0 or "ultra-low-K" materials with a K value less than about 2.7, both of which are beneficial for reducing parasitic effects between displaced conductor layers. Exemplary materials include, for example, porous carbon-doped oxides (p-SiCOH), nanoporous organosilicones, and black diamond films. Other conductor lines and ILDs disclosed herein can be made of the same materials.

[0062] Conductor lines 95a, 95b, 95c, and 95d are manufactured to have a desired thickness z1, vias 110a and 110b are manufactured to have a desired height z2, and ILD 97 is manufactured to have a desired thickness z3 before both vias 110a and 110b and lines 95a, 95b, 95c, and 95d. These thicknesses z1, z2, and z3 can be thicknesses determined by standard design rules, which can be achieved by... Figure 2 Depicted in and at least partially in Figure 3 Many metallization layers 60, 65, 70, 75, 80, 85, and 90 are depicted for use. However, as will be noted in more detail below, other metallization layers, especially metallization layer 80 which will be described below, will deviate from the standard thickness and heights z1, z2, and z3 to achieve different RC behaviors for fine-pitch lines.

[0063] Refer again Figure 3Metallization layer 75 consists of an etch stop layer 130 fabricated on metallization layer 70. The purpose of etch stop layer 130 will be described in more detail below. Metallization layer 75 includes multiple conductor lines 135a, 135b, 135c, 135d, and 135e (and other invisible conductor lines) and multiple conductive vias 140a and 140b scattered in ILD 137. Although only a few conductor lines 135a, 135b, 135c, 135d, and 135e are depicted, it should be understood that metallization layer 75 and any of the other metallization layers 60, 75, 80, 85, and 90 may include more such lines. In this illustrative arrangement, conductor lines 135a, 135b, 135c, 135d, and 135e, as well as conductor lines 95a, 95b, 95c, 95d, and 95e, are aligned in the same general direction, i.e., extending into and out of the page. However, in other arrangements, the conductor lines can change their orientation from one metallization layer to the next. For example, conductor lines 95a, 95b, 95c, 95d, and 95e in metallization layer 70 can enter and exit the page, while conductor lines 135a, 135b, 135c, 135d, and 135e can be aligned parallel to the page and therefore orthogonal to conductor lines 95a, 95b, 95c, 95d, and 95e, and vice versa. This alternation of arrangement orientations can exist for some or all of the metallization layers. Conductor lines 135a, 135b, 135c, 135d, and 135e, as well as conductive vias 140a and 140b, can be arranged as described above for conductor lines 95a, 95b, 95c, 95d, and 95e and conductive vias 110a, 110b, and 110c in metallization layer 70. Therefore, lines 135a, 135b, and 135d may each include a barrier layer 145 and a bulk conductor portion 150, and lines 135c and 135e, as well as conductive vias 140a and 140b, may similarly include a continuous barrier layer 145 and a bulk conductor portion 150. ILD 137 may be similar to ILD 97 described above. The same dimensions z1, z2, and z3 may be used for lines 135a, 135b, 135c, 135d, and 135e, vias 140a and 140b, and ILD 137. Note that the unmarked dashed lines define conductor line 135c and via 140a, and line 135a and via 140b. These dashed lines simply represent the invisible lower surfaces of conductor lines 135c and 135e, very similar to lower surfaces 112a and 112b.

[0064] Still referencing Figure 3The vias 140a and 140b are electrically interconnected with one or more of the conductor lines 95c and 95e of the metallization layer 70. A barrier metal layer 160 is formed at the locations where the vias 140a and 140b connect to the underlying lines 95c and 95e. The barrier layer 160 may be composed of Ti, TiN, Ta, TaN, Ta, Ru, Co, and laminates thereof. The purpose of the barrier layer 160 is to protect the bulk conductor material 105 of the conductor lines 95c and 95e during manufacturing, especially during times when exposure to air or other processes may damage the bulk conductor material 105.

[0065] Conductor lines 95a, 95b, 95c, 95d, and 95e of metallization layer 70 and conductor lines 135a, 135b, 135c, 135d, and 135e of metallization layer 75 can be manufactured with a pre-selected thickness z1, vias 110 and 140 can be manufactured with a pre-selected via height z2, and ILDs 97 and 137 can be manufactured with a pre-selected height z3. Dimensions z1, z2, and z3 can always be used in the various metallization layers 65, 70, 75, 80, 85, and 90, with a few exceptions described in detail below. While this use of standard thicknesses and heights z1, z2, and z3 simplifies processing from one layer to the next, it should be understood that these parameters can also vary between layers. Note that conductor lines 95a, 95b, 95c, 95d, and 95e of metallization layer 70, and conductor lines 135a, 135b, 135c, 135d, and 135e of the metallization layer, are configured to have a design aspect ratio A1 given by the following formula:

[0066]

[0067] Now we will combine Figure 3Metallization layer 80 is described. Metallization layer 75 differs substantially from metallization layers 75 and 70 in several important respects. Like metallization layers 75 and 70, metallization layer 80 includes multiple conductor lines 175a, 175b, 175c, 175d, and 175e, and multiple conductive vias, one of which is visible and labeled 180a. In addition to via 180a, numerous such conductive vias may be present. Note that a barrier layer 182 is formed between the conductive via 180a and the underlying conductor line 135a. Barrier layer 182 can be constructed using the same type of material as described above for barrier layer 160. However, conductor lines 175a, 175b, 175c, 175d, and 175e are constructed using a single damascene layer in a dual damascene layer process. Conductor lines 175b, 175c, 175d, and 175e are laterally separated by air gaps 185a, 185b, and 185c formed in dielectric layer 187, which has portions dispersed between conductor lines 175b, 175c, 175d, and 175e. Conductor lines 175a, 175b, 175c, 175d, and 175e are each freely positioned in a first line portion 190 in a first ILD 195 and a second line portion 200 formed on the lower portion 190 and generally positioned in another ILD 205, and a portion of dielectric layer 187 in which air gaps 185a, 185b, and 185c are formed to some extent. The first line portion 190 is constructed using a dual damascene process to simultaneously fabricate both the first line portion 190 and the conductive via 180a (and other invisible vias). Another etch stop layer 213 is fabricated between ILD 195 and 137. The second line portions 200 of conductor lines 175a, 175b, 175c, 175d, and 175e may each include a barrier layer 215 and a bulk conductor portion 220. The first line portions 190 of lines 175a, 175b, 175d, 175d, and 175e may each include a barrier layer 225 and a bulk conductor portion 230; however, the barrier layer 225, the bulk conductor portion 230, and the via 180a of the first line portion 190 of conductor line 175a are fabricated as a dual damascene and are therefore continuous. Note that the unmarked dashed line defines the first line portion 190 of line 175a and the via 180a. This dashed line simply represents the invisible lower surface of the first line portion 190 of line 175a, which is very similar to the lower surfaces 112a and 112d of conductor lines 95a and 95d, respectively. An etch stop layer 210 is fabricated between ILDs 195 and 205.

[0068] It is desirable to minimize the spacing x3 between adjacent conductor lines 175b and 175c or 175d and 175e in the metallization layer 80 to provide improved packing density. Therefore, the spacing x3 between adjacent conductor lines 175b and 175c or 175d and 175e can be the same as or even less than the spacing x2 used elsewhere. However, making the spacing x3 smaller than x2 proportionally increases the lateral capacitance between lines (such as lines 175d and 175e) in the same layer. Another consideration that can increase the capacitance between adjacent conductor lines (such as lines 175d and 175e) is the shear length of such adjacent lines 175d and 175e. For example, if the metallization layer 80 is used for signal routing in a significantly horizontal manner, conductor lines 175a, 175b, 175d, 175d, and 175e will tend to have longer travel. Longer travel translates to increased capacitance. To offset the increase in capacitance caused by the reduction in lateral spacing from x2 to x3 and / or the increase in line length, dielectric layer 187 is preferably made of a low-k or ultra-low-k material (such as those described above) and is fabricated with air gaps 185a, 185b, and 185c. The use of low-k dielectric layer 187 with air gaps 185a, 185b, and 185c reduces the capacitance between adjacent lines (such as between lines 175b and 175c, and between lines 175c and 175d, etc.).

[0069] Conductor lines 175a, 175b, 175c, 175d, and 175e, and via 180a, can be manufactured to have a higher aspect ratio A1 than conductor lines 95a, 95b, 95c, 95d, and 95e and via 110a, or lines 135a, 135b, 135c, 135d, and 135e and vias 140a and 140b. The relatively high and therefore larger conductor lines 175a, 175b, 175c, 175d, and 175e have a proportionally smaller resistance than lines of comparable width 95a, 95b, 95c, 95d, and 95e, and 135a, 135b, 135c, 135d, and 135e. In this illustrative arrangement, conductor lines 175a, 175b, 175c, 175d, and 175e can be manufactured to have a thickness z4, which is a multiple of the line thickness z1 used elsewhere (such as in metallization layers 70 and 75). For example, z4 can be given by the following formula:

[0070] z4=k1z1 (2)

[0071] Where k1 is a multiplier. Note that the thickness z4 is a combination of the thickness z5 of the second line portion 200 and the thickness z6 of the first line portion 190. The thickness z5 of the second line portion 200 is a multiple of the line thickness z1 used elsewhere (such as in metallization layers 70 and 75). For example, z5 can be given by the following formula:

[0072] z5=k2z1 (3)

[0073] Where k2 is a multiplier. The thickness z6 of the first line portion 190 is a multiple of the line thickness z1 used elsewhere (such as in metallization layers 70 and 75). For example, z6 is given by the following formula:

[0074] z6=k3z1 (4)

[0075] Where k3 is a multiplier. The via 180a can be manufactured with a height z7 that is a multiple of the via height z2 used elsewhere (such as in metallization layers 70 and 75). For example, z7 is given by the following formula:

[0076] z7=k4z2

[0077] Where k4 is a multiplier. ILD 195 is manufactured with a pre-selected height z8, where z8 is given by the following formula:

[0078] z8=z6+z7 (5)

[0079] ILD 205 is manufactured with a pre-selected height z5. The thickness z8 and etching depth used to create the first line portion 190 will determine the values ​​of z7 and z6. The following table lists some exemplary values:

[0080] Table 1

[0081]

[0082] By stacking the first line portion 190 and the second line portion 200, larger conductor lines 175a, 175b, 175c, 175d and 175e with lower resistance can be constructed to have an aspect ratio A2 given by the following formula:

[0083]

[0084] The aspect ratio is greater than the standard aspect ratio A2, without having to attempt the extremely difficult high aspect ratio dielectric directional etching technique. However, it should be noted that as the aspect ratio A2 increases, the capacitance C between adjacent lines (such as conductor lines 175a and 175b, etc.) increases due to the increased overlap area between adjacent lines 175a and 175b, etc. However, since the increased capacitance C is offset by the decreased resistance R, the total RC product (i.e., resistance multiplied by capacitance) should remain relatively constant. In this illustrative arrangement, the process is tailored such that the thickness of conductor lines 175a, 175b, 175c, 175d, and 175e is 1.5 times thicker than that of conductor lines 95a, 95b, 95c, 95d, 95e, 135a, 135b, 135c, 135d, and 135e, and via 180a is 1.5 times thicker than vias 110a, 140a, etc. However, it should be understood that the multipliers k1, k2, k3, and k4 can take multiple values. Note that the value of z7 can be selected to generate an acceptable vertical capacitance between conductor lines 175a, 175b, etc., and the underlying conductors (such as conductor lines 135a, 135b, etc.). Furthermore, the value of z7 sets the value of the combination of the via height z7 and the first line height z6, and z7 and z6 are approximately inversely proportional according to the following formula:

[0085]

[0086] It should be understood that air gaps 185a, 185b, and 185c do not necessarily extend through the entire wide area of ​​the semiconductor chip 15 (i.e., into and out of the page and along...). Figure 1 (The y-axis is shown in the diagram). In practice, air gaps 185a, 185b, and 185c can have various lengths and are discontinuous, i.e., composed of segments, to avoid being located near the through-hole location. In this regard, attention will now also be paid to... Figure 5 , Figure 5 yes Figure 3 The cross-sectional view taken at section 5-5. Note that section 5-5 passes through ILD205, dielectric layer 187, and air gaps 185a, 185b, and 185c. Figure 3 Another air gap 185d, invisible in the middle. The second wire portions 200 of conductor wires 175a, 175b, 175c, 175d, and 175 are shown in section 5-5, exposing the barrier layer 215 and the block conductor 220. From Figure 5 It can be seen that air gaps 185a and 185b terminate before the via location indicated by the dashed circle 235, and both air gaps 185c and 185d terminate before the via location indicated by the dashed circle 235. Treating via locations 235 and 240 as forbidden zones for air gaps 185a, 185b, etc., avoids the possibility of via material overflow due to process deviations during subsequent via masking and etching.

[0087] Now we will combine Figures 6 to 26 An exemplary method for fabricating metallization layer 80 is described. Some of the process steps described below are common to the fabrication of other metallization layers, such as metallization layers 70 and 75, and their commonality will be noted in those cases. The process can be performed at the wafer level or the die level. Now focus Figure 6 , Figure 6 It is similar to Figure 3 However, only the metallization layers 70 and 75 that were manufactured are depicted, as well as those used in the manufacturing process. Figure 2 and Figure 3 The image depicts a cross-sectional view of the initial process of metallization layer 80. It should be understood that metallization layer 70 has undergone multiple processing steps to fabricate ILD 97, conductor lines 95a, 95b, 95c, 95d, and 95e, vias 110a and 110b, and etch stop layer 130, and the same applies to metallization layer 75, ILD 137, conductor traces or lines 135a, 135b, 135c, 135d, and 135e, and vias 140a and 140b. Dual damascene processing is used to simultaneously fabricate lines and vias, such as conductor lines 95a and 95d and the underlying vias 110a and 110b, and conductor lines 135c and 135e and the underlying vias 140a and 140b. Now, let's focus again on... Figure 2 and Figure 3 The initial fabrication of the metallization layer 80 depicted in the image. (Example: ...) Figure 6 As shown, an etch stop layer 213 is first fabricated on the metallization layer 75. The etch stop layer 213 is advantageously made of a material relatively resistant to etching processes used for etching. Figure 3 The trenches and vias in the later-deposited ILD195 are shown. Exemplary materials used for the etch stop layer 213 include ALO. X Materials such as SiCN and silicon oxynitride can be used. The etch stop layer 213 can be fabricated using well-known CVD techniques.

[0088] Next, as follows Figure 7 As shown, ILD 195 is fabricated on etch stop layer 213 and the underlying metallization layers 70 and 75. As described above, ILD 195 can be made of the material type described for ILD 97 and deposited to a thickness z8. It is conceivable that the thickness of etch stop layer 213 is relatively thin compared to the thickness of the overlying ILD 195, and therefore the depth z8 is combined with the thickness of etch stop layer 213. As described above, ILD 195 can be deposited using a well-known CVD process.

[0089] Next and as Figure 8As shown, a hard mask layer 250 is applied to ILD 195, and a resist mask 255 is applied to the hard mask layer 250 and patterned to have appropriate openings 260. The hard mask material layer 250 is advantageously composed of silicon nitride or other suitable hard mask material and will be used as a hard etching mask for fabricating within it. Figure 3 The trenches in the ILD 195 of the first line portion 190 depicted are defined by subsequent etching. Therefore, the openings 260 in the resist mask 255 are appropriately sized and positioned to correspond to the future locations of those first line portions 190. The hard mask material layer 255 can be deposited using well-known CVD processes, and the mask 255 can be coated and patterned using well-known spin coating or other coating processes, followed by suitable baking and photolithography. The metallization layers 70, 75, etch stop layer 213, and ILD 195 remain unaffected by these processing steps.

[0090] Next and as Figure 9 As shown, the hard mask material layer 250 undergoes an etching process to create a plurality of openings 265 therein, the plurality of openings being aligned with the openings 260 and the resist layer 255 and corresponding as described above. Figure 3 The future position of the first line portion 190 is depicted. The hard mask layer 250 can be etched using well-known directional etching techniques and chemicals, such as reactive ion etching using, for example, CF4+O2, NF3, or other suitable chemicals. Endpoint detection can be performed by timing or emission spectroscopy. The metallization layers 70, 75, etch stop layer 213, and ILD 195 remain unaffected by these processing steps. After etching to define the opening 265 in the hard mask layer 250, the resist mask 255 is stripped using well-known ashing, solvent stripping, or a combination of both, and a second resist mask 270 is applied to the hard mask layer 250 and the second resist mask is as shown. Figure 10 The pattern shown is illustrated. Mask 270 can be made of the same type of material and in a manner consistent with... Figure 9 The mask 255 depicted is processed in the same manner. However, here the mask 270 is photolithographically patterned to have multiple openings, one of which is shown and labeled 275. These multiple openings are appropriately sized and located where through-holes (such as...) will subsequently be fabricated. Figure 3 At the location of the via 180a shown. Those openings 265 in the hard mask layer 250 that are only used for subsequent trench etching are covered by the mask 270. The metallization layers 70, 75, the etch stop layer 213, and the ILD 195 remain unaffected by these processing steps.

[0091] Next and as Figure 11As depicted, with the resist mask 270 in place and appropriately patterned to have openings 275, directional etching is performed on the ILD 195 to produce vias 280 aligned with the mask openings 275. These vias 280 will typically have the same coverage area, although not necessarily the same as... Figure 3 The subsequent final depth of the via 180a, which is formed later, is the same. The ILD 195 can be etched using well-known directional etching techniques and chemicals, such as reactive ion etching using, for example, CF4, CF4+O2, SF6, NF3, or other suitable chemicals. Endpoint detection can be performed by timing or emission spectroscopy. After etching the opening 280 in the ILD 195, the resist mask 270 is as follows... Figure 12 As shown, the photoresist stripping technique described elsewhere herein is used. The metallization layers 70, 75, etch stop layer 213, and ILD195 remain unaffected by these processing steps. However, the hard mask 250 is now exposed and ready to be used as an etch mask.

[0092] Next and as Figure 13 As shown, a second etching of ILD 195 is performed, this time using a hard mask 250 as the etching mask. Here, the etching creates trenches 285 in ILD 195 at the location of the hard mask opening 265, and thus also in the later-formed first line portion 190 (see...). Figure 3 A trench is created at the location of ). This etching also deepens the via holding portion 280 up to the etch stop layer 213. A newly bonded section can also be used here. Figure 11 The same etching technique is described. Of course, the etch stop layer 213 is advantageously made of a material relatively resistant to the etching chemicals used to perform the ILD etching. Note that this etching produces a shoulder 290. When viewed from above, this shoulder 290 will appear as an edge with a periphery corresponding to the coverage area of ​​the via 280, and if the via 280 is circular, the shoulder 290 will also appear circular when viewed from above. The metallization layers 70 and 75, as well as the ILD 195, remain unaffected by these processing steps.

[0093] After etching the defined trench 285 and deepening the via 280, the hard mask layer 250 as follows Figure 14 The hard mask layer 250 is etched away to expose ILD 195, as well as trench 285 and via. A variety of well-known etching techniques, such as hot phosphoric acid impregnation or dry etching techniques described elsewhere herein for etching openings 265 in the hard mask 250, can be used to remove the hard mask layer 250. The metallization layers 70 and 75 remain unaffected by these processing steps.

[0094] Next and as Figure 15As shown, another etching process is performed. Before fabricating the conductive via 180a, which makes ohmic contact with the underlying conductor line 135a, an opening must be created in the etch stop layer 213 at the location of the via 280. As... Figure 15 As shown, rapid etching with a chemical composition suitable for penetrating the etch stop layer 215 is performed using a well-known etch chemical that is selective for ILD 195 with plasma. It is conceivable that the etching used to create opening 292 is sufficiently brief to avoid materially affecting the structural integrity of ILD 195. Metallization layers 70 and 75 remain unaffected by these processing steps.

[0095] Next and as Figure 16 As shown, a barrier metal deposition process is performed to establish a barrier layer 182 that makes an ohmic contact with the underlying conductor line 135a. The barrier layer 182 can be fabricated using well-known CVD, PVD, or electroplating processes. The metallization layers 70 and 75 remain unaffected by these processing steps.

[0096] Next and as Figure 17 As shown, a barrier layer 225 is deposited on ILD 195 to fill vias 280 and trenches 285. The barrier layer 225 can be fabricated using well-known CVD or PVD processes. A portion of the barrier layer 225 contacts the barrier layer 182. Metallization layers 70 and 75 remain unaffected by these processing steps.

[0097] Next and as Figure 18 As shown, an electroplating process is advantageously performed to establish a blanket-covered conductor layer 294. The conductor layer 294 is then polished to create… Figure 3 The block conductor portion 230 is depicted and described above. A blanket-covered conductor layer 294 fills over the barrier layer 225 and, of course, fills the trenches 285 and vias 280. At this stage, the blanket-covered conductor layer 294... Figure 19 As shown, a process such as chemical mechanical polishing (CMP) is used to remove the portions of the blanket-covered conductor layer 294 and the barrier layer 225 protruding above the ILD 195, thereby creating the first line portion 190 and simultaneously establishing a conductive via 180a due to the dual damascene nature. The metallization layers 70 and 75, as well as the etch stop layer 213, remain unaffected by these processing steps. It should now be understood that, despite having different line thicknesses and via heights, the techniques just described for creating the first line portion 190 and via 180a can be used to fabricate... Figure 3 The conductor lines 95a, 95b, 95c, 95d, 95e, 135a, 135b, 135c, 135d and 135e shown, as well as vias 110a, 110b, 140a and 140b, ILD 97 and 137, etch stop layer 130, and barrier layer 170 of metallization layers 70 and 75.

[0098] Next and as Figure 20 As shown, etch stop layer 210 is fabricated on ILD 195 and above the first line portion 190 using the same type of materials and techniques disclosed elsewhere for etch stop layer 213. Metallization layers 70 and 75, as well as etch stop layer 213, remain unaffected by these processing steps.

[0099] Next and as Figure 21 As shown, ILD 205 is fabricated on etch stop layer 210. The same type of materials and techniques used to fabricate ILD 195 can be used to fabricate ILD 205. Metallization layers 70 and 75, ILD 195, and etch stop layer 213 remain unaffected by these processing steps.

[0100] from Figure 22 As can be seen, the processing steps used to establish the first line portion 190 are repeated to establish the second line portion 200 in the ILD 205. This second line portion, together with the lower portion 190, constitutes conductor lines 175a, 175b, 175c, 175d, and 175e. These include the aforementioned hard masking and multiple photoresist masking steps and etching, followed by material deposition and polishing to establish complete conductor lines 175a, 175b, 175c, 175d, and 175e, each composed of a barrier layer 215 and a bulk conductor layer 220. The metallization layers 70 and 75, as well as the etch stop layer 213, remain unaffected by these processing steps.

[0101] Next and as Figure 23 As shown, resist mask 295 is applied to ILD 205 and appropriately patterned to have openings 300 corresponding to the desired coverage areas and locations for openings to be etched into ILD 205 (in which the air gaps 185a, 185b, 185c, and 185d disclosed above will be created). The resist mask 295 and the openings 300 therein can be applied and patterned using the same type of technique discussed above for other photoresist masks. Metallization layers 70 and 75, ILD 195, and etch stop layer 213 remain unaffected by these processing steps.

[0102] Next and as Figure 24 As shown, the ILD 205 is oriented to create a plurality of openings 305 aligned with the masked openings 300. This etching for creating the openings 300 can be performed in several ways. Figure 24In the exemplary arrangement disclosed herein, etching is performed such that opening 305 penetrates not only ILD 205 but also etch stop layer 210 and a portion of ILD 195, but stops before the bottom 310 of the first line portion 190. The depth of opening 305 will determine the vertical range of subsequently formed air gaps 185a, 185b, 185c, and 185d. Higher air gaps 185a, 185b, 185c, and 185d exhibit lower capacitance, but it may be desirable to etch opening 305 in a manner that does not reach the bottom 310 or even penetrate the etch stop layer 210. Etching chemicals and techniques for etching ILD 195 disclosed elsewhere herein may be used here. Metallization layers 70 and 75 and etch stop layer 213 remain unaffected by these processing steps.

[0103] Next and as Figure 25 As shown, a dielectric layer 187 is fabricated over ILD 205 using the well-known CVD process and materials disclosed above. Prior to using the CVD process on dielectric layer 187, the dielectric layer is stripped using techniques disclosed elsewhere herein. Figure 24 The resist mask 295 is depicted in the figure. As the CVD process for establishing layer 187 proceeds, the sidewalls and bottom 310 of the openings 305 in ILD 205 and ILD 195 are gradually coated with dielectric material 187 until bridging occurs at locations 312a, 312b, and 312c, which establishes the aforementioned air gaps 185a, 185b, and 185c. The metallization layers 70 and 75, as well as the etch stop layer 213, remain unaffected by these processing steps.

[0104] Next and as Figure 26 As shown, a dielectric material for metallization layer 85 is applied over dielectric layer 187, and numerous other processing steps for manufacturing the metallization layer can be performed. Typically, these will be the types of processing steps used to manufacture metallization layers without any air gaps 185a, 185b, and 185c, such as those used to manufacture, for example, metallization layer 75. Metallization layers 70 and 75, etch stop layer 213, dielectric layer 187, and ILDs 195 and 205 remain unaffected by these processing steps.

[0105] As described above, the dimensions of the ILD used for the air-gap metallization layer, as well as the conductor lines and vias, can be customized to achieve a certain level of capacitance and resistance. For example, Figure 28 It is similar to Figure 3However, an alternative exemplary cross-sectional view of metallization layer 80' is provided, which utilizes the same basic single damascene process to establish conductive lines and vias in a dual damascene process. However, in this exemplary arrangement, different multipliers can be used to alter the spatial relationships of various conductor structures. In this exemplary arrangement, the process is tailored such that the thickness z4 of conductor lines 175a', 175b', 175c', and 175d' is 2.0 times thicker than the thickness z1 of conductor lines 95a, 95b, 95c, 95d, and 95e of metallization layer 70, and the height z7 of via 180a' is the same as the height z2 of vias 110a and 110b. The same basic linewidth x1 can be used. Table 2 below shows some exemplary parameters.

[0106] Table 2

[0107]

[0108] It should be understood that the multipliers k1, k2, k3, and k4 can take multiple values. The thickness z8 of ILD 195 can be customized to accommodate thicknesses z4, z5, z6, and height z7. The air gaps 185a', 185b', and 185c' in the dielectric layer 187 will be larger than... Figure 3 The arrangement shown is higher, and ILD 195 is etched deeper between lines 175a' and 175b', etc. The same basic stacked line structure utilizing the first line portion 190 and the second line portion 200 is used, albeit with appropriate thickness. Note that the aspect ratios of conductor lines 175a', 175b', 175c', and 175d' can be greater than the aspect ratio of the metallization layer 70.

[0109] exist Figure 28 In another illustrative alternative arrangement depicted, the process is tailored such that the thickness z4 of the conductor lines 175a", 175b", 175c", 175d", and 175e" of the metallization layer 80" is 1.5 times thicker than the conductor lines 95a", 95b", 95c", 95d", and 95e of the metallization layer 70, and the height of the via 180a" is 2.0 times thicker than the vias 110a, 140a, etc. However, it should be understood that the multipliers k1, k2, k3, and k4 can take multiple values. Table 3 below shows some exemplary parameters.

[0110] Table 3

[0111]

[0112] The thickness z8 of the ILD 195 can be customized to accommodate thicknesses z4, z5, z6, and height z7. (Compared to...) Figure 3Compared to the arrangement shown, the air gaps 185a”, 185b”, and 185c” in dielectric layer 187 will be shorter, and ILD 195 is not etched between 175a” and 175b”, etc. In fact, etch stop layer 210 is disposed at the lower limit of dielectric layer 187 in which air gaps 185a”, 185b”, and 185c” are formed. The same basic stacked line structure utilizing first line portion 190 and second line portion 200 is used, albeit with appropriate thickness. Note that the aspect ratio of conductor lines 175a”, 175b”, 175c”, 175d”, and 175e” can be greater than the aspect ratio of metallization layer 70.

[0113] Any of the disclosed semiconductor chip arrangements can be placed in an electronic device. Figure 29 A semiconductor chip device 10, disassembled from an electronic device 350, is shown. The electronic device may be a computer, digital television, handheld mobile device, personal computer, server, memory device, expansion board (such as a graphics card), or any other computing device employing semiconductors.

[0114] While this disclosure may have various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that this valve is not intended to be limited to the specific forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor chip (15) comprising: a substrate (50); a plurality of metallization layers (75, 80) on the substrate; a first conductor line (175b) in one of the metallization layers and a second conductor line (175c) in the one of the metallization layers, the second conductor line being spaced apart from the first conductor line, each of the first and second conductor lines having a first line portion (190) and a second line portion (200) stacked on the first line portion, wherein the first line portion (190) is located within a first dielectric layer (195) and the second line portion (200) is located within a second dielectric layer (205); and a third dielectric layer (187) having a portion located between the first and second conductor lines, the portion having an air gap (185a).

2. The semiconductor chip of claim 1, wherein a third conductor line (175a) of the one of the metallization layers comprises a first line portion (190) and a second line portion (200) stacked on the first line portion, the one of the metallization layers having a conductive via (180a), the first line portion and the conductive via having a shared contiguous bulk conductor portion (230) and a shared contiguous barrier layer (225).

3. The semiconductor chip of claim 1, wherein the second line portion has a first thickness and the air gap has a second thickness that is greater than the first thickness.

4. The semiconductor chip of claim 1, comprising a plurality of conductor lines in another one of the metallization layers, each of the plurality of conductor lines having a first thickness, the first conductor line of the one metallization layer having a second thickness that is greater than the first thickness.

5. The semiconductor chip of claim 1, comprising a plurality of conductive vias (140a, 140b) in another one of the metallization layers, each of the plurality of conductive vias having a first thickness, a third conductor line of the one of the metallization layers comprising a first line portion and a second line portion stacked on the first line portion, the one of the metallization layers having a conductive via connected to the first line portion, the conductive via having a second thickness that is greater than the first thickness.

6. The semiconductor chip of claim 1, wherein the one of the metallization layers (80) comprises the first dielectric layer (195) and the second dielectric layer (205) stacked on the first dielectric layer, each of the first and second conductor lines being partially located in the first dielectric layer and partially located in the second dielectric layer.

7. The semiconductor chip of claim 1, comprising a plurality of conductor lines (135a, 135b) in another one of the metallization layers (75), the plurality of conductor lines having a first lateral spacing, the first and second conductor lines of the one metallization layer having a second lateral spacing that is less than the first lateral spacing.

8. The semiconductor chip of claim 1, comprising a circuit board (20) on which the semiconductor chip is mounted.

9. The semiconductor chip of claim 1, further comprising: wherein the plurality of metallization layers comprises a first metallization layer (75) on the substrate and a second metallization layer (80) on the first metallization layer; a plurality of conductor lines (135a, 135b) in the first metallization layer, each of the conductor lines having an aspect ratio (A); wherein the first conductor line (175b) is in the second metallization layer and the second conductor line (175c) is in the second metallization layer, the second conductor line being spaced apart from the first conductor line, each of the first and second conductor lines having an aspect ratio (A2) that is greater than the aspect ratio of the plurality of conductor lines.

10. The semiconductor chip of claim 9, wherein a third conductor line (175a) of the second metallization layer comprises a first line portion (190) and a second line portion (200) stacked on the first line portion, the second metallization layer having a conductive via, the first line portion and the conductive via having a shared continuous bulk conductor portion and a shared continuous barrier layer.

11. The semiconductor chip of claim 9, comprising a plurality of conductive vias in the first metallization layer, each of the plurality of conductive vias having a first thickness, a third conductor line of the second metallization layer comprising a first line portion and a second line portion stacked on the first line portion, the second metallization layer having a conductive via (180a) connected to the first line portion, the conductive via having a second thickness that is greater than the first thickness.

12. The semiconductor chip of claim 9, wherein the second metallization layer comprises a first dielectric layer (195) and a second dielectric layer (205) stacked on the first dielectric layer, each of the first and second conductor lines being partially positioned in the first dielectric layer and partially positioned in the second dielectric layer.

13. The semiconductor chip of claim 9, wherein the plurality of conductor lines have a first lateral spacing, the first and second conductor lines of the second metallization layer having a second lateral spacing that is less than the first lateral spacing.

14. The semiconductor chip of claim 9, comprising a circuit board (20) on which the semiconductor chip is mounted.

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