Quiet mechanism with reduced pop noise in audio amplifier system and method

Abstract

A system and method for improved noise performance of an audio amplifier are provided. In one example, the system includes a multi-stage amplifier including at least a first stage amplifier and a second stage amplifier. The system also includes a plurality of switches disposed within the multi-stage amplifier to configure the multi-stage amplifier. The system also includes a control signal configured to control the multi-stage amplifier to a normal amplification mode or a mute state, wherein the multi-stage amplifier is adapted to amplify an input signal in the normal amplification mode, the multi-stage amplifier is adapted to output a zero signal in the mute state, and an internal amplification stage of the multi-stage amplifier is disabled in the mute state, and an output stage of each of at least the first stage amplifier and the second stage amplifier is electrically shorted and / or shorted to a fixed bias voltage in the mute state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 62 / 789,461, filed on January 7, 2019, and entitled “MUTE MECHANISM WITH REDUCED POPNOISE IN AUDIO AMPLIFIER SYSTEMS AND METHODS,” and U.S. Patent Application No. 16 / 357,244, filed on March 18, 2019, and entitled “MUTE MECHANISM WITH REDUCED POP NOISE IN AUDIO AMPLIFIER SYSTEMS AND METHODS,” which are hereby incorporated by reference. Technical Field

[0003] According to one or more examples, the present disclosure relates generally to processing analog signals and, more particularly, for example, to improving noise performance within high performance audio amplifiers. Background Art

[0004] Many modern devices, such as laptops, computer tablets, MP3 players, and smart phones, provide high-fidelity audio signals for internal or external speaker connectivity. Such systems can generate audio content digitally, convert digital signals to analog signals, amplify analog signals, and transmit the amplified analog current signals to audio transducers. In some high-fidelity systems, multi-stage audio amplifiers include noise suppression circuits to reduce unwanted noise when the audio signal has a low level. To prevent unwanted noise, conventional noise suppression circuits may short-circuit the output of the multi-stage audio amplifier. Unfortunately, conventional noise suppression circuits may not be able to adjust the bias of the internal amplifier stage. When the noise suppression is released, the internal nodes of the internal amplifier stage are not at the correct voltage for signal amplification, and voltage glitches may be caused on the increased input signal, and the amplifier output may produce "popping noise". In addition, conventional noise suppression circuits can short-circuit the resistor amplifier feedback to reduce signal noise. However, if only the resistor feedback is short-circuited, the multi-stage amplifier still generates circuit noise, which causes unwanted noise on the audio output signal. As a result, for example, a user may experience a less pleasant listening experience using a headphone device.In view of the foregoing, there remains a need in the art for improved low signal level noise reduction that provides improved audio amplifier performance. Summary of the invention

[0005] The present disclosure provides systems and methods that address the need in the art for improved noise reduction within amplifiers used in modern devices, such as modern devices that include speaker connectivity.

[0006] In various examples, a system includes: a multi-stage amplifier, the multi-stage amplifier including at least a first-stage amplifier and a second-stage amplifier; a plurality of switches disposed within the multi-stage amplifier to configure the multi-stage amplifier; and a control signal configured to control the multi-stage amplifier to a normal amplification mode or a mute state,

[0007] wherein the multi-stage amplifier is adapted to amplify an input signal in the normal amplification mode, wherein the multi-stage amplifier is adapted to output a zero signal in the mute state, and wherein an internal amplification stage of the multi-stage amplifier is disabled in the mute state, and an output stage of each of the at least first-stage amplifier and the second-stage amplifier is electrically short-circuited and / or shorted to a fixed bias voltage in the mute state.

[0008] In various examples, a system includes: a multi-stage amplifier including a plurality of amplifier stages; a plurality of switches disposed within the multi-stage amplifier and coupled to an output of each of the plurality of amplifier stages; an envelope detection circuit adapted to sense a voltage at an output port of the multi-stage amplifier and control the plurality of switches in response to the sensed voltage to electrically connect the output of each of the plurality of amplifier stages to a DC voltage signal substantially equal to a quiescent operating voltage of each of the plurality of amplifier stages.

[0009] In various examples, a method includes: supplying a multi-stage amplifier including a plurality of amplifier stages; disposing a plurality of switches within the multi-stage amplifier and coupled to an output of each of the plurality of amplifier stages; sensing, by an envelope detection circuit, a voltage at an output port of the multi-stage amplifier; and in response to the sensed voltage, controlling, by the envelope detection circuit, the plurality of switches to electrically connect the output of each of the plurality of amplifier stages to a DC voltage signal that is substantially equal to a quiescent operating voltage of each of the plurality of amplifier stages.

[0010] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of the present disclosure, as well as the realization of its additional advantages, will be provided to those skilled in the art by considering the following detailed description of one or more examples. Reference will be made to the attached sheets of the drawings which will first be briefly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various aspects of the present disclosure and its advantages may be better understood with reference to the following drawings and the following detailed description. It should be understood that similar reference numerals are used to identify similar elements illustrated in one or more of the drawings, wherein the illustrations in the drawings are for the purpose of illustrating examples of the present disclosure, and not for the purpose of limiting the examples of the present disclosure. The components in the drawings are not necessarily to scale, but emphasis is placed on clearly illustrating the principles of the present disclosure.

[0012] Figure 1 A schematic diagram of a multi-stage amplifier including a conventional noise suppression circuit is illustrated.

[0013] Figure 2 An exemplary schematic diagram of a multi-stage amplifier with improved noise reduction according to examples of the present disclosure is illustrated.

[0014] Figure 3 An exemplary schematic diagram of a differential multi-stage amplifier with improved noise reduction according to examples of the present disclosure is illustrated.

[0015] Figure 4 An exemplary schematic diagram of a single-ended multi-stage amplifier with improved noise reduction according to the present disclosure is illustrated.

[0016] Figure 5 is a flow chart illustrating a method of operation for a noise reduction circuit in a multi-stage amplifier according to an example of the present disclosure. DETAILED DESCRIPTION

[0017] The present disclosure describes systems and methods that address the need in the art for improved noise reduction mechanisms in multi-stage amplifiers of modern devices that include internal and external speaker amplifier functionality.The following discussion will be directed to a multi-stage audio amplifier with an example of a noise reduction mechanism.

[0018] Figure 1 FIG. 1 is a schematic diagram of a multi-stage amplifier 100 including a conventional noise suppression circuit. Figure 1As shown in , the multi-stage amplifier 100 includes a first stage amplifier 102, a second stage amplifier 104, a noise suppression switch 106, and an envelope detection and control circuit 108. In one example, the multi-stage amplifier 100 is implemented as a multi-stage differential amplifier, wherein the first stage amplifier 102 and the second stage amplifier 104 are implemented as differential amplifiers. In another example, the multi-stage amplifier 100 is implemented as a multi-stage single-ended amplifier, wherein the first stage amplifier 102 and the second stage amplifier 104 are implemented as single-ended amplifiers. The first stage amplifier 102 receives an input signal 101 at an inverting input port 102A and receives an input signal 103 at a non-inverting input port 102B. The first stage amplifier 102 provides an amplified output signal 105 at an inverting port 102C, and passes the amplified output signal 105 to an inverting input port 104A of the second stage amplifier 104. The first stage amplifier 102 provides an amplified output signal 107 at a non-inverting port 102D and passes the amplified output signal 107 to a non-inverting input port 104B of the second stage amplifier 104. The second stage amplifier 104 provides a multi-stage amplifier output signal 109 at an output port 104C and a multi-stage amplifier output signal 111 at an output port 104D.

[0019] In one example, the noise suppression switch 106 includes a switch wiper 106A electrically connected to the multi-stage amplifier output signal 109 and a switch wiper 106B electrically connected to the multi-stage amplifier output signal 111. The envelope detection and control circuit 108 is implemented to control the switch arm 106C of the noise suppression switch 106 to open and close the noise suppression switch 106. In one example, the noise suppression switch 106 is closed by the envelope detection and control circuit 108 to short the multi-stage amplifier output signal 109 to the multi-stage amplifier output signal 111 during a period in which the input signals 101 and 103 have a low level.

[0020] exist Figure 1 In the example shown in , when the noise suppression switch 106 is closed, the multi-stage amplifier 100 feedback is interrupted. In this regard, even a small input offset at the inverting input port 102A and the non-inverting input port 102B will result in a large signal at the output port 104C and the output port 104D. The large signal at the output port of the multi-stage amplifier 100 will cause contention between the closed switch 106 and the multi-stage amplifier 100, which causes a large current to flow through the switch 106, and the switch 106 will need to be sized accordingly to avoid electrical stress and / or thermal overload. In addition, when the multi-stage amplifier 100 transitions from the noise suppression condition to the active condition, all internal nodes of the multi-stage amplifier 100 will take time to stabilize to their desired values. During this stabilization time, there may be undesirable pop noise at the output port of the multi-stage amplifier 100.

[0021] Therefore, there is a need in the art for improved low signal level noise reduction that provides improved audio amplifier performance.

[0022] Figure 2 An exemplary schematic diagram of a multi-stage amplifier 200 with improved noise reduction according to an example of the present disclosure is illustrated. Figure 2 As shown in , the multi-stage amplifier 200 includes a plurality of amplifier stages (e.g., a first stage amplifier 202 and a second stage amplifier 204), switches 206A-206C, and an envelope detection circuit 208. In one example, the multi-stage amplifier 200 is implemented as a multi-stage differential amplifier, wherein the first stage amplifier 202 and the second stage amplifier 204 are implemented as differential amplifiers electrically coupled in series. In another example, the multi-stage amplifier 200 is implemented as a multi-stage single-ended amplifier, wherein the first stage amplifier 202 and the second stage amplifier 204 are implemented as single-ended amplifiers electrically coupled in series. In some examples, the multi-stage amplifier 200 is implemented using one or more single-ended amplifier stages and / or one or more differential amplifier stages. For example, in one non-limiting example, the multi-stage amplifier 200 includes a first stage amplifier 202 and a second stage amplifier 204 implemented as differential amplifier stages and a third stage amplifier (e.g., not shown) implemented as a single-ended amplifier stage.

[0023] In various examples, a system includes a multi-stage amplifier including a squelch circuit that reduces noise in operation. The system may include a multi-stage amplifier 200 including at least a first stage amplifier 202 and a second stage amplifier 204. The system may also include one or more switches 106 disposed within the multi-stage amplifier 200 to configure the multi-stage amplifier 200 between a squelch state and a normal amplification mode. A control signal (e.g., output from an envelope detection circuit 208) controls the switches of the multi-stage amplifier 200 to switch between the normal amplification mode and the squelch state. In the normal amplification mode, the multi-stage amplifier 200 will amplify an input signal. In the squelch state, the amplifier is disabled and the multi-stage amplifier is adapted to output a zero signal, which may include entering a static operating state, a DC operating state, or shorting the output port to effectively squelch the amplifier. In some examples, in the mute state, internal amplification stages (eg, 202 and 204 of the illustrated example) of the multi-stage amplifier 200 are also disabled, and output ports of the internal amplification stages are shorted to each other and / or connected to a replica bias voltage signal.

[0024] In some examples, at least one of the stages of the multi-stage amplifier is configured as a differential amplifier, and the outputs of the internal amplifier stages of the differential amplifier (e.g., output stages) are electrically shorted to each other in the muted state. In some examples, at least one of the stages of the multi-stage amplifier is configured as a single-ended amplifier, and the internal amplifier stages of the single-ended amplifier are shorted to a fixed bias voltage in the muted state. In various examples, the output of the multi-stage amplifier 200 is electrically shorted to a ground signal in the muted state (e.g., when at least one of the stages of the multi-stage amplifier is configured as a single-ended amplifier).

[0025] In various examples, the multi-stage amplifier 200 is implemented to receive an input signal 201 at an inverting input port 202A of a first stage amplifier 202 and an input signal 203 at a non-inverting input port 202B. Figure 2 As shown in FIG. 1 , the first stage amplifier 202 provides an amplified output signal 205 at an inverting output port 202C and passes the amplified output signal 205 to an inverting input port 204A of the second stage amplifier 204. The first stage amplifier 202 provides an amplified output signal 207 at a non-inverting output port 202D and passes the amplified output signal 207 to a non-inverting input port 204B of the second stage amplifier 204. The second stage amplifier 204 provides a multi-stage amplifier output signal 209 at a non-inverting output port 204C and provides a multi-stage amplifier output signal 211 at an inverting output port 204D (e.g., a differential output port pair).

[0026] In some examples, the envelope detection circuit 208 is implemented to sense a voltage at an input port of the multi-stage amplifier 200 (e.g., at the inverting input port 202A and the non-inverting input port 202B), and to control the switches 206A-206C in response to the sensed voltage. In some examples, the envelope detection circuit 208 controls the switches 206A-206C in response to the sensed voltage being lower than an idle noise threshold (e.g., a multi-stage amplifier idle noise threshold) of the multi-stage amplifier 200. In some examples, the idle noise threshold is negative 130 dB for a low input signal level. However, other idle noise thresholds are possible for other multi-stage amplifier implementations, such as negative 135 dB and / or negative 140 dB.

[0027] In some examples, the switch 206 is disposed within the multi-stage amplifier 200 and coupled to the output of each of the amplifier stages (e.g., the first stage amplifier 202 and the second stage amplifier 204). The envelope detection circuit 208 controls the switches 206A-206C to electrically connect the differential output pair of each of the amplifier stages (e.g., such as the inverting output port 202C and the non-inverting output port 202D of the first stage amplifier 202, and the non-inverting output port 204C and the inverting output port 204D of the second stage amplifier 204) to a DC voltage signal substantially equal to the quiescent operating voltage of each of the amplifier stages in response to the sensed voltage. In various examples, the intermediate amplifier stage (e.g., such as the first stage amplifier 202) disables its output before connecting the DC voltage signal to the output port to avoid any electrical stress or voltage contention at the output port. In some examples, at least one switch 206 of the plurality of switches is coupled to an input port of the multi-stage amplifier 200, and the multi-stage amplifier 200 is operable to electrically connect the input port to the DC voltage signal.

[0028] In one example, the switch 206A includes a switch arm 216A electrically connected to the inverting input port 202A and a switch arm 216B electrically connected to the non-inverting input port 202B. The envelope detection circuit 208 is implemented to control the switch arm 216C of the switch 206A to open and close the switch 206A. In one example, the switch 206A is closed by the envelope detection circuit 208 to electrically short the inverting input port 202A to the non-inverting input port 202B (e.g., short the differential input port pair) during a period when the input signals 201 and 203 are below the idle noise threshold level of the multi-stage amplifier 200. In addition, the envelope detection circuit 208 is implemented to close the switch 206B and the switch 206C when the input signal 201 and the input signal 203 are below the idle noise threshold level of the multi-stage amplifier 200. In some examples, control signals (not shown) are provided to first stage amplifier 202 and second stage amplifier 204 to command a mute function of first stage amplifier 202 and second stage amplifier 204 in response to a detected input signal being below an idle noise threshold.

[0029] In one example, each switch 206 is implemented as an n-channel metal oxide semiconductor field effect transistor (NMOSFET) switch. In another example, each switch 206 is implemented as a complementary switch including an n-channel metal oxide semiconductor field effect transistor switch and a p-channel metal oxide semiconductor field effect transistor (PMOSFET) switch electrically connected in series.

[0030] like Figure 2As shown in , for the multi-stage differential amplifier implementation, the envelope detection circuit 208 controls the switch 206B to electrically connect the inverting output port 202C of the first stage amplifier 202 to the non-inverting output port 202D. The envelope detection circuit 208 controls the switch 206C to electrically connect the non-inverting output port 204C of the second stage amplifier 204 to the inverting output port 204D. In this regard, when the sensed voltage is lower than the idle noise threshold of the multi-stage differential amplifier, the envelope detection circuit 208 electrically connects each of the plurality of differential amplifier output ports to each other.

[0031] In one example, Figure 2 The multi-stage differential amplifier implementation includes a differential amplifier replica bias voltage signal substantially equal to a quiescent operating voltage (e.g., a quiescent operating voltage of each of the first stage amplifier 202 and the second stage amplifier 204). In some examples, the differential amplifier replica bias voltage signal is substantially equal to a common mode voltage of each of the first stage amplifier 202 and the second stage amplifier 204. In one example, when the sensed voltage is lower than Figure 2 When the idle noise threshold of the multi-stage differential amplifier implementation is exceeded, the switch 206A is controlled to electrically connect the differential amplifier replica bias voltage signal to each of the inverting input port 202A and the non-inverting input port 202B (eg, a differential input pair).

[0032] In another example, when the sensed voltage is lower than Figure 2 When the sensed voltage is lower than the idle noise threshold of the multi-stage differential amplifier implementation, the switch 206B is controlled to electrically connect the differential amplifier replica bias voltage signal to each of the inverting output port 202C and the non-inverting output port 202D, and the switch 206C is controlled to electrically connect the differential amplifier replica bias voltage signal to each of the non-inverting output port 204C and the inverting output port 204D. In yet another example, when the sensed voltage is lower than the idle noise threshold, the switch 206A is controlled to electrically short the inverting input port 202A and the non-inverting input port 202B (e.g., a differential input pair) to each other.

[0033] Figure 3 FIG. 2 illustrates an exemplary schematic diagram of a differential multi-stage amplifier 300 with improved noise reduction according to an example of the present disclosure. Figure 3As shown in , the differential multi-stage amplifier 300 is implemented as a two-stage amplifier. In this regard, the differential multi-stage amplifier 300 includes a first-stage differential amplifier 302 and a second-stage differential amplifier 304 (e.g., the second-stage differential amplifier 304 illustrated by node 365 (outp) and node 366 (outn)). The first-stage differential amplifier 302 includes a multi-stage differential amplifier input port 303, which includes a first input port PMOSFET transistor 303A and a second input port PMOSFET transistor 303B. The first-stage differential amplifier 302 also includes: a first current source 319 including PMOSFET transistors 319A and 319B, a second current source 320 including NMOSFET transistors 320A and 320B, a third current source 321 including PMOSFET transistors 321A and 321B, and a fourth current source 322 including NMOSFET transistors 322A and 322B. The drain terminals of the NMOSFET transistor 320B of the second current source 320 and the NMOSFET transistor 322B of the fourth current source 322 are connected to a ground signal 327 .

[0034] The PMOSFET transistor power switch 361 is electrically connected to a voltage source 360 ​​at a source terminal and electrically connected to the multi-stage differential amplifier input port 303 at a drain terminal. In one example, the voltage source 360 ​​is a five volt DC voltage source. In other examples, the voltage source 360 ​​is a 10 volt DC voltage source. However, the voltage source 360 ​​can be any DC voltage source suitable for providing a voltage to the multi-stage differential amplifier input port 303.

[0035] The first stage differential amplifier 302 includes a first floating battery 324, which includes an NMOSFET transistor 324A connected in parallel with a PMOSFET transistor 324B. The first current source 319 and the second current source 320 are connected to the first floating battery 324. The first stage differential amplifier 302 also includes a second floating battery 326, which includes an NMOSFET transistor 326A connected in parallel with a PMOSFET transistor 326B. The third current source 321 and the fourth current source 322 are connected to the second floating battery 326.

[0036] The first stage differential amplifier 302 includes a first output stage 370 including a PMOSFET transistor 371 and a PMOSFET transistor 373. The first stage differential amplifier 302 includes a second output stage 380 including an NMOSFET transistor 372 and an NMOSFET transistor 374. The first output stage 370 and the second output stage 380 are connected to the second stage differential amplifier 304 at nodes 365 and 366.

[0037] In one example, envelope detection circuit 208 (e.g., such as Figure 2 The envelope detection circuit 208 of the embodiment of the present invention controls switches 306A, 306B, and 306C to be closed simultaneously. Switch 306A electrically shorts PMOSFET transistor 371 to PMOSFET transistor 373 at node 351 and node 353, respectively. Switch 306B electrically shorts NMOSFET transistor 372 to NMOSFET transistor 374 at node 352 and node 354, respectively. Switch 306C electrically shorts node 365 of the second stage differential amplifier 304 to node 366. In this regard, when the sensed voltage is lower than the idle noise threshold, each of the first stage differential amplifier 302, the first output stage 370, and the second output stage 380 transistors are shorted to each other. In addition, when the sensed voltage is lower than the idle noise threshold, the output of the second stage differential amplifier 304 is shorted at node 365 and node 366.

[0038] Figure 4 FIG. 4 illustrates an exemplary schematic diagram of a multi-stage single-ended amplifier 400 with improved noise reduction according to the present disclosure. Figure 4 As shown in FIG. 4 , the multi-stage single-ended amplifier 400 includes a first-stage single-ended amplifier 402 and a second-stage single-ended amplifier 404. The first-stage single-ended amplifier 402 includes a multi-stage single-ended amplifier input port 403, which includes a first input port PMOSFET transistor 403A and a second input port PMOSFET transistor 403B. The first-stage single-ended amplifier 402 also includes a first current source 419 and a second current source 421, the first current source 419 includes PMOSFET transistors 419A and 419B, and the second current source 421 includes PMOSFET transistors 421A and 421B. The first-stage single-ended amplifier 402 also includes a current mirror circuit 415, and the current mirror circuit 415 includes NMOSFET transistors 415A-415D connected to the first current source 419. The PMOSFET transistor power switch 461 is electrically connected to the voltage source 460 at the source terminal and the multi-stage single-ended amplifier input port 403 at the drain terminal. In one example, the voltage source 460 is a five-volt DC voltage source. In other examples, the voltage source 460 is a 10-volt DC voltage source. However, the voltage source 460 may be any DC voltage source suitable for providing a voltage to the multi-stage single-ended amplifier input port 403 .

[0039] like Figure 4As shown in , the second stage single-ended amplifier 404 includes an output PMOSFET transistor 451 and an output NMOSFET transistor 452. The output PMOSFET transistor 451 is connected to the normal operation switch 407C at the drain terminal, and the output NMOSFET transistor 452 is connected to the normal operation switch 407D at the source terminal. Both the normal operation switch 407C and the normal operation switch 407D are connected to the switch 406C. When closed, the switch 406C is connected to the ground signal 427 through the operation of the envelope detection circuit 208. In this regard, when the sensed voltage is lower than the multi-stage single-ended amplifier idle noise threshold, the envelope detection circuit 208 controls the switch 406C to electrically connect the switch 406C to the ground signal 427.

[0040] In one example, while switch 406C is connected to ground signal 427, envelope detection circuit 208 controls switch 406A and switch 406B. Switch 406A and switch 406B are used to reconfigure internal circuit nodes of first stage single-ended amplifier 402. For example, switch 406A is closed to connect voltage source 460 to the drain terminal of NMOSFET transistor 442. Switch 406B is closed to connect the drain terminal of PMOSFET transistor 441 to ground signal 427.

[0041] In addition, at the same time as the switch 406C is closed, the envelope detection circuit 208 controls the normal operation switch 407A, the normal operation switch 407B, the normal operation switch 407C, and the normal operation switch 407D. The normal operation switch 407C is opened to disconnect the drain terminal of the PMOSFET transistor 441 from the output port 411 of the second-stage single-ended amplifier 404. The normal operation switch 407D is opened to disconnect the drain terminal of the NMOSFET transistor 442 from the output port 411 of the second-stage single-ended amplifier 404.

[0042] Normal operation switch 407A is opened to disconnect the drain terminal of NMOSFET transistor 442 from the source terminal of PMOSFET transistor 441. Normal operation switch 407B is opened to disconnect the source terminal of NMOSFET transistor 442 from the drain terminal of PMOSFET transistor 441. In this regard, NMOSFET transistor 442 is reconfigured to be connected to the gate terminal of output NMOSFET transistor 452 of second single-ended amplifier 404, and node 432 of first stage single-ended amplifier 402 is reconfigured to be substantially equal to a single-ended replica bias voltage signal of approximately five-tenths of a volt (e.g., such as before opening normal operation switch 407C and normal operation switch 407D). In some examples, the single-ended amplifier replica bias voltage signal is substantially equal to the quiescent operating voltage of first stage single-ended amplifier 402.

[0043] The PMOSFET transistor 441 is reconfigured to connect the source terminal of the output PMOSFET transistor 451 of the second stage single-ended amplifier 404 to the gate terminal, and the node 431 of the first stage single-ended amplifier 402 is reconfigured to be substantially equal to the single-ended amplifier replica bias voltage signal of approximately seven-tenths of a volt (e.g., such as before the normal operation switch 407C and the normal operation switch 407D are opened). In some examples, the single-ended amplifier replica bias voltage signal is substantially equal to the quiescent operating voltage of the first stage single-ended amplifier 402.

[0044] In this regard, the envelope detection circuit 208 controls the normal operation switch 407A, the normal operation switch 407B, the normal operation switch 407C, and the normal operation switch 407D and the switches 406A, 406B, and 406A to electrically connect the output ports of the first stage single-ended amplifier 402 and the second stage single-ended amplifier 404 to the single-ended amplifier replica bias voltage signal when the sensed voltage is below the multi-stage single-ended amplifier idle threshold. In various examples, when the sensed voltage is below the multi-stage single-ended amplifier idle noise threshold, the envelope detection circuit 208 controls the plurality of switches to electrically connect the multi-stage single-ended amplifier input port 403 to the single-ended amplifier replica bias voltage signal. In other examples, when the sensed voltage is below the multi-stage single-ended amplifier idle noise threshold, the envelope detection circuit 208 controls the plurality of switches to electrically connect the multi-stage single-ended amplifier input port 403 to the ground signal 427.

[0045] Figure 5 5 is a flow chart illustrating a method 500 for operation of a noise reduction circuit according to an example of the present disclosure. The method 500 begins with the operation of step 502, supplying a multistage amplifier including a plurality of amplifier stages. In one example, the multistage amplifier may be implemented as a differential multistage amplifier. In another example, the multistage amplifier may be implemented as a single-ended multistage amplifier. In yet another example, the multistage amplifier may be implemented as one or more differential amplifier stages and one or more single-ended amplifier stages all connected in series.

[0046] The method 500 may also include an operation of setting a plurality of switches within the multi-stage amplifier (step 504). In one example, the plurality of switches may be coupled to an output of each of the plurality of amplifier stages. In another example, the plurality of switches may be coupled to one or more internal nodes and / or components of each of the plurality of amplifier stages.

[0047] The method 500 may also include an operation of sensing, by the envelope detection circuit, a voltage at an output of the multi-stage amplifier (step 506). In some examples, the voltage is sensed at an input of the multi-stage amplifier. In other examples, the voltage is sensed at an input and / or output of one or more amplifier stages of the multi-stage amplifier.

[0048] The method 500 may also include the following operation (step 508): in response to the sensed voltage, controlling the plurality of switches by the envelope detection circuit to electrically connect the output of each of the plurality of amplifier stages to a DC voltage signal substantially equal to a quiescent operating voltage of each of the plurality of amplifier stages.

[0049] In view of the present disclosure, it will be appreciated that a multi-stage amplifier 200 implemented in accordance with various examples set forth herein can provide noise reduction of a multi-stage amplifier audio output signal when an amplifier input low-level audio signal is detected. The multi-stage amplifier 200 includes a plurality of switches disposed within the multi-stage amplifier and coupled to an output of each of a plurality of amplifier stages. An envelope detection circuit is configured to sense an input voltage signal and control the plurality of switches to electrically connect an output of each of the plurality of amplifier stages to a DC voltage signal and / or reconfigure an internal operating voltage within the amplifier stage, all for providing improved low signal level noise reduction for improved audio amplifier performance.

[0050] In applicable situations, the various examples provided by the disclosure can be implemented using hardware, software, or a combination of hardware and software. In addition, in applicable situations, the various hardware components and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both, without departing from the spirit of the disclosure. In applicable situations, the various hardware components and / or software components set forth herein can be separated into subcomponents comprising software, hardware, or both, without departing from the scope of the disclosure. In addition, in applicable situations, it is expected that software components can be implemented as hardware components, and vice versa.

[0051] The foregoing disclosure is not intended to limit the present disclosure to the precise form disclosed or to the specific field of use. Therefore, it is contemplated that various alternative examples and / or modifications to the present disclosure (whether explicitly described or implied herein) are possible in light of the present disclosure. Having thus described examples of the present disclosure, one of ordinary skill in the art will recognize that changes may be made in form and detail without departing from the scope of the present disclosure. Therefore, the present disclosure is limited only by the claims.

Claims

1. A system for improving noise performance, comprising: A multi-stage amplifier, the multi-stage amplifier comprising at least a first-stage amplifier and a second-stage amplifier; a plurality of switches disposed within the multi-stage amplifier to configure the multi-stage amplifier; an envelope detection circuit configured to generate a control signal to control the multi-stage amplifier to a normal amplification mode or a mute state; wherein the multi-stage amplifier is adapted to amplify an input signal in the normal amplification mode; wherein the multi-stage amplifier is adapted to output a zero signal in the quiet state; as well as The internal amplification stages of the multi-stage amplifier are disabled in the mute state, and the output stage of each of the at least first stage amplifier and the second stage amplifier is electrically short-circuited and / or shorted to a fixed bias voltage in the mute state.

2. The system of claim 1, wherein at least one of the stages of the multi-stage amplifier is configured as a differential amplifier, and wherein outputs of internal amplifier stages of the differential amplifier are electrically shorted to each other in the mute state.

3. The system of claim 1 , wherein at least one of the stages of the multi-stage amplifier is configured as a single-ended amplifier, wherein an output of an internal amplifier stage of the single-ended amplifier is shorted to a fixed bias voltage in the mute state, and wherein the output of the multi-stage amplifier is electrically shorted to a ground signal in the mute state.

4. A system for improving noise performance, comprising: a multi-stage amplifier, the multi-stage amplifier comprising a plurality of amplifier stages; a plurality of switches disposed within the multi-stage amplifier and coupled to an output of each of the plurality of amplifier stages; An envelope detection circuit, the envelope detection circuit being adapted to: sensing a voltage at an output port of the multi-stage amplifier; as well as In response to the sensed voltage, the plurality of switches are controlled to electrically connect an output of each of the plurality of amplifier stages to a DC voltage signal substantially equal to a quiescent operating voltage of each of the plurality of amplifier stages.

5. The system of claim 4 , wherein the envelope detection circuit is adapted to control the plurality of switches in response to the sensed voltage being below an idle noise threshold of the multi-stage amplifier, and wherein at least one of the plurality of switches is coupled to an input port of the multi-stage amplifier, the multi-stage amplifier being operable to electrically connect the input port to the DC voltage signal by the envelope detection circuit.

6. The system of claim 4 , wherein the multi-stage amplifier is a multi-stage differential amplifier, the multi-stage differential amplifier comprising a plurality of differential amplifiers electrically coupled in series, wherein each of the plurality of differential amplifiers comprises a differential output port pair, the differential output port pair comprising an inverting output port and a non-inverting output port, and wherein the envelope detection circuit is adapted to control the plurality of switches to electrically connect the inverting output port of each of the plurality of differential amplifiers to the non-inverting output port when the sensed voltage is below an idle noise threshold of the multi-stage differential amplifier.

7. The system of claim 6, further comprising a differential amplifier replica bias voltage signal configured to be substantially equal to the quiescent operating voltage, wherein the envelope detection circuit is adapted to control the plurality of switches to electrically connect the differential amplifier replica bias voltage signal to each input of the differential input pair of the multi-stage differential amplifier when the sensed voltage is below an idle noise threshold of the multi-stage differential amplifier.

8. The system of claim 7, wherein the envelope detection circuit is adapted to control the plurality of switches to electrically connect the differential amplifier replica bias voltage signal to each output of the differential output pair of the multi-stage differential amplifier when the sensed voltage is below an idle noise threshold of the multi-stage differential amplifier.

9. The system of claim 7, wherein the envelope detection circuit is adapted to control the plurality of switches to electrically short the pair of differential input ports of the multi-stage differential amplifier to each other when the sensed voltage is below an idle noise threshold of the multi-stage differential amplifier.

10. The system of claim 4, wherein the multi-stage amplifier is a multi-stage single-ended amplifier comprising a plurality of single-ended amplifiers electrically coupled in series.

11. The system of claim 10, further comprising a single-ended amplifier replica bias voltage signal configured to be substantially equal to the quiescent operating voltage, wherein the envelope detection circuit is adapted to control the plurality of switches to electrically connect the output port of the single-ended amplifier to the single-ended amplifier replica bias voltage signal when the sensed voltage is below a multi-stage single-ended amplifier idle noise threshold.

12. The system of claim 11, wherein the envelope detection circuit is adapted to control the plurality of switches to electrically connect the multi-stage single-ended amplifier input port to the single-ended amplifier replica bias voltage signal when the sensed voltage is below a multi-stage single-ended amplifier idle noise threshold.

13. The system of claim 12, wherein the envelope detection circuit is adapted to control the plurality of switches to electrically connect the multi-stage single-ended amplifier input port to a ground signal when the sensed voltage is below a multi-stage single-ended amplifier idle noise threshold.

14. A method for improving noise performance, comprising: supplying a multi-stage amplifier comprising a plurality of amplifier stages; disposing a plurality of switches within the multi-stage amplifier and coupled to an output of each of the plurality of amplifier stages; sensing a voltage at an output port of the multi-stage amplifier by an envelope detection circuit; as well as In response to the sensed voltage, the plurality of switches are controlled by the envelope detection circuit to electrically connect an output of each of the plurality of amplifier stages to a DC voltage signal substantially equal to a quiescent operating voltage of each of the plurality of amplifier stages.

15. The method of claim 14, wherein the controlling further comprises controlling the plurality of switches when the sensed voltage is below a multi-stage amplifier idle noise threshold.

16. The method of claim 14, wherein the multi-stage amplifier is a multi-stage differential amplifier, the multi-stage differential amplifier comprising a plurality of differential amplifiers electrically coupled in series, and wherein each of the plurality of differential amplifiers comprises a differential output port pair, the differential output port pair comprising an inverting output port and a non-inverting output port, the method further comprising controlling the plurality of switches to electrically connect the inverting output port of each of the plurality of differential amplifiers to the non-inverting output port when the sensed voltage is lower than an idle noise threshold of the multi-stage differential amplifier.

17. The method of claim 16, further comprising a differential amplifier replica bias voltage signal, the differential amplifier replica bias voltage signal being configured to be substantially equal to the quiescent operating voltage, the method further comprising: controlling the plurality of switches to electrically connect the differential amplifier replica bias voltage signal to each input of a differential input pair of the multi-stage differential amplifier when the sensed voltage is below an idle noise threshold of the multi-stage differential amplifier; as well as When the sensed voltage is below an idle noise threshold of the multi-stage differential amplifier, the plurality of switches are controlled to electrically connect the differential amplifier replica bias voltage signal to each output of a differential output pair of the multi-stage differential amplifier.

18. The method of claim 16, further comprising controlling the plurality of switches to electrically short the differential input pair of the multi-stage differential amplifier to each other when the sensed voltage is below an idle noise threshold of the multi-stage differential amplifier.

19. The method of claim 14, wherein the multi-stage amplifier is a multi-stage single-ended amplifier, the multi-stage single-ended amplifier comprising a plurality of single-ended amplifiers electrically coupled in series, and further comprising a single-ended amplifier replica bias voltage signal configured to be substantially equal to the quiescent operating voltage, the method further comprising: When the sensed voltage is lower than a multi-stage single-ended amplifier idle noise threshold, electrically connecting the output ports of the plurality of single-ended amplifiers to the single-ended amplifier replica bias voltage signal; as well as When the sensed voltage is below the multi-stage single-ended amplifier idle noise threshold, the multi-stage single-ended amplifier input port is electrically connected to the single-ended amplifier replica bias voltage signal.

20. The method of claim 19, further comprising electrically connecting the multi-stage single-ended amplifier input port to a ground signal when the sensed voltage is below a multi-stage single-ended amplifier idle noise threshold.

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