Display substrate, display device

Abstract

The present disclosure provides a display substrate, which includes a display area and a capacitance compensation area. A first edge of the display area is a curve, and the capacitance compensation area is arranged along the first edge; a plurality of first gate lines, and the plurality of first gate lines extend in a first direction in the display area and pass through the capacitance compensation area. A shape of a portion of the first gate line located in the capacitance compensation area matches a shape of the first edge; a plurality of data lines, and the plurality of data lines extend in a second direction in the display area, and the first direction intersects with the second direction. The display substrate further includes: a plurality of capacitance compensation lines, and the plurality of capacitance compensation lines are arranged in the capacitance compensation area and extend along the second direction. Each data line corresponds to a capacitance compensation line, and the capacitance compensation line is electrically connected to the corresponding data line. The present disclosure further provides a display device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a display substrate and a display device. Background Art

[0002] In order to pursue a large screen-to-body ratio, more and more display devices are designed with a special-shaped (Notch) area above the screen to prevent cameras and various sensors. The lack of pixels in the Notch area results in a smaller capacitance in the Notch area than in the normal area, and the capacitance difference causes a difference in the display effect between the Notch area and the normal area. To reduce the display effect difference between the Notch area and the normal area, it is necessary to perform capacitance compensation on the data lines (Source) in the Notch area.

[0003] In some related technologies, when performing capacitance compensation on the data lines in the Notch area, the wiring method is relatively complex and the capacitance compensation effect is poor. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate. The display substrate includes a display area and a capacitance compensation area. A first edge of the display area is a curve, and the capacitance compensation area is arranged along the first edge; a plurality of first gate lines, the plurality of first gate lines extend in a first direction in the display area and pass through the capacitance compensation area, and a shape of a portion of the first gate line located in the capacitance compensation area matches a shape of the first edge; a plurality of data lines, the plurality of data lines extend in a second direction in the display area, the first direction intersects the second direction, and the display substrate further includes:

[0006] A plurality of capacitance compensation lines, the plurality of capacitance compensation lines are arranged in the capacitance compensation area and extend along the second direction, each data line corresponds to a capacitance compensation line, and the capacitance compensation line is electrically connected to the corresponding data line.

[0007] In some embodiments, the display area includes multiple columns of pixel units, each capacitance compensation line corresponds to one column of pixel units, a width of the capacitance compensation line in the first direction is positively correlated with a number of missing pixel units in the corresponding column; a number of missing pixel units in any column is a difference between a theoretical number of pixel units and a number of pixel units in that column.

[0008] In some embodiments, the capacitance compensation region includes a transition region and a first compensation region and a second compensation region located on both sides of the transition region, and the bending directions of the portions of the first edge corresponding to the first compensation region and the second compensation region are opposite;

[0009] The width of the capacitance compensation line in the first direction in the first compensation region and the width of the capacitance compensation line in the first direction in the second compensation region are not less than the width of the capacitance compensation line in the first direction in the transition region.

[0010] In some embodiments, the display region includes multiple columns of pixel units, and each capacitance compensation line corresponds to one column of pixel units; the portion of the first edge corresponding to the first compensation region protrudes relative to the display region, and the portion of the first edge corresponding to the second compensation region is concave relative to the display region;

[0011] The width of the capacitance compensation line in the first direction in the first compensation region is the same as the width of the capacitance compensation line in the first direction in the transition region;

[0012] The width of the capacitance compensation line in the first direction in the second compensation region is positively correlated with the number of missing pixel units in the corresponding column; the number of missing pixel units in any column is the difference between the theoretical number of pixel units and the number of pixel units in that column.

[0013] In some embodiments, in the second compensation region, the difference between the width of the capacitance compensation line in the first direction in the column corresponding to the missing n + l + 1 pixel units and the width of the capacitance compensation line in the first direction in the column corresponding to the missing n + l pixel units and the difference between the width of the capacitance compensation line in the first direction in the column corresponding to the missing n + l pixel units and the width of the capacitance compensation line in the first direction in the column corresponding to the missing n + l - 1 pixel units is a first predetermined value; where l is the minimum value of the missing pixel units in the corresponding column in the second compensation region, and n is a natural number.

[0014] In some embodiments, the width of the capacitance compensation line in the first direction in the column corresponding to the missing n + l pixel units satisfies the following formula:

[0015]

[0016]

[0017] Where r nw is the width of the capacitance compensation line corresponding to the column lacking n pixel units in the first direction; r1 is the width of the capacitance compensation line corresponding to the column lacking l pixel units in the first direction; m is the maximum value of the pixel units lacking in the corresponding columns in the second compensation area.

[0018] In some embodiments, in the second compensation area, the difference between the width of the capacitance compensation line corresponding to the column lacking n + l + 1 pixel units in the first direction and the width of the capacitance compensation line corresponding to the column lacking n + l pixel units in the first direction is equal to the difference between the width of the capacitance compensation line corresponding to the column lacking n + l pixel units in the first direction and the width of the capacitance compensation line corresponding to the column lacking n + l - 1 pixel units in the first direction; where l is the minimum value of the pixel units lacking in the corresponding columns in the second compensation area, and n is a natural number.

[0019] In some embodiments, the display substrate further includes an electrostatic discharge connection line and a plurality of touch signal lines;

[0020] The electrostatic discharge connection line is disposed in the capacitance compensation area, and the shape of the electrostatic discharge connection line matches the first edge;

[0021] A plurality of the touch signal lines extend from the display area to the capacitance compensation area along the second direction, and the touch signal lines are electrically connected to the electrostatic discharge connection line.

[0022] In some embodiments, the capacitance compensation area includes a plurality of opening areas defined by a plurality of the first gate lines and a plurality of the capacitance compensation lines. In each opening area, the ratio of the total area of the first gate line and the capacitance compensation line to the area of the opening area is not greater than 1 / 4.

[0023] In a second aspect, an embodiment of the present disclosure provides a display device, including an auxiliary component and any one of the display substrates in the first aspect of the embodiments of the present disclosure. The auxiliary component and the display area in the display substrate are respectively located on both sides of the capacitance compensation area in the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure, and do not constitute a limitation to the present disclosure. By describing the detailed exemplary embodiments with reference to the drawings, the above and other features and advantages will become more obvious to those skilled in the art. In the drawings:

[0025] Figure 1 is a schematic diagram of a linear compensation method;

[0026] Figure 2It is a schematic diagram of a display substrate in an embodiment of the present disclosure;

[0027] Figure 3 It is a schematic diagram of a compensation space for performing capacitance compensation on data lines in a Notch region in an embodiment of the present disclosure;

[0028] Figure 4 It is a schematic diagram of a capacitance compensation region of another display substrate in an embodiment of the present disclosure;

[0029] Figure 5A It is a schematic diagram showing the relationship between the relative compensation space and the number of missing pixel units in the present disclosure implementation;

[0030] Figure 5B It is a schematic diagram showing the relationship between the relative compensation space and the number of missing pixel units in the linear compensation method;

[0031] Figure 6A It is a schematic diagram showing the relationship between the ideal compensation amount and the number of missing pixel units;

[0032] Figure 6B It is a schematic diagram showing the relationship between the capacitance compensation amount and the number of missing pixel units in the linear compensation method;

[0033] Figure 6C It is a schematic diagram showing the relationship between the capacitance compensation amount and the number of missing pixel units in an embodiment of the present disclosure;

[0034] Figure 6D It is a schematic diagram showing the relationship between the capacitance compensation amount and the number of missing pixel units of another kind in an embodiment of the present disclosure. Detailed implementation manners

[0035] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the display substrate and display device provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0036] In the following, example embodiments will be described more fully with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0037] Without conflict, the various embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0038] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] The terms used herein are for describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms "comprises" and / or "consists of" are used in this specification, the specified features, integers, steps, operations, elements, and / or components are present, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0040] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present disclosure. Accordingly, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Thus, the embodiments are not limited to the embodiments shown in the figures, but include modifications of configurations formed based on manufacturing processes. Therefore, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be restrictive.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0042] Figure 1 is a schematic diagram of a wiring method for capacitively compensating data lines in the Notch region in some related technologies. As Figure 1 shown, the routing direction of the data line 04 for capacitive compensation in the Notch region 02 changes with the change of the compensation position, and the routing direction of the data line for capacitive compensation at each position is perpendicular to the routing direction of the gate line (Gate) 03, that is, the included angle θ0 between the gate line 03 and the data line 04 is 90°. In Figure 1 where the width of the gate line 03 is a and the width of the data line 04 is b, the overlapping area of the gate line 03 and the data line 04 at each position is S0 = a × b. As Figure 1As shown in the figure, the gate line 03 runs along the x direction and passes through the Notch region 02. The more pixels are missing in the Notch region 02 compared to the normal region, the more gate lines 03 pass through. For example, the number of missing pixels at C is greater than that at B and A, and the number of gate lines 03 passing through C is greater than that passing through B and A. Since the overlapping area between the gate line 03 and the data line 04 at each position is S0 = a × b, the above capacitance compensation for the data lines in the Notch region is a linear compensation. The inventors of the present disclosure have found that the wiring method in which the wiring directions of the data lines for capacitance compensation at each position are perpendicular to the wiring direction of the gate lines is relatively complex, and the capacitance compensation amount is small, with a large difference from the ideal compensation amount, and the improvement of the display effect in the Notch region is not obvious; moreover, the compensation space is affected by the compensation position, which in turn affects the ultraviolet (UV) transmittance and is likely to have an adverse impact on the production of the display substrate.

[0043] In view of this, in a first aspect, referring to Figure 2 , an embodiment of the present disclosure provides a display substrate, which includes a display area 1 and a capacitance compensation area 2. The first edge 11 of the display area 1 is a curve, and the capacitance compensation area 2 is arranged along the first edge 11; a plurality of first gate lines 3, the plurality of first gate lines 3 extend along the first direction x in the display area 1 and pass through the capacitance compensation area 2, and the shape of the part of the first gate line 3 located in the capacitance compensation area 2 matches the shape of the first edge 11; a plurality of data lines 4, the plurality of data lines 4 extend along the second direction y in the display area 1, the first direction x intersects with the second direction y, and the display substrate further includes:

[0044] A plurality of capacitance compensation lines 5, the plurality of capacitance compensation lines 5 are arranged in the capacitance compensation area 2 and extend along the second direction y. Each data line 4 corresponds to a capacitance compensation line 5, and the capacitance compensation line 5 is electrically connected to the corresponding data line 4.

[0045] As Figure 2 shown, the wiring direction of the capacitance compensation line 5 for capacitance compensation at each position in the Notch region is consistent with the second direction y, and the included angle between the wiring direction of the capacitance compensation line 5 for capacitance compensation and the wiring direction of the first gate line 3 changes with the change of the compensation position. Figure 2 The width of the first gate line 3 in is a, the width of the capacitance compensation line 5 is b, the included angle between the wiring direction of the capacitance compensation line 5 at any compensation position and the wiring direction of the first gate line 3 is θ1, and θ1 is less than or equal to 90°. The overlapping area between the capacitance compensation line 5 and the first gate line 3

[0046] It should be noted that, in the embodiment of the present disclosure, the compensation space for capacitance compensation of the data lines in the Notch area refers to the spacing between adjacent data lines or capacitance compensation lines 5 used for capacitance compensation. Figure 3 FIG. 1 is a schematic diagram of a compensation space for performing capacitance compensation on a data line in a Notch area in an embodiment of the present disclosure. Figure 3 As shown, in the linear compensation method, the compensation space is c; in the embodiment of the present disclosure, the compensation space is d, c=d×sinθ1, so d≥c. Figure 5A A schematic diagram of the relationship between the relative compensation space and the number of missing pixel units in the implementation of the present disclosure, wherein the vertical axis is the relative compensation space and the horizontal axis is the number of missing pixel units; Figure 5B It is a schematic diagram of the relationship between the relative compensation space and the number of missing pixel units in the linear compensation method, wherein the vertical axis is the relative compensation space and the horizontal axis is the number of missing pixel units. It can be seen that in the display substrate provided by the embodiment of the present disclosure, compared with the linear capacitance compensation method, the compensation space is increased, and the compensation space of each compensation position remains consistent. The increase in compensation space is conducive to further increasing the capacitance compensation amount of the data line in the Notch area by increasing the width of the capacitance compensation line 5, while ensuring the UV transmittance, which is conducive to curing the sealant during the display substrate manufacturing process and improving the reliability of the display substrate.

[0047] The embodiments of the present disclosure do not impose any special limitation on the width of the capacitance compensation line.

[0048] In some embodiments, the display area 1 includes multiple columns of pixel units, each capacitance compensation line 5 corresponds to a column of pixel units, and the width of the capacitance compensation line 5 in the first direction x is positively correlated with the number of missing pixel units in the corresponding column; the number of missing pixel units in any column is the difference between the theoretical number of pixel units and the number of pixel units in the column.

[0049] It should be noted that the theoretical pixel unit data is the number of pixel units in a column of pixel units in the normal area, and the missing pixel unit number is the number of pixel units missing from a column of pixel units in the Notch area relative to a column of pixel units in the normal area.

[0050] In the embodiment of the present disclosure, the more pixel units are missing in any column, the greater the difference between the capacitance of the data line in the Notch area and the capacitance of the data line in the normal area. The width of the capacitance compensation line 5 in the first direction x is set to be positively correlated with the number of pixel units missing in the corresponding column, so that the capacitance of each data line 4 in the display substrate can be kept consistent, thereby effectively reducing the difference in display effects at different locations on the display substrate.

[0051] In some embodiments, Figure 2As shown, the capacitance compensation region 2 includes a transition region 21 and a first compensation region 22 and a second compensation region 23 located on both sides of the transition region 21. The bending directions of the portions of the first edge 11 corresponding to the first compensation region 22 and the portions corresponding to the second compensation region 23 are opposite;

[0052] The width of the capacitance compensation line 5 in the first compensation region 22 in the first direction x and the width of the capacitance compensation line 5 in the second compensation region 23 in the first direction x are not less than the width of the capacitance compensation line 5 in the transition region 21 in the first direction x.

[0053] It should be noted that the transition region 21 corresponds to the inflection point position of the first edge 11, and the bending direction of the first edge 11 changes at the inflection point position. When the widths of the gate line 3 and the capacitance compensation line 5 in the transition region 21, the first compensation region 22, and the second compensation region 23 are the same, the UV transmittance of the transition region 21 is the smallest. Therefore, the width of the capacitance compensation line 5 in the first compensation region 22 in the first direction x and the width of the capacitance compensation line 5 in the second compensation region 23 in the first direction x are not less than the width of the capacitance compensation line 5 in the transition region 21 in the first direction x, which can increase the capacitance compensation amount for the data line in the Notch region by increasing the width of the capacitance compensation line 5 while ensuring the UV transmittance everywhere in the capacitance compensation region 2.

[0054] In the embodiments of the present disclosure, there is no special limitation on the width of the capacitance compensation line 5 in the first compensation region 22 in the first direction x and the width of the capacitance compensation line 5 in the second compensation region 23 in the first direction x. In some embodiments, the width of the capacitance compensation line 5 in the first compensation region 22 in the first direction x is equal to the width of the capacitance compensation line 5 in the second compensation region 23 in the first direction x. For example, both are the width of the capacitance compensation line 5 in the transition region 21 in the first direction x.

[0055] In some embodiments, the display region 1 includes multiple columns of pixel units, and each capacitance compensation line 5 corresponds to one column of pixel units; the portion of the first edge 11 corresponding to the first compensation region 22 protrudes relative to the display region 1, and the portion of the first edge 11 corresponding to the second compensation region 23 is concave relative to the display region 1;

[0056] The width of the capacitance compensation line 5 in the first compensation region 22 in the first direction x is the same as the width of the capacitance compensation line 5 in the transition region 21 in the first direction x;

[0057] The width of the capacitance compensation line 5 in the second compensation region 23 in the first direction x is positively correlated with the number of missing pixel units in the corresponding column; the number of missing pixel units in any column is the difference between the theoretical number of pixel units and the number of pixel units in that column.

[0058] It should be noted that, in the embodiments of the present disclosure, the portion of the first edge 11 corresponding to the first compensation region 22 protrudes relative to the display region 1, and in the first compensation region 22, the change in the number of missing pixel units in each column is small. By setting the width of the capacitance compensation line 5 in the first compensation region 22 to be the same as the width of the capacitance compensation line 5 in the transition region 21, it can not only meet the requirement of consistent capacitance compensation amount for the data line, but also ensure the UV transmittance of the first compensation region 22.

[0059] The embodiments of the present disclosure do not make special limitations on the specific relationship between the width of the capacitance compensation line 5 in the second compensation region 23 in the first direction x and the number of missing pixel units in the corresponding column. In some embodiments, as the number of missing pixel units increases, the width of the capacitance compensation line 5 in the first direction x increases in an arithmetic progression.

[0060] Correspondingly, in some embodiments, in the second compensation region 23, the difference between the width of the capacitance compensation line in the first direction x of the column corresponding to the missing n + l + 1 pixel units and the width of the capacitance compensation line in the first direction x of the column corresponding to the missing n + l pixel units, and the difference between the width of the capacitance compensation line in the first direction x of the column corresponding to the missing n + l pixel units and the width of the capacitance compensation line in the first direction x of the column corresponding to the missing n + l - 1 pixel units is a first predetermined value; where l is the minimum value of the missing pixel units in the corresponding column in the second compensation region 23, and n is a natural number.

[0061] In some embodiments, the width of the capacitance compensation line in the first direction x of the column corresponding to the missing n + l pixel units satisfies the following formula:

[0062]

[0063]

[0064] where r n is the width of the capacitance compensation line in the first direction x of the column corresponding to the missing n pixel units; r1 is the width of the capacitance compensation line in the first direction x of the column corresponding to the missing l pixel units; m is the maximum value of the missing pixel units in the corresponding column in the second compensation region.

[0065] In some embodiments, in the second compensation region, the difference in the width in the first direction between the capacitance compensation lines corresponding to the columns lacking n + l + 1 pixel units and the capacitance compensation lines corresponding to the columns lacking n + l pixel units is equal to the difference in the width in the first direction between the capacitance compensation lines corresponding to the columns lacking n + l pixel units and the capacitance compensation lines corresponding to the columns lacking n + l - 1 pixel units; where l is the minimum value of the pixel units lacking in the corresponding columns in the second compensation region, and n is a natural number.

[0066] Figure 6A It is a schematic diagram of the relationship between the ideal compensation amount and the number of missing pixel units; Figure 6B It is a schematic diagram of the relationship between the capacitance compensation amount and the number of missing pixel units in the linear compensation method; Figure 6C It is a schematic diagram of the relationship between the capacitance compensation amount and the number of missing pixel units when the widths of the capacitance compensation lines 5 in the first transition region 22 and the second transition region 23 are set to the widths of the capacitance compensation lines 5 in the transition region 21 in the embodiments of the present disclosure; Figure 6D It is a schematic diagram of the relationship between the capacitance compensation amount and the number of missing pixel units when the widths of the capacitance compensation lines 5 in the first transition region 22 are set to the widths of the capacitance compensation lines 5 in the transition region 21 and the widths of the capacitance compensation lines 5 in the second transition region 23 are increased in an arithmetic progression in the embodiments of the present disclosure. Wherein, the vertical axis is the relative capacitance compensation amount, and the horizontal axis is the number of missing pixel units. As can be seen from Figures 6A to 6D It can be seen that in the display substrate provided by the embodiments of the present disclosure, the capacitance compensation amount is greater than the capacitance compensation amount in the linear compensation method.

[0067] In some embodiments, as Figure 4 shown, the display substrate further includes an electrostatic discharge connection line 6 and a plurality of touch signal lines 7;

[0068] The electrostatic discharge connection line 6 is disposed in the capacitance compensation region 2, and the shape of the electrostatic discharge connection line 6 matches the first edge 11;

[0069] A plurality of touch signal lines 7 extend from the display region 1 to the capacitance compensation region 2 along the second direction y, and the touch signal lines 7 are electrically connected to the electrostatic discharge connection line 6.

[0070] In some embodiments, the capacitance compensation region 2 includes a plurality of opening regions defined by a plurality of first gate lines 3 and a plurality of capacitance compensation lines 5. In each of the opening regions, the total area of the first gate lines 3 and the capacitance compensation lines 5 is not greater than 1 / 4 of the area of the opening region.

[0071] In each of the opening regions, the ratio of the total area of the first gate line 3 and the capacitance compensation line 5 to the area of the opening region is not greater than 1 / 4, which can ensure that the UV transmittance of the capacitance compensation region 2 is not less than 25%, facilitating the curing of the sealant during the production process of the display substrate and improving the reliability of the display substrate.

[0072] In a second aspect, an embodiment of the present disclosure provides a display device, including an auxiliary component and any one of the display substrates described in the first aspect, where the auxiliary component and the display region in the display substrate are respectively located on both sides of the capacitance compensation region in the display substrate.

[0073] Example embodiments have been disclosed herein, and although specific terms have been employed, they are used for and should be construed only for general descriptive purposes and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly specified, features, characteristics, and / or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various forms and details may be changed without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A display substrate, the display substrate includes a display area and a capacitance compensation area, a first edge of the display area is a curve, and the capacitance compensation area is disposed along the first edge; a plurality of first gate lines, the plurality of first gate lines extend in a first direction in the display area and pass through the capacitance compensation area, and a shape of a portion of the first gate line located in the capacitance compensation area matches a shape of the first edge; A plurality of data lines, and the plurality of data lines extend in a second direction in the display area, and the first direction intersects with the second direction. It is characterized in that The display substrate further includes: A plurality of capacitance compensation lines, and the plurality of capacitance compensation lines are disposed in the capacitance compensation area and extend in the second direction. Each data line corresponds to a capacitance compensation line, and the capacitance compensation line is electrically connected to the corresponding data line; And at any compensation position in the capacitance compensation area, the included angle between the extending direction of the capacitance compensation line and the extending direction of the first gate line is less than 90°, and the included angles between the extending directions of the capacitance compensation lines at at least some compensation positions and the extending direction of the first gate line are different; The display area includes multiple columns of pixel units. Each capacitance compensation line corresponds to one column of pixel units. The width of the capacitance compensation line in the first direction is positively correlated with the number of missing pixel units in the corresponding column; the number of missing pixel units in any column is the difference between the theoretical number of pixel units and the number of pixel units in that column; The capacitance compensation area includes a plurality of opening areas defined by a plurality of the first gate lines and a plurality of the capacitance compensation lines. In each opening area, the ratio of the total area of the first gate line and the capacitance compensation line to the area of the opening area is not greater than 1 / 4.

2. The display substrate according to claim 1, characterized in that The capacitance compensation area includes a transition area and a first compensation area and a second compensation area located on both sides of the transition area. The bending directions of the part of the first edge corresponding to the first compensation area and the part corresponding to the second compensation area are opposite; The width of the capacitance compensation line in the first direction in the first compensation area and the width of the capacitance compensation line in the first direction in the second compensation area are not less than the width of the capacitance compensation line in the first direction in the transition area.

3. The display substrate according to claim 2, wherein The display area includes multiple columns of pixel units. Each capacitance compensation line corresponds to one column of pixel units; the part of the first edge corresponding to the first compensation area protrudes relative to the display area, and the part of the first edge corresponding to the second compensation area is concave relative to the display area; The width of the capacitance compensation line in the first direction in the first compensation area is the same as the width of the capacitance compensation line in the first direction in the transition area; The width of the capacitance compensation line in the first direction in the second compensation area is positively correlated with the number of missing pixel units in the corresponding column; the number of missing pixel units in any column is the difference between the theoretical number of pixel units and the number of pixel units in that column.

4. The display substrate according to claim 3, wherein, In the second compensation area, the difference between the width of the capacitance compensation line in the first direction corresponding to the column missing n + l + 1 pixel units and the width of the capacitance compensation line in the first direction corresponding to the column missing n + l pixel units and the difference between the width of the capacitance compensation line in the first direction corresponding to the column missing n + l pixel units and the width of the capacitance compensation line in the first direction corresponding to the column missing n + l - 1 pixel units is a first predetermined value; wherein, l is the minimum value of the missing pixel units in the corresponding column in the second compensation area, and n is a natural number.

5. The display substrate according to claim 4, wherein, The width of the capacitance compensation line corresponding to the column lacking n + l pixel units in the first direction satisfies the following formula: Among them, r n is the width of the capacitance compensation line corresponding to the column missing n pixel units in the first direction; r1 is the width of the capacitance compensation line corresponding to the column missing l pixel units in the first direction; m is the maximum value of the pixel units missing in the corresponding column in the second compensation area.

6. The display substrate according to claim 3, wherein In the second compensation region, the difference between the width of the capacitance compensation line corresponding to the column lacking n + l + 1 pixel units in the first direction and the width of the capacitance compensation line corresponding to the column lacking n + l pixel units in the first direction is equal to the difference between the width of the capacitance compensation line corresponding to the column lacking n + l pixel units in the first direction and the width of the capacitance compensation line corresponding to the column lacking n + l - 1 pixel units in the first direction; where l is the minimum value of the pixel units lacking in the corresponding column in the second compensation region, and n is a natural number.

7. The display substrate according to claim 1, wherein The display substrate further includes an electrostatic discharge connection line and a plurality of touch signal lines; The electrostatic discharge connection line is disposed in the capacitance compensation region, and the shape of the electrostatic discharge connection line matches the first edge; A plurality of the touch signal lines extend from the display region to the capacitance compensation region along the second direction, and the touch signal lines are electrically connected to the electrostatic discharge connection line.

8. A display device, comprising an auxiliary component and the display substrate according to any one of claims 1 to 7, wherein the auxiliary component and the display region in the display substrate are respectively located on both sides of the capacitance compensation region in the display substrate.

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