Chip packaging structure and chip packaging structure and forming method thereof

Abstract

The present disclosure provides a chip packaging structure and a method for forming the chip packaging structure. The method for forming the chip packaging structure includes providing a circuit substrate, forming a conductive adhesive layer above a polymer layer and a conductive pad, forming a nickel layer above the conductive adhesive layer, and bonding a chip to the circuit substrate through a conductive bump. The circuit substrate includes a substrate, a conductive pad, and a polymer layer, the polymer layer is located above the substrate and the conductive pad, and the polymer layer has a first opening exposing the conductive pad. The conductive adhesive layer directly contacts and conformally covers the polymer layer and the conductive pad. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are formed of different materials. The conductive bump is located between the nickel layer and the chip.

Description

Technical Field

[0001] The present disclosure relates to a chip packaging structure and a method for forming the same. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and using photolithography processes to pattern the various material layers to form circuit components and elements on the material layers.

[0003] Typically, dozens or hundreds of integrated circuits are manufactured on a single semiconductor wafer. The integrated circuits are sawed along the cutting paths to singulate the die. The individual dies are then packaged separately to form a package. The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, so that more components can be integrated into a given area. However, as the feature size continues to decrease, it becomes more difficult to continue the process. Therefore, how to form a reliable package of electronic components with high integration density is a challenge. Summary of the invention

[0004] The purpose of the present disclosure is to provide a chip packaging structure and a method for forming the chip packaging structure to solve at least one of the above problems.

[0005] Some embodiments of the present disclosure provide a method for forming a chip packaging structure, including providing a circuit substrate, forming a conductive adhesive layer above a polymer layer and a conductive pad, forming a nickel layer above the conductive adhesive layer, and bonding a chip to the circuit substrate through a conductive bump. The circuit substrate includes a substrate, a conductive pad, and a polymer layer, the polymer layer is located above the substrate and the conductive pad, and the polymer layer has a first opening exposing the conductive pad. The conductive adhesive layer directly contacts and conformally covers the polymer layer and the conductive pad. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are formed of different materials. The conductive bump is located between the nickel layer and the chip.

[0006] Some embodiments of the present disclosure provide a method for forming a chip packaging structure, including providing a circuit substrate, the circuit substrate including a substrate, a first conductive pad and a first polymer layer, the first conductive pad is located above the first surface of the substrate, the first polymer layer is located above the first surface and the first conductive pad, the first polymer layer has a first opening, and the first opening exposes the first conductive pad; forming a first conductive adhesive layer above the first polymer layer and the first conductive pad, the first conductive adhesive layer directly contacts the first polymer layer and the first conductive pad; forming a solder structure above the first conductive adhesive layer; and bonding the chip to the circuit substrate through an under-bump metallurgical layer and a first conductive bump, the under-bump metallurgical layer being located between the chip and the first conductive bump, the conductive bump being connected to the first conductive adhesive layer and the under-bump metallurgical layer, the solder structure forming a portion of the first conductive bump, and the first thickness of the under-bump metallurgical layer being substantially equal to the second thickness of the first conductive adhesive material layer.

[0007] Some embodiments of the present disclosure provide a chip packaging structure, including a circuit substrate, a conductive adhesive layer, a nickel layer, a chip and a conductive bump. The circuit substrate includes a substrate, a first conductive pad, a second conductive pad and a polymer layer, the first conductive pad and the second conductive pad are respectively located above the first surface and the second surface of the substrate, the first conductive pad is narrower than the second conductive pad, and the polymer layer is located on the first surface and above the first conductive pad. The conductive adhesive layer passes through the polymer layer and is located above the first conductive pad, wherein the conductive adhesive layer directly contacts the polymer layer and the first conductive pad. The nickel layer is located above the conductive adhesive layer, wherein the nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are formed of different materials. The chip is located above the circuit substrate. The conductive bump is located between the nickel layer and the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not shown in proportion and are only used for illustration. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0009] Figures 1A to 1E are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0010] Figure 2 is a cross-sectional view of stages of a process for forming a chip package structure according to some embodiments.

[0011] FIG. 3A to FIG. 3C is a cross-sectional view of various stages of a process for forming a chip package structure according to some embodiments.

[0012] Figure 4is a cross-sectional view of stages of a process for forming a chip package structure according to some embodiments.

[0013] FIG. 5A to FIG. 5D are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0014] FIG. 6A to FIG. 6E are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0015] 7A to 7C are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0016] FIG. 8A to FIG. 8D are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0017] 9A to 9C are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0018] FIG. 10A to FIG. 10C are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0019] FIG. 11A to FIG. 11C are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0020] The reference numerals are as follows:

[0021] 110: Circuit board

[0022] 111:Substrate

[0023] 111a,111b: Surface

[0024] 112: Substrate through hole

[0025] 113a,113b,114a,114b,574: circuit layer

[0026] 115a,115b,515,578: Conductive pad

[0027] 115a1,118a1,142,922,932,1032: Top surface

[0028] 116a,116b,576: Guide hole

[0029] 117a, 117b: Insulation layer

[0030] 118a, 118b: polymer layer

[0031] 120,610: Conductive adhesive layer

[0032] 120a, 610a: conductive adhesive material layer

[0033] 122,124: Conductive layer

[0034] 122a, 124a: Material layer

[0035] 122b,124b,924,934,1034: Side wall

[0036] 124a1,132,322,516a,517a,622,812,1012,1112,P1,P2: Open

[0037] 130,310,320,620,710,810,910,1010,1110: Mask layer

[0038] 140,530a: Solder structure

[0039] 140a, 140b, 1150a: solder layer

[0040] 140c,1150: solder balls

[0041] 500,501,600,601,700,800,801,900,901,1000,1001,1100,1101: Chip packaging structure

[0042] 510: Chip

[0043] 511:Semiconductor substrate

[0044] 511a: front surface

[0045] 511b: rear surface

[0046] 512: Component

[0047] 513: Dielectric layer

[0048] 514:Internal connection layer

[0049] 516,572: Insulation layer

[0050] 517: Buffer layer

[0051] 520: Under-bump metallurgical layer

[0052] 530: Conductive bump

[0053] 540,541: Adhesive layer

[0054] 550: Heat sink cover

[0055] 560: Conductive bump

[0056] 570: Circuit board

[0057] 820,920,1020,1120: Nickel layer

[0058] 830,930,1030,1130: Palladium layer

[0059] 840,940,1140: Gold layer

[0060] 1022,1122: Groove

[0061] 1040: Covering layer

[0062] A: Cutting Road

[0063] T1, T2, T3, T4, T5, T6: thickness

[0064] U: Bottom filling layer

[0065] W1,W2,W3,W4: Width DETAILED DESCRIPTION

[0066] Many different implementation methods or examples are disclosed below to implement the different features of the provided subject matter. The following describes specific embodiments of the components and their arrangements to illustrate the present disclosure. Of course, these embodiments are only for illustration and should not be used to limit the scope of the present disclosure. For example, it is mentioned in the specification that the first characteristic component is formed above the second characteristic component, which includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which there are other features between the first characteristic component and the second characteristic component, that is, the first characteristic component and the second characteristic component are not in direct contact. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present disclosure and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0067] In addition, spatially related terms may be used, such as "below", "below", "down", "above", "upper" and similar terms. These spatially related terms are for the convenience of describing the relationship between one (some) element or feature and another (some) element or feature in the diagram. These spatially related terms are intended to cover different orientations of the device including the feature. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used therein will also be interpreted according to the orientation after the rotation. It should be understood that additional operations can be provided before, during, and after the above method, and for other embodiments of the above method, some of the described operations can be replaced or removed.

[0068] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during, and / or after the stages described in the embodiments. For different embodiments, some of the stages described may be replaced or removed. Additional features may be added to the semiconductor device structure. For different embodiments, some of the functions described below may be replaced or removed. Although some embodiments are discussed by using operations performed in a specific order, the operations may be performed in other logical orders.

[0069] Figures 1A to 1E is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 1A As shown, according to some embodiments, a circuit substrate 110 is provided. According to some embodiments, the circuit substrate 110 includes a substrate 111, a substrate through hole (or a plated through hole (PTH)) 112, a circuit layer 113a, a circuit layer 113b, a circuit layer 114a and a circuit layer 114b, a conductive pad 115a and a conductive pad 115b, a guide hole 116a and a guide hole 116b, an insulating layer 117a and an insulating layer 117b, and a polymer layer 118a and a polymer layer 118b.

[0070] According to some embodiments, the substrate 111 has a surface 111a and a surface 111b. According to some embodiments, the surface 111a is opposite to the surface 111b. In some embodiments, the substrate 111 is made of an insulating material, such as a fiber material, a polymer material (such as a polymer organic material), or a glass material. For example, the fiber material includes a glass fiber material.

[0071] In some other embodiments, according to some embodiments, the substrate 111 is made of a semiconductor material or a conductive material. The semiconductor material includes, for example, silicon or germanium. The conductive material includes, for example, a metal material.

[0072] According to some embodiments, through-substrate via 112 passes through substrate 111. According to some embodiments, wiring layer 113a and wiring layer 113b are formed over surface 111a and surface 111b, respectively. According to some embodiments, through-substrate via 112 electrically connects wiring layer 113a to wiring layer 113b.

[0073] According to some embodiments, if the substrate 111 is made of a semiconductor material or a conductive material, an insulating layer (not shown) is formed between the substrate 111 and the substrate through hole 112 and between the substrate 111 and the circuit layers 113a and 113b to electrically insulate the substrate 111 from the substrate through hole 112 and the circuit layers 113a and 113b.

[0074] According to some embodiments, a wiring layer 114a, a conductive pad 115a, a guide hole 116a, an insulating layer 117a, and a polymer layer 118a are formed on the surface 111a. According to some embodiments, the wiring layer 114a and the guide hole 116a are located in the insulating layer 117a. According to some embodiments, the conductive pad 115a is located above the insulating layer 117a. According to some embodiments, the guide hole 116a provides electrical connection between the wiring layer 113a and the wiring layer 114a and between the wiring layer 114a and the conductive pad 115a.

[0075] According to some embodiments, polymer layer 118a is formed over insulating layer 117a and conductive pad 115a. According to some embodiments, polymer layer 118a has openings P1. According to some embodiments, openings P1 respectively expose conductive pads 115a thereunder. According to some embodiments, polymer layer 118a partially covers conductive pad 115a.

[0076] According to some embodiments, the polymer layer 118a is a solder resist (SR) layer, an Ajinomoto build-up film (ABF) or a prepreg (PP). According to some embodiments, the solder resist layer is made of a solder resist material. According to some embodiments, the polymer layer 118a is made of any suitable polymer material, such as a resin or a polyimide.

[0077] According to some embodiments, a wiring layer 114b, a conductive pad 115b, a guide hole 116b, an insulating layer 117b, and a polymer layer 118b are formed above the surface 111b. According to some embodiments, the wiring layer 114b and the guide hole 116b are located in the insulating layer 117b. According to some embodiments, the conductive pad 115b is located above the insulating layer 117b. According to some embodiments, the guide hole 116b provides electrical connection between the wiring layer 113b and the wiring layer 114b and between the wiring layer 114b and the conductive pad 115b.

[0078] According to some embodiments, polymer layer 118b is formed over insulating layer 117b and conductive pad 115b. According to some embodiments, polymer layer 118b has openings P2. According to some embodiments, openings P2 expose conductive pads 115b, respectively. According to some embodiments, polymer layer 118b partially covers conductive pad 115b.

[0079] According to some embodiments, the polymer layer 118b is a solder resist layer, a sulfonyl laminate film, or a prepreg material. According to some embodiments, the solder resist layer is made of a solder resist (SR) material. According to some embodiments, the polymer layer 118b is made of any suitable polymer material, such as a resin or a polyimide.

[0080] In some embodiments, the conductive pad 115a is narrower than the conductive pad 115b. In other words, according to some embodiments, the width W1 of the conductive pad 115b is greater than the width W2 of the conductive pad 115a. According to some embodiments, the width W1 is in the range of about 200 μm to about 600 μm. According to some embodiments, the width W2 is in the range of about 20 μm to about 110 μm. In some embodiments, the (maximum) width W3 of the opening P2 is greater than the (maximum) width W4 of the opening P1.

[0081] The substrate through hole 112, the circuit layers 113a, 113b, the circuit layers 114a, 114b, the conductive pads 115a, 115b, and the guide holes 116a, 116b are made of conductive materials, such as metal materials or alloys thereof, according to some embodiments. According to some embodiments, the metal material includes aluminum, copper or tungsten.

[0082] like Figure 1A As shown, according to some embodiments, a conductive adhesive material layer 120a is formed over the polymer layer 118a and the conductive pad 115a. According to some embodiments, the conductive adhesive material layer 120a conformally covers the top surface 118a1 of the polymer layer 118a, the inner wall S of the opening P1, and the top surface 115a1 of the conductive pad 115a.

[0083] According to some embodiments, the conductive adhesive material layer 120a is in direct contact with the polymer layer 118a and the conductive pad 115a. According to some embodiments, the conductive adhesive material layer 120a passes through the polymer layer 118a. According to some embodiments, the conductive adhesive material layer 120a is a single-layer structure. In some other embodiments, the conductive adhesive material layer 120a is a multi-layer structure.

[0084] According to some embodiments, the conductive adhesive material layer 120a is made of nickel (Ni), titanium (Ti), copper (Cu), palladium (Pd), alloys thereof, combinations thereof, or other suitable metals or alloys. According to some embodiments, the conductive adhesive material layer 120a is formed using a deposition process (e.g., a sputtering process) or a plating process (e.g., an electroless plating process).

[0085] like Figure 1B As shown, according to some embodiments, a mask layer 130 is formed over the conductive adhesive material layer 120a. According to some embodiments, the mask layer 130 has an opening 132. According to some embodiments, the opening 132 exposes the conductive adhesive material layer 120a over or near the conductive pad 115a. According to some embodiments, the mask layer 130 is made of a photoresist material, such as a polymer material.

[0086] like Figure 1B As shown, according to some embodiments, a solder layer 140a is formed in the opening 132. According to some embodiments, the solder layer 140a is formed over the conductive adhesive material layer 120a. According to some embodiments, the solder layer 140a is in direct contact with the conductive adhesive material layer 120a.

[0087] According to some embodiments, the solder layer 140a is made of a suitable solder material such as tin (Sn) or a tin alloy. According to some embodiments, the solder layer 140a is formed using a plating process, such as an electroplating process. According to some embodiments, the conductive adhesive material layer 120a serves as a seed layer in the electroplating process.

[0088] like Figure 1B to Figure 1C As shown, according to some embodiments, the mask layer 130 and the conductive adhesive material layer 120a under the mask layer 130 are removed. According to some embodiments, the remaining conductive adhesive material layer 120a under the solder layer 140a forms a conductive adhesive layer 120. According to some embodiments, the conductive adhesive layer 120 can improve the adhesion relationship between the solder layer 140a and the polymer layer 118a and between the solder layer 140a and the conductive pad 115a.

[0089] like Figure 1D As shown, according to some embodiments, a reflow process is performed on the solder layer 140a. According to some embodiments, the solder layer 140a after reflow forms a solder structure 140. According to some embodiments, the solder structure 140 has a top surface 142. According to some embodiments, the top surface 142 is a curved top surface. According to some embodiments, the process temperature of the reflow process is in the range of about 200°C to about 300°C.

[0090] like Figure 1E As shown, according to some embodiments, a thermo-compression process is performed on the solder structure 140 to flatten the top surface 142 of the solder structure 140. According to some embodiments, the process temperature of the thermo-compression process is in a range of about 50°C to about 150°C.

[0091] In some embodiments, the conductive adhesive layer 120 is a single layer structure. In some other embodiments, such as Figure 2 As shown, according to some embodiments, the conductive adhesive layer 120 is a multi-layer structure. According to some embodiments, the conductive adhesive layer 120 includes a conductive layer 122 and a conductive layer 124.

[0092] In some embodiments, conductive layer 122 is made of copper, and conductive layer 124 is made of nickel. In some other embodiments, conductive layer 122 is made of titanium, and conductive layer 124 is made of copper, according to some embodiments. In other embodiments, conductive layer 122 is made of palladium, and conductive layer 124 is made of copper, according to some embodiments.

[0093] FIG. 3A to FIG. 3C is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 3A As shown, according to some embodiments, in Figure 1A After the step of forming the conductive adhesive material layer 120a above or near the conductive pad 115a, a mask layer 310 is formed. According to some embodiments, the mask layer 310 is also called a dry film. According to some embodiments, the mask layer 310 is made of a polymer material.

[0094] like Figures 3A to 3B As shown in the figure, according to some embodiments, the conductive adhesive material layer 120a exposed from the mask layer 310 is removed. According to some embodiments, the conductive adhesive material layer 120a remaining under the mask layer 310 forms the conductive adhesive layer 120.

[0095] like Figure 3C As shown, according to some embodiments, the mask layer 310 is removed. Figure 3C As shown, according to some embodiments, a mask layer 320 is formed over the polymer layer 118a. According to some embodiments, the mask layer 320 has an opening 322 exposing the conductive adhesive layer 120. According to some embodiments, the mask layer 320 is made of a photoresist material, such as a polymer material.

[0096] like Figure 3C As shown, according to some embodiments, a printing process is performed to form a solder layer 140b in the opening 322. According to some embodiments, the solder layer 140b is made of a suitable solder material such as tin (Sn) or a tin alloy. Thereafter, according to some embodiments, Figure 1D As shown, the mask layer 320 is removed, and a reflow process is performed on the solder layer 140 b to form the solder structure 140 .

[0097] Figure 4 is a cross-sectional view of a stage of a process for forming a chip package structure according to some embodiments. Figure 4 As shown, according to some embodiments, in Figure 3B After the step of removing the mask layer 310. Figure 4 As shown, according to some embodiments, solder balls 140c are disposed above the conductive adhesive layer 120. Thereafter, as shown in FIG. Figure 1DAs shown, the solder ball 140 c is reflowed to form the solder structure 140 according to some embodiments.

[0098] FIG. 5A to FIG. 5D is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Figure 5A As shown, according to some embodiments, in Figure 1E After the steps of providing a chip 510 , according to some embodiments, the chip 510 includes a semiconductor substrate 511 , a device 512 , a dielectric layer 513 , an interconnect layer 514 , a conducting pad 515 , an insulating layer 516 , and a buffer layer 517 .

[0099] According to some embodiments, the semiconductor substrate 511 has a front surface 511a and a rear surface 511b opposite to the front surface 511a. In some embodiments, the semiconductor substrate 511 is made of at least one element semiconductor material, including silicon or germanium with a single crystal, polycrystalline or amorphous structure. In some other embodiments, the semiconductor substrate 511 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or an alloy semiconductor, such as SiGe or GaAsP or a combination thereof. The semiconductor substrate 511 may also include a multilayer semiconductor, a semiconductor on insulator (SOI), such as silicon on insulator or germanium on insulator, or a combination thereof.

[0100] In some embodiments, device 512 is formed in semiconductor substrate 511 above or adjacent to front surface 511a. According to some embodiments, device 512 includes active devices (such as transistors, diodes, etc.) and / or passive devices (such as resistors, capacitors, inductors, etc.).

[0101] According to some embodiments, dielectric layer 513 is formed on front surface 511a and element 512. According to some embodiments, dielectric layer 513 is made of an oxide material, such as silicon oxide. In some other embodiments, dielectric layer 513 is made of a polymer material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), epoxy resin, photosensitive material or other suitable material.

[0102] According to some embodiments, the interconnect layer 514 is formed over the dielectric layer 513. According to some embodiments, the interconnect layer 514 includes a dielectric layer (not shown) and a conductive interconnect structure (not shown) in the dielectric layer.

[0103] According to some embodiments, the conductive pad 515 is formed on the interconnect layer 514. According to some embodiments, the conductive pad 515 is electrically connected to the element 512 through the interconnect layer 514. According to some embodiments, the conductive pad 515 is made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy.

[0104] According to some embodiments, the insulating layer 516 is formed over the outer peripheral portion of the interconnect layer 514 and the conductive pad 515. According to some embodiments, the insulating layer 516 has an opening 516a that exposes the central portion of the conductive pad 515.

[0105] According to some embodiments, the insulating layer 516 is made of a dielectric material, such as undoped silicate glass (USG), silicon nitride, silicon oxide, or silicon oxynitride. According to some embodiments, the insulating layer 516 is formed using a deposition process (such as a chemical vapor deposition process or a physical vapor deposition process) and an etching process.

[0106] According to some embodiments, buffer layer 517 is formed over insulating layer 516. According to some embodiments, buffer layer 517 is also formed over a peripheral portion of conductive pad 515.

[0107] According to some embodiments, the buffer layer 517 has an opening 517a that exposes a central portion of the conductive pad 515. According to some embodiments, the buffer layer 517 serves to buffer bonding stress of a bump formed over the conductive pad 515 during a subsequent bonding process.

[0108] According to some embodiments, the buffer layer 517 is made of a material softer than the insulating layer 516 and / or the conductive pad 515. According to some embodiments, the buffer layer 517 is made of a polymer material such as epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or other suitable materials.

[0109] like Figure 5A As shown, according to some embodiments, an under bump metallurgy (UBM) layer 520 is formed on the conductive pad 515 and the buffer layer 517 adjacent to the conductive pad 515. According to some embodiments, the under bump metallurgy layer 520 is made of titanium, titanium nitride, tantalum, tantalum nitride, copper, or a copper alloy including silver, chromium, nickel, tin and / or gold.

[0110] like Figure 5AAs shown, in accordance with some embodiments, a solder structure 530a is formed over the under bump metallurgy layer 520. In accordance with some embodiments, the solder structure 530a is made of a suitable solder material such as tin (Sn) or a tin alloy.

[0111] like Figure 5B As shown, according to some embodiments, the chip 510 is bonded to the circuit substrate 110 through the conductive bump 530. According to some embodiments, the conductive bump 530 is located between the conductive adhesive layer 120 and the under-bump metallurgical layer 520, and is connected to the conductive adhesive layer 120 and the under-bump metallurgical layer 520. In some embodiments, the conductive bump 530 is formed by Figure 1E and Figure 5A The solder structure 140 and the solder structure 530a are formed.

[0112] In some embodiments, thickness T1 of conductive adhesive layer 120 is substantially equal to thickness T2 of UBM layer 520. According to some embodiments, thickness T1 ranges from about 0.5 μm to about 2 μm. According to some embodiments, thickness T2 ranges from about 0.5 μm to about 2 μm.

[0113] According to some embodiments, the term "substantially equal to" in the present application means "within 10%". For example, according to some embodiments, the term "substantially equal to" means that the difference between thickness T1 and thickness T2 is within 10% of the average thickness of under bump metallurgy layer 520 and conductive adhesion layer 120. This difference may be caused by the process.

[0114] According to some embodiments, since the thickness T1 is substantially equal to the thickness T2, the tensile stress applied to the conductive bump 530 by the conductive adhesive layer 120 is substantially equal to the tensile stress applied to the conductive bump 530 by the under bump metallurgy layer 520. Therefore, according to some embodiments, in the conductive bump 530, the tensile stresses applied by the conductive adhesive layer 120 and the under bump metallurgy layer 520 are substantially balanced with each other.

[0115] According to some embodiments, the balance of tensile stress prevents cracks from being generated in the conductive bumps 530. According to some embodiments, the yield of the conductive bumps 530 is thus improved. According to some embodiments, the yield of the wafer packaging structure having the conductive adhesive layer 120, the under-bump metallurgy layer 520, and the conductive bumps 530 is also improved.

[0116] like Figure 5B As shown, according to some embodiments, an underfill layer U is formed between the chip 510 and the circuit substrate 110. According to some embodiments, the underfill layer U surrounds the conductive bump 530. According to some embodiments, the underfill layer U includes an insulating material, such as a polymer material.

[0117] like Figure 5B As shown, according to some embodiments, an adhesive layer 540 is formed over the circuit substrate 110. According to some embodiments, the adhesive layer 540 surrounds the chip 510 and the bottom filling layer U. According to some embodiments, the adhesive layer 540 has a ring shape. According to some embodiments, the adhesive layer 540 is made of a polymer, such as epoxy resin or silicone resin. According to some embodiments, the adhesive layer 540 is formed using a dispensing process.

[0118] like Figure 5B As shown, according to some embodiments, an adhesive layer 541 is formed on the chip 510. According to some embodiments, the adhesive layer 541 is made of a mixture of silver paste, tin paste, metal powder and polymer, or other suitable adhesive materials with good thermal conductivity. According to some embodiments, the adhesive layer 541 is formed using a dispensing process.

[0119] like Figure 5B As shown, according to some embodiments, the heat dissipation cover 550 is disposed above the chip 510 and the adhesive layer 540 and the bonding layer 541. According to some embodiments, the heat dissipation cover 550 is made of a high thermal conductivity material, such as a metal material (aluminum or copper), an alloy material (such as stainless steel) or aluminum silicon carbide (AlSiC). In other embodiments, the adhesive layer 540 and the bonding layer 541 are first formed on the heat dissipation cover 550, and then the heat dissipation cover 550, the adhesive layer 540, and the bonding layer 541 are disposed above the chip 510 and the circuit substrate 110.

[0120] like Figure 5C As shown, according to some embodiments, a conductive bump 560 is formed over the conductive pad 115b and in the opening P2. According to some embodiments, the conductive bump 560 is made of a suitable solder material such as tin (Sn) or a tin alloy.

[0121] like Figure 5C As shown, according to some embodiments, a cutting process is performed on the circuit substrate 110 along the scribe line A to cut through the circuit substrate 110 to form a chip package structure 500 .

[0122] like Figure 5D As shown, according to some embodiments, the chip package structure 500 is bonded to a circuit substrate 570 through a conductive bump 560 . According to some embodiments, the circuit substrate 570 includes an insulating layer 572 , a circuit layer 574 , a guide hole 576 , and a conductive pad 578 .

[0123] According to some embodiments, the wiring layer 574 and the via 576 are located in the insulating layer 572. According to some embodiments, the conductive pad 578 is located on the insulating layer 572. According to some embodiments, the via 576 provides electrical connection between the wiring layers 574 and between the wiring layers 574 and the conductive pad 578.

[0124] According to some embodiments, the wiring layer 574, the via 576, and the conductive pad 578 are made of a conductive material, such as a metal material or an alloy thereof, such as aluminum, copper, or tungsten.

[0125] According to some embodiments, a chip package structure (or board-level package structure) 501 is substantially formed in this step. According to some embodiments, the chip package structure 501 includes a chip package structure 500, a conductive bump 560, and a circuit substrate 570. According to some embodiments, the chip package structure 501 is a ball grid array (BGA) package structure.

[0126] FIG. 6A to FIG. 6E is a cross-sectional view of various stages of a process for forming a chip package structure according to some embodiments. Fig. 6A As shown, Fig. 6A The steps are similar to Figure 1A The steps, except Fig. 6A The step of forming a conductive adhesive material layer 610a over the polymer layer 118b and the conductive pad 115b during the step of forming the conductive adhesive material layer 120a over the polymer layer 118a and the conductive pad 115a.

[0127] In some embodiments, the conductive adhesive material layer 120a and the conductive adhesive material layer 610a are made of the same material. According to some embodiments, the conductive adhesive material layer 610a is made of nickel (Ni), titanium (Ti), copper (Cu), palladium (Pd), alloys thereof, combinations thereof, or other suitable metals or alloys. According to some embodiments, a deposition process is used to form the conductive adhesive material layer 610a, such as an electroless plating process.

[0128] In some other embodiments (not shown), the conductive adhesive material layer 120a and the conductive adhesive material layer 610a are formed in different processes. According to some embodiments, the conductive adhesive material layer 120a and the conductive adhesive material layer 610a are made of different materials.

[0129] like Figure 6B As shown, according to some embodiments, executing Figures 1B to 1E and FIG. 5A to FIG. 5BThe steps are performed to form a conductive adhesive layer 120, a chip 510, an under-bump metallurgy layer 520, a conductive bump 530, an underfill layer U, an adhesive layer 540, and a heat dissipation cover 550 on the circuit substrate 110.

[0130] like Figure 6C As shown, according to some embodiments, the circuit substrate 110 is turned upside down. Figure 6C As shown, according to some embodiments, a mask layer 620 is formed over the conductive adhesive material layer 610a. According to some embodiments, the mask layer 620 has an opening 622. According to some embodiments, the opening 622 exposes the conductive adhesive material layer 610a over or near the conductive pad 115b. According to some embodiments, the mask layer 620 is made of a photoresist material such as a polymer material.

[0131] like Figure 6C As shown, according to some embodiments, a solder layer 560a is formed in the opening 622. According to some embodiments, the solder layer 560a is formed over the conductive adhesive material layer 610a. According to some embodiments, the solder layer 560a is in direct contact with the conductive adhesive material layer 610a.

[0132] According to some embodiments, the solder layer 560a is made of a suitable solder material, such as tin (Sn) or a tin alloy. According to some embodiments, the solder layer 560a is formed using a plating process, such as an electroplating process. According to some embodiments, the conductive adhesive material layer 610a is used as a seed layer in the electroplating process.

[0133] like FIG. 6C to FIG. 6D As shown, according to some embodiments, the mask layer 620 and the conductive adhesive material layer 610a below the mask layer 620 are removed. According to some embodiments, the conductive adhesive material layer 610a remaining below the solder layer 560a forms a conductive adhesive layer 610.

[0134] like Fig.6D As shown, according to some embodiments, a reflow process is performed on the solder layer 560a. According to some embodiments, the reflowed solder layer 560a forms a conductive bump 560. According to some embodiments, the conductive bump 560 has a spherical shape.

[0135] like Fig.6D As shown, according to some embodiments, a cutting process is performed on the circuit substrate 110 along the scribe lines A to cut through the circuit substrate 110 , thereby forming a chip package structure 600 .

[0136] like Fig. 6EAs shown, according to some embodiments, the chip package structure 600 is bonded to a circuit substrate 570 via a conductive bump 560 . According to some embodiments, the circuit substrate 570 includes an insulating layer 572 , a circuit layer 574 , a guide hole 576 , and a conductive pad 578 .

[0137] According to some embodiments, the wiring layer 574 and the via 576 are located in the insulating layer 572. According to some embodiments, the conductive pad 578 is located on the insulating layer 572. According to some embodiments, the via 576 provides electrical connection between the wiring layers 574 and between the wiring layers 574 and the conductive pad 578.

[0138] According to some embodiments, the wiring layer 574, the via 576, and the conductive pad 578 are made of a conductive material, such as a metal material or an alloy thereof, such as aluminum, copper, or tungsten.

[0139] In this step, according to some embodiments, a chip packaging structure (or board-level packaging structure) 601 is substantially formed. According to some embodiments, the chip packaging structure 601 includes a chip packaging structure 600 , a conductive bump 560 , and a circuit substrate 570 .

[0140] In some embodiments, FIG. 6A to FIG. 6D As shown, the conductive adhesive layer 610 is formed by depositing a conductive adhesive material layer 610a and removing the conductive adhesive material layer 610a under the mask layer 620. In some other embodiments (eg FIG. 7A to FIG. 7B ), the conductive adhesive layer 610 is formed by depositing a conductive adhesive material layer 610a and removing the conductive adhesive material layer 610a exposed from the mask layer.

[0141] 7A to 7C is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Fig. 7A As shown, according to some embodiments, in Figure 6B After the step of turning the circuit substrate 110 upside down. Fig. 7A As shown, according to some embodiments, a mask layer 710 is formed on the conductive adhesive material layer 610a on or near the conductive pad 115b. According to some embodiments, the mask layer 710 is also called a dry film. According to some embodiments, the mask layer 710 is made of a polymer material.

[0142] like FIG. 7A to FIG. 7B As shown, according to some embodiments, the conductive adhesive material layer 610a exposed from the mask layer 710 is removed. According to some embodiments, the conductive adhesive material layer 610a remaining under the mask layer 710 forms the conductive adhesive layer 610. Figure 7B As shown, according to some embodiments, the mask layer 710 is removed.

[0143] Thereafter, according to some embodiments, as Figure 7C As shown, conductive bumps 560 are formed over conductive adhesive layer 610. According to some embodiments, a printing process (similar to Figure 3C printing process) or ball mounting process (ball mounting process, similar to Figure 4 The conductive bump 560 is formed by a ball mounting process) and a reflow process.

[0144] like Figure 7C As shown, according to some embodiments, a cutting process is performed on the circuit substrate 110 along the scribe line A to cut through the circuit substrate 110 to form a chip package structure 700 .

[0145] FIG. 8A to FIG. 8D is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Fig. 8A As shown, according to some embodiments, a circuit substrate 110 is provided. Fig. 8A As shown, according to some embodiments, a material layer 122a is formed over the polymer layer 118a and the conductive pad 115a.

[0146] According to some embodiments, material layer 122a conformally covers top surface 118a1 of polymer layer 118a, inner wall S of opening P1 of polymer layer 118a, and top surface 115a1 of conductive pad 115a. According to some embodiments, material layer 122a directly contacts polymer layer 118a and conductive pad 115a.

[0147] like Fig. 8A As shown, according to some embodiments, a material layer 124a is formed over the material layer 122a. According to some embodiments, the material layer 124a conformally covers the material layer 122a. According to some embodiments, the material layer 124a has a groove 124a1 in the opening P1. According to some embodiments, the material layer 122a and the material layer 124a are made of different materials. According to some embodiments, the material layer 122a is made of titanium or palladium. According to some embodiments, the material layer 124a is made of copper.

[0148] In some embodiments, material layer 122a is made of titanium, material layer 124a is made of copper, and material layer 122a and material layer 124a are formed using a sputtering process. In some embodiments, material layer 122a is made of palladium, material layer 124a is made of copper, and material layer 122a and material layer 124a are formed using an electroless plating process. According to some embodiments, material layer 122a and material layer 124a together form a conductive adhesive material layer 120a.

[0149] like Figure 8BAs shown, according to some embodiments, a mask layer 810 is formed over the material layer 124a. According to some embodiments, the mask layer 810 has an opening 812, and the opening 812 exposes the material layer 124a above or near the conductive pad 115a. According to some embodiments, the mask layer 810 is made of a photoresist material, such as a polymer material.

[0150] like Figure 8B As shown, according to some embodiments, a nickel layer 820 is formed in the opening 812 and the groove 124a1. According to some embodiments, the nickel layer 820 is filled in the groove 124a1. According to some embodiments, the nickel layer 820 is thicker than the conductive adhesive material layer 120a. In other words, according to some embodiments, the thickness T3 of the nickel layer 820 is greater than the thickness T4 of the conductive adhesive material layer 120a. According to some embodiments, the thickness T3 is within the range of about 3 μm to about 30 μm. According to some embodiments, the thickness T4 is within the range of about 0.5 μm to about 2 μm.

[0151] The nickel layer 820 can prevent the copper of the conductive pad 115a from migrating into a conductive bump subsequently formed over the nickel layer 820 during subsequent high current density operations. Therefore, the electromigration problem of the nickel layer 820 can be reduced.

[0152] According to some embodiments, nickel layer 820 is made of nickel or its alloy. According to some embodiments, material layer 122a and material layer 124a and nickel layer 820 are made of different materials. According to some embodiments, nickel layer 820 is formed using a plating process, such as an electroless plating process.

[0153] like Figure 8B As shown, according to some embodiments, a palladium layer 830 is formed over the nickel layer 820. According to some embodiments, the palladium layer 830 is thinner than the nickel layer 820. According to some embodiments, the palladium layer 830 is made of palladium or its alloy. According to some embodiments, the palladium layer 830 is formed using a plating process, such as an electroless plating process.

[0154] like Figure 8B As shown, according to some embodiments, a gold layer 840 is formed over the palladium layer 830. According to some embodiments, the gold layer 840 is thinner than the nickel layer 820. According to some embodiments, the gold layer 840 is made of gold or its alloy. According to some embodiments, the gold layer 840 is formed using a plating process, such as an immersion plating process.

[0155] like Figure 8CAs shown, according to some embodiments, the mask layer 810 and the material layer 122a and the material layer 124a below the mask layer 810 are removed. According to some embodiments, the material layer 122a remaining below the nickel layer 820 forms the conductive layer 122. According to some embodiments, the material layer 124a remaining below the nickel layer 820 forms the conductive layer 124. According to some embodiments, the conductive layer 122 and the conductive layer 124 together form the conductive adhesive layer 120.

[0156] like FIG. 8C to FIG. 8D As shown, according to some embodiments, executing Figure 1D to Figure 1E and FIG. 5A to FIG. 5B The steps are performed to form the chip 510, the under-bump metallurgy layer 520, the conductive bump 530, the bottom filling layer U, the adhesive layer 540, and the heat dissipation cover 550 on the circuit substrate. According to some embodiments, after the chip 510 is bonded to the circuit substrate 110, the palladium layer 830 and the gold layer 840 are dispersed (or dissolved) in the conductive bump 530. According to some embodiments, the conductive bump 530 is in direct contact with the nickel layer 820.

[0157] like Fig.8D As shown, according to some embodiments, executing Figure 5C Steps are performed to form conductive bumps 560 on the conductive pads 115b and form a chip package structure 800. For simplicity, according to some embodiments, Fig.8D Only one chip package structure 800 is shown.

[0158] like Fig.8D As shown, according to some embodiments, executing Figure 5D The step of bonding the circuit substrate 110 to the circuit substrate 570 through the conductive bump 560 is performed. According to some embodiments, the conductive bump 560 is located between the conductive pad 115 b of the circuit substrate 110 and the conductive pad 578 of the circuit substrate 570 .

[0159] In this step, according to some embodiments, a chip packaging structure (or board-level packaging structure) 801 is substantially formed. According to some embodiments, the chip packaging structure 801 includes a chip packaging structure 800, a conductive bump 560, and a circuit substrate 570. According to some embodiments, the chip packaging structure 801 is a ball grid array (BGA) packaging structure.

[0160] 9A to 9C is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Fig.9A As shown, according to some embodiments, in Fig. 8AAfter the step of forming the conductive pad 115a, a mask layer 910 is formed on the material layer 124a above or near the conductive pad 115a. According to some embodiments, the mask layer 910 is also referred to as a dry film. According to some embodiments, the mask layer 910 is made of a polymer material.

[0161] like FIG. 9A to FIG. 9B As shown, according to some embodiments, the material layer 122a and the material layer 124a not covered by the mask layer 910 are removed. According to some embodiments, the material layer 122a remaining under the mask layer 910 forms the conductive layer 122. According to some embodiments, the material layer 124a remaining under the mask layer 910 forms the conductive layer 124. According to some embodiments, the conductive layer 122 and the conductive layer 124 together form the conductive adhesive layer 120. Fig. 9B As shown, according to some embodiments, mask layer 910 is removed.

[0162] like Fig. 9B As shown, according to some embodiments, a nickel layer 920 is formed over the conductive adhesive layer 120. According to some embodiments, the nickel layer 920 covers the top surface 120c and the sidewalls 120b of the conductive adhesive layer 120.

[0163] According to some embodiments, the nickel layer 920 is thicker than the conductive adhesive layer 120. That is, according to some embodiments, the thickness T5 of the nickel layer 920 is greater than the thickness T6 of the conductive adhesive layer 120. According to some embodiments, the thickness T5 is in the range of about 3 μm to about 30 μm. According to some embodiments, the thickness T6 is in the range of about 0.5 μm to about 2 μm.

[0164] According to some embodiments, the nickel layer 920 is made of nickel or an alloy thereof. According to some embodiments, the nickel layer 920 is formed using a plating process, for example, using an electroless plating process.

[0165] like Fig. 9B As shown, according to some embodiments, a palladium layer 930 is formed over the nickel layer 920. According to some embodiments, the palladium layer 930 conformally covers the top surface 922 and the sidewalls 924 of the nickel layer 920. According to some embodiments, the palladium layer 930 is thinner than the nickel layer 920.

[0166] According to some embodiments, the palladium layer 930 is made of palladium or its alloy. According to some embodiments, the palladium layer 930 is formed using a plating process, for example, using an electroless plating process.

[0167] like Fig. 9BAs shown, according to some embodiments, a gold layer 940 is formed over the palladium layer 930. According to some embodiments, the gold layer 940 conformally covers the top surface 932 and the sidewalls 934 of the palladium layer 930. According to some embodiments, the gold layer 940 is thinner than the nickel layer 920. According to some embodiments, the gold layer 940 is made of gold or its alloy. According to some embodiments, the gold layer 940 is formed using a plating process, such as an immersion plating process.

[0168] like FIG. 9B to FIG. 9C As shown, according to some embodiments, executing FIG. 5A to FIG. 5B The steps are performed to form the chip 510, the under-bump metallurgy layer 520, the conductive bumps 530, the underfill layer U, the adhesive layer 540, and the heat dissipation cover 550 above the circuit substrate 110. According to some embodiments, after the chip 510 is bonded to the circuit substrate 110, the palladium layer 930 and the gold layer 940 are dissolved in the conductive bumps 530.

[0169] like Fig. 9C As shown, according to some embodiments, executing Figure 5C The step of forming the conductive bump 560 on the conductive pad 115b and forming the chip package structure 900. For simplicity, according to some embodiments, Fig. 9C Only one chip package structure 900 is shown.

[0170] like Fig. 9C As shown, according to some embodiments, executing Figure 5D The step of bonding the circuit substrate 110 to the circuit substrate 570 through the conductive bump 560 is performed. According to some embodiments, the conductive bump 560 is located between the conductive pad 115 b of the circuit substrate 110 and the conductive pad 578 of the circuit substrate 570 .

[0171] In this step, according to some embodiments, a chip packaging structure (or board-level packaging structure) 901 is substantially formed. According to some embodiments, the chip packaging structure 901 includes a chip packaging structure 900, a conductive bump 560, and a circuit substrate 570. According to some embodiments, the chip packaging structure 901 is a ball grid array (BGA) packaging structure.

[0172] FIG. 10A to FIG. 10C is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Fig. 10A As shown, according to some embodiments, in Fig. 8A After the step of , a mask layer 1010 is formed over the material layer 124a. According to some embodiments, the mask layer 1010 has an opening 1012, and the opening 1012 exposes the material layer 124a over or near the conductive pad 115a. According to some embodiments, the mask layer 1010 is made of a photoresist material, such as a polymer material.

[0173] like Fig. 10A As shown, according to some embodiments, a nickel layer 1020 is formed in the opening 1012 of the mask layer 1010 and the groove 124a1 of the material layer 124a. According to some embodiments, the nickel layer 1020 conformally covers the material layer 124a. According to some embodiments, the nickel layer 1020 has a groove 1022 partially in the groove 124a1.

[0174] According to some embodiments, the nickel layer 1020 is thicker than the conductive adhesive material layer 120a. According to some embodiments, the nickel layer 1020 is made of nickel or its alloy. According to some embodiments, the nickel layer 1020 is formed using a plating process, such as an electroless plating process.

[0175] like Fig. 10A As shown, according to some embodiments, a copper layer 1030 is formed over the nickel layer 1020 and in the groove 1022. According to some embodiments, the copper layer 1030 is thicker than the nickel layer 1020. According to some embodiments, the copper layer 1030 fills the groove 1022. According to some embodiments, the copper layer 1030 is made of copper or its alloy. According to some embodiments, the copper layer 1030 is formed using a plating process, such as an electroless plating process.

[0176] like FIG. 10A to FIG. 10B As shown, according to some embodiments, the mask layer 1010 and the material layer 122a and the material layer 124a below the mask layer 1010 are removed. According to some embodiments, the material layer 122a remaining below the nickel layer 1020 forms the conductive layer 122. According to some embodiments, the material layer 124a remaining below the nickel layer 1020 forms the conductive layer 124. According to some embodiments, the conductive layer 122 and the conductive layer 124 together form the conductive adhesive layer 120.

[0177] Fig. 10B As shown, according to some embodiments, a capping layer 1040 is formed on the copper layer 1030, the nickel layer 1020, and the conductive adhesive layer 120. According to some embodiments, the capping layer 1040 conformally covers the top surface 1032 and the sidewall 1034 of the copper layer 1030, the sidewall 1021 of the nickel layer 1020, the sidewall 122b of the conductive layer 122, and the sidewall 124b of the conductive layer 124. According to some embodiments, the capping layer 1040 is used to prevent the copper layer 1030, the nickel layer 1020, and the conductive adhesive layer 120 from being oxidized.

[0178] According to some embodiments, the capping layer 1040 is made of a material different from the copper layer 1030, the nickel layer 1020, and the conductive adhesive layer 120. According to some embodiments, the capping layer 1040 is made of tin or an organic material.

[0179] According to some embodiments, the organic material includes an organic solderability preservative (OSP) material. The organic solderability preservative material includes benzotriazole, benzimidazoles, or a combination and derivative thereof. In some embodiments, the cap layer 1040 is formed by immersing the metal surfaces of the copper layer 1030, the nickel layer 1020, and the conductive adhesive layer 120 in an organic solderability preservative solution, which may contain a compound of alkylimidazole, benzotriazole, rosin, rosin esters, or benzimidazole. In some other embodiments, the cap layer 1040 is made of phenylimidazole or other imidazole compounds including 2-arylimidazole as an active ingredient.

[0180] like FIG. 10B to FIG. 10C As shown, according to some embodiments, executing FIG. 5A to FIG. 5B The steps are performed to form the chip 510, the under-bump metallurgy layer 520, the conductive bump 530, the bottom filling layer U, the adhesive layer 540 and the heat dissipation cover 550 on the circuit substrate 110. According to some embodiments, the conductive bump 530 is located between the copper layer 1030 and the chip 510. According to some embodiments, after the chip 510 is bonded to the circuit substrate 110, the cover layer 1040 is dissolved in the conductive bump 530.

[0181] like Fig. 10C As shown, according to some embodiments, executing Figure 5C The step of forming the conductive bump 560 on the conductive pad 115b and forming the chip package structure 1000 is performed. For simplicity, according to some embodiments, Fig. 10C Only one chip package structure 1000 is shown.

[0182] like Fig. 10C As shown, according to some embodiments, executing Figure 5D The step of bonding the circuit substrate 110 to the circuit substrate 570 through the conductive bump 560 is performed. According to some embodiments, the conductive bump 560 is located between the conductive pad 115 b of the circuit substrate 110 and the conductive pad 578 of the circuit substrate 570 .

[0183] In this step, according to some embodiments, a chip packaging structure (or board-level packaging structure) 1001 is substantially formed. According to some embodiments, the chip packaging structure 1001 includes a chip packaging structure 1000, a conductive bump 560, and a circuit substrate 570. According to some embodiments, the chip packaging structure 1001 is a ball grid array (BGA) packaging structure.

[0184] FIG. 11A to FIG. 11C is a cross-sectional view of various stages of a process for forming a chip packaging structure according to some embodiments. Fig.11A As shown, according to some embodiments, in Fig. 8A After the step of , a mask layer 1110 is formed over the material layer 124a. According to some embodiments, the mask layer 1110 has an opening 1112, and the opening 1112 exposes the material layer 124a over or near the conductive pad 115a. According to some embodiments, the mask layer 1110 is made of a photoresist material, such as a polymer material.

[0185] like Fig.11A As shown, according to some embodiments, a nickel layer 1120 is formed in the opening 1112 of the mask layer 1110 and the groove 124a1 of the material layer 124a. According to some embodiments, the nickel layer 1120 conformally covers the material layer 124a. According to some embodiments, the nickel layer 1120 has a groove 1122 partially in the groove 124a1.

[0186] According to some embodiments, nickel layer 1120 is thicker than conductive adhesive material layer 120a. According to some embodiments, nickel layer 1120 is made of nickel or its alloy. According to some embodiments, nickel layer 1120 is formed using a plating process, such as an electroless plating process.

[0187] like Fig.11A As shown, according to some embodiments, a palladium layer 1130 is formed over the nickel layer 1120. According to some embodiments, the palladium layer 1130 is thinner than the nickel layer 1120. According to some embodiments, the palladium layer 1130 is made of palladium or its alloy. According to some embodiments, the palladium layer 1130 is formed using a plating process, such as an electroless plating process.

[0188] like Fig.11A As shown, according to some embodiments, a gold layer 1140 is formed over the palladium layer 1130. According to some embodiments, the gold layer 1140 is thinner than the nickel layer 1120. According to some embodiments, the gold layer 1140 is made of gold or its alloy. According to some embodiments, the gold layer 1140 is formed using a plating process, such as an immersion plating process.

[0189] like Fig.11A As shown, according to some embodiments, a solder layer 1150a is formed in the opening 1112 and over the gold layer 1140. According to some embodiments, the solder layer 1150a is thicker than the nickel layer 1120. According to some embodiments, the solder layer 1150a is made of tin or its alloy. According to some embodiments, the solder layer 1150a is formed using a plating process, such as an electroplating process or an electroless plating process.

[0190] like FIG. 11A to FIG. 11BAs shown, according to some embodiments, the mask layer 1110 and the material layer 122a and the material layer 124a below the mask layer 1110 are removed. According to some embodiments, the material layer 122a remaining below the nickel layer 1120 forms the conductive layer 122. According to some embodiments, the material layer 124a remaining below the nickel layer 1120 forms the conductive layer 124. According to some embodiments, the conductive layer 122 and the conductive layer 124 together form the conductive adhesive layer 120.

[0191] like Fig. 11B As shown, according to some embodiments, a reflow process is performed on the solder layer 1150a. According to some embodiments, the reflowed solder layer 1150a forms a solder ball 1150. The gold layer 1140 and the palladium layer 1130 are dissolved in the solder ball 1150. According to some embodiments, the solder ball 1150 is in direct contact with the nickel layer 1120.

[0192] like FIG. 11B to FIG. 11C As shown, according to some embodiments, executing FIG. 5A to FIG. 5B The steps are performed to form a chip 510, an under-bump metallurgy layer 520, a conductive bump 530, an underfill layer 1120, an adhesive layer 540, and a heat dissipation cover 550 on the circuit substrate 110. According to some embodiments, the conductive bump 530 is located between the nickel layer 1120 and the under-bump metallurgy layer 520. A portion of the conductive bump 530 is formed by a solder ball 1150.

[0193] like Fig. 11C As shown, according to some embodiments, executing Figure 5C The step of forming the conductive bump 560 on the conductive pad 115b and forming the chip package structure 1100 is performed. For simplicity, according to some embodiments, Fig. 11C Only one chip package structure 1100 is shown.

[0194] like Fig. 11C As shown, according to some embodiments, executing Figure 5D The step of bonding the circuit substrate 110 to the circuit substrate 570 through the conductive bump 560 is performed. According to some embodiments, the conductive bump 560 is located between the conductive pad 115 b of the circuit substrate 110 and the conductive pad 578 of the circuit substrate 570 .

[0195] In this step, according to some embodiments, a chip packaging structure (or board-level packaging structure) 1101 is substantially formed. According to some embodiments, the chip packaging structure 1101 includes a chip packaging structure 1100, conductive bumps 560, and a circuit substrate 570. According to some embodiments, the chip packaging structure 1101 is a ball grid array (BGA) packaging structure.

[0196] The processes and materials used to form the chip package structures 600, 700, 800, 900, 1000 and 1100 may be similar to or the same as the processes and materials used to form the chip package structure 500. The processes and materials used to form the chip package structures 601, 801, 901, 1001 and 1101 may be similar to or the same as the processes and materials used to form the chip package structure 501. Figures 1A to 11C Elements denoted by the same reference numerals have similar or identical structures and materials, and thus their detailed description is omitted.

[0197] According to some embodiments, a chip packaging structure and a method for forming the same are provided. This method (a method for forming a chip packaging structure) forms a conductive adhesive layer between a circuit substrate and a conductive bump to improve adhesion between the conductive bump and a polymer layer of the circuit substrate and between the conductive bump and a conductive pad of the circuit substrate. This method forms a nickel layer between the conductive adhesive layer and the conductive bump. The nickel layer can prevent the material of the conductive pad from migrating into the conductive bump during high current density operation. Therefore, the nickel layer reduces the problem of electromigration.

[0198] The present disclosure provides a method for forming a chip packaging structure, including providing a circuit substrate, forming a conductive adhesive layer above a polymer layer and a conductive pad, forming a nickel layer above the conductive adhesive layer, and bonding a chip to the circuit substrate through a conductive bump. The circuit substrate includes a substrate, a conductive pad, and a polymer layer, the polymer layer is located above the substrate and the conductive pad, and the polymer layer has a first opening exposing the conductive pad. The conductive adhesive layer directly contacts and conformally covers the polymer layer and the conductive pad. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are formed of different materials. The conductive bump is located between the nickel layer and the chip.

[0199] In some embodiments, before the operation of bonding the chip to the circuit substrate, a gold layer is formed over the nickel layer, and after bonding the chip to the circuit substrate, the gold layer is dissolved in the conductive bump. In some embodiments, the operation of forming the conductive adhesive layer, the nickel layer, and the gold layer includes: forming a conductive adhesive material layer over the polymer layer and the conductive pad; forming a mask layer over the conductive adhesive material layer, wherein the mask layer has a second opening, and the second opening exposes the conductive adhesive material layer over or near the conductive pad; forming a nickel layer in the second opening; forming a gold layer over the nickel layer; and removing the mask layer and the conductive adhesive material layer under the mask layer, and the conductive adhesive material layer remaining under the nickel layer forms a conductive adhesive layer. In some embodiments, the operation of forming the conductive adhesive layer includes: forming a conductive adhesive material layer over the polymer layer and the conductive pad; forming a mask layer over the conductive adhesive material layer over or near the conductive pad; removing the conductive adhesive material layer exposed from the mask layer, wherein the conductive adhesive material layer remaining under the mask layer forms a conductive adhesive layer; and removing the mask layer. In some embodiments, the gold layer covers the sidewalls and top surface of the nickel layer. In some embodiments, after the operation of forming a gold layer over the nickel layer, a solder ball is formed over the nickel layer, wherein the gold layer is dissolved in the solder ball, and a portion of the conductive bump is formed from the solder ball. In some embodiments, before the operation of bonding the chip to the circuit substrate, a copper layer is formed over the nickel layer, wherein the conductive bump is located between the copper layer and the chip. In some embodiments, the nickel layer conformally covers the conductive adhesive layer, and the nickel layer has a groove, the groove is partially located in the first opening, and the copper layer fills the groove. In some embodiments, a cap layer is formed, and the cap layer covers the top surface of the copper layer and the first side wall, the second side wall of the nickel layer, and the third side wall of the conductive adhesive layer. In some embodiments, the cap layer is formed of tin or an organic material.

[0200] Some embodiments of the present disclosure provide a method for forming a chip packaging structure, including providing a circuit substrate, the circuit substrate including a substrate, a first conductive pad and a first polymer layer, the first conductive pad is located above the first surface of the substrate, the first polymer layer is located above the first surface and the first conductive pad, the first polymer layer has a first opening, and the first opening exposes the first conductive pad; forming a first conductive adhesive layer above the first polymer layer and the first conductive pad, the first conductive adhesive layer directly contacts the first polymer layer and the first conductive pad; forming a solder structure above the first conductive adhesive layer; and bonding the chip to the circuit substrate through an under-bump metallurgical layer and a first conductive bump, the under-bump metallurgical layer being located between the chip and the first conductive bump, the conductive bump being connected to the first conductive adhesive layer and the under-bump metallurgical layer, the solder structure forming a portion of the first conductive bump, and the first thickness of the under-bump metallurgical layer being substantially equal to the second thickness of the first conductive adhesive material layer.

[0201] In some embodiments, the operation of forming a first conductive adhesive layer and a solder structure includes: forming a conductive adhesive material layer over the first polymer layer and the first conductive pad; forming a mask layer over the conductive adhesive material layer, wherein the mask layer has a second opening, and the second opening exposes the conductive adhesive material layer adjacent to or above the first conductive pad; forming a solder layer in the second opening; removing the mask layer and the conductive adhesive material layer below the mask layer, wherein the conductive adhesive material layer remaining below the solder layer forms a first conductive adhesive layer; and reflowing the solder layer to form a solder structure. In some embodiments, the operation of forming a first conductive adhesive material layer includes: forming a conductive adhesive material layer over the first polymer layer and the first conductive pad; forming a first mask layer over the conductive adhesive material layer adjacent to or above the first conductive pad; removing the conductive adhesive material exposed from the first mask layer, wherein the conductive adhesive material remaining below the first mask layer forms the first conductive adhesive layer; and removing the first mask layer. In some embodiments, the operation of forming a solder structure above the first conductive adhesive layer includes: forming a second mask layer above the first polymer layer, wherein the second mask layer has a second opening exposing the first conductive adhesive layer; printing a solder layer into the second opening; removing the second mask layer; and reflowing the solder layer to form the solder structure. In some embodiments, the operation of forming a solder structure above the first conductive adhesive layer includes: disposing a solder ball above the first conductive adhesive layer; and reflowing the solder ball to form the solder structure. In some embodiments, a hot pressing process is performed above the solder structure to flatten the top surface of the solder structure. In some embodiments, the first conductive adhesive layer is formed by an electroless plating process or a sputtering process. In some embodiments, the circuit substrate also includes a second conductive pad and a second polymer layer, the second conductive pad is located above the second surface of the substrate, the first conductive pad is narrower than the second conductive pad, the second polymer layer is located above the second surface and the second conductive pad, and the second polymer layer has a second opening exposing the second conductive pad, and the method for forming a chip packaging structure also includes: when forming a first conductive adhesive layer above the first polymer layer and the first conductive pad, forming a second conductive adhesive layer above the second polymer layer and the second conductive pad; and after bonding the chip to the circuit substrate, forming a second conductive bump above the second conductive adhesive layer.

[0202] Some embodiments of the present disclosure provide a chip packaging structure, including a circuit substrate, a conductive adhesive layer, a nickel layer, a chip and a conductive bump. The circuit substrate includes a substrate, a first conductive pad, a second conductive pad and a polymer layer, the first conductive pad and the second conductive pad are respectively located above the first surface and the second surface of the substrate, the first conductive pad is narrower than the second conductive pad, and the polymer layer is located on the first surface and above the first conductive pad. The conductive adhesive layer passes through the polymer layer and is located above the first conductive pad, wherein the conductive adhesive layer directly contacts the polymer layer and the first conductive pad. The nickel layer is located above the conductive adhesive layer, wherein the nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are formed of different materials. The chip is located above the circuit substrate. The conductive bump is located between the nickel layer and the chip.

[0203] In some embodiments, the nickel layer covers the sidewalls and the top surface of the conductive adhesion layer.

[0204] The above content summarizes the features of many embodiments, so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art may have no difficulty in designing or modifying other processes and structures based on the present disclosure to achieve the same purpose and / or obtain the same advantages as the embodiments of the present disclosure. Any person skilled in the art should also understand that different changes, substitutions and modifications are made without departing from the spirit and scope of the present disclosure, and such equivalent creations do not exceed the spirit and scope of the present disclosure.

Claims

1. A method for forming a chip packaging structure, comprising: A circuit substrate is provided, the circuit substrate comprising a substrate, a conducting pad and a polymer layer, wherein the polymer layer is located above the substrate and the conducting pad, and the polymer layer has a first opening exposing the conducting pad; forming a conductive adhesive layer over the polymer layer and the conductive pad, wherein the conductive adhesive layer directly contacts and conformally covers the polymer layer and the conductive pad; forming a nickel layer on the conductive adhesive layer, wherein the nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are formed of different materials; forming a copper layer above the nickel layer, wherein the conductive bump is located between the copper layer and the chip; as well as A chip is bonded to the circuit substrate through a conductive bump, wherein the conductive bump is located between the nickel layer and the chip.

2. The method for forming a chip package structure according to claim 1, further comprising: Before the chip is bonded to the circuit substrate, a gold layer is formed on the nickel layer, wherein after the chip is bonded to the circuit substrate, the gold layer is dissolved in the conductive bump.

3. The method for forming a chip package structure according to claim 2, wherein the operation of forming the conductive adhesive layer, the nickel layer and the gold layer comprises: forming a conductive adhesive material layer over the polymer layer and the conductive pad; forming a mask layer above the conductive adhesive material layer, wherein the mask layer has a second opening, and the second opening exposes the conductive adhesive material layer above or near the conductive pad; forming the nickel layer in the second opening; forming the gold layer over the nickel layer; as well as The mask layer and the conductive adhesive material layer under the mask layer are removed, wherein the conductive adhesive material layer remaining under the nickel layer forms the conductive adhesive layer.

4. The method for forming a chip package structure according to claim 2, wherein the operation of forming the conductive adhesive layer comprises: forming a conductive adhesive material layer over the polymer layer and the conductive pad; forming a mask layer on the conductive adhesive material layer above or near the conductive pad; removing the conductive adhesive material layer exposed from the mask layer, wherein the conductive adhesive material layer remaining under the mask layer forms the conductive adhesive layer; as well as The mask layer is removed.

5. The method for forming a chip packaging structure according to claim 4, wherein the operation of forming the conductive adhesive layer comprises: forming a conductive adhesive material layer over the polymer layer and the conductive pad; forming a mask layer on the conductive adhesive material layer above or near the conductive pad; removing the conductive adhesive material layer exposed from the mask layer, wherein the conductive adhesive material layer remaining under the mask layer forms the conductive adhesive layer; as well as The mask layer is removed.

6. The method for forming a chip package structure according to claim 2, further comprising: After the operation of forming the gold layer over the nickel layer, a solder ball is formed over the nickel layer, wherein the gold layer is dissolved in the solder ball and a portion of the conductive bump is formed from the solder ball. 7 . The method for forming a chip package structure as claimed in claim 1 , wherein the nickel layer conformally covers the conductive adhesive layer, and the nickel layer has a groove, the groove is partially located in the first opening, and the copper layer fills the groove.

8. The method for forming a chip package structure according to claim 7, further comprising: A capping layer is formed, which covers a top surface and a first side wall of the copper layer, a second side wall of the nickel layer, and a third side wall of the conductive adhesive layer.

9. The method for forming a chip package structure according to claim 8, further comprising: Before the chip is bonded to the circuit substrate, a copper layer is formed on the nickel layer, wherein the conductive bump is located between the copper layer and the chip.

10. A method for forming a chip packaging structure, comprising: A circuit substrate is provided, the circuit substrate comprising a substrate, a first conducting pad and a first polymer layer, wherein the first conducting pad is located above a first surface of the substrate, the first polymer layer is located above the first surface and the first conducting pad, and the first polymer layer has a first opening, and the first opening exposes the first conducting pad; A first conductive adhesive layer is formed on the first polymer layer and the first conductive pad, comprising: forming a conductive adhesive material layer over the first polymer layer and the first conductive pad; forming a first mask layer over the conductive adhesive material layer near or above the first conductive pad; removing the conductive adhesive material layer exposed from the first mask layer, wherein the conductive adhesive material layer remaining under the first mask layer forms the first conductive adhesive layer; and removing the first mask layer, wherein the first conductive adhesive layer directly contacts the first polymer layer and the first conductive pad; forming a solder structure over the first conductive adhesive layer; and A chip is joined to the circuit substrate via a lower bump metallurgical layer and a first conductive bump, wherein the lower bump metallurgical layer is located between the chip and the first conductive bump, the first conductive bump is connected to the first conductive adhesive layer and the lower bump metallurgical layer, the solder structure forms a part of the first conductive bump, and a first thickness of the lower bump metallurgical layer is equal to a second thickness of the first conductive adhesive layer.

11. The method for forming a chip package structure according to claim 10, wherein the operation of forming the first conductive adhesive layer and the solder structure comprises: forming a conductive adhesive material layer over the first polymer layer and the first conductive pad; forming a mask layer above the conductive adhesive material layer, wherein the mask layer has a second opening, and the second opening exposes the conductive adhesive material layer adjacent to or located above the first conducting pad; forming a solder layer in the second opening; removing the mask layer and the conductive adhesive material layer below the mask layer, wherein the conductive adhesive material layer remaining below the solder layer forms the first conductive adhesive layer; as well as The solder layer is reflowed to form the solder structure.

12. The method for forming a chip package structure according to claim 10, wherein the operation of forming the solder structure above the first conductive adhesive layer comprises: forming a second mask layer above the first polymer layer, wherein the second mask layer has a second opening exposing the first conductive adhesive layer; printing a solder layer into the second opening; removing the second mask layer; as well as The solder layer is reflowed to form the solder structure.

13. The method for forming a chip package structure according to claim 10, wherein the operation of forming the solder structure above the first conductive adhesive layer comprises: disposing a solder ball over the first conductive adhesive layer; as well as The solder balls are reflowed to form the solder structure.

14. The method for forming a chip package structure according to claim 13, further comprising: A thermal compression process is performed over the solder structure to planarize a top surface of the solder structure. 15 . The method for forming a chip package structure as claimed in claim 10 , wherein the first conductive adhesive layer is formed by an electroless plating process or a sputtering process.

16. The method for forming a chip package structure as claimed in claim 10, wherein the circuit substrate further comprises a second conducting pad and a second polymer layer, the second conducting pad is located above a second surface of the substrate, the first conducting pad is narrower than the second conducting pad, the second polymer layer is located above the second surface and the second conducting pad, and the second polymer layer has a second opening exposing the second conducting pad, and the method for forming a chip package structure further comprises: When the first conductive adhesive layer is formed on the first polymer layer and the first conductive pad, a second conductive adhesive layer is formed on the second polymer layer and the second conductive pad; as well as After the chip is bonded to the circuit substrate, a second conductive bump is formed on the second conductive adhesive layer.

17. A chip packaging structure, comprising: A circuit substrate, comprising a substrate, a first conductive pad, a second conductive pad and a polymer layer, wherein the first conductive pad and the second conductive pad are respectively located above a first surface and a second surface of the substrate, the first conductive pad is narrower than the second conductive pad, and the polymer layer is located above the first surface and the first conductive pad; a conductive adhesive layer passing through the polymer layer and located above the first conductive pad, wherein the conductive adhesive layer directly contacts the polymer layer and the first conductive pad; a nickel layer located above the conductive adhesive layer, wherein the nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are formed of different materials; a copper layer disposed above the nickel layer; A chip is located above the circuit substrate; as well as A conductive bump is located between the copper layer and the chip. 18 . The chip package structure as claimed in claim 17 , wherein the nickel layer covers a side wall and a top surface of the conductive adhesive layer.

Images